MICROCHIP PIC18F6520, PIC18F8520, PIC18F6620, PIC18F8620, PIC18F6720 DATA SHEET
...
PIC18F6520/8520/6620/8620/6720/8720
Data Sheet
64/80-Pin High-Performance,
256 Kbit to 1 Mbit Enhanced Flash
Microcontrollers with A/D
2004 Microchip Technology Inc. DS39609B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL, SmartShunt and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net,
dsPICworks, ECAN, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MP LI B,
MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC,
Select Mode, SmartSensor, SmartTel and Total Endurance
are trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system certificat io n f or
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in October
2003. The Com pany’s quality sy stem proces ses and pro cedures are for
its PICmicro
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping devices, Serial
DS39609B-page ii 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/
8620/6720/8720
64/80-Pin High-Performance, 256 Kbit to 1 Mbit
Enhanced Flash Microcontrollers with A/D
High-Performance RISC CPU:
• C compiler optimized architecture/instruction set:
- Source code compatible with the PIC16 and
PIC17 instruction sets
• Linear program memory addressing to 128 Kbytes
• Linear data memory addr essing to 3840 bytes
• 1 Kbyte of data EEPROM
• Up to 10 MIPs operation:
- DC – 40 MHz osc./clock input
- 4 MHz – 10 MHz os c./clock input with PLL ac ti v e
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, so ftware accessible hardware stack
• 8 x 8 Single Cycle Har dware Multiplier
External Memory Interface (PIC18F8X20 Devices Only):
• Address c apability of up to 2 Mbytes
• 16-bit interface
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Four ext ernal inte rrupt pins
• Timer0 module: 8-bit/16-bit timer/counter
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter
• Timer3 module: 16-bit timer/counter
• Timer4 module: 8-bit timer/counter
• Secondary oscillator clock option – Timer1/Timer3
• Five Capture/Compare/ PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (T
- Compare is 16-bit, max. resolution 100 ns (T
- PWM output: PWM resolution is 1 to 10-bit
• Master Synchronous Serial Port (MSSP) module
with two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
2
-I
C™ Master and Slave mode
• Two Addressable USART modules:
- Supports RS-485 and RS-232
• Parallel Slave Port (PSP) module
CY/16)
CY)
Analog Features:
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Conversion available during Sleep
• Programmable 16-level Low-Voltage Detection
(LVD) module:
- Supports interrupt on Low-Voltage Detection
• Programmable Brown-out Reset (PBOR)
• Dual analog comparators:
- Programmable input/output configuration
Special Microcontroller Features:
• 100,000 erase/write cycl e Enhan ced Flas h
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second programming time
• Flash/Data EEPROM Retention: > 40 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWR T)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable code protection
• Power sa ving Sleep mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• MPLAB
®
In-Circuit Debug (ICD) via two pins
CMOS Technology:
• Low-power, high-speed Flash technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
Program Memory Data Memory
Device
PIC18F6520 32K 16384 2048 1024 52 12 5 Y Y 2 2/3 N 40
PIC18F6620 64K 32768 3840 1024 52 12 5 Y Y 2 2/3 N 25
PIC18F6720 128K 65536 3840 1024 52 12 5 Y Y 2 2/3 N 25
PIC18F8520 32K 16384 2048 1024 68 16 5 Y Y 2 2/3 Y 40
PIC18F8620 64K 32768 3840 1024 68 16 5 Y Y 2 2/3 Y 25
PIC18F8720 128K 65536 3840 1024 68 16 5 Y Y 2 2/3 Y 25
2004 Microchip Technology Inc. DS39609B-page 1
Bytes
# Single-W ord
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
10-bit
A/D
(ch)
CCP
(PWM)
SPI
MSSP
Master
USART
2
I
C
Timers
8-bit/16-bit
Ext
Bus
Max
OSC
F
(MHz)
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams
PIC18F6620
DS39609B-page 2 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams (Continued)
80-Pin TQFP
RH1/A17
RH0/A16
(2)
RE5/AD13
RE6/AD14
(3)
RE7/CCP2/AD15
(3)
RE2/CS/AD10
RE3/AD11
RE4/AD12
(3)
(3)
(3)
(3)
(3)
(3)
(3)
RD0/PSP0/AD0
VDD
VSS
RD1/PSP1/AD1
RD2/PSP2/AD2
RD3/PSP3/AD3
RD4/PSP4/AD4
RD5/PSP5/AD5
RD6/PSP6/AD6
RD7/PSP7/AD7
RJ0/ALE
RJ1/OE
RH2/A18
RH3/A19
RE1/WR/AD9
RE0/RD/AD8
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
MCLR
/VPP
RG4/CCP5
V
VDD
RF7/SS
RF6/AN11
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15
RH6/AN14
(3)
(3)
SS
80
787776
79
75
74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2122232425262728293031
DD
AVSS
AV
RH4/AN12
RF0/AN5
RF1/AN6/C2OUT
RA3/AN3/VREF+
RH5/AN13
73
727170
69
PIC18F8520
PIC18F8620
PIC18F8720
32
SS
V
REF-
RA1/AN1
RA2/AN2/V
VDD
RA0/AN0
686766
333435
(1)
RA4/T0CKI
RA5/AN4/LVDIN
RC1/T1OSI/CCP2
65
646362
37
36
RC6/TX1/CK1
RC0/T1OSO/T13CKI
38
RC7/RX1/DT1
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
RJ5/CE
RJ4/BA0
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V
SS
OSC2/CLKO/RA6
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RJ7/UB
RJ6/LB
(1)
Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set.
2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode.
3: PSP is available only in Microcontroller mode.
2004 Microchip Technology Inc. DS39609B-page 3
PIC18F6520/8520/6620/8620/6720/8720
Table of Contents
1.0 Device Overview..........................................................................................................................................................................7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset .......................................................................................................................................................................................... 29
4.0 Memory Organization................................................................................................................................................................. 39
5.0 F la sh Program Memory.................... ......................... ................................................................................................................. 61
6.0 External Memory Interface......................................................................................................................................................... 71
7.0 Data EEPROM Memory........ ......................... ............................................................. ............................................................... 79
8.0 8 X 8 Hard ware Multiplier............................................................. ..............................................................................................85
9.0 Interrupts.................................................................................................................................................................................... 87
10.0 I/O Ports.............................. ......................... ................................................ ............................................................................103
11.0 Timer0 Module ......................................................................................................................................................................... 131
12.0 Timer1 Module ......................................................................................................................................................................... 135
13.0 Timer2 Module ......................................................................................................................................................................... 141
14.0 Timer3 Module ......................................................................................................................................................................... 143
15.0 Timer4 Module ......................................................................................................................................................................... 147
16.0 Capture/Compare/PWM (CCP) Modules .................................................................................................................................149
17.0 Master Synchronous Serial Port (MSSP) Module ....................................................................................................................157
18.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )..............................................................197
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 213
20.0 Comparator Module............................................................................................. .. .... .... .. .........................................................223
21.0 Comparator Voltage Reference Module......................................... .. .... .. .... .. ....... .... .. .... .. ....... .... .. ............................................ 229
22.0 Low-Voltage Detect..................................................................................................................................................................233
23.0 Special Features of the CPU....................................................................................................................................................239
24.0 Instruction Set Summary..........................................................................................................................................................259
25.0 Development Support. .............................................................................................................................................................. 301
26.0 Electrical Characteristics ..........................................................................................................................................................307
27.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................343
28.0 Packaging Information.............................. ................................................................................................................................357
Appendix A: Revision History.............................................................................................................................................................361
Appendix B: Device Differences......................................................................................................................................................... 361
Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 362
Appendix D: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 362
Appendix E: Migration from High-End to Enhanced Devices.............................................................................................................363
Index .................................................................................................................................................................................................. 365
On-Line Support........................................................................ .... .. ......... .... .. .... .... ....... .... ................................................................. 375
Systems Information and Upgrade Hot Line......................................................................................................................................375
Reader Response.............................................................................................................................................................................. 376
PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377
DS39609B-page 4 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to bet ter suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
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2004 Microchip Technology Inc. DS39609B-page 5
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609B-page 6 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F6520 • PIC18F8520
• PIC18F6620 • PIC18F8620
• PIC18F6720 • PIC18F8720
This family offers the same advantages of all PIC18
microcontrollers – namely, high computational
performance at a n economic al price – wit h the additio n of
high endurance Enhanced Flash program memory. The
PIC18FXX20 fami ly al so pro vide s an enha nced rang e of
program memory options and versatile analog features
that make it ideal for complex, high-performance
applications.
1.1 Key Features
1.1.1 EXPANDED MEMORY
The PIC18FXX20 fami ly introd uces the w idest range of
on-chip, Enhanced Flash program memory available
on PICmic ro® microcontrollers – up to 128 Kbyte (or
65,536 words), the largest ever offered by Microchip.
For users with more modest code requirements, the
family also includes members with 32 Kbyte or
64 Kbyte.
Other memory features are:
• Data RAM and Data EEPROM: The
PIC18FXX20 family also provides plenty of room
for application data. Depending on the device,
either 2048 or 3840bytes of data RAM are
available. All devices have 1024bytes of data
EEPROM for long-term retention of nonvolatile
data.
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
1.1.2 EXTERNAL MEMORY INTERFACE
In the event that 128 Kbytes of program memory is
inadequate for an application, the PIC18F8X20
members of the family also implement an External
Memory Interface. This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim.
With the addition of new operat ing modes, the External
Memory Interface offers many new options, including:
• Operatin g the microcont roller entirel y from external
memory
• Using combinations of on-chip and external
memory, up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code, or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.3 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping fr om 64-pin to 80-pin devices.
1.1.4 OTHER SPECIAL FEA TURES
• Communications: The PIC18FXX20 family
incorporates a range of serial communications
peripherals, includin g 2 independen t USARTs and
a Master SSP module, capable of both SPI and
I2C (Master and Slave) modes of operation. For
PIC18F8X20 device s, one of the genera l purpos e
I/O ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
• CCP Modules: All devices in the family
incorporate five Capt ure/Com par e/PWM mo dules
to maximize flexibility in control applications. Up
to four different time bases may be used to
perform several different operations at once.
• Analog Features: All devices in the family
feature 10-bit A/D converters, with up to 16 input
channels, as well as the ability to perform
conversions during Sleep mode. Also included
are dual analog comparators with programmable
input and output configuration, a programmable
Low-Voltage Detect module and a programmable
Brown-out Reset module.
• Self-programmability: These devices can write
to their own program memory spaces under internal software control. By us ing a bootloader routi ne
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.
2004 Microchip Technology Inc. DS39609B-page 7
PIC18F6520/8520/6620/8620/6720/8720
1.2 Details on Individual Family Members
3. A/D channels (12 for PIC18F6X20 devices,
16 for PIC18F8X20)
4. I/O pins (52 on PIC18F6X20 devices, 68 on
The PIC18FXX 20 devices ar e available in 64-pin and
80-pin packages. They are differentiated from each
other in five ways:
1. Flash program memory (32 Kbytes for
PIC18FX520 devices, 64Kbytes for
PIC18FX620 devices and 128 Kbytes for
PIC18FX720 devices)
2. Data RAM (2048 bytes for PIC18FX520
devices, 3840 bytes for PIC18FX620 and
PIC18FX720 devices)
PIC18F8X20)
5. External program memory interface (present
only on PIC18F8X20 devices)
All other features for devic es in the PIC18FXX2 0 family
are identical. Thes e are summarized in Table 1-1.
Block diagra ms of the PIC1 8F6X20 and PIC 18F8X20
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
TABLE 1-1: PIC18FXX20 DEVICE FEATURES
Features PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720
Operating Frequency DC – 40 MHz DC – 25 MHz DC – 25 MHz DC – 40 MHz DC – 25 MHz DC – 25 MHz
Program Memory
(Bytes)
Program Memory
(Instructions)
Data Memory
(Bytes)
Data EEPROM
Memory (Bytes)
External Me mory
Interface
Interrupt Sources 17 17 17 18 18 18
I/O Ports Ports A, B, C,
Timers 5 5 5 5 5 5
Capture/Compare/
PWM Modules
Serial Communications MSSP,
Parallel Communications PSP PSP PSP PSP PSP PSP
10-bit Analog-to-Digital
Module
Resets (and Delays) POR, BOR,
Programmable
Low-Voltage Detect
Programmable
Brown-out Reset
Instruction Set 77 Instructions 77 Instructions 77 Instructions 77 Instructions 77 Instruct ions 77 Instructions
Package 64-pin TQFP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP
32K 64K 128K 32K 64K 128K
16384 32768 65536 16384 32768 65536
2048 3840 3840 2048 3840 3840
1024 1024 1024 1024 1024 1024
No No No Yes Yes Yes
Ports A, B, C, D,
D, E, F, G
55 5555
Addressable
USART (2)
12 input
channels
RESET
Instruction,
Stack Full,
Stack Un derflow
(PWRT , OST)
Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes
E, F, G
MSSP,
Addressable
USART (2)
12 input
channels
POR, BOR,
RESET
Instruction,
Stack Ful l,
Stack Und erf low
(PWRT, OST)
Ports A, B, C, D,
E, F, G
MSSP,
Addressable
USART (2)
12 input
channels
POR, BOR,
RESET
Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Ports A, B, C,
D, E, F, G, H, J
MSSP,
Addressable
USART (2)
16 input
channels
POR, BOR,
RESET
Instruction,
Stack Full,
Sta ck Underflow
(PWRT, OST)
Ports A, B, C,
D, E, F, G, H, J
MSSP,
Addressable
USART (2)
16 input
channels
POR, BOR,
RESET
Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Ports A, B, C,
D, E, F, G, H, J
MSSP,
Addressable
USART (2)
16 input
channels
POR, BOR,
RESET
Instruction,
Stack Full,
Sta ck Underflow
(PWRT, OST)
DS39609B-page 8 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-1: PIC18F6X20 BLOCK DIAGRAM
Address Latch
Address<12>
Data Latch
Data RAM
12
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
PORTB
RB0/INT0
RB1/INT1
OSC2/CLKO
OSC1/CLKI
Instruction
Decode &
Control
Timing
Generation
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
BSR
Decode
FSR0
FSR1
FSR2
inc/dec
logic
Bank0, F
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
MCLR
/VPP
VDD, VSS
Synchronous
Serial Port
BOR
Comparator
USART1
2004 Microchip Technology Inc. DS39609B-page 9
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM
Address Latch
Program Memory
System Bus Interface
Data Latch
AD15:AD0, A19:A16
OSC2/CLKO
OSC1/CLKI
Synchronous
Serial Port
BOR
LVD
21
(1)
Instruction
Decode &
Control
Timing
Generation
Precision
Band Gap
Reference
Timer0
T able Pointer<21>
21
inc/dec logic
21
Table Latch
16
USART1
PCLATU
PCLATH
PCU
Program Counter
31 Level Stack
8
ROM Latch
IR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MCLR
/VPP
Timer1
8
PCH PCL
VDD, VSS
USART2
Timer2
8
4
BSR
Decode
BITOP
Timer3
3
8
EEPROM
Data Bus<8>
Data Latch
Data RAM
Address Latch
12
Address<12>
12 4
Bank0, F
FSR0
FSR1
FSR2
inc/dec
logic
PRODLPRODH
8 x 8 Multiply
WREG
8
8
ALU<8>
8
Data
Timer4
12
8
8
8
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
PORTJ
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RE0/RD/AD8
RE1/WR/AD9
RE2/CS/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/CCP2/AD15
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
RD7/PSP7/AD7:
RD0/PSP0/AD0
RH3/AD19:RH0/AD16
RH7/AN15:RH4/AN12
Comparator
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
CCP1 CCP2 CCP3 CCP4 CCP5
10-bit
A/D
DS39609B-page 10 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
PIC18F6X20 PIC18F8X20
Pin
Type
Buffer
Type
Description
/VPP
MCLR
MCLR
VPP
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
79
I
P
39 49
IICMOS/ST
40 50
O
O
I/O
ST
CMOS
—
—
TTL
Master Clear (input) or programming
voltage (output) .
Master Cl ear (Reset) input. This pin is
an active-low Reset to the device.
Programming voltage inpu t.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock
source input. ST buf fe r when co nfigured
in RC mode; otherwise CMOS.
External cl ock source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/ CLKO pins).
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
General purpose I/O pin.
DD)
2004 Microchip Technology Inc. DS39609B-page 11
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA2
AN2
V
RA3/AN3/VREF+
RA3
AN3
V
RA4/T0CKI
RA4
T0CKI
RA5/AN4/LVDIN
RA5
AN4
LVDIN
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
REF-
REF-
REF+
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
24 30
23 29
22 28
21 27
28 34
27 33
Pin
Type
I/O
I/O
I/O
I/O
I/OIST/OD
I/O
Buffer
Type
TTL
I
Analog
TTL
I
Analog
TTL
I
Analog
I
Analog
TTL
I
Analog
I
Analog
ST
TTL
I
Analog
I
Analog
Description
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
Digital I/O – Open-drain when
configured as output.
Timer0 external clock input.
Digital I/O.
Analog input 4.
Low-Voltage Detect input.
DD)
DS39609B-page 12 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/INT3/CCP2
RB3
INT3
(1)
CCP2
RB4/KBI0
RB4
KBI0
RB5/KBI1/PGM
RB5
KBI1
PGM
RB6/KBI2/PGC
RB6
KBI2
PGC
RB7/KBI3/PGD
RB7
KBI3
PGD
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
6: AV
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
48 58
47 57
46 56
45 55
44 54
43 53
42 52
37 47
Pin
Type
I/O
I
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I/O
I
I/O
I/O
I/O
Buffer
Type
TTL
ST
TTL
ST
TTL
ST
TTL
ST
ST
TTL
ST
TTL
ST
ST
TTL
ST
ST
TTL
ST
Description
PORTB is a bidirectional I/O port. PORTB
can be soft ware programmed for internal
weak pull-ups on all inputs.
Digital I/O.
External interrupt 0.
Digital I/O.
External interrupt 1.
Digital I/O.
External interrupt 2.
Digital I/O.
External interrupt 3.
Capture2 input, Compare2 output,
PWM2 output.
Digital I/O.
Interrupt-on-change pin.
Digital I/O.
Interrupt-on-change pin.
Low-V olt age ICSP Pro gramm ing enabl e
pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming clock.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming data.
DD)
2004 Microchip Technology Inc. DS39609B-page 13
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
T1OSI
(2)
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX1/CK1
RC6
TX1
CK1
RC7/RX1/DT1
RC7
RX1
DT1
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
30 36
29 35
33 43
34 44
35 45
36 46
31 37
32 38
Pin
Type
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
ST
—
ST
ST
CMOS
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
Description
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input/Compare2 output/
PWM2 output.
Digital I/O.
Capture1 input/Compare1 output/
PWM1 output.
Digital I/O.
Synchronous serial clock input/output
for SPI mode.
Synchronous serial clock input/output
2
C mode.
for I
Digital I/O.
SPI data in.
2
C data I/O .
I
Digital I/O.
SPI data out.
Digital I/O.
USART 1 asynchronous transmit.
USART 1 synchronous clock
(see RX1/DT1).
Digital I/O.
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX1/CK1).
DD)
DS39609B-page 14 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X20 PIC18F8X20
RD0/PSP0/AD0
58 72
RD0
PSP0
(3)
AD0
RD1/PSP1/AD1
55 69
RD1
PSP1
(3)
AD1
RD2/PSP2/AD2
54 68
RD2
PSP2
(3)
AD2
RD3/PSP3/AD3
53 67
RD3
PSP3
(3)
AD3
RD4/PSP4/AD4
52 66
RD4
PSP4
(3)
AD4
RD5/PSP5/AD5
51 65
RD5
PSP5
(3)
AD5
RD6/PSP6/AD6
50 64
RD6
PSP6
(3)
AD6
RD7/PSP7/AD7
49 63
RD7
PSP7
(3)
AD7
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
6: AV
proper operation of the part in user or ICSP modes. See parameter D001A for details.
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
Description
PORTD is a bidirectional I/O port. These
pins have TTL input buffers when external
memory is enabled.
Digital I/O.
Parallel Slave Port data.
External memory address/data 0.
Digital I/O.
Parallel Slave Port data.
External memory address/data 1.
Digital I/O.
Parallel Slave Port data.
External memory address/data 2.
Digital I/O.
Parallel Slave Port data.
External memory address/data 3.
Digital I/O.
Parallel Slave Port data.
External memory address/data 4.
Digital I/O.
Parallel Slave Port data.
External memory address/data 5.
Digital I/O.
Parallel Slave Port data.
External memory address/data 6.
Digital I/O.
Parallel Slave Port data.
External memory address/data 7.
DD)
2004 Microchip Technology Inc. DS39609B-page 15
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X20 PIC18F8X20
RE0/RD
/AD8
24
RE0
RD
(3)
AD8
RE1/WR
/AD9
13
RE1
WR
(3)
AD9
RE2/CS
/AD10
64 78
RE2
CS
(3)
AD10
RE3/AD11
RE3
AD1 1
RE4/AD12
(3)
63 77
62 76
RE4
AD12
RE5/AD13
RE5
(3)
AD13
RE6/AD14
RE6
(3)
AD14
RE7/CCP2/AD15
RE7
(1,4)
CCP2
(3)
AD15
61 75
60 74
59 73
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
Pin
Type
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
ST
TTL
Description
PORTE is a bidirectional I/O port.
Digital I/O.
Read control for Parallel Slave Port
R and CS pins).
(see W
External memory address/data 8.
Digital I/O.
Write control for Parallel Slave Port
S and RD pins).
(see C
External memory address/data 9.
Digital I/O.
Chip select control for Parallel Slave
Port (see RD
and WR).
External memory address/data 10.
Digital I/O.
External memory address/data 11.
Digital I/O.
External memory address/data 12.
Digital I/O.
External memory address/data 13.
Digital I/O.
External memory address/data 14.
Digital I/O.
Capture2 input/Compare2 output/
PWM2 output.
External memory address/data 15.
DD)
DS39609B-page 16 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RF0/AN5
RF0
AN5
RF1/AN6/C2OUT
RF1
AN6
C2OUT
RF2/AN7/C1OUT
RF2
AN7
C1OUT
RF3/AN8
RF1
AN8
RF4/AN9
RF1
AN9
RF5/AN10/CV
RF1
AN10
CV
RF6/AN11
RF6
AN1 1
RF7/SS
RF7
SS
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
REF
REF
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Microcontroller).
multiplexed with either RB3 or RC1.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
18 24
17 23
16 18
15 17
14 16
13 15
12 14
11 13
Pin
Type
I/O
I
I/O
I
O
I/O
I
O
I/O
I
I/O
I
I/O
I
O
I/O
I
I/O
I
Buffer
Type
ST
Analog
ST
Analog
ST
ST
Analog
ST
ST
Analog
ST
Analog
ST
Analog
Analog
ST
Analog
ST
TTL
Description
PORTF is a bidirectional I/O port.
Digital I/O.
Analog input 5.
Digital I/O.
Analog input 6.
Comparator 2 output.
Digital I/O.
Analog input 7.
Comparator 1 output.
Digital I/O.
Analog input 8.
Digital I/O.
Analog input 9.
Digital I/O.
Analog input 10.
Comparator V
Digital I/O.
Analog input 11.
Digital I/O.
SPI slave select input.
REF output.
DD)
2004 Microchip Technology Inc. DS39609B-page 17
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RG0/CCP3
RG0
CCP3
RG1/TX2/CK2
RG1
TX2
CK2
RG2/RX2/DT2
RG2
RX2
DT2
RG3/CCP4
RG3
CCP4
RG4/CCP5
RG4
CCP5
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
6: AV
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
35
46
57
68
810
Pin
Type
I/O
I/O
I/O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST
ST
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
Description
PORTG is a bidirectional I/O port.
Digital I/O.
Capture3 input/Compare3 output/
PWM3 output.
Digital I/O.
USART 2 asynchronous transmit.
USART 2 synchronous clock
(see RX2/DT2).
Digital I/O.
USART 2 asynchronous receive.
USART 2 synchronous data
(see TX2/CK2).
Digital I/O.
Capture4 input/Compare4 output/
PWM4 output.
Digital I/O.
Capture5 input/Compare5 output/
PWM5 output.
DD)
DS39609B-page 18 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RH0/A16
RH0
A16
RH1/A17
RH1
A17
RH2/A18
RH2
A18
RH3/A19
RH3
A19
RH4/AN12
RH4
AN12
RH5/AN13
RH5
AN13
RH6/AN14
RH6
AN14
RH7/AN15
RH7
AN15
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
6: AV
proper operation of the part in user or ICSP modes. See parameter D001A for details.
PIC18F6X20 PIC18F8X20
Pin Number
—79
—80
—1
—2
—22
—21
—20
—19
Pin
Type
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
Buffer
Type
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
Analog
ST
Analog
ST
Analog
ST
Analog
Description
PORTH is a bidirectional I/O port
Digital I/O.
External memory address 16.
Digital I/O.
External memory address 17.
Digital I/O.
External memory address 18.
Digital I/O.
External memory address 19.
Digital I/O.
Analog input 12.
Digital I/O.
Analog input 13.
Digital I/O.
Analog input 14.
Digital I/O.
Analog input 15.
DD)
(5)
.
2004 Microchip Technology Inc. DS39609B-page 19
PIC18F6520/8520/6620/8620/6720/8720
RJ0/ALE
RJ0
ALE
RJ1/OE
RJ1
OE
RJ2/WRL
RJ2
WRL
RJ3/WRH
RJ3
WRH
RJ4/BA0
RJ4
BA0
RJ5/CE
RJ5
CE
RJ6/LB
RJ6
LB
RJ7/UB
RJ7
UB
VSS 9, 25,
V
DD 10, 26,
(6)
AV
SS
—62
—61
—60
—59
—39
—40
—41
—42
41, 56
38, 57
20 26 P — Ground reference for analoglogi411.2rence for anal2.6(r an)12TJ7(r an)4.9203 /L.9SS 57
11, 31,
51, 70
12, 32,
48, 71
PORTJ is a bidirectional I/O port
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
P — Ground reference for logic and I/O pins.
P — Positive supply for logic and I/O pins.
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
Digital I/O.
External memory address latch enable.
Digital I/O.
External memory output enable.
Digital I/O.
External memory write low control.
Digital I/O.
External memory write high control.
Digital I/O.
External memory Byte Address 0 control.
Digital I/O.
External memory chip enable control.
Digital I/O.
External memory low byte sele ct.
Digital I/O.
External memory high byte select.
(5)
.
DS39609B-page 20 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.0 OSCILLATOR CONFIGURATIONS
2.1 Oscillator Types
The PIC18FXX20 devices can be operated in eight
different oscillator modes. The user can program three
configuration bits (FOSC2, FOSC1 and FOSC0) to
select one o f these eight modes:
1. LP Low-Power Cry stal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HS+PLL High-Speed Crys tal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor
6. RCIO External Resistor/Capac ito r with
I/O pin enabled
7. EC External Clock
8. ECIO External Clock with I/O pin
enabled
2.2 Crystal Oscillator/Ceramic Resonators
In XT, LP, HS or HS+PLL Oscill ato r m od es , a c ry st a l or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18FXX20 oscillator design requires the use of
a parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer ’s
specifications.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)
(1)
C1
C2
(1)
XTAL
(2)
RS
OSC1
OSC2
(3)
RF
PIC18FXX20
Sleep
To
Internal
Logic
T ABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Tested:
Mode Freq C1 C2
XT 455 kHz
2.0 MHz
4.0 MHz
HS 8.0 MHz
16.0 MHz
These values are for design guidance only.
See notes following this table.
Resonators Used:
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used di d not have built-in capac itors.
Note 1: Higher capac itance inc reases th e stabilit y
of the oscillator, but also increases the
start-up time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components, or verify oscillator
performance.
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
DD, or when
Note 1: See Table2-1 and Table 2-2 for recommended
2004 Microchip Technology Inc. DS39609B-page 21
values of C1 and C2.
2: A s eries resist or (R
strip cut crystals.
F varies with the oscillator mode chosen.
3: R
S) may be required for AT
PIC18F6520/8520/6620/8620/6720/8720
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Ranges T ested:
Mode Freq C1 C2
LP 32 kHz
200 kHz
XT 1 MHz
4 MHz
HS 4 MHz
20 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the above crystal
frequencies for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following this table for additional
information.
Note 1: Higher capacit ance increa ses the st ability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its
own characteristics, the user should
consult the resonator/crystal manufacturer for appropriate values of external
components, or verify oscillator
performance.
S may be required to avoid overdriving
4: R
crystals with low driv e lev e l spe ci fic ati on.
5: Always verify oscillator performance over
DD and temperature range that is
the V
expected for the application.
An external clock sourc e may also be conne cted to th e
OSC1 pin in the HS, XT and LP modes, as shown in
Figure 2-2.
15-22 pF 15-22 pF
15-22 pF 15-22 pF
15-22 pF 15-22 pF8 MHz
DD, or when
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
Clock from
Ext. System
Open
OSC1
PIC18FXX20
OSC2
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit, due
to normal process parameter variation. Furthermore,
the difference in lead frame cap acitance bet ween package types will also affect the oscillation frequency,
especially for low C
take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.
FIGURE 2-3: RC OSCILLATOR MODE
VDD
REXT
CEXT
VSS
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
The RCIO Oscillato r mode f unc tions like t he RC m ode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
EXT) and capacitor (CEXT) val-
EXT values. Th e user also needs to
OSC1
Internal
Clock
PIC18FXX20
OSC2/CLKO
OSC/4
EXT > 20 pF
C
DS39609B-page 22 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.4 External Clock Input
The EC and ECIO Oscillator mode s require an externa l
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5 µs start-up required after a Power-on Reset, or
wake-up from Sleep mo de.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
F
OSC/4
The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
OSC1
PIC18FXX20
OSC2
FIGURE 2-5: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Clock from
Ext. System
RA6
OSC1
PIC18FXX20
I/O (OSC2)
2.5 HS/PLL
A Phase Locked Loop circuit (PLL) is provided as a
programmable option for us ers that want to multip ly the
frequency of the incoming cry sta l oscil lator sig nal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL is one o f the modes of the FO SC<2:0> co nfiguration bits. The oscillator mode is specified during
device programming.
The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. I f they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed “onthe-fly”. To enable or disable it, the controller must
either cycle through a Power-on Re set, or switch the
clock source from the main oscillator to the Timer1
oscillator and b ack again. See Se ction 2.6 “Oscillator
Switching Feature” for details on os cillator s witching.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T
PLL.
FIGURE 2-6: PLL BLOCK DIAGRAM
(from Configuration
bit Register)
OSC2
OSC1
2004 Microchip Technology Inc. DS39609B-page 23
HS Osc
PLL Enable
Crystal
Osc
Phase
Comparator
FIN
FOUT
Loop
Filter
Divide by 4
VCO
SYSCLK
MUX
PIC18F6520/8520/6620/8620/6720/8720
2.6 Oscillator Switching Feature
The PIC18FXX20 devices inc lude a fea ture that a llow s
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
For the PIC18FXX20 devices, this alternate clock
source is the Timer1 oscillator. If a low-frequency
crystal (32 kHz, for ex am pl e ) ha s bee n at tac he d to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low-power
FIGURE 2-7: DEVICE CLOCK SOURCES
PIC18FXX20
OSC2
OSC1
T1OSO
T1OSI
Main Oscillator
Sleep
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN
) bit in Configuration Regis ter 1H to a
‘0’. Clock switching is disabled in an erased device.
See Section 12.0 “Timer1 Module” for further details
of the Timer1 oscillator. See Section 23.0 “Special
Features of the CPU” for Configuration register
details.
4 x PLL
TOSC
TT1P
TOSC/4
MUX
Clock
Source
TSCLK
Clock Source Option
for other Modules
DS39609B-page 24 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock sourc e sw it ching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>), controls the clock switching. When the
SCS bit is ‘0’, the system cloc k s our ce c om es fr om the
main oscillator that i s s el ec ted b y t he FO SC c onfiguration bits in Configuration Register 1H. When the SCS
bit is set, the system clock source will come from the
Timer1 o scillato r. The SCS bit is cleared on all forms of
Reset.
REGISTER 2-1: OSCCON REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
— — — — — — —SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SCS: System Clock Switch bit
When OSCSEN Configuration bit = 0 and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When
OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Note: The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (S CS bit force d
cleared) and the main oscillator will
continue to be the system clock source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. DS39609B-page 25
PIC18F6520/8520/6620/8620/6720/8720
2.6.2 OSCILLATOR TRANSITIONS
PIC18FXX20 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is swit ching to. This
ensures that the n ew c lo ck s ourc e is s t able and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is s hown in Figure2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1
T1OSI
OSC1
Internal
System
Clock
SCS
(OSCCON<0>)
Program
Counter
Note 1:Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
TSCS
PC + 2PC
Q3Q2Q1Q4Q3Q2
Q4 Q1
PC + 4
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (TOST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
DS39609B-page 26 2004 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
If the main oscil lator is config ured for HS-P LL mode, an
oscillator start-up time (T
time-out (T
PLL), will occur. The PLL time-out is typica lly
OST), plus an additional PLL
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
2 ms and allows the PLL to lock to the main oscillator
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4 Q1
T1OSI
OSC1
TOST
OSC2
PLL Clock
Input
Internal System
Program Counter
Note 1:TOST = 1024 TOSC (drawing not to scale).
Clock
(OSCCON<0>)
SCS
PC PC + 2
TPLL
TT1P
TOSC
1 234 5678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2
PC + 4
Q3
Q4
If the main oscillato r is c onfigur ed in th e RC, R CIO, EC
or ECIO modes, th ere is no os cillator start-up time-out.
Operation will resume after eight cycles of the main
indicating the trans ition from the T imer1 oscillator to th e
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
oscillator have been counted. A timing diagram,
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4
T1OSI
OSC1
OSC2
Internal System
Clock
(OSCCON<0>)
Note 1:RC Oscillator mode assumed.
SCS
Program
Q1
PC PC + 2
Q1 Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
2004 Microchip Technology Inc. DS39609B-page 27
PIC18F6520/8520/6620/8620/6720/8720
2.7 Effects of Sleep Mode on the On-Chip Oscillator
When the device e xecutes a SLEEP i nstructio n, the onchip clocks and oscillator are turn ed off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
2.8 Power-up Delays
Power up delays are con trolled by two timers so that n o
external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset un til the device p ower supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fix ed del ay of 72 ms (nom in al) o n
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequenc e following a Power-on Reset is diff erent from other oscil lator modes. The time-out se quence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWR T timer is used to provide
an additional fixed 2 ms (nominal) time-out to allow th e
PLL ample time to lock to the incoming cloc k frequency .
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull high At logic low
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating Configured as PORTA, bit 6
EC Floating At logic low
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
Feedback inverter disabled at quiescent
voltage level
DS39609B-page 28 2004 Microchip Technology Inc.
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