MICROCHIP PIC18F6390, PIC18F6490, PIC18F8390, PIC18F8490 DATA SHEET

PIC18F6390/6490/8390/8490

Data Sheet

64/80-Pin Flash Microcontrollers

with LCD Driver and nanoWatt Technology

 2004 Microchip Technology Inc. Preliminary DS39629B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS39629B-page ii Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

64/80-Pin Flash Microcontrol lers with LCD Driver

and nanoW att Technology

LCD Driver Module Features:

• Direct driving of LCD panel

• Up to 48 segm ents: Software Selectable

• Programmable LCD timing module:

- Multiple LCD timing sources available

- Up to 4 commons: Static, 1/2, 1/3 or 1/4 mu ltiplex

- Static, 1/2 or 1/3 bias configuration

• Can drive LCD panel while in Sleep mode

Power Managed Modes:

• Run: CPU on, peripheral s on

• Idle: CPU off, peripheral s on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 µA typical

• Sleep current down to 0.1 µA typical

• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• T wo -Spe ed Os ci ll ator Start-up

Flexible Oscillator Struc ture:

• Four Crystal modes:

- LP: up to 200 kHz

- XT: up to 4 MHz

- HS: up to 40 MHz

- HSPLL: 4-10 MHz (16-40 MHz internal)

• 4x Phase Lock Loop (available for crystal and

internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe sh ut down of dev ice if prim ary
or secondary clock fails

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Four external interrupts

• Four input-change interrupts

• Four 8-bit/16-bit Timer/Counter modules

• Real-Time Clock (RTC) Software module:

- Configurable 24-hour clock, calendar , auto matic
100-year or 12800-year, day-of-w eek calculator

- Uses Timer1

• Up to 2 Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I

2

C™

Master and Slave modes

• Addressable USART module:

- Supports RS-485 and RS-232

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-wake-up on Start bit

- Auto-baud Detect

• 10-bit, up to 12-channel Analog-to-Digital
Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

Special Microcontroller Features:

• C compiler optimized architecture

- Optional extended instruct ion set designed to

optimize re-entrant code

• 1000 erase/wr i te cy c le Fl as h pr ogram memory typical

• Flash Retention: 100 years typical

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 132 s

- 2% stability over V

• In-Circuit Serial Programming ™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

DD and temperature

Program Memory

Device

PIC18F6390 8K 4096 768 50 128 12 2 Y Y 1/1 2 1/3
PIC18F6490 16K 8192 768 50 128 12 2 Y Y 1/1 2 1/3
PIC18F8390 8K 4096 768 66 192 12 2 Y Y 1/1 2 1/3
PIC18F8490 16K 8192 768 66 192 12 2 Y Y 1/1 2 1/3

 2004 Microchip Technology Inc. Preliminary DS39629B-page 1

Flash

(bytes)

# Single-Word

Instructions

Data

Memory

SRAM
(bytes)

I/O

LCD

(pixel)

10-bit

A/D (ch)

CCP

(PWM)

SPI

MSSP

Master

Comparators

2

I

C™

AUSART

EUSART/

Timers

8/16-bit

PIC18F6390/6490/8390/8490

Pin Diagrams

64-Pin TQFP

/SEG31

(1)

LCDBIAS2
LCDBIAS1

RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28

RG3/SEG27

/VPP/RG5

MCLR

RG4/SEG26

V
VDD

RF7/SS/SEG25

RF6/AN11/SEG24

RF5/AN10/CV

RF2/AN7/C1OUT/SEG20

REF/SEG23

RF4/AN9/SEG22
RF3/AN8/SEG21

LCDBIAS3

COM0

RE4/COM1

RE5/COM2

RE6/COM3

64

63 62 61

1
2
3
4
5
6
7

SS

8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26

DD

RE7/CCP2

RD0/SEG0

V

VSS

PIC18F6390
PIC18F6490

RD1/SEG1

RD2/SEG2

54 53 52 5158 57 56 5560 59

27 28

RD3/SEG3

RD4/SEG4

29 30

RD5/SEG5

RD6/SEG6

50 49

31

RD7/SEG7

32

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC

SS

V
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13

DD

AVSS

AV

REF-/SEG16

RF0/AN5/SEG18

RA2/AN2/V

RF1/AN6/C2OUT/SEG19

RA3/AN3/VREF+/SEG17

SS

V

VDD

RA1/AN1

RA0/AN0

(1)

RC6/TX1/CK1

RC7/RX1/DT1

RA4/T0CKI/SEG14

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA5/AN4/HLVDIN/SEG15

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

DS39629B-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

RH2/SEG45
RH3/SEG44

LCDBIAS2
LCDBIAS1

RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28

RG3/SEG27

/VPP/RG5

MCLR

RG4/SEG26

V

SS

VDD

RF7/SS/SEG25

RF6/AN11/SEG24

RF5/AN10/CV

RF2/AN7/C1OUT/SEG20

REF/SEG23

RF4/AN9/SEG22
RF3/AN8/SEG21

RH7/SEG43

RH6/SEG42

PIC18F6390/6490/8390/8490

/SEG31

(1)

LCDBIAS3

COM0

RE4/COM1

RH0/SEG47

RH1/SEG46

80

78

79

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32

RE5/COM2

77 76 75

RD0/SEG0

RE6/COM3

RE7/CCP2

PIC18F8390
PIC18F8490

DD

V

VSS

RD1/SEG1

RD2/SEG2

68 67 66 6572 71 70 6974 73

33 34

RD3/SEG3

RD4/SEG4

35 36

RD5/SEG5

RD6/SEG6

RD7/SEG7

64 63 62 61

37

38

RJ0/SEG32

RJ1/SEG33

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

39

RJ2/SEG34
RJ3/SEG35
RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
V

SS

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13
RJ7/SEG36
RJ6/SEG37

DD

AVSS

AV

RH5/SEG41

RH4/SEG40

RF0/AN5/SEG18

RF1/AN6/C2OUT/SEG19

REF-/SEG16

RA2/AN2/V

RA3/AN3/VREF+/SEG17

SS

V

RA1/AN1

RA0/AN0

(1)

VDD

RJ5/SEG38

RJ4/SEG39

RC6/TX1/CK1

RC7/RX1/DT1

RA4/T0CKI/SEG14

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

RA5/AN4/HLVDIN/SEG15

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 3

PIC18F6390/6490/8390/8490

Table of Contents

1.0 Device Overview ..........................................................................................................................................................................7

2.0 Oscillator Configurations ............................................................................................................................................................ 31

3.0 Power Managed Modes ............................... .. .... ..... .. .. .. .... .. .. .. ..... .. .... .. .. .. .. .. ....... .. .. .. .. .. .... ..... .................................................... 41

4.0 Reset .......................................................................................................................................................................................... 51

5.0 Memory Organization.................................................................................................................................................................65

6.0 Flash Progr a m Mem o ry............. ................. ................. ................................................ ...............................................................87

7.0 8 x 8 Hardware Multiplier...................................................................... ...................................................................................... 91

8.0 Interrupts .................................................................................................................................................................................... 93

9.0 I/O Ports................................ ................................................................................................................................................... 109

10.0 Timer0 Module ......................................................................................................................................................................... 131

11.0 Timer1 Module ......................................................................................................................................................................... 135

12.0 Timer2 Module ......................................................................................................................................................................... 141

13.0 Timer3 Module ......................................................................................................................................................................... 143

14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 147

15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157

16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 197

17.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUS ART ) ........................................................... 217

18.0 10-Bit Analog-to-Digital Converter (A/D) Module .....................................................................................................................231

19.0 Comparator Module.......................................................................... .... .. .... .. ......... .... .. .... ......................................................... 241

20.0 Comparator Voltage Reference Module................................................................................................................................... 247

21.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................251

22.0 Liquid Crystal Display (LCD) Driver Module.............................................................................................................................257

23.0 Special Features of the CPU.............. ................ ................. ................. ................. ............... .................................................... 281

24.0 Instruction Set Summary.......................................................................................................................................................... 295

25.0 Development Support............................................................................................................................................................... 345

26.0 Electrical Characteristics.......................................................................................................................................................... 351

27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 387

28.0 Packaging Informa tio n..... ................. ................ ................. ................. ...................................................................................... 389

Appendix A: Revision History............................................................................................................................................................. 393

Appendix B: Device Differences......................................................................................................................................................... 393

Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 394

Appendix D: Migration from Baseline to Enhanced Devices..............................................................................................................394

Appendix E: Migration from Mid-Range to Enhanced Devices ..........................................................................................................395

Appendix F: Migration from High-End to Enhanced Devices.............................................................................................................395

Index .................................................................................................................................................................................................. 397

On-Line Support.................................................................... .. .... .... .. ......... .. .... .... .. ......... .. .................................................................407

Systems Information and Upgrade Hot Line......................................................................................................................................407

Reader Response.............................................................................................................................................................................. 408

PIC18F6390/6490/8390/8490 Product Identification System ............................................................................................................ 409

DS39629B-page 4 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

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 2004 Microchip Technology Inc. Preliminary DS39629B-page 5

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 6 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F6390 • PIC18F8390

• PIC18F6490 • PIC18F8490

This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price. In addition to
these features, the PIC18F6390/6490/8390/8490
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F6390/6490/8390/8490
family incorporate a range of features that can
significantly reduce power consumption during
operation. Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled, bu t the peripheral s still
active. In these st ates, powe r consumpt ion can be
reduced even further – t o as litt le as 4% of nor mal
operation requirements.

• On-the-Fly Mode Switching: The power
managed modes a re invo ked b y user code durin g
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.

• Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer have been reduced by up to
80%, with typical values of 1.1 µA and 2.1 µA,
respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F6390/6490/8390/8490
family offer nine different oscillator options, allowing
users a wide range o f choices i n develo ping applica tion
hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• Two External RC Oscillator modes, with the same

pin options as the External Clock modes.

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31kHz, stable over
temperature and V
user selectable cl oc k frequ enc ie s betw ee n
125 kHz to 4 MHz for a total of eight clock
frequencies. This option frees the two oscillator
pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and
Internal Oscillator modes, which allows clock
speeds of up to 40MHz. Used with the internal
oscillator, the PLL gives users a complete
selection of clock speeds from 31 kHz to 32 MHz
– all without using an external crystal or clock
circuit.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller i s
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset or wake-up from Sleep
mode until the primary clock source is available.

DD), as well as a range of six

 2004 Microchip Technology Inc. Preliminary DS39629B-page 7

PIC18F6390/6490/8390/8490

1.2 O ther Special Features

• Memory Endurance: The Flas h cells for prog ram
memory are rated to last for approximately a
thousand erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 100 years.

• Extended Instruction Set: The
PIC18F6390/6490/8390/8490 family introduces
an optional extension to th e PIC18 instr uction set,
which adds 8 new instructions and an Indexed
Addressing mode. This extension, enabled as a
device configuration option, has been specifically
designed to optimize re-entrant application code
originally developed in high-level languages such
as C.

• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detec tion an d a 16-bit Baud
Rate Generator for improved resolu tion. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world, without
using an external crystal (or its accompanying
power requirement).

• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated withou t wai ting for a sampling period and
thus, reduces code overhead.

• Extended Watchdog Timer (WDT): This
enhanced version in corpora tes a 1 6-bit pre scale r,
allowing a time-out range from 4 ms to over
10 minutes that is s tabl e acros s opera ting vo lta ge
and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F 6390/6490 /8390/8490 famil y are
available in 64-pin (PIC18F6X90) and 80-pin
(PIC18F8X90) packages. Block diagrams for the two
groups are sho wn in Figure 1-1 and Figure 1-2, respec­tively.

The devices are differentiated from each other in three
ways:

1. I/O Ports: 7 bidirectional ports on 64-pin

devices; 9 bidirectional ports on 80-pin devices.

2. LCD Pixels: 128 (32 SEGs x 4 COMs) pixels can

be driven by 64-pin devices; 192 (48 SEGs x
4 COMs) pixels can be driven by 80-pin devices.

3. Flash Program Memory: 8 Kbytes for

PIC18FX390 devices; 16 Kbytes for PIC18FX490.

All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Like all Microchip PIC18 devices, members of the
PIC18F6390/6490/8390/8490 family are available as
both standard and low-voltage devices. Standard
devices with Flash memory, designated with an “F” in
the part number (such a s PIC18F63 90), acc ommoda te
an operating V
parts, designated by “LF” (such as PIC18LF6490),
function over an extended VDD range of 2.0V to 5.5V.

DD range of 4.2V to 5.5V. Low-voltage

DS39629B-page 8 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-1: DEVICE FEATURES

Features PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 8K 16K 8K 16K
Program Memory (Instruction s) 4096 8192 4096 8192
Data Memory (Bytes) 768 768 768 768
Interrupt Sources 22 22 22 22
I/O Ports Ports A, B, C, D, E,

F, G

Number of pixels the LCD Driver
can drive

Timers 4444
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications MSSP, AUSART

10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels
Resets (and Delays) POR, BOR, RESET

Programmable Low-Voltage Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions;

Packages 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP

128 (32 SEGs x 4

COMs)

Enhanced USART

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G

128 (32 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

192 (48 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

192 (48 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

 2004 Microchip Technology Inc. Preliminary DS39629B-page 9

PIC18F6390/6490/8390/8490

FIGURE 1-1: PIC18F6X90 (64-PIN) BLOCK DIAGRAM

Table Point e r <2 1 >

inc/dec logic

21

20

Address Latch

Program Memory

(48/64Kbytes)

Data Latch

8

Instruction Bus <16>

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

Table Latch

IR

Data Bus<8>

8

PCH PCL

8

Data Latch

Data Memory
(3.9 Kbytes)

Address Latch

Data Address<12>

4

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Address

12

12

Access

PORTA

PORTB

4

12

PORTC

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/SEG16
RA3/AN3/VREF+/SEG17
RA4/T0CKI/SEG14
RA5/AN4/HLVDIN/SEG15
OSC2/CLKO

RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1

(3)

/RA6

/SEG13

/SEG12

(1)

BOR

HLVD

Comparators

ADC

10-bit

CCP1

Instruction

Decode and

Control

MSSP

Timer2Timer1 Timer3Timer0

EUSART1

3

BITOP

8

PRODLPRODH

8 x 8 Multiply

W

8

8

ALU<8>

8

PORTD

RD7/SEG7:RD0/SEG0

8

Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RE7 when CCP2MX is not set.

2: RG5 is only available when MCLR
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations ” for additional information.

functionality is disabled.

DS39629B-page 10 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

FIGURE 1-2: PIC18F8X90 (80-PIN) BLOCK DIAGRAM

Data Latch

Data Memory

(3.9 Kbytes)

Address Latch

12

Data Address<12>

Instruction

Decode and

Control

BSR

FSR0
FSR1
FSR2

inc/dec

logic

Access

 2004 Microchip Technology Inc. Preliminary DS39629B-page 11

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

MCLR/VPP/RG5

MCLR
VPP

RG5

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

39

40

7

I

P

I

I

I

CMOS

I/O

O
O

I/O

Master Clear (input) or programming voltage (input).

ST

ST

ST

TTL

—
—

TTL

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Osc ill ato r mode .
In RC mode, OSC2 pin outputs CLKO, whi ch has
1/4 the frequency of OSC1 and denotes t he
instruction cycle rate.
General purpose I/O pin.

DD)

DS39629B-page 12 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V
SEG16

RA3/AN3/V

RA3
AN3
V
SEG17

RA4/T0CKI/SEG14

RA4
T0CKI
SEG14

RA5/AN4/HLVDIN/SEG15

RA5
AN4
HLVDIN
SEG15

RA6 See the OSC2/CLKO/RA6 pin.

REF-/SEG16

REF-

REF+/SEG17

REF+

24

23

22

21

28

27

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

I/O

ST/OD

I

ST

O

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.

Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.

RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 13

DD)

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0

RB0
INT0

RB1/INT1/SEG8

RB1
INT1
SEG8

Pin Number

TQFP

48

47

Pin

Buffer

Type

Type

I/OITTL

I/O

TTL

I

O

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull- ups on all inputs.

Digital I/O.

ST

ST

External interrupt 0.

Digital I/O.
External interrupt 1.
SEG8 output for LCD.

RB2/INT2/SEG9

RB2
INT2
SEG9

RB3/INT3/SEG10

RB3
INT3
SEG10

RB4/KBI0/SEG11

RB4
KBI0
SEG11

RB5/KBI1

RB5
KBI1

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

46

45

44

43

42

37

I/O

TTL

I

ST

O

Analog

I/O

TTL

I

ST

O

Analog

I/O

TTL

I

TTL

O

Analog

I/OITTL

TTL

I/O

TTL

I

TTL

I/O

I/O
I/O

ST

TTL

I

TTL

ST

Digital I/O.
External interrupt 2.
SEG9 output for LCD.

Digital I/O.
External interrupt 3.
SEG10 output for LCD.

Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.

Digital I/O.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DD)

DS39629B-page 14 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/SEG13

RC2
CCP1
SEG13

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO/SEG12

RC5
SDO
SEG12

30

29

33

34

35

36

I/O

O

I

I/O

I

I/O

I/O
I/O

O

I/O
I/O
I/O

I/O

I

I/O

I/O

O
O

ST

—

ST

ST

CMOS

ST

ST
ST

Analog

ST
ST
ST

ST
ST
ST

ST

—

Analog

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture2 input/Compare2 output/PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
SEG13 output for LCD.

Digital I/O.
Synchronous serial clock input/output for SPI™ mode.
Synchron ous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.
SEG12 output for LCD.

2

C™ mode.

RC6/TX1/CK1

RC6
TX1
CK1

RC7/RX1/DT1

RC7
RX1
DT1

31

32

I/O

O

I/O

I/O

I

I/O

ST

—

ST

ST
ST
ST

Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).

Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).

 2004 Microchip Technology Inc. Preliminary DS39629B-page 15

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0

RD0
SEG0

RD1/SEG1

RD1
SEG1

RD2/SEG2

RD2
SEG2

RD3/SEG3

RD3
SEG3

RD4/SEG4

RD4
SEG4

RD5/SEG5

RD5
SEG5

RD6/SEG6

RD6
SEG6

RD7/SEG7

RD7
SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

58

55

54

53

52

51

50

49

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

Digital I/O.
SEG0 output for LCD.

Digital I/O.
SEG1 output for LCD.

Digital I/O.
SEG2 output for LCD.

Digital I/O.
SEG3 output for LCD.

Digital I/O.
SEG4 output for LCD.

Digital I/O.
SEG5 output for LCD.

Digital I/O.
SEG6 output for LCD.

Digital I/O.
SEG7 output for LCD.

DD)

DS39629B-page 16 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

LCDBIAS1

LCDBIAS1

LCDBIAS2

LCDBIAS2

LCDBIAS3

LCDBIAS3

COM0

COM0

RE4/COM1

RE4
COM1

RE5/COM2

RE5
COM2

RE6/COM3

RE6
COM3

RE7/CCP2/SEG31

RE7

(2)

CCP2
SEG31

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

64

63

62

61

60

59

2

I Analog BIAS1 input for LCD.

1

I Analog BIAS2 input for LCD.

I Analog BIAS3 input for LCD.

O Analog COM0 out put for LC D.

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O
I/O

ST
ST

O

Analog

Digital I/O.
COM1 output for LCD.

Digital I/O.
COM2 output for LCD.

Digital I/O.
COM3 output for LCD.

Digital I/O.
Capture 2 input/Compare 2 output/PWM 2 output.
SEG31 output for LCD.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 17

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5/SEG18

RF0
AN5
SEG18

RF1/AN6/C2OUT/SEG19

RF1
AN6
C2OUT
SEG19

RF2/AN7/C1OUT/SEG20

RF2
AN7
C1OUT
SEG20

RF3/AN8/SEG21

RF3
AN8
SEG21

RF4/AN9/SEG22

RF4
AN9
SEG22

RF5/AN10/CV

RF5
AN10

REF

CV
SEG23

REF/SEG23

18

17

16

15

14

13

I/O

O

I/O

O
O

I/O

O
O

I/O

O

I/O

O

I/O

O
O

I

I

I

I

I

I

ST
Analog
Analog

ST
Analog

—

Analog

ST
Analog

—

Analog

ST
Analog
Analog

ST
Analog
Analog

ST
Analog
Analog
Analog

Digital I/O.
Analog input 5.
SEG18 output for LCD.

Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.

Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.

Digital I/O.
Analog input 8.
SEG21 output for LCD.

Digital I/O.
Analog input 9.
SEG22 output for LCD.

Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.

RF6/AN11/SEG24

RF6
AN11
SEG24

RF7/SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

DS39629B-page 18 Preliminary  2004 Microchip Technology Inc.

/SEG25
RF7
SS
SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

12

11

I/O

O

I/O

O

I

I

ST
Analog
Analog

ST

TTL

Analog

Digital I/O.
Analog input 11.
SEG24 output for LCD.

Digital I/O.
SPI™ slave select input.
SEG25 output for LCD.

DD)

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/SEG30

RG0
SEG30

RG1/TX2/CK2/SEG29

RG1
TX2
CK2
SEG29

RG2/RX2/DT2/SEG28

RG2
RX2
DT2
SEG28

RG3/SEG27

RG3
SEG27

RG4/SEG26

RG4
SEG26

RG5 See MCLR
VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.

SS 20 P — Ground reference for analog modules.

AV
AVDD 19 P — Positive supply for analog modules.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

3

I/OOST

Analog

4

I/O
I/O

5

I/O
I/O

6

I/OOST

8

I/OOST

ST

O
O

O

I

—

ST

Analog

ST
ST
ST

Analog

Analog

Analog

Digital I/O.
SEG30 output for LCD.

Digital I/O.
AUSART2 asynchronous transmit.
AUSART2 synchronous clock (see related RX2/DT2).
SEG29 output for LCD.

Digital I/O.
AUSART2 asynchronous receive.
AUSART2 synchronous data (see related TX2/CK2).
SEG28 output for LCD.

Digital I/O.
SEG27 output for LCD.

Digital I/O.
SEG26 output for LCD.

/VPP/RG5 pin.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 19

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

/VPP/RG5

MCLR

MCLR
VPP

RG5

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2
CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

49

50

9

I

P

I

I

I

CMOS

I/O

O
O

I/O

Master Clear (input) or programming voltage (input).

ST

ST

ST

TTL

—
—

TTL

Master Clear (Reset) input. This pin is an activ e-lo w
Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.

DD)

DS39629B-page 20 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V
SEG16

RA3/AN3/V

RA3
AN3
V
SEG17

RA4/T0CKI/SEG14

RA4
T0CKI
SEG14

RA5/AN4/HLVDIN/SEG15

RA5
AN4
HLVDIN
SEG15

RA6 See the OSC2/CLKO/RA6 pin.

REF-/SEG16

REF-

REF+/SEG17

REF+

30

29

28

27

34

33

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

I/O

ST/OD

I

ST

O

Analog

I/O

TTL

I

Analog

I

Analog

O

Analog

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.

Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.

Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.

RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 21

DD)

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0

RB0
INT0

RB1/INT1/SEG8

RB1
INT1
SEG8

Pin Number

TQFP

58

57

Pin

Buffer

Type

Type

I/OITTL

I/O

I

O

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.

ST

TTL

ST

External interrupt 0.

Digital I/O.
External interrupt 1.
SEG8 output for LCD.

RB2/INT2/SEG9

RB2
INT2
SEG9

RB3/INT3/SEG10

RB3
INT3
SEG10

RB4/KBI0/SEG11

RB4
KBI0
SEG11

RB5/KBI1

RB5
KBI1

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

56

55

54

53

52

47

I/O

TTL

I

ST

O

Analog

I/O

TTL

I

ST

O

Analog

I/O

TTL

I

TTL

O

Analog

I/OITTL

TTL

I/O

TTL

I

TTL

I/O

I/O
I/O

ST

TTL

I

TTL

ST

Digital I/O.
External interrupt 2.
SEG9 output for LCD.

Digital I/O.
External interrupt 3.
SEG10 output for LCD.

Digital I/O.
Interrupt-on-change pin.
SEG1 1 out put for LC D.

Digital I/O.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

DD)

DS39629B-page 22 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1)

CCP2

RC2/CCP1/SEG13

RC2
CCP1
SEG13

RC3/SCK/SCL

RC3
SCK
SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO/SEG12

RC5
SDO
SEG12

36

35

43

44

45

46

I/O

O

I/O
I/O

I/O
I/O

O

I/O
I/O
I/O

I/O
I/O

I/O

O
O

I

I

I

ST

—

ST

ST

CMOS

ST

ST
ST

Analog

ST
ST
ST

ST
ST
ST

ST

—

Analog

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 extern al clock inpu t.

Digital I/O.
Timer1 oscillator input.
Capture2 input/Compare2 output/PWM2 output.

Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
SEG13 output for LCD.

Digital I/O.
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I

Digital I/O.
SPI data in.

2

C data I/O.

I

Digital I/O.
SPI data out.
SEG12 output for LCD.

2

C™ mode.

RC6/TX1/CK1

RC6
TX1
CK1

RC7/RX1/DT1

RC7
RX1
DT1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

37

38

I/O

O

I/O

I/O
I/O

ST

—

ST

ST

I

ST
ST

Digital I/O.
EUSART1 asynchronou s trans m it.
EUSART1 synchronous clock (see related RX1/DT1).

Digital I/O.
EUSART1 asynchronou s rece iv e.
EUSART1 synchronous data (see related TX1/CK1).

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 23

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0

RD0
SEG0

RD1/SEG1

RD1
SEG1

RD2/SEG2

RD2
SEG2

RD3/SEG3

RD3
SEG3

RD4/SEG4

RD4
SEG4

RD5/SEG5

RD5
SEG5

RD6/SEG6

RD6
SEG6

RD7/SEG7

RD7
SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

72

69

68

67

66

65

64

63

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

Digital I/O.
SEG0 output for LCD.

Digital I/O.
SEG1 output for LCD.

Digital I/O.
SEG2 output for LCD.

Digital I/O.
SEG3 output for LCD.

Digital I/O.
SEG4 output for LCD.

Digital I/O.
SEG5 output for LCD.

Digital I/O.
SEG6 output for LCD.

Digital I/O.
SEG7 output for LCD.

DD)

DS39629B-page 24 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

LCDBIAS1

LCDBIAS1

LCDBIAS2

LCDBIAS2

LCDBIAS3

LCDBIAS3

COM0

COM0

RE4/COM1

RE4
COM1

RE5/COM2

RE5
COM2

RE6/COM3

RE6
COM3

RE7/CCP2/SEG31

RE7

(2)

CCP2
SEG31

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

4

3

78

77

76

75

74

73

I Analog BIAS1 input for LCD.

I Analog BIAS2 input for LCD.

I Analog BIAS3 input for LCD.

O Analog COM0 output for LCD.

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O
I/O

ST
ST

O

Analog

Digital I/O.
COM1 output for LCD.

Digital I/O.
COM2 output for LCD.

Digital I/O.
COM3 output for LCD.

Digital I/O.
Capture 2 input/Compare 2 output/P WM 2 output.
SEG31 output for LCD.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 25

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5/SEG18

RF0
AN5
SEG18

RF1/AN6/C2OUT/SEG19

RF1
AN6
C2OUT
SEG19

RF2/AN7/C1OUT/SEG20

RF2
AN7
C1OUT
SEG20

RF3/AN8/SEG21

RF3
AN8
SEG21

RF4/AN9/SEG22

RF4
AN9
SEG22

RF5/AN10/CV

RF5
AN10

REF

CV
SEG23

REF/SEG23

24

23

18

17

16

15

I/O

O

I/O

O
O

I/O

O
O

I/O

O

I/O

O

I/O

O
O

I

I

I

I

I

I

ST

Analog
Analog

ST

Analog

—

Analog

ST

Analog

—

Analog

ST

Analog
Analog

ST

Analog
Analog

ST

Analog
Analog
Analog

Digital I/O.
Analog input 5.
SEG18 output for LCD.

Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.

Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.

Digital I/O.
Analog input 8.
SEG21 output for LCD.

Digital I/O.
Analog input 9.
SEG22 output for LCD.

Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.

RF6/AN11/SEG24

RF6
AN11
SEG24

RF7/SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

DS39629B-page 26 Preliminary  2004 Microchip Technology Inc.

/SEG25
RF7
SS
SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

14

13

I/O

O

I/O

O

I

I

ST
Analog
Analog

ST

TTL

Analog

Digital I/O.
Analog input 11.
SEG24 output for LCD.

Digital I/O.
SPI™ slave select input.
SEG25 output for LCD.

DD)

PIC18F6390/6490/8390/8490

PORTG is a bidirectional I/O port.

RG0/SEG30

RG0
SEG30

5

I/OOST

Analog

Digital I/O.
SEG36.9( 7 gA32(T)1e17t5.999 53.96 4EG)5.9(3SnF46i5.)]TJ0 -1.2267 TD0.0012 0.004eA2E12 0.698D0.0087[(S.e04 Micro)-p1e1780.9p0 7003cD0.0016dM4e73Tc0.0008 Tw4(efP6Tf912A.)]TJ04g73 2.44 TD]TJ.00h0

 2004 Microchip Technology Inc. Preliminary DS39629B-page 27

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTH is a bidirectional I/O port.

RH0/SEG47

RH0
SEG47

RH1/SEG46

RH1
SEG46

RH2/SEG45

RH2
SEG45

RH3/SEG44

RH3
SEG44

RH4/SEG40

RH4
SEG40

RH5/SEG41

RH5
SEG41

RH6/SEG42

RH6
SEG42

RH7/SEG43

RH7
SEG43

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

79

80

22

21

20

19

I/O

OSTAnalog

I/O

OSTAnalog

1

I/O

OSTAnalog

2

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

I/O

OSTAnalog

Digital I/O.
SEG47 output for LCD.

Digital I/O.
SEG46 output for LCD.

Digital I/O.
SEG45 output for LCD.

Digital I/O.
SEG44 output for LCD.

Digital I/O.
SEG40 output for LCD.

Digital I/O.
SEG41 output for LCD.

Digital I/O.
SEG42 output for LCD.

Digital I/O.
SEG43 output for LCD.

DD)

DS39629B-page 28 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Pin

Type

Buffer

Type

Description

PORTJ is a bidirectional I/O port.

RJ0/SEG32

RJ0
SEG32

RJ1/SEG33

RJ1
SEG33

RJ2/SEG34

RJ2
SEG34

RJ3/SEG35

RJ3
SEG35

RJ4/SEG39

RJ4
SEG39

RJ5/SEG38

RJ5
SEG38

RJ6/SEG37

RJ6
SEG37

RJ7/SEG36

RJ7
SEG36

V

SS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
DD 12, 32, 48, 71 P — Positive supply for logic and I/O pins.

V
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

62

61

60

59

39

40

41

42

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

Digital I/O.
SEG32 output for LCD.

Digital I/O.
SEG33 output for LCD.

Digital I/O.
SEG34 output for LCD.

Digital I/O.
SEG35 output for LCD.

Digital I/O.
SEG39 output for LCD.

Digital I/O
SEG38 output for LCD.

Digital I/O.
SEG37 output for LCD.

Digital I/O.
SEG36 output for LCD.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 29

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 30 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

PIC18F6390/6490/839 0/8490 devices can be operated
in ten different o scillato r mo des. The user ca n progra m
the configuration bi ts, FOSC3:FOSC 0, in Configuratio n
Register 1H to select one of these ten modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

5. RC Ext ernal Resistor/Capacitor with

F

OSC/4 output on RA6

6. RCIO External Resistor/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with F

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

OSC/4 output

OSC/4 output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See T able2-1 and T able 2-2 for initial values of

2: A series resistor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXXXX

S) may be required for AT

To

Internal
Logic

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s
specifications.

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

56 pF
47 pF
33 pF

27 pF
22 pF

56 pF
47 pF
33 pF

27 pF

22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators

listed below for basic start-up and operation. These
values are not optimized.

Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following Table 2-2 for additional

information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

 2004 Microchip Technology Inc. Preliminary DS39629B-page 31

PIC18F6390/6490/8390/8490

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc T y pe

Crystal

Freq

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed

below for basic start-up and operation . These values

are not optimized.

Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following this table for additional

information.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher cap acita nce increase s the stabi lity

of oscillator, but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs m ay be requir ed to avoid overdrivi ng

crystals with low driv e lev e l spe ci fic ati on.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

T ypical Cap acitor V alues

Tested:

C1 C2

DD, or when

An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 External Clock Input

The EC and ECIO Oscillator mode s require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK

INPUT OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

F

OSC/4

The ECIO Oscillator mo de func tio ns lik e t he EC mod e,
except that the OSC2 pin becomes an additional gen­eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

Clock from
Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

INPUT OPERATION
(ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

DS39629B-page 32 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

2.4 RC Oscillat or

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:

• Supply voltage

• Values of the external resistor (R
capacitor (C

EXT)

• Operating temperature

Given the same device, operating voltage and
temperature and component values, there will also be
unit-to-unit frequency variations. These are due to
factors such as:

• Normal manufacturing variation

• Difference in lead frame capacitance between
package types (especially for low C

• Variations within the tolerance of limits of REXT

EXT

and C

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-5 shows how the R/C combination is
connected.

EXT) and

EXT values)

2.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crys tals, or users who require higher
clock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode make s use of the HS mode osc illator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.

The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 configu rati on bi ts are programmed
for HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM

(HS MODE)

HS Oscillator Enable

PLL Enable

(from Configuration Register 1H)

FIGURE 2-5: RC OSCILLATOR MODE

VDD

REXT

OSC1

CEXT
VSS

F

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

OSC/4

OSC2/CLKO

EXT > 20 pF

C

Internal

Clock

PIC18FXXXX

The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

VDD

REXT

CEXT

VSS

RA6

OSC1

I/O (OSC2)

Internal

Clock

PIC18FXXXX

OSC2

OSC1

HS Mode

Crystal

Oscillator

IN

F
FOUT

÷4

Phase

Comparator

Loop
Filter

VCO

SYSCLK

MUX

2.5.2 PLL AND INTOSC

The PLL is also ava ilabl e to th e inte rnal os cill ator bl ock
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock
output of up to 32MHz. The operation of INTOSC with
the PLL is describ ed in Section 2.6.4 “PLL in INTOSC
Modes”.

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

C

EXT > 20 pF

 2004 Microchip Technology Inc. Preliminary DS39629B-page 33

PIC18F6390/6490/8390/8490

2.6 Internal Oscillator Block

The PIC18F6390/6490/8390/8490 devices include an
internal oscillator block, which generates two different
clock signals; either can be used as the micro­controller’s clock source. This may eliminate the need
for external oscillator circuits on the OSC1 and/or
OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock fre quency from 12 5 kHz
to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also ena bled autom atically when an y of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• T wo-Spe ed Start-up

• LCD with INTRC as its clock source
These features are discussed in greater detail in

Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register2-2).

2.6.1 INTIO MODES

Using the internal oscillator as the clock source elimi­nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.

• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.

2.6.2 INTOSC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0MHz.

The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user’s applica­tion. This is do ne by writi ng to the OSC TUNE regi ster
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

OSC/4,

When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code ex ecution c ontinues during th is shi ft.
There is no indication that the shift has occurred.

The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.

The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.

2.6.4 PLL IN INTOSC MODES

The 4x frequency multiplier can be used with the inter­nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32MHz.

Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.

The PLL is availa ble when the device is configured to use
the internal oscillator block as its primary clock source
(FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL
will only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If
both of these condit ions a re not m et, the PLL is disabl ed.

The PLLEN control bit is only functional in those inter­nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.

2.6.5 INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSTUNE register . Thi s has no effect on
the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are
discussed in Section 2.6.5.1 “Compensating with

the AUSART”, Section 2.6.5.2 “Compensating with
the Timers” and Section2.6.5.3 “Compensating
with the Timers”, but other techniques may be used.

DS39629B-page 34 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

2.6.5.1 Compensating with the AUSART

An adjustment may be required when the AUSART
begins to generate frami ng errors or rec eive s dat a with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSTUNE to
reduce the clock frequency. On the other hand, errors
in data may sugge st that the clock speed is too low. To
compensate, incre ment OSTUNE to increase the clock
frequency.

2.6.5.2 Compensating with the Timers

This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillat or.

Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator
block is r unni ng to o fas t. To adjust for thi s, d ecrem ent
the OSCTUNE register.

2.6.5.3 Compensating with the Timers

A CCP module can use free running Timer1 (or
Timer3), cl oc ked by the internal oscillator bl ock and an
external event with a known period (i.e., AC power
frequency). The time of the first event is capt ured in th e
CCPRxH:CCPRxL registe rs and is recor ded. When the
second event causes a capture, the time of the first
event is subtracted from the time of the second event.
Since the period of the external event is known, the
time difference between events can be calculated.

If the measured time is much greater than the
calculated time, then the internal oscillator block is
running too fast. To compensate, decrement the
OSTUNE register. If the measured time is much less
than the calculated time, then the internal oscillator
block is running too slow. To compensate, increment
the OSTUNE register.

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0

INTSRC PLLEN

bit 7 bit 0

(1)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

— TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable

and read as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.

bit 5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

• •

00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111

• •

• •
10000 = Minimum frequency

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 35

PIC18F6390/6490/8390/8490

2.7 Clock Sources and

Oscillator Switching

Like previous PIC18 devices, the
PIC18F6390/6490/839 0/8490 f amily inclu des a featu re
that allows the devic e clock so urce to be swit ched fro m
the main oscillator to an alternate low-frequency clock
source. PIC18F6390/6490/8390/8490 devices offer
two alternate clock sources. When an alternate clock
source is enabled, the vario us power m anaged oper at­ing modes are available.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the Ex ternal Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.

The s econdary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.

PIC18F6390/6490/839 0/84 90 d ev ic es o f fe r the Timer1
oscillator as a secon dary oscilla tor . This osc illator , in all
power managed modes , is often the time base for func­tions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP mode oscillator circuit, loading
capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in
Section 11.3 “Timer1 Oscillator”.

In addition to being a prim ary clock source, the internal
oscillator block is available as a power managed
mode clock source. T he IN TR C s ource is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

The clock sour ces fo r th e PI C18F 6390 /6490/ 839 0/84 90
devices are shown in Figure 2-8. See Section 23.0
“Special Features of the CPU” for configuration
register det a ils.

FIGURE 2-8: PIC18F6390/6490/8390/8490 CLOCK DIAGRAM

PIC18F6X90/8X90

8 MHz
4 MHz
2 MHz
1 MHz

500 kHz

Postscaler

250 kHz
125 kHz

1

31 kHz

0

4 x PLL

OSCCON<6:4>

111

110

101

100

MUX

011

010

001

000

OSCTUNE<7>

HSPLL, INTOSC/PLL

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

8 MHz

Source

INTRC

Source

31 kHz (INTRC)

OSCTUNE<6>

8 MHz

(INTOSC)

LP, XT, HS, RC, EC

T1OSC

Internal Oscillator

FOSC3:FOSC0

Peripherals

MUX

CPU

Clock

Control

Clock Source Option
for other Modules

WDT, PWRT, FSCM
and Two-Speed Start-up

IDLEN

OSCCON<1:0>

DS39629B-page 36 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the pri­mary clock (defined by the FOSC: FOSC0 confi guration
bits), the secondary clock (Timer1 oscillator) and the
internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an
immediate change on the internal oscillator’s output.

When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which inter­nal oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC sel ects INTRC
(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a ve ry low clock speed. R egardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bit s ind ic ate wh ich clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized a nd is prov iding the device c lock in RC C lock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock, or the internal oscillator block has just started
and is not yet stable.

The IDLEN bit dete rmines if th e dev ice go es in to Slee p
mode or one of the Idle modes when the SLEEP
instruction is executed.

The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0

“Power Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis­ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before
executing the SLEEP ins truction, or a very
long delay may occur while the Timer1
oscillator starts.

2.7.2 OSCILLATOR TRANSITIONS

PIC18F6390/6490/8390/8490 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short p ause in the device cl ock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 37

PIC18F6390/6490/8390/8490

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep m ode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator start-up timer time-out has expired; primary oscillator is running
0 = Oscillator start-up timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block
01 = Timer1 oscillator
00 = Primary oscillator

(3)

(1)

(1)

(2)

)

R-0 R/W-0 R/W-0

Note 1: Depends on state of the IESO configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see

Section 2.6.3 “OSCTUNE Register”.

3: Default output frequency of INTOSC on Reset.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39629B-page 38 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

2.8 Effects of Power Managed Modes on the Various Clock Sources

When PRI_IDLE mode is selected, the designated pri­mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the o scillat or) will sto p oscillat ing.

In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.

In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support var­ious special features, regardless of the power managed
mode (see Section 23.2 “Watchdog Timer (WDT)”
through Section 23.4 “Fail-Safe Clock Monitor” for
more information on WDT, Fail-Safe Clock Monitor and
Two-Speed S tart-up). The INTOSC output at 8MHz may
be used directly to clock the device, or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).

Enabling any on-chip feature that will operate during
Sleep will increas e the current cons umed during S leep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
INTn pins and others). Peri pheral s that m ay add si gnif­icant current consumption are listed in Section 26.2

“DC Characteristics: Power-Down and Supply
Current”.

2.9 Power-up Delays

Power-up delays are controlled by two timers, s o that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum­stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-10). It is enabled by clearing (= 0) the
PWRTEN

The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the
device is kept in Res et for an add iti onal 2ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequ enc y.

There is a delay of interval T
Table 26-10) following POR while the controller
becomes ready to execute instruc tions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when an y of the EC, RC or INTIO
modes are used as the primary clock source.

configuration bit.

CSD (parameter 38,

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent

voltage level

Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 39

Feedback inverter disabled at quiescent
voltage level

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 40 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

3.0 POWER MANAGED MODES

PIC18F6390/6490/8390/8490 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective p ower conservation i n applications
where resources may be limited (i.e., battery-powered
devices).

There are three categories of power managed modes:

• Sleep mode

• Idle modes

• Run modes

These categories define which portions of the device
are clocked and some times , what sp eed. The R un and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.

The power managed modes include several power
saving features. One of these is the clock switching
feature, offered in other PIC18 devices, allowing the
controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PICmicro
clocks are stopped.

®

devices, where all device

3.1.1 CLOCK SOURCES

The SCS1:SCS0 bits allow the sele ction of one o f three
clock sources for power managed modes. They are:

• the primary clock, as defined by the
FOSC3:FOSC0 configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER MANAGED

MODES

Entering Power Managed Ru n mode, or s witching from
one power managed mode to another, begins by
loading the OSCCON register. The SCS1:SCS0 bits
select the clock source and determine which Run or
Idle mode is being used. Changing th ese bits causes
an immediate switch to the new clock source,

3.1 Selecting Power Managed Modes

Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit con trols CPU clocking , while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 41

PIC18F6390/6490/8390/8490

3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS

The length of the transition between clock sources is
the sum of two cycles o f the old clo ck so urce an d three
to four cycl es of the new clock so urce. This formula
assumes that the new clock source is stable.

Three bits indicate the current clock source and its
status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a
given power managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output provides
a stable 8 MHz clock source to a divider that actually
drives the device clock. When the T1RUN bit is set, the
Timer1 oscillator provides the clock. If none of these
bits are set, then either the INTRC clock source clocks
the device, or the INTOSC source is not yet stable.

If the internal oscillator block is configured as the
primary clock source by the FOSC3:FOSC0
configuration bits, then both the OSTS and IOFS bits
may be set when in PRI_RUN or PRI_IDLE modes.
This indicates that the primary clock (INTOSC output)
is generating a stable 8 MHz output. Entering another
RC Power Managed mode at the same frequency
would clear the OSTS bit.

Note 1: Caution s hould be used when modifying a

single IRCF bit. I f V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.

DD is less than 3V, it is

DD.

3.1.4 MULTIPLE SLEEP COMMANDS

The power managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power managed mode specified by the new
setting.

3.2 Run Modes

In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset un less Two-Speed S t art-u p
is enabled (see Section 23.3 “Two-Speed Start-up”
for details). In this m ode, the OSTS bi t is set. Th e IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.7.1 “Oscillator
Control Register”).

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the T imer1 os cillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.

SEC_RUN mode is en tered by sett ing th e SCS1:SCS 0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RU N mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.

On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clo ck bec omes r eady, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock
provides the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.

DS39629B-page 42 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q4Q3Q2

Q1

Q1

Q4Q3Q2 Q1 Q3Q2

T1OSI
OSC1

CPU
Clock

Peripheral
Clock

Program
Counter

123 n-1n

Clock Transition

PC + 2PC

PC + 4

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

T1OSI

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

(1)

TOST

PC

Q3 Q4 Q1

Q2 Q2 Q3

(1)

TPLL

12

n-1 n

Clock

PC + 2

Q1

Q2

PC + 4

SCS1:SCS0 bits changed

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

OSTS bit set

 2004 Microchip Technology Inc. Preliminary DS39629B-page 43

PIC18F6390/6490/8390/8490

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications whic h are not h ighly timin g sensiti ve, or do
not require high-speed clocks at all times.

If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there ar e no distinguishable
differences between PRI_RUN and RC_RUN modes
during execution. However, a clock switch delay will occur
during entry to and exit from RC_RUN mode. Therefore,
if the primary clock source is the internal oscillator block,
the use of RC_RUN mode is not recommended.

This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recom mended that the SCS0
bit also be cleared; this is to maintain software
compatibility with future devices. When the clock
source is switched to the INTOSC multiplexer (see
Figure 3-3), the primary osc illato r is sh ut d own a nd th e
OSTS bit is cleared.The IRCF bits may be modified at
any time to immediately change the clock speed.

Note: Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V

DD/FOSC specifications are violated.

DD.

If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source provides the device
clocks.

If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T

IOBST.

If the IRCF bits were prev io us ly at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.

On transitions from RC_RUN mode to PRI_RUN, the
device continues to be clocked from the INTOSC
multiplexer whil e the prim ary clock is st arted. W hen the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock provides the device
clock. The IDLEN and SCS bits are not af fe cte d by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

Q4Q3Q2

Q1

123 n-1n

Clock Transition

PC + 2PC

Q4Q3Q2 Q1 Q3Q2

INTRC
OSC1

CPU
Clock

Peripheral
Clock

Program
Counter

Q1

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q3 Q4

Q1

Q1

INTOSC

Multiplexer

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

SCS1:SCS0 bits changed

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST

(1)

PC

Q2

Q3

TPLL

OSTS bit set

Q4

(1)

12 n-1n

Clock

Transition

PC + 2

Q2

Q1

PC + 4

PC + 4

Q2

Q3

DS39629B-page 44 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

3.3 Sleep Mode

The Power Managed Sleep mode in the
PIC18F6390/6490/8390/8490 devices is identical to
the Legacy Sleep mode offered in all other PICmicro
devices. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (see Figure 3-5). All clock source status bits
are cleared.

Entering the Sleep m ode from any other mo de does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.

When a wake ev ent occurs i n Sleep mo de (by int errupt,
Reset or WDT time-out), the device wil l not be clocke d
until the primary clock source becomes ready (see
Figure 3-6), or it will be clocked from the internal oscil­lator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabl ed (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock provides the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction
is executed, the peripherals will be clocked from the
clock source selected using the SCS1:SCS0 bits;
however , the CPU will not be clocked. The cloc k source
status bits are not affected. Setting IDLEN and execut­ing SLEEP provi des a quick method of swi tching from a
given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue
to operate. If the T imer1 oscill ator is enable d, it will also
continue to run.

Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wak e even t occur s, CPU
execution is delayed by an interval of T
(parameter 38, Table26-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT
time-out will resul t i n a WD T wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.

CSD

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q4Q3Q2

Q1Q1

OSC1

CPU

Clock

Peripheral

Clock

Sleep

Program

Counter

PC + 2PC

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Note 1: T

Q1 Q2 Q3 Q4 Q1 Q2

(1)

TOST

Wake Event

OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

(1)

TPLL

PC

OSTS bit set

Q3 Q4 Q1 Q2

PC + 2

Q3 Q4

Q1 Q2 Q3 Q4

PC + 6PC + 4

 2004 Microchip Technology Inc. Preliminary DS39629B-page 45

PIC18F6390/6490/8390/8490

3.4.1 PRI_IDLE MODE

This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resump tion of devic e operation with its more
accurate pri mary clock source, si nce the cl ock source
does not have to “warm up” or transition from another
oscillator.

When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allo w the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).

PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc­tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disab led, th e peri pherals c ontinu e
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 config uration bit s. The OSTS bit
remains set (see Figure3-7).

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO PRI_IDLE MODE

Q1

OSC1

CPU Clock

Q1

Q2

Q3

Q4

CSD is

Peripheral

Clock

Program

Counter

PC PC + 2

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

TCSD

PC

Wake Event

Q2

DS39629B-page 46 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set­ting the IDLEN bit and executi ng a SLEEP instru ction. If
the device is in anot her Run mode, se t IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscil lator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.

When a wake event occ urs, the pe ripherals co ntinue to
be clocked from the Timer1 oscillator. After an interval

CSD following the wake event, the CPU begins

of T
executing code being clocked by the Timer1 oscillator.
The IDLEN and SCS bits are not affected by the
wake-up; the Timer1 oscillator continues to run (see
Figure 3-8).

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mod e.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.

3.4.3 RC_IDLE MODE

In RC_IDLE mode, t he CPU is disabled but the p erip h­erals continue to b e c loc ke d fro m th e i ntern al osc il lat or
block using the INTOSC multiplexer. This mode allows
for controllable pow er cons ervation duri ng Idle p eriods.

From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in an other Run mode, first s et IDLEN, th en set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recomm ended that SC S0 also be cleare d;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is sw itched to the IN TOSC multip lexer , the
primary oscillator is shut down and the OSTS bit is
cleared.

If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set after the INTOSC output
becomes stable after an interval of T
(parameter 39, Table26-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled; the IOF S bit will r emain cl ear and t here wil l be
no indication of the current clock source.

When a wake event occ urs, the pe ripherals continue to
be clocked from the INTOSC multiplexer. After a delay

CSD following the wake event, the CPU begins

of T
executing code being clocked by the INTOSC multi­plexer . The IDLEN and SCS bit s are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.

IOBST

 2004 Microchip Technology Inc. Preliminary DS39629B-page 47

PIC18F6390/6490/8390/8490

3.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is
triggered b y an interrupt , a Reset or a WD T time-out.
This section discusses the triggers that cause exits
from power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Section 3.2 “Run Modes” through
Section 3.4 “Idle Modes”).

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the
device to exit from an Idle or Sleep mode to a Run
mode. To enable this functionality, an interrupt source
must be enabled by setting its enable bit in one of the
INTCON or PIE registers. Th e exit sequ ence is initiate d
when the corresponding interrupt flag bit is set.

On all exits from Idl e or Sleep mod es by inte rrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 8.0 “Interrupts”).

A fixed delay of in terval T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instructi on execution r esumes on th e first clock c ycle
following this delay.

3.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending
on which power managed mode the device is in when
the time-out occurs.

If the devic e is not exec uti ng co de (al l Id le mo des and
Sleep mode), the time-out w i ll re sul t in an ex it fro m th e
power managed mode (see Sec tion 3.2 “Run Modes”
and Section 3.3 “Sleep Mode”). If the device is
executing code (a ll R un mod es) , the time-o ut will resu lt
in a WDT Reset (se e Section 23.2 “Watchdog Timer
(WDT)”).

The WDT timer and postscaler are cleared by execut­ing a SLEEP or CLRWDT instruction, lo sing a currently
selected clock source (if the Fail-Safe Clock Monitor is
enabled) and modifying the IRCF bits in the OSCCON
register if the internal os cillator block is the device clock
source.

CSD, following the wake event,

3.5.3 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillat or block is
the new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.

Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source ha s cle are d. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready, or a power managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY

Certain exits from power managed modes do not
invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval

CSD, following the wake event, is still required when

T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.

DS39629B-page 48 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Exit Delay

Clock Ready Status

Bit (OSCCON)

Primary Device Clo ck

(PRI_IDLE mode)

T1OSC or INTRC

INTOSC

(1)

(3)

None

(Sleep mode)

LP, XT, HS

HSPLL

EC, RC, INTRC

INTOSC

(1)

(3)

LP, XT, HS TOST

HSPLL T

EC, RC, INTRC

INTOSC

(1)

(2)

LP, XT, HS TOST

HSPLL T

EC, RC, INTRC

INTOSC

(1)

(2)

LP, XT, HS TOST

HSPLL T

EC, RC, INTRC

INTOSC

(1)

(2)

(2)

T

CSD

(4)

TCSD

TCSD

(2)

(5)

(2)

rc

(5)

rc

(4)

(4)

OST + t

TIOBST

OST + t

None IOFS

(4)

TCSD

(2)

rc

(5)

(4)

OST + t

TIOBST

OSTS

OSTS

OSTS

OSTS

Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.

2: TCSD (parameter 38) is a required delay when wak in g from Sl eep and all Idle modes and run s co nc urren tly

with any other required delays (see Section 3.4 “Idle Modes”).

3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

OST is the Oscillator Start-up Timer (parameter 32). t

4: T

also designated as T

PLL.

is the PLL Lock-out Timer (parameter F12); it is

rc

5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

—

IOFS

—

IOFS

—

—

IOFS

 2004 Microchip Technology Inc. Preliminary DS39629B-page 49

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 50 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

4.0 RESET

The PIC18F6390/6490/8390/8490 devices differentiate
between various kinds of Reset:

a) Power-on Reset (POR)
b) MCLR
c) MCLR Reset during power managed modes
d) Watchdog Timer (WDT) Reset (during

e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset

This section discusses Resets generated by MCLR

Reset during normal operation

execution)

,

4.1 RCON Register

Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.

The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in

Section 8.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.

POR and BOR and covers the ope rati on o f the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are co v ere d i n Section 23.2 “Watchdog
Timer (WDT)”.

A simplified b lock di agram of the On -Chip Re set Ci rcuit
is shown in Figure 4-1.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

External Reset

MCLR

VDD

OSC1

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

( )_IDLE

Time-out

V

Detect

Brown-out

OST/PWRT

32 µs

(1)

INTRC

2: See Table4-2 for time-out situations.

MCLRE

Sleep

WDT

DD Rise

Reset

POR Pulse

OST

10-bit Ripple Counter

PWRT

11-bit Ripple Counter

BOREN

1024 Cycles

65.5 ms

S

Chip_Reset

R

Q

Enable PWRT

Enable OST

(2)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 51

PIC18F6390/6490/8390/8490

REGISTER 4-1: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1

IPEN SBOREN

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit

If BOREN1:BOREN0 =

1 = BOR is enabled
0 = BOR is disabled

If BOREN1:BOREN0 =
Bit is disabled and read as ‘0’.

Note 1: If SBOREN is enabled, its Reset state is ‘1’; other wise, it is ‘0’.

bit 5 Unimplemented: Read as ‘0’
bit 4 RI

bit 3 TO

bit 2 PD

bit 1 POR

bit 0 BOR

: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after

a Brown-out Reset occur s)

: Watchdog Time-out Flag bit

1 = Set by po wer-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction

: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

01:

00, 10 or 11:

U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

—RITO PD POR BOR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been

detected, so that subsequent Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming

that POR

DS39629B-page 52 Preliminary  2004 Microchip Technology Inc.

was set to ‘1’ by software immediately after POR).

PIC18F6390/6490/8390/8490

4.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 Extended MCU devices
have a noise filter in the MCLR
detects and ignores small pulses.

The MCLR
including the WDT.

In PIC18F6390/6490/8390/8490 devices, the MCLR
input can be disabl ed with the MCL RE configuratio n bit.
When MCLR
input. See Section 9.7 “PORTG, TRISG and LATG
Registers” for more information.

pin is not drive n low by any inter nal Reset s,

is disabled, the pin becomes a digital

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip

Reset path which

 2004 Microchip Technology Inc. Preliminary DS39629B-page 53

PIC18F6390/6490/8390/8490

4.4 Brown-out Reset (BOR)

PIC18F6390/6490/8390/8490 devices implement a
BOR circuit that provides the user with a number of
configuration and power saving options. The BOR is
controlled by the BORV1:BORV0 and
BOREN1:BOREN0 configuration bits. There are a total
of four BOR configurations, which are summarized in
Table 4-1.

The BOR threshold is set by t he BOR V1:BOR V0 bit s. If
BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of V
D005) for greater than T
the device. A Reset may or may not occur if V
below V
Brown-out Reset until V

If the Power-up T imer is enabl ed, it will be inv oked after
V
Reset for an additional time delay, T
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.

BOR and the Power-up Timer (PWRT) are
independently configured. Enabling the BOR Reset
does not automatically enable the PWRT.

BOR for less than TBOR. The chip will remain in

DD rises above VBOR; it then will keep the chip in

DD rises above VBOR, the Power-up

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.

DD below VBOR (parameter

BOR (parameter 35 ) will reset

DD falls

DD rises above VBOR.

PWRT

Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment withou t ha vi ng to reprogram the device to
change the BOR configuration. It also allows the user
to tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.

Note: Even whe n BOR is u nder softwar e control,

the BOR Reset voltage level is still set by
the BORV1:BORV0 configuration bits. It
cannot be changed in software.

4.4.2 DETECTING BOR

When BOR is enab led, the BO R bit always resets to ‘0’
on any BOR or P OR event. This makes it diff icult to
determine if a BOR event has occurre d jus t by rea ding
the state of BOR
simultaneously check the state of both POR
This assumes th at the POR
immediately after any POR event. IF BOR

is ‘1’, it can be reliably assum ed that a BOR event

POR
has occurred.

alone. A more reliable method is to

and BOR.

bit is reset to ‘1’ in softwa re

is ‘0’ while

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however , the BOR is au tom ati ca lly dis abl ed . When the
device returns to any other operating mode, BOR is
automatically re-enabled.

This mode allows for applications to recover from
brown-out situations while actively executing code,
when the device requires BOR protection the most. At
the same time, it save s additional po wer in Sleep mod e
by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Status of

BOREN1 BOREN0

00Unavailable BOR i s disabled; must be enabled by reprogramming the configuration

01Available BOR is enabled in software; operation controlled by SBOREN.
10Unavailable BOR is enabled in hardware and active during the Run and Idle modes,

11Unavailable BOR is enabled in hardware; must be disabled by reprogramming the

DS39629B-page 54 Preliminary  2004 Microchip Technology Inc.

SBOREN

(RCON<6>)

bits.

disabled during Sleep mode.

configuration bits.

BOR Operation

PIC18F6390/6490/8390/8490

4.5 Device Reset Timers

PIC18F6390/6490/8390/8490 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

4.5.1 POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of
PIC18F6390/6490/8390/8490 devices is an 11-bit
counter which uses the INTRC source as the clock
input. This yields an approximate time interval of
2048 x 32 µs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.

The power-up time delay depe nd s on the INTRC cl oc k
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.

The PWRT is enabled by clearing the PWRTEN
configuration bit.

4.5.2 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is ov er (par a me t er 3 3 ). T h is en su re s t ha t
the crystal oscillator or resonator has started and is
stabilized.

The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power managed modes.

4.5.3 PLL LOCK TIME-OUT

With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.

PLL) is typically 2 ms and follows

4.5.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).

2. Then, the OST is activated.

The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figure s 4-3 through 4-6 also apply
to devices operating in XT or LP m odes. F or devi ces i n
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.

Since the time-outs occur from the POR pulse, if MC LR
is kept low long enough, all time-outs will expire.
Bringing MCLR
(Figure 4-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.

high will begin execution immediately

TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

HSPLL 66 ms
HS, XT, LP 66 ms
EC, ECIO 66 ms
RC, RCIO 66 ms
INTIO1, INTIO2 66 ms

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 55

PWRTEN = 0 PWRTEN = 1

(1)

+ 1024 TOSC + 2 ms

Power-up

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(1)
(1)
(1)

(2)

and Brown-out

(2)

1024 TOSC + 2 ms

Exit from

Power Managed Mode

(2)

——
——
——

1024 TOSC + 2 ms

(2)

PIC18F6390/6490/8390/8490

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

PWRT TI ME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

NOT TIED TO VDD): CASE 1

TOST

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

DS39629B-page 56 Preliminary  2004 Microchip Technology Inc.

NOT TIED TO VDD): CASE 2

TOST

PIC18F6390/6490/8390/8490

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

5V

VDD

MCLR

INTERNAL POR

0V

PWRT

T

1V

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RES ET

TOST

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

PLL TIME-OUT

TOST

TPLL

INTERNAL RESET

Note: TOST = 1024 clock cycles.

T

PLL ≈ 2 ms max. First three stages of the PWRT timer.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 57

PIC18F6390/6490/8390/8490

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other

Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.

Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI
PD

, POR and BOR, are set or cleared differently in

, TO,

different Reset situations, as indicated in Table 4-3.
These bits are use d in softwar e to determine the nature
of the Reset.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition

Program

Counter

SBOREN RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u

Brown-out Reset 0000h u

Reset during Power

MCLR

0000h u

(2)
(2)
(2)

Managed Run modes
MCLR Reset during Power

0000h u

(2)

Managed Idle modes and Sleep
WDT Time-ou t during Full Power

0000h u

(2)

or Power Managed Run modes
MCLR during Full Power

0000h u

(2)

Execution
Stack Full Reset (STVREN = 1) 0000h u
Stack Underflow Reset

0000h u

(2)
(2)

(STVREN = 1)
Stack Underflow Error (not an

0000h u

(2)

actual Reset, STVREN = 0)
WDT Time-out during Power

PC + 2

(1)

(2)

u

Managed Idle or Sleep modes
Interrupt Exit from Power

PC + 2

(1)

(2)

u

Managed modes

Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Re set state is ‘0’.

RCON Register STKPTR Register

0uuuu u u

111u0 u u

u1uuu u u

u10uu u u

u0uuu u u

uuuuu u u

uuuuu 1 u

uuuuu u 1

uuuuu u 1

u00uu u u

uu0uu u u

DS39629B-page 58 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Resets

MCLR

Register

Applicable

Devices

TOSU 6X90 8X90 ---0 0000 ---0 0000 ---0 uuuu
TOSH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TOSL 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
STKPTR 6X90 8X90 uu-0 0000 00-0 0000 uu-u uuuu
PCLATU 6X90 8X90 ---0 0000 ---0 0000 ---u uuuu
PCLATH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PCL 6X90 8X90 0000 0000 0000 0000 PC + 2
TBLPTRU 6X90 8X90 --00 0000 --00 0000 --uu uuuu
TBLPTRH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 6 X90 8X90 0000 0000 0000 0000 uuuu uuuu
TABLAT 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PRODH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 6X90 8X90 0000 000x 0000 000u uuuu uuuu
INTCON2 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
INTCON3 6X90 8X90 1100 0000 1100 0000 uuuu uuuu
INDF0 6X90 8X90 N/A N/A N/A
POSTINC0 6X90 8X90 N/A N/A N/A
POSTDEC0 6X90 8X90 N/A N/A N/A
PREINC0 6X90 8X90 N/A N/A N/A
PLUSW0 6X90 8X90 N/A N/A N/A
FSR0H 6X90 8X90 ---- xxxx ---- uuuu ---- uuuu
FSR0L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 6X90 8X90 N/A N/A N/A
POSTINC1 6X90 8X90 N/A N/A N/A
POSTDEC1 6X90 8X90 N/A N/A N/A
PREINC1 6X90 8X90 N/A N/A N/A
PLUSW1 6X90 8X90 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interru pt and the G IEL or GIEH bi t is set, th e PC is loade d with the in terrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or G IEH bit is se t, the T O SU, T O SH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

(2)

(3)
(3)
(3)
(3)

(1)
(1)
(1)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 59

PIC18F6390/6490/8390/8490

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register

ADRESH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 6X90 8X90 --00 0000 --00 0000 --uu uuuu
ADCON1 6X90 8X90 --00 0000 --00 0000 --uu uuuu
ADCON2 6X90 8X90 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 6X90 8X90 --00 0000 --00 0000 --uu uuuu
CCPR2H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 6X90 8X90 --00 0000 --00 0000 --uu uuuu
CVRCON 6X90 8X90 000- 0000 000- 0000 uuu- uuuu
CMCON 6X90 8X90 0000 0111 0000 0111 uuuu uuuu
TMR3H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
SPBRG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
RCREG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXREG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXSTA1 6X90 8X90 0000 0010 0000 0010 uuuu uuuu
RCSTA1 6X90 8X90 0000 000x 0000 000x uuuu uuuu
IPR3 6X90 8X90 -111 ---- -111 ---- -uuu ----
PIR3 6X90 8X90 -000 ---- -000 ---- -uuu ----
PIE3 6X90 8X90 -000 ---- -000 ---- -uuu ----
IPR2 6X90 8X90 11-- 1111 11-- 1111 uu-- uuuu
PIR2 6X90 8X90 00-- 0000 00-- 0000 uu-- uuuu
PIE2 6X90 8X90 00-- 0000 00-- 0000 uu-- uuuu
IPR1 6X90 8X90 -111 1111 -111 1111 -uuu uuuu
PIR1 6X90 8X90 -000 0000 -000 0000 -uuu uuuu
PIE1 6X90 8X90 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 6X90 8X90 00-0 0000 00-0 0000 uu-u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interru pt and the G IEL or GIEH bi t is set, th e PC is loade d with the in terrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or G IEH bit is se t, the T O SU, T O SH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Applicable

Devices

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

(1)

(1)

(1)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 61

PIC18F6390/6490/8390/8490

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register

Applicable

Devices

Power-on Reset,

Brown-out Reset

TRISJ 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISH 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISG 6X90 8X90 ---1 1111 ---1 1111 ---u uuuu
TRISF 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISE 6X90 8X90 1111 ---- 1111 ---- uuuu ----
TRISD 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISC 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISB 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISA

(5)

6X90 8X90 1111 1111

(5)

LATJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATG 6X90 8X90 ---x xxxx ---u uuuu ---u uuuu
LATF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATE 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATA

(5)

6X90 8X90 xxxx xxxx

(5)

PORTJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTG 6X90 8X90 --xx xxxx --uu uuuu --uu uuuu
PORTF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA

(5)

6X90 8X90 xx0x 0000

(5)

SPBRGH1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 6X90 8X90 01-0 0-00 01-0 0-00 uu-u u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interru pt and the G IEL or GIEH bi t is set, th e PC is loade d with the in terrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or G IEH bit is se t, the T O SU, T O SH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

WDT Reset

RESET Instruction

Stack Rese ts

1111 1111

uuuu uuuu

uu0u 0000

(5)

(5)

(5)

Wake-up via WDT

or Interrupt

uuuu uuuu

uuuu uuuu

uuuu uuuu

(5)

(5)

(5)

DS39629B-page 62 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register

LCDDATA23 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA22 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA21 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA20 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA19 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA18 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA17
LCDDATA16 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA15 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA14 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA13 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA12 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA11
SPBRG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
RCREG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXREG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXSTA2 6X90 8X90 0000 0010 0000 0010 uuuu uuuu
RCSTA2 6X90 8X90 0000 000x 0000 000x uuuu uuuu
LCDDATA10
LCDDATA9 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA8 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA7 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA6 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA5
LCDDATA4 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA3 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA2 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA1 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA0 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interru pt and the G IEL or GIEH bi t is set, th e PC is loade d with the in terrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or G IEH bit is se t, the T O SU, T O SH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Applicable

Devices

6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu

6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu

6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu

6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

 2004 Microchip Technology Inc. Preliminary DS39629B-page 63

PIC18F6390/6490/8390/8490

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets

MCLR

Register

LCDSE5 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE4 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE3 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE2 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE1 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE0 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
LCDCON 6X90 8X90 000- 0000 000- 0000 uuu- uuuu
LCDPS 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interru pt and the G IEL or GIEH bi t is set, th e PC is loade d with the in terrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or G IEH bit is se t, the T O SU, T O SH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Applicable

Devices

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Rese ts

Wake-up via WDT

or Interrupt

DS39629B-page 64 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

5.0 MEMORY ORGANIZATION

There are two types of memory in PIC18 Flash
microcontroller devices:

• Program Memory

• Data RAM
As Harvard architecture dev ices, the dat a and progra m

memories use separate busses; this allows for
concurrent access of the two memory spaces.

Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0

“Flash Program Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory sp ace. Accessi ng a loca tion betwee n
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).

The PIC18FX390 have 8 Kbytes of Flash memory and
can store up to 4,096 single-word instructions and
PIC18FX490 have 16 Kbytes of Flash memory and can
store up to 8,192 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.

The program memory maps for
PIC18F6390/6490/8390/8490 devices are shown in
Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MA P AND S TACK FOR PIC1 8F639 0/ 649 0/ 839 0/849 0 D EVI CES

PC<20:0>

CALL,RCALL,RETURN
RETFIE,RETLW

Stack Level 1

Stack Level 31

21

•

•

•

CALL,RCALL,RETURN
RETFIE,RETLW

PC<20:0>

Stack Level 1

•

•

•

Stack Level 31

21

Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector

On-Chip

Program Memory

Read ‘0’

0000h
0008h

0018h

1FFFh
2000h

1FFFFFh

User Memory Space

Reset Vector
High Prio rity Interrupt Vector
Low Priority Interrupt Vector

On-Chip

Program Memory

Read ‘0’

0000h
0008h

0018h

3FFFh
4000h

User Memory Space

1FFFFFh

 2004 Microchip Technology Inc. Preliminary DS39629B-page 65

PIC18F6390/6490/8390/8490

5.1.1 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the
instruction to fetch for execu tion. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byt e, or PCH re gister, contains
the PC<15:8> bits; i t is not directly re adable or writ able.
Updates to the PCH register are perfo rmed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to P CLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).

The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The return address s tack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto th e stac k when a CALL or RCALL instruc­tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a
5-bit St ack Poi nter. The stack sp ace is no t par t of either
program or data space. The Stack Pointer is readable
and writable and the address on the top of the stack is
readable and writable through the top-of-stack Special
File Registers. Data can also be pushed to, or popped
from the stack using these registers.

A CALL type instru ctio n caus es a pus h ont o the stac k;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN ty pe ins truc ti on c au se s
a pop from the stack; the contents of the location
pointed to by the STKPTR register are transferred to
the PC and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bit s in dic ate if the stack is
full, has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is read­able and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack
location pointed to by the low er five bi ts of th e STKPT R
register (Figure 5-2). This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU:TOSH:TOSL registers. These
values can be placed on a us er defined s oftware st ack.
At return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>

11111
11110
11101

TOSLTOSHTOSU

34h1Ah00h

00011

Top-of-Stack

DS39629B-page 66 Preliminary  2004 Microchip Technology Inc.

001A34h

000D58h

00010
00001
00000

STKPTR<4:0>

00010

PIC18F6390/6490/8390/8490

5.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Reg ister 5-1) contains the S t ack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.

After the PC is pus hed o nto the st ack 31 times (wi thout
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.

The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over­flow Reset Enable) configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a de scription of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.

If STVREN is cleared, the STKFUL bi t will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.

When the stack has been popped enough times to
unload the stac k, the next pop will ret urn a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software, or until a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the
program to the Reset vector where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.

5.1.2.3 PUSH and POP Instruction s

Since the Top-of-Stack is readable and writable, the
ability to push value s on to the st ac k an d pul l va lues off
the stack, without disturbing normal program execu­tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and T OS L can be m odifie d to plac e dat a
or a return address on the stack.

The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.

The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.

REGISTER 5-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL

bit 7 bit 0

bit 7 STKFUL: Stack Full Flag bit

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed

(1)

bit 6

bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits

STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred
0 = Stack underflow did not occur

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

STKUNF

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

(1)

— SP4 SP3 SP2 SP1 SP0

(1)

(1)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 67

PIC18F6390/6490/8390/8490

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Regist er 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condi tion will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. This stack is only one level deep and is
neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push val ues into t he s tack re gist ers. The v alue s in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.

If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priori ty interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.

If interrupt priority is not used, all interrupts ma y use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be use d
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine cal l, a CALL label, FAST instruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.

Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER
;STACK

•

•

SUB1 •

•

RETURN FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY

There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A computed GOTO is accomplished by adding an of fs et
to the program counter. An example is shown in
Example 5-2.

A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an of fs et into the table before
executing a call to tha t t a ble . The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.

The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

MOVF OFFSET, W

CALL TABLE
ORG nn00h
TABLE ADDWF PCL

RETLW nnh

RETLW nnh

RETLW nnh

.

.

.

5.1.4.2 Table Reads

A better method of storing data in program memory
allows two bytes of dat a to be stored in each instruction
location.

Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
register (TBLPTR) specifies the byte address and the
Table Latch regist er (TABLAT) contains th e da t a th at i s
read from the program memory. Data is transferred
from program memory one byte at a time.

Table read operation is discussed further in
Section 6.1 “Table Reads”.

DS39629B-page 68 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q 4). Internall y, the program cou nter is
incremented on every Q1; the instruction is fetched
from the program memory and lat ched int o the Instru c­tion Register (IR) d uring Q4. The ins truction is d ecoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.

FIGURE 5-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1
Q2
Q3
Q4
PC

OSC2/CLKO

(RC mode)

Q1

PC PC + 2 PC + 4

Execute INST (PC – 2)

Fetch INST (PC)

Q1

Execute INST (PC)

Fetch INST (PC + 2)

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instructio n fetch and execute ar e pipe­lined in such a m anner that a fetc h takes one i nstruction
cycle, while the decode and execute take another
instructio n cy cle. H owe ver, due to the pip elini ng, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to chan ge (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example5-3).

A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.

In the execution cy cle, the fetch ed instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

Q2 Q3 Q4

Q1

Execute INST (PC + 2)

Fetch INST (PC + 4)

Internal
Phase
Clock

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branche s. These take tw o cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 69

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

PIC18F6390/6490/8390/8490

5.2.3 INSTRUCTIONS IN PROGRAM MEMORY

The program memory is addressed in bytes. Instruc­tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction bo undaries , the PC incr ements in step s
of 2 and the LSB will alway s read ‘0’ (see Section 5.1.1
“Program Counter”).

Figure 5-4 shows an exam ple of h ow in st ruc tion w ord s
are stored in the program memory.

The CALL and GOTO instructions have the absolute pro­gram memory address embedded into the instruction.
Since instructions are always stored on word bound­aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same ma nner. The
offset value stored in a branch instruction represent s the

number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.

5.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instructi on set has four two-wor d
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruc tio ns alwa ys has
‘1111’ as its four M ost Si gnific ant bi ts; the ot her 12 bit s
are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for case s when the two-word ins truction is
preceded by a co nd i ti ona l in st ru ct i on t h at c han ge s t he
PC. Example 5-4 shows how this works.

Note: See Section 5.5 “Program Memory and

the Extended Instruction Set” for

information on two-word ins tructions in the
extended instruction set.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

Word Address

000000h
000002h
000004h
000006h

000012h
000014h

Program Memory
Byte Locations

Instruction 1: MOVLW 055h
Instruction 2: GOTO 0006h

Instruction 3: MOVFF 123h, 456h

→

LSB = 1 LSB = 0 ↓

0Fh 55h 000008h
EFh 03h 00000Ah
F0h 00h 00000Ch
C1h 23h 00000Eh
F4h 56h 000010h

EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

DS39629B-page 70 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

5.3 Data Memory Organization

Note: The operation of some aspects of data

memory are changed when the PIC18
extended instruction set is enabled. See

Section 5.6 “Data Memory and the
Extended Instruction Set” for more

information.

The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many
as 16 banks that contain 256 bytes each;
PIC18F6390/6490/8390/8490 devices implement
only 4 banks. Figure 5-5 shows the data memory
organization for the PIC18F6390/6490/8390/8490
devices.

The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functio ns, while GPRs are us ed for data
storage and scratchpad operations in the user’s
application. Any re ad of an unimpl emented location will
read as ‘0’s.

The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.

To ensure that commonly used registers (SFRs and
select GPRs) c an b e ac cess ed i n a si ngle cycle, PI C18
devices impl em ent an Ac ce ss Ba nk . Th is i s a 256-byte
memory space that pr ovid es fa st acces s to SFRs a nd
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.2 “Access Bank” provides a
detailed description of the Access RAM.

5.3.1 BANK SEL ECT REGISTER

Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom­plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.

Most instruct ions in th e PIC18 in struct ion set ma ke use
of the bank poin ter, known as the Bank Select Reg ister
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; the y will always read ‘ 0’ and cannot be
written to. The BSR can be l oaded direc tly by using the
MOVLB instruction.

The value of the BSR indicates the bank in data
memory; the 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-6.

Since up to 16 regis ters m ay share the s ame l ow-order
address, the user must alway s be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit addre ss of F9 h, while the BSR
is 0Fh will end up resetting the program counter.

While any bank can be s el ec ted, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the Status register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This i nstruction ig nores the
BSR completely when it ex ecutes. All o ther instruction s
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 71

PIC18F6390/6490/8390/8490

FIGURE 5-5: DATA MEMORY MAP FOR PIC18F6390/6490/8390/8490 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010

= 0011

Bank 0

Bank 1

Bank 2

Bank 3

to

Data Memory Map

00h

Access RAM

FFh

00h

FFh

00h

FFh

Unused

Read as 00h

GPR

GPR

GPR

000h
05Fh
060h
0FFh
100h

1FFh
200h

2FFh
300h

When a = 0:

The BSR is ignored and the
Access Bank is used.

The first 128 bytes are
general purpose RAM
(from Bank 0).

The second 128 bytes are
Special Function Registers
(from Bank 15).

When a = 1:

The BSR specifies the bank
used by the instruction.

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h
5Fh

60h
FFh

= 1110

= 1111

DS39629B-page 72 Preliminary  2004 Microchip Technology Inc.

Bank 14

Bank 15

00h

FFh

GPR

SFR

EFFh
F00h
F58h
F60h

FFFh

Banked SFRs

PIC18F6390/6490/8390/8490

FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

(1)

7

0000

Bank Select

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

BSR

0010

(2)

the registers of the Access Bank.

000h

0

100h

200h

300h

E00h

F00h

FFFh

Data Memory

Bank 0
Bank 1

Bank 2

Bank 3
through
Bank 13

Bank 14

Bank 15

00h
FFh

00h
FFh

00h
FFh

00h

FFh
00h

FFh
00h

FFh

7

111 11111

From Opcode

11111111

(2)

0

5.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means th at the user must a lways
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.

T o stre amline acces s for the most commonl y used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Block 15 . The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-5).

The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the inst ru ct i on
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.

Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 80h and
above, this means th at use rs can ev aluate an d operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for da ta values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.

The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.

5.3.3 GENERAL PURPOSE REGISTER FILE

PIC18 devices may have banked memory in the GPR
area. This is dat a RAM, whic h is avai lable for us e by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 73

PIC18F6390/6490/8390/8490

5.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and p eripheral modul es for controllin g
the desired operation of the device. These reg isters are
implemented as static RAM. SFRs start at the top of
data memory (FF Fh) and extend downw ard to oc cupy
three-quarters of Bank 15 (from F 40h to FFF h). A list of
these registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s Status register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that
peripheral.

The SFRs are typically distributed among the
peripherals whose fun cti ons th ey c ontr ol. U nus ed SFR
locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2

FFEh TOSH FDEh POSTINC2
FFDh TOSL FDDh POSTDEC2
FFCh STKPTR FDCh PREINC2

FFBh PCLATU FDBh PLUSW2

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ

FF9h PCL FD9h FSR2L FB9h —
FF8h TBLPTRU FD8h STATUS FB8h —
FF7h TBLPTRH FD7h TMR0H FB7h
FF6h TBLPTRL FD6h TMR0L FB6h
FF5h TABLAT FD5h T0CON F B5h CVRCON F95h TRISD
FF4h PRODH FD4h
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h IN T CO N FD2h HLVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ
FF0h INTCON3 FD0h RCON FB0h —

FEFh INDF0
FEEh POSTINC0
FEDh POSTDEC0
FECh PREINC0
FEBh PLUSW0

(1)

FCFh TMR1H FAFh SPBRG1 F8Fh LATG

(1)

(1)

(1)

(1)

FCEh TMR1L FAEh RCREG1 F8Eh LATF
FCDh T1CON FADh TXREG1 F8Dh LATE
FCCh TMR2 FACh TXSTA1 F8Ch LATD

FCBh PR2 FABh RCSTA1 F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh

FE9h FSR0L FC9h SSPBUF FA9h
FE8h WREG FC8h SSPADD FA8h
FE7h INDF1
FE6h POSTINC1
FE5h POSTDEC1
FE4h PREINC1
FE3h PLUSW1

(1)

(1)

(1)

(1)

(1)

FC7h SSPSTAT FA7h —
FC6h SSPCON1 FA6h —
FC5h SSPCON2 FA5h IPR3 F85h PORTF
FC4h ADRESH FA4h PIR3 F84h PORTE

FC3h ADRESL FA3h PIE3 F83h PO RTD
FE2h FSR1H FC2h A DCON0 FA2h IPR2 F82h PORTC
FE1h FS R1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

(1)

FBFh CCPR1H F9Fh IPR1

(1)

(1)

(1)

(1)

(2)

—

FBEh CCPR1L F9Eh PIR1
FBDh CCP1CON F9Dh PIE1
FBCh CCPR2H F9Ch MEMCON
FBBh CCPR2L F9Bh O SCTUNE

(2)
(2)
(2)

—

(2)

—

F99h TRISH
F98h TRISG
F97h TRISF
F96h TRISE

FB4h CMCON F94h TRISC

(2)

(2)

—

(2)

—

(2)

—

(2)
(2)

F90h LATH

F8Ah LATB

F89h LATA
F88h PORTJ
F87h PORTH
F86h PORTG

(3)

(3)

(3)

(3)

(3)

(3)

(3)

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.

4: This register is implemented but unused on 64-pin devices.

DS39629B-page 74 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

T ABLE 5-1: SP ECIA L FUN CT ION RE GISTER MAP FOR PIC18F6 39 0/6 49 0/ 8 39 0/ 84 90 DEV ICE S

(CONTINUED)

Address Name Address Name Address Name Address Name

F7Fh SPBRGH1 F6Fh SPBRG2 F5Fh LCDSE5

F7Eh BAUDCON1 F6Eh RCREG2 F5Eh LCDSE4
F7Dh —
F7Ch LCDDATA23

F7Bh LCDDATA22

F7Ah LCDD ATA21 F6Ah LCDDATA10

(2)

(4)
(4)

F6Dh TXREG2 F5Dh LCDSE3 F4Dh —
F6Ch TXSTA2 F5Ch LCDSE2 F4Ch —

F6Bh RCSTA2 F5Bh LCDSE1 F4Bh —

(4)

F5Ah LCDSE0 F4Ah —

(3)
(3)

F4Fh —
F4Eh —

F79h LCDD ATA20 F69h LCDDATA9 F59h LCDCON F49h —

F78h LCDD ATA19 F68h LCDDATA8 F58h LCDPS F48h —

F77h LCDD ATA18 F67h LCDDATA7 F57h —

F76h LCDDATA17

F75h LCDDATA16

F74h LCDD ATA15 F64h LCDDATA4

(4)
(4)

F66h LCDDATA6 F56h —
F65h LCDDATA5

(4)
(4)

F55h —

F54h —
F73h LCDD ATA14 F63h LCDDATA3 F53h —
F72h LCDD ATA13 F62h LCDDATA2 F52h —
F71h LCDD ATA12 F61h LCDDATA1 F51h —
F70h LCDDATA11

(4)

F60h LCDDATA0 F50h —

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

F47h —
F46h —
F45h —
F44h —
F43h —
F42h —
F41h —
F40h —

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.

4: This register is implemented but unused on 64-pin devices.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 75

PIC18F6390/6490/8390/8490

TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 59, 66
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 59, 66
STKPTR STKFUL STKUNF
PCLATU
PCLATH Holding Register for PC<15:8> 0000 0000 59, 66
PCL PC Low Byte (PC<7:0>) 0000 0000 59, 66
TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 59, 88
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 59, 88
TABLAT Program Memory Table Latch 0000 0000 59, 88
PRODH Product Register High Byte xxxx xxxx 59, 91
PRODL Product Register Low Byte xxxx xxxx 59, 91
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 59, 95
INTCON2 RBPU
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 59, 97
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 59, 82
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 59, 83
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 59, 83
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 59, 83
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register),

FSR0H
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 59, 82
WREG Working Register xxxx xxxx 59
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 59, 82
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 59, 83
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 59, 83
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 59, 83
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register),

FSR1H
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 60, 82
BSR
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 60, 82
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 60, 83
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 60, 83
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 60, 83
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register),

FSR2H
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 60, 82
STATUS

Legend: x = unknown , u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6 .4 “P LL in

4: The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 59, 66

— Return Stack Pointer 00-0 0000 59, 67

— — — Holding Register for PC<20:16> ---0 0000 59, 66

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 59, 88

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 59, 96

value of FSR0 offset by W

— — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 59, 82

value of FSR1 offset by W

— — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 60, 82

— — — — Bank Select Register ---- 0000 60, 71

value of FSR2 offset by W

— — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 60, 82

— — —NOVZDCC---x xxxx 60, 80

Section 4.4 “Brown-out Reset (BOR)” .

INTOSC Modes”.

read-only.
When disabled, these bits read as ‘0’.

Value on

POR, BOR

N/A 5 9, 83

N/A 5 9, 83

N/A 6 0, 83

Details

on page:

DS39629B-page 76 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

T ABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMR0H Timer0 Register High Byte 0000 0000 60, 132
TMR0L Timer0 Register Low Byte xxxx xxxx 60, 132
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 60, 131
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 38, 60
HLVDCON VDIRMAG
WDTCON
RCON IPEN SBOREN

TMR1H Timer1 Register High Byte xxxx xxxx 60, 137
TMR1L Timer1 Register Low Byte xxxx xxxx 60, 137
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR2 Timer2 Register

PR2 Timer2 Period Register 1111 1111 60, 141
T2CON
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 60, 158,

SSPADD SSP Address Register in I
SSPSTAT SMP CKE D/A

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 60, 159,

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 60, 169
ADRESH A/D Result Register High Byte xxxx xxxx 61, 240
ADRESL A/D Result Register Low Byte xxxx xxxx 61, 240
ADCON0
ADCON1
ADCON2 ADFM
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 61, 152,

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 61, 152,

CCP1CON
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 61, 152,

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 61, 152,

CCP2CON
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 000- 0000 61, 247
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 61, 241
TMR3H Timer3 Register High Byte xxxx xxxx 61, 145
TMR3L Timer3 Register Low Byte xxxx xxxx 61, 145
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC

Legend: x = unknown , u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in

4: The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.

— — — — — — —SWDTEN--- ---0 60, 288

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 60, 141

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 61, 231
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 61, 232

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61, 147

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 61, 147

Section 4.4 “Brown-out Reset (BOR)” .

INTOSC Modes”.

read-only.
When disabled, these bits read as ‘0’.

— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 60, 251

(1)

—RITO PD POR BOR 0q-1 11q0 52, 60,

TMR1CS TMR1ON 0000 0000 60, 135

2

C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 60, 166

PSR/WUA BF 0000 0000 60, 158,

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 61, 233

TMR3CS TMR3ON 0000 0000 61, 143

Value on

POR, BOR

0000 0000

Details

on page:

107

60, 141

166

167

168

155

155

155

155

 2004 Microchip Technology Inc. Preliminary DS39629B-page 77

PIC18F6390/6490/8390/8490

TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

SPBRG1 EUSART1 Baud Rate Generator 0000 0000 61, 201
RCREG1 EUSART1 Receive Register 0000 0000 61, 208
TXREG1 EUSART1 Transmit Register 0000 0000 61, 206
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0000 61, 198
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 199
IPR3
PIR3
PIE3
IPR2 OSCFIP CMIP
PIR2 OSCFIF CMIF
PIE2 OSCFIE CMIE
IPR1
PIR1
PIE1
OSCTUNE INTSRC PLLEN

(2)

TRISJ

(2)

TRISH
TRISG

— LCDIP RC2IP TX2IP — — — — -111 ---- 61, 106
— LCDIF RC2IF TX2IF — — — — -000 ---- 61, 100
— LCDIE RC2IE TX2IE — — — — -000 ---- 61, 103

— — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 61, 105
— — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 61, 99

— — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 61, 102
— ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 61, 104
— ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 61, 98
— ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 61, 101

(3)

— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 61

Data Direction Control Register for PORTJ 1111 1111 62, 130
Data Direction Control Register for PORTH 1111 1111 62, 128

— — — Data Direction Cont rol Register for PORTG ---1 1111 62, 126

TRISF Data Direction Control Register for PORTF 1111 1111 62, 124
TRISE Data Direction Control Register for PORTE

— — — — 1111 ---- 62, 121
TRISD Data Direction Control Register for PORTD 1111 1111 62, 119
TRISC Data Direction Control Register for PORTC 1111 1111 62, 117
TRISB Data Direction Control Register for PORTB 1111 1111 62, 114
TRISA TRISA7

(2)

LATJ
LATH
LATG

(2)

Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 62, 130
Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 62, 128

— — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 62, 126

(5)

TRISA6

(5)

Data Direction Control Register for PORTA 1111 1111 62, 111

LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 62, 124
LATE Re ad PO RTE Data Latch, Write PORTE Data Latch

— — — — xxxx xxxx 62, 121
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 62, 119
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 62, 117
LATB Re ad PO RTB Data Latch, Write PORTB Data Latch xxxx xxxx 62, 114
LATA LATA7

(2)

PORTJ
PORTH
PORTG

Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 62, 130

(2)

Read PORTH pins, Write PORTH Data Latch xxxx xxxx 62, 128

— —RG5

(5)

LATA6

(5)

Read PORTA Data Latch, Write PORTA Data Latch xxxx xxxx 62, 111

(4)

Read PORTG pins <4:0>, Write PORTG Data Latch <4:0> --xx xxxx 62, 126
PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 62, 124
PORTE Read PORTE pins, Write PORTE Data Latch

— — — — xxxx xxxx 62, 121
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 62, 119
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 62, 117
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 62, 114
PORTA RA7

(5)

RA6

(5)

Read PORTA pins, Write PORTA Data Latch xx0x 0000 62, 111

Legend: x = unknown , u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

Section 4.4 “Brown-out Reset (BOR)” .
2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6 .4 “P LL in

INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is

read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.

Details

on page:

DS39629B-page 78 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

T ABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPBRGH1 EUSART1 Baud Rate Generator High Byte 0000 0000 62 , 201
BAUDCON1 ABDOVF RCIDL
LCDDATA23
LCDDATA22
LCDDATA21 S31C3 S30 C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 xxxx xxxx 63, 261
LCDDATA20 S23C3 S22 C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 xxxx xxxx 63, 261
LCDDATA19 S15C3 S14 C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 xxxx xxxx 63, 261
LCDDATA18 S07C3 S06 C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 xxxx xxxx 63, 261
LCDDATA17
LCDDATA16
LCDDATA15 S31C2 S30 C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 xxxx xxxx 63, 261
LCDDATA14 S23C2 S22 C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 xxxx xxxx 63, 261
LCDDATA13 S15C2 S14 C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 xxxx xxxx 63, 261
LCDDATA12 S07C2 S06 C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 xxxx xxxx 63, 261
LCDDATA11
SPBRG2 AUSART2 Baud Rate Generator 0000 0000 63, 220
RCREG2 AUSART2 Receive Register 0000 0000 63, 224
TXREG2 AUSART2 Transmit Register 0000 0000 63, 222
TXSTA2 CSRC TX9 TXEN SYNC
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 63, 219
LCDDATA10
LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 xxxx xxxx 63, 261
LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 xxxx xxxx 63, 261
LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 xxxx xxxx 63, 261
LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 xxxx xxxx 63, 261
LCDDATA5
LCDDATA4
LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 xxxx xxxx 63, 261
LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 xxxx xxxx 63, 261
LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 xxxx xxxx 63, 261
LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 xxxx xxxx 63, 261
LCDSE5
LCDSE4
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 64, 261
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 64, 261
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 64, 261
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 64, 261
LCDCON LCDEN SLPEN WERR
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 64, 259

Legend: x = unknown , u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

(6)

S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 xxxx xxxx 63, 261

(6)

S39C3 S38C3 S37C3 S36C3 S35C3 S34C3 S33C3 S32C3 xxxx xxxx 63, 261

(6)

S47C2 S46C2 S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 xxxx xxxx 63, 261

(6)

S39C2 S38C2 S37C2 S36C2 S35C2 S34C2 S33C2 S32C2 xxxx xxxx 63, 261

(6)

S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 xxxx xxxx 63, 261

(6)

S39C1 S38C1 S37C1 S36C1 S35C1 S34C1 S33C1 S32C1 xxxx xxxx 63, 261

(6)

S47C0 S46C0 S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 xxxx xxxx 63, 261

(6)

S39C0 S38C0 S37C0 S36C0 S35C0 S34C0 S33C0 S32C0 xxxx xxxx 63, 261

(2)
(2)

2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.

3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in

4: The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is

5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.

SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 0000 0000 64, 261
SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 64, 260

Section 4.4 “Brown-out Reset (BOR)” .

INTOSC Modes”.

read-only.
When disabled, these bits read as ‘0’.

— SCKP BRG16 — WUE ABDEN 01-0 0-00 62, 200

— BRGH TRMT TX9D 0000 0010 63, 218

— CS1 CS0 LMUX1 LMUX0 000- 0000 64, 258

Value on

POR, BOR

Details

on page:

 2004 Microchip Technology Inc. Preliminary DS39629B-page 79

PIC18F6390/6490/8390/8490

5.3.5 STATUS REGISTER

The St atus register , s hown in Register5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any instruction.

If the St atus regis ter is the dest ination for an instructio n
that affect s the Z, DC, C, OV or N bit s, the re sults of the
instruction are not written; instead, the status is
updated according to t he i nstruc tion pe rformed . There­fore, the result of an instru cti on w i th the Status register
as its destinatio n may be dif ferent than intended . As an
example, CLRF STATUS will set the Z bit and leave the
remaining status bits unchanged (‘000u u1uu’).

REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDCC

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).

1 = Result was negative
0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

Note: For borrow,

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either bit 4 or bit 3 of the source register.

bit 0 C: Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow,

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.

bit

the polarity is reversed. A subtraction is executed by adding the

bit

the polarity is reversed. A subtraction is executed by adding the

It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status
register , b ecaus e thes e ins tructi ons d o not af fect t he Z,
C, DC, OV or N bits in the Status register.

For other instructions that do not affect status bits, see
the instruction set summaries in Table 24-2 and
Table 24-3.

Note: The C and DC bits operate as a borrow and

digit borrow

bit respectively, in subtraction.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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5.4 Data Addressing Modes

Note: The execution of some instructions in the

core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.

While the program memory can be addressed in only
one way – through the program counter – information
in the data memory sp ace c an be a ddress ed in severa l
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on whic h operands are used and whe ther or
not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect
An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing With Literal Offset”.

5.4.1 INHERENT AND LITERAL ADDRESSING

Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affec ts the dev ice, or they operat e implic itly on
one register. This addressing mode is known as
Inherent Addressing. Exa mp les includ e SLEEP, RESET
and DAW.

Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.

5.4.2 DIRECT ADDRESSING

Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address spec ifies either a re gister address in
one of the banks of d ata RAM ( Section 5.3.3 “General

Purpose Register File”), or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.

The Access RAM bit ‘a’ determines how the addre ss i s
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register” ) are used with
the address to determine the complete 12-bit address
of the register . When ‘a’ i s ‘0’, the address is interp reted
as being a regist er in the Access Bank. Address ing that
uses the Access RAM is sometimes also known as
Direct Forc ed Addressing mode.

A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
op codes. In those cases, the BSR is ignored entirely.

The destination of the operati on’s results is determined
by the destination bit ‘d ’. Wh en ‘d’ is ‘1’, the results are
stored back in t he s o ur c e re g is ter, over wr iti n g i ts or i gi ­nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destin ation tha t is i mplicit in the inst ruction; their
destination is either the target register being operated
on, or the W r egister.

5.4.3 INDIRECT ADDRESSING

Indirect addressi ng allows the user to acces s a locatio n
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the location s to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Reg isters , they can also be directl y mani p­ulated under program control. This makes FSRs very
useful in imp lem ent ing data str uct ures , s uch as tabl es
and arrays in data memory.

The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic mani pulati on of the poi nter val ue wi th
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
indexed addressing and othe r S t ack Poi nter operation s
for program memory in data memory.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING
INDIRECT ADDRESSING

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then
; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

 2004 Microchip Technology Inc. Preliminary DS39629B-page 81

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5.4.3.1 FSR Registers and the
INDF Operand

At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, s o each
FSR pair holds a 12-bi t va lue. T his repre sen ts a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.

Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are

FIGURE 5-7: INDIRECT ADDRESSING

Using an instruction with one of the
indirect addressing registers as the

operand....

...uses the 12-bit address stored in
the FSR pair associated with that

register....

xxxx1111 11001100

ADDWF, INDF1, 1

FSR1H:FSR1L

mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the con tents of their c orresponding FSR a s
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.

Because indirect addres sing uses a full 1 2-bit a ddress ,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.

000h

Bank 0

100h

200h

300h

07

7

0

Bank 1

Bank 2

Bank 3

through

Bank 13

...to determine the data memory
location to be used in that operation.

In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.

E00h

F00h

FFFh

Bank 14

Bank 15

Data Memory

DS39629B-page 82 Preliminary  2004 Microchip Technology Inc.

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5.4.3.2 FSR Registers and POST IN C,
POSTDEC, PREINC and PLUSW

In addition to the IND F operand, each F SR register p air
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specif ic action on i ts stored v alue. They a re:

• POSTDEC: accesses the FSR value, then

automatically decrements it by ‘1’ afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by ‘1’ afterwards

• PREINC: incremen t s the FSR valu e by ‘1’, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses
the new value in the operation.

In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.

Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll­overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the Status register (e.g., Z, N, OV, etc.).

The PLUSW register can be used to implement a form
of indexed addressing in t he data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as softw are stacks, insi de of data memory.

5.4.3.3 Operations by FSRs on FSRs

Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam­ple, using an FSR to point to one of the virtual regis ters
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.

On the other hand, using the virtua l registers to write to
an FSR pair may not occu r as plan ned. I n th ese cas es,
the value will be written to the FSR p air , but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.

Similarly, operations by indirect addressing are gener­ally permitted on all other SFRs. U sers sho uld exerc ise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 83

PIC18F6390/6490/8390/8490

5.5 Program Memory and the Extended Instruction Set

The operation of progra m mem ory is un affected by the
use of the extended instruction set.

Enabling the extended instruction set adds five addi­tional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.

5.6 Data Memory and the Extended Instruction Set

Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically , t he use of the Ac cess Bank for ma ny of the
core PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space. This mode also alters the behavior of
indirect addressing using FSR2 and its associated
operands.

What does not change is just as im po rtant. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remains unchanged.

5.6.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair a nd its a ssociated fil e operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – ca n in voke a form of indexed add r es sin g
using an offse t sp ecified in the instruction. This special
addressing mode is known as Inde xed A ddressing w ith
Literal Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this
addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);
and

• The file addres s arg um ent is le ss th an or e qual to
5Fh.

Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direc t addressing), or a s
an 8-bit address i n the Acc ess Bank. In stead, the value
is interpr eted as an offset value to an addres s pointe r
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.

5.6.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc­tions that only use Inherent or Literal Addressing
modes are unaffecte d.

Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’), or include a fi le address of 60h o r above.
Instructions meeting these criteria will continue to
execute as before. A comp aris on of the dif fere nt possi­ble addressing modes when the extended instruction
set is enabled is shown in Figure 5-8.

Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.

DS39629B-page 84 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When a = 0 and f ≥ 60h:

The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.

Locations below 060h are not
available in this addressing
mode.

When a = 0 and f ≤ 5Fh:

The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.

Note that in this mode, the
correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

000h

060h

100h

F00h

F40h

FFFh

000h

060h

100h

F00h

F40h

FFFh

Bank 0

Bank 1
through
Bank 14

Bank 15

SFRs

Data Memory

Bank 0

Bank 1
through
Bank 14

Bank 15

SFRs

Data Memory

00h
60h

Access RAM

FSR2H FSR2L

FFh

ffffffff001001da

Valid range

for ‘f’

BSR

00000000

ffffffff001001da

When a = 1 (all values of f):

The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Sel ect

000h

060h

100h

Bank 0

Bank 1
through
Bank 14

Register (BSR). The address
can be in any implemented
bank in the data memory
space.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 85

F00h

F40h

FFFh

Bank 15

SFRs

Data Memory

PIC18F6390/6490/8390/8490

DS39629B-page 86 Preliminary 

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6.0 FLASH PROGRAM MEMORY

In PIC18F6390/6490/8390/8490 devices, the program
memory is implemented as read-only Flash memory. It
is readable over the entire VDD range during normal
operation. A read from pr ogram memory is e xecuted on
one byte at a time.

6.1 Table Reads

For PIC18 devices, there are two operations that allow
the processor to move bytes between the program
memory space and the data RAM: table read (TBLRD)
and table write (TBLWT).

Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and dat a RAM.

The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register, TABLAT.

FIGURE 6-1: TABLE READ OPERATION

Table reads work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address.

Because the program memory cannot be written to or
erased under normal operation, the TBLWT operation is
not discussed here.

Note 1: Although it cannot be used in

PIC18F6390/6490/8390/8490 devices in
normal operation, the TBLWT instruction
is still implemented in the instruction set.
Executing the instruction takes two
instruction cycles, but effectively results
in a NOP.

2: The TBLWT instruction is available only in

programming modes and is used during
In-Circuit Serial Programming™ (ICSP™).

Instruction: TBLRD*

Table Pointer

TBLPTRU

Note 1: Table Pointer register points to a byte in program memory.

TBLPTRH TBLPTRL

(1)

Program Memory
(TBLPTR)

Program Memory

Table Latch (8-bit)

TABLAT

 2004 Microchip Technology Inc. Preliminary DS39629B-page 87

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6.2 Control Registers

Two control registers are used in conjunction with the
TBLRD instruction: the TABLAT register and the
TBLPTR register set.

6.2.1 TABLE LATCH REGISTER (TABLAT)

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.

6.2.2 TABLE POINTER REGISTER (TBLPTR)

The Table Pointer regi st er (TBL PTR) addresses a byte
within the program memory. It is comprised of three
SFR registers: Table Pointer Upper Byte, T a ble Poin ter
High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six
bits of TBLPTRU are used with TBLPTRH and
TBLPTRL to form a 22-bit wide pointer.

The contents of TBLPTR indicates a location in
program memory space. The low-order 21 bits allow
the device to address the full 2 Mbytes of program
memory space. The 22nd bit allows access to the
configuration space, including the device ID, user ID
locations and the configuration bits.

The TBLPTR register set is updated when executing a
TBLRD in one of four ways, based on the instruction’s
arguments. These are detailed in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.

When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into T AB LAT.

TABLE 6-1: TABLE POINTER

OPERATIONS WITH TBLRD
INSTRUCTIONS

Example Operation on Table Pointer

TBLRD* TBLPTR is not modified
TBLRD*+ TBLPTR is incremented after the read
TBLRD*- TBLPTR is decremented after the read
TBLRD+* TBLPTR is i ncr em ent ed be fore th e read

6.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.

TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.

The internal program memory is typically organize d by
words. The Least Significant b it of th e address selects
between the high and low bytes of the word. Figure 6-2
shows the interface between the internal program
memory and the TABLA T.

A typical method for reading data from program memory
is shown in Example 6-1.

FIGURE 6-2: READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

Instruction Register

(IR)

DS39629B-page 88 Preliminary  2004 Microchip Technology Inc.

FETCH

(Odd Byte Address)

TBLPTR = xxxxx1

TBLRD

TBLPTR = xxxxx0

TABLAT

Read Register

PIC18F6390/6490/8390/8490

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVF WORD_ODD

TABLE 6-2: REGISTERS ASSOCIATED WITH READING PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 59
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 59
TABLAT Program Memory Table Latch 59

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.

Reset

Values on

Page

59

 2004 Microchip Technology Inc. Preliminary DS39629B-page 89

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 90 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

7.0 8 x 8 HARDWARE MULTIPLIER

7.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier pe rforms an unsigned
operation and yields a 16-bit result that is stored in the
product re gister pair P RODH:PR ODL. T he mult ipli er ’s
operation does not affect any flags in the Status
register.

Making multiplication a hardware operation allows it to
be completed in a s ingle instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many
applications previously reserved for digital signal
processors. A comparison of various hardware and
software multiply operations, along with the savings in
memory and execution time, is shown in Table 7-1.

7.2 Operation

Example 7-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.

Example 7-2 shows the s equence to d o an 8 x 8 si gned
multiplication. To account for the signed bits of the
arguments, eac h argume nt’s Most Signi ficant b it (MSb)
is tested and the appropriate subtractions are done.

EXAMPLE 7-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

TABLE 7-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine Multiply Method

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

Without hardware multiply 13 69 6.9 µs27.6 µs69 µs

Hardware multiply 1 1 100 ns 400 ns 1 µs

Without hardware multiply 33 91 9.1 µs36.4 µs91 µs

Hardware multiply 6 6 600 ns 2.4 µs6 µs

Without hardware multiply 21 242 24.2 µs96.8 µs 242 µs

Hardware multiply 28 28 2.8 µs 11.2 µs28 µs

Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs

Hardware multiply 35 40 4.0 µs16.0 µs40 µs

Program

Memory
(Words)

Cycles

(Max)

@ 40 MHz @ 10 MHz @ 4 MHz

Time

 2004 Microchip Technology Inc. Preliminary DS39629B-page 91

PIC18F6390/6490/8390/8490

+

Example 7-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 7-1 shows the
algorithm that is used . The 32-bit re sult is st ored in four
registers (RES3:RES0).

EQUATION 7-1: 16 x 16 UNSIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L)

16

) +

8

) +

8

) +

EXAMPLE 7-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

EQUATION 7-2: 16 x 16 SIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0= ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216)
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

16

) +

8

) +

8

) +

EXAMPLE 7-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the signed bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.

DS39629B-page 92 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

8.0 INTERRUPTS

The PIC18F6390/6490/8390/8490 devices have multi­ple interrupt sources and an interrupt priority feature
that allows most interrupt sources to be assigned a
high priority level or a low pri ority level. The high priorit y
interrupt vector is at 0008h and the low priorit y interrupt
vector is at 0018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.

There are t hirteen r egisters which are used to c ontrol
interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3
It is recommended that the Microchip header files

supplied with MPLAB
names in these registers. This allows the assembler/
compiler to automatical ly ta ke care of the pla ceme nt of
these bits within the specified register.

In genera l, int errupt sour ces h ave th ree bits to cont rol
their operation. They are:

• Flag bit to indicate that an interrupt event
occurred

• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally . Setti ng the GIEH bit (INTC ON<7>) enable s all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the prio rity bit cleared ( low priority ).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.

®

IDE be used for the symb olic bit

When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro
Compatibilit y mode, the in terrupt prior ity bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disab les all periph eral interrupt s ources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interru pt priority
levels are used, this wi ll be either the GIEH or G IEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and set s the GIE bit (GIEH or GI EL
if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or
the PORTB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.

®

mid-range devices. In

 2004 Microchip Technology Inc. Preliminary DS39629B-page 93

PIC18F6390/6490/8390/8490

FIGURE 8-1: PIC18F6X90/8X90 INTERRUPT LOGIC

TMR0IF

TMR0IE
TMR0IP

RBIF

RBIE
RBIP

INT1IF

INT1IE
INT1IP

INT2IF

INT2IE
INT2IP

TMR0IF
TMR0IE
TMR0IP

INT0IF
INT0IE

INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP

IPEN

GIEL/PEIE

RBIF
RBIE
RBIP

GIEL/PEIE

Wake-up if in

Interrupt to CPU
Vector to Location
0008h

GIEH/GIE

Interrupt to CPU
Vector to Location

DS39629B-page 94 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

8.1 INTCON Registers

The INTCON registers are readable and writable
registers which c ontai n various enable, priority a nd flag
bits.

Note: Interrupt flag bits are set when an inter rupt

condition occurs, rega rdless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.

REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN =

1 = Enables all unmasked interrupts
0 = Disables all interr upts

When IPEN =

1 = Enables all high priority interrupts
0 = Disables all interrupts

bit 6 PEIE/GIEL: Periphera l Interr upt Enab le bit

When IPEN =

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interr upts

When IPEN =

1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change inte rrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has ov erflowed (must be clear ed in software)
0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

Note: A mismatch condition will continue to set this bit. Reading PORTB will end the

0:

1:

0:

1:

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS39629B-page 95

PIC18F6390/6490/8390/8490

REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

bit 7 bit 0

bit 7 RBPU

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

bit 3 INTEDG3: External Interrupt 3 Edge Select bit

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

bit 1 INT3IP: INT3 External Interrupt Priority bit

bit 0 RBIP: RB Port Change Interrupt Priority bit

: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enable d by indi vi dua l port latc h val ue s

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = Interrupt on rising edge
0 = Interrupt on falling edge

1 = High priority
0 = Low priority

1 = High priority
0 = Low priority

1 = High priority
0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its correspon ding enable bit o r the global interrup t enable bit. User so ftware should
ensure the appropriate i nterrup t flag b its are cl ear prio r to enab ling a n interru pt. Thi s
feature allows for software polling.

DS39629B-page 96 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3

R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

bit 7 bit 0

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority
0 = Low priority

bit 5 INT3IE: INT3 External Interrupt Enable bit

1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt

bit 2 INT3IF: INT3 External Interrupt Flag bit

1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt cond ition occurs, regardless of the sta te

of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an inter­rupt. This feature allows for software polli ng.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 97

PIC18F6390/6490/8390/8490

8.2 PIR Registers

The PIR registers conta in the ind ividu al flag bi ts fo r the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).

Note 1: Interrupt flag bit s are set when an interrupt

condition occurs, regardl ess of the state of
its corresponding enable bit or the global
interrupt enable bit, GIE (INTCON<7>).

2: User software should ensure the

appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.

REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete

bit 5 RC1IF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RC1REG, is full (cleared when RC1REG is read)
0 = The EUSART receive buffer is empty

bit 4 TX1IF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer, TX1REG, is empty (cleared when TX1REG is written)
0 = The EUSART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred

Compare mode:

1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred

PWM mode:
Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39629B-page 98 Preliminary  2004 Microchip Technology Inc.