MICROCHIP PIC18F6390, PIC18F6490, PIC18F8390, PIC18F8490 DATA SHEET

PIC18F6390/6490/8390/8490

Data Sheet

64/80-Pin Flash Microcontrollers

with LCD Driver and nanoWatt Technology

 2004 Microchip Technology Inc. Preliminary DS39629B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

DS39629B-page ii Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

64/80-Pin Flash Microcontrol lers with LCD Driver

and nanoW att Technology

LCD Driver Module Features:

• Direct driving of LCD panel

• Up to 48 segm ents: Software Selectable

• Programmable LCD timing module:

- Multiple LCD timing sources available

- Up to 4 commons: Static, 1/2, 1/3 or 1/4 mu ltiplex

- Static, 1/2 or 1/3 bias configuration

• Can drive LCD panel while in Sleep mode

Power Managed Modes:

• Run: CPU on, peripheral s on

• Idle: CPU off, peripheral s on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 µA typical

• Sleep current down to 0.1 µA typical

• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• T wo -Spe ed Os ci ll ator Start-up

Flexible Oscillator Struc ture:

• Four Crystal modes:

- LP: up to 200 kHz

- XT: up to 4 MHz

- HS: up to 40 MHz

- HSPLL: 4-10 MHz (16-40 MHz internal)

• 4x Phase Lock Loop (available for crystal and

internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe sh ut down of dev ice if prim ary or secondary clock fails

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Four external interrupts

• Four input-change interrupts

• Four 8-bit/16-bit Timer/Counter modules

• Real-Time Clock (RTC) Software module:

- Configurable 24-hour clock, calendar , auto matic 100-year or 12800-year, day-of-w eek calculator

- Uses Timer1

• Up to 2 Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ (all 4 modes) and I

C™

Master and Slave modes

• Addressable USART module:

- Supports RS-485 and RS-232

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-wake-up on Start bit

- Auto-baud Detect

• 10-bit, up to 12-channel Analog-to-Digital Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

Special Microcontroller Features:

• C compiler optimized architecture

- Optional extended instruct ion set designed to

optimize re-entrant code

• 1000 erase/wr i te cy c le Fl as h pr ogram memory typical

• Flash Retention: 100 years typical

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 132 s

- 2% stability over V

• In-Circuit Serial Programming ™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

DD and temperature

Program Memory

Device

PIC18F6390 8K 4096 768 50 128 12 2 Y Y 1/1 2 1/3 PIC18F6490 16K 8192 768 50 128 12 2 Y Y 1/1 2 1/3 PIC18F8390 8K 4096 768 66 192 12 2 Y Y 1/1 2 1/3 PIC18F8490 16K 8192 768 66 192 12 2 Y Y 1/1 2 1/3

 2004 Microchip Technology Inc. Preliminary DS39629B-page 1

Flash

(bytes)

# Single-Word

Instructions

Data

Memory

SRAM (bytes)

I/O

LCD

(pixel)

10-bit

A/D (ch)

CCP

(PWM)

SPI

MSSP

Master

Comparators

C™

AUSART

EUSART/

Timers

8/16-bit

PIC18F6390/6490/8390/8490

Pin Diagrams

64-Pin TQFP

/SEG31

(1)

LCDBIAS2 LCDBIAS1

RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28

RG3/SEG27

/VPP/RG5

MCLR

RG4/SEG26

V VDD

RF7/SS/SEG25

RF6/AN11/SEG24

RF5/AN10/CV

RF2/AN7/C1OUT/SEG20

REF/SEG23

RF4/AN9/SEG22 RF3/AN8/SEG21

LCDBIAS3

COM0

RE4/COM1

RE5/COM2

RE6/COM3

63 62 61

1 2 3 4 5 6 7

8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26

RE7/CCP2

RD0/SEG0

VSS

PIC18F6390 PIC18F6490

RD1/SEG1

RD2/SEG2

54 53 52 5158 57 56 5560 59

27 28

RD3/SEG3

RD4/SEG4

29 30

RD5/SEG5

RD6/SEG6

50 49

RD7/SEG7

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC

V OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13

AVSS

REF-/SEG16

RF0/AN5/SEG18

RA2/AN2/V

RF1/AN6/C2OUT/SEG19

RA3/AN3/VREF+/SEG17

VDD

RA1/AN1

RA0/AN0

(1)

RC6/TX1/CK1

RC7/RX1/DT1

RA4/T0CKI/SEG14

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA5/AN4/HLVDIN/SEG15

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

DS39629B-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

RH2/SEG45 RH3/SEG44

LCDBIAS2 LCDBIAS1

RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28

RG3/SEG27

/VPP/RG5

MCLR

RG4/SEG26

VDD

RF7/SS/SEG25

RF6/AN11/SEG24

RF5/AN10/CV

RF2/AN7/C1OUT/SEG20

REF/SEG23

RF4/AN9/SEG22 RF3/AN8/SEG21

RH7/SEG43

RH6/SEG42

PIC18F6390/6490/8390/8490

/SEG31

(1)

LCDBIAS3

COM0

RE4/COM1

RH0/SEG47

RH1/SEG46

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32

RE5/COM2

77 76 75

RD0/SEG0

RE6/COM3

RE7/CCP2

PIC18F8390 PIC18F8490

VSS

RD1/SEG1

RD2/SEG2

68 67 66 6572 71 70 6974 73

33 34

RD3/SEG3

RD4/SEG4

35 36

RD5/SEG5

RD6/SEG6

RD7/SEG7

64 63 62 61

RJ0/SEG32

RJ1/SEG33

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

RJ2/SEG34 RJ3/SEG35 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC V

OSC2/CLKO/RA6 OSC1/CLKI/RA7 V

RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13 RJ7/SEG36 RJ6/SEG37

AVSS

RH5/SEG41

RH4/SEG40

RF0/AN5/SEG18

RF1/AN6/C2OUT/SEG19

REF-/SEG16

RA2/AN2/V

RA3/AN3/VREF+/SEG17

RA1/AN1

RA0/AN0

(1)

VDD

RJ5/SEG38

RJ4/SEG39

RC6/TX1/CK1

RC7/RX1/DT1

RA4/T0CKI/SEG14

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

RA5/AN4/HLVDIN/SEG15

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 3

PIC18F6390/6490/8390/8490

1.0 Device Overview ..........................................................................................................................................................................7

2.0 Oscillator Configurations ............................................................................................................................................................ 31

3.0 Power Managed Modes ............................... .. .... ..... .. .. .. .... .. .. .. ..... .. .... .. .. .. .. .. ....... .. .. .. .. .. .... ..... .................................................... 41

4.0 Reset .......................................................................................................................................................................................... 51

5.0 Memory Organization.................................................................................................................................................................65

6.0 Flash Progr a m Mem o ry............. ................. ................. ................................................ ...............................................................87

7.0 8 x 8 Hardware Multiplier...................................................................... ...................................................................................... 91

8.0 Interrupts .................................................................................................................................................................................... 93

9.0 I/O Ports................................ ................................................................................................................................................... 109

10.0 Timer0 Module ......................................................................................................................................................................... 131

11.0 Timer1 Module ......................................................................................................................................................................... 135

12.0 Timer2 Module ......................................................................................................................................................................... 141

13.0 Timer3 Module ......................................................................................................................................................................... 143

14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 147

15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157

16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 197

17.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUS ART ) ........................................................... 217

18.0 10-Bit Analog-to-Digital Converter (A/D) Module .....................................................................................................................231

19.0 Comparator Module.......................................................................... .... .. .... .. ......... .... .. .... ......................................................... 241

20.0 Comparator Voltage Reference Module................................................................................................................................... 247

21.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................251

22.0 Liquid Crystal Display (LCD) Driver Module.............................................................................................................................257

23.0 Special Features of the CPU.............. ................ ................. ................. ................. ............... .................................................... 281

24.0 Instruction Set Summary.......................................................................................................................................................... 295

25.0 Development Support............................................................................................................................................................... 345

26.0 Electrical Characteristics.......................................................................................................................................................... 351

27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 387

28.0 Packaging Informa tio n..... ................. ................ ................. ................. ...................................................................................... 389

Appendix A: Revision History............................................................................................................................................................. 393

Appendix B: Device Differences......................................................................................................................................................... 393

Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 394

Appendix D: Migration from Baseline to Enhanced Devices..............................................................................................................394

Appendix E: Migration from Mid-Range to Enhanced Devices ..........................................................................................................395

Appendix F: Migration from High-End to Enhanced Devices.............................................................................................................395

Index .................................................................................................................................................................................................. 397

On-Line Support.................................................................... .. .... .... .. ......... .. .... .... .. ......... .. .................................................................407

Systems Information and Upgrade Hot Line......................................................................................................................................407

Reader Response.............................................................................................................................................................................. 408

PIC18F6390/6490/8390/8490 Product Identification System ............................................................................................................ 409

DS39629B-page 4 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

 2004 Microchip Technology Inc. Preliminary DS39629B-page 5

PIC18F6390/6490/8390/8490

NOTES:

DS39629B-page 6 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the following devices:

• PIC18F6390 • PIC18F8390

• PIC18F6490 • PIC18F8490

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price. In addition to these features, the PIC18F6390/6490/8390/8490 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F6390/6490/8390/8490 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled, bu t the peripheral s still active. In these st ates, powe r consumpt ion can be reduced even further – t o as litt le as 4% of nor mal operation requirements.

• On-the-Fly Mode Switching: The power managed modes a re invo ked b y user code durin g operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 µA and 2.1 µA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F6390/6490/8390/8490 family offer nine different oscillator options, allowing users a wide range o f choices i n develo ping applica tion hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes, with the same

pin options as the External Clock modes.

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC source (approximately 31kHz, stable over temperature and V user selectable cl oc k frequ enc ie s betw ee n 125 kHz to 4 MHz for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds from 31 kHz to 32 MHz – all without using an external crystal or clock circuit.

Besides its ava ilability as a cloc k source, the intern al oscillator block pro vid es a s t ab le re fere nce source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller i s switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset or wake-up from Sleep mode until the primary clock source is available.

DD), as well as a range of six

 2004 Microchip Technology Inc. Preliminary DS39629B-page 7

PIC18F6390/6490/8390/8490

1.2 O ther Special Features

• Memory Endurance: The Flas h cells for prog ram memory are rated to last for approximately a thousand erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 100 years.

• Extended Instruction Set: The PIC18F6390/6490/8390/8490 family introduces an optional extension to th e PIC18 instr uction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as C.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation an d provides support for th e LIN bus protocol. Other enhancements include Automatic Baud Rate Detec tion an d a 16-bit Baud Rate Generator for improved resolu tion. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world, without using an external crystal (or its accompanying power requirement).

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated withou t wai ting for a sampling period and thus, reduces code overhead.

• Extended Watchdog Timer (WDT): This enhanced version in corpora tes a 1 6-bit pre scale r, allowing a time-out range from 4 ms to over 10 minutes that is s tabl e acros s opera ting vo lta ge and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F 6390/6490 /8390/8490 famil y are available in 64-pin (PIC18F6X90) and 80-pin (PIC18F8X90) packages. Block diagrams for the two groups are sho wn in Figure 1-1 and Figure 1-2, respectively.

The devices are differentiated from each other in three ways:

1. I/O Ports: 7 bidirectional ports on 64-pin

devices; 9 bidirectional ports on 80-pin devices.

2. LCD Pixels: 128 (32 SEGs x 4 COMs) pixels can

be driven by 64-pin devices; 192 (48 SEGs x 4 COMs) pixels can be driven by 80-pin devices.

3. Flash Program Memory: 8 Kbytes for

PIC18FX390 devices; 16 Kbytes for PIC18FX490.

All other features fo r device s in this family are identi cal. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

Like all Microchip PIC18 devices, members of the PIC18F6390/6490/8390/8490 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an “F” in the part number (such a s PIC18F63 90), acc ommoda te an operating V parts, designated by “LF” (such as PIC18LF6490), function over an extended VDD range of 2.0V to 5.5V.

DD range of 4.2V to 5.5V. Low-voltage

DS39629B-page 8 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-1: DEVICE FEATURES

Features PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 8K 16K 8K 16K Program Memory (Instruction s) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 Interrupt Sources 22 22 22 22 I/O Ports Ports A, B, C, D, E,

F, G

Number of pixels the LCD Driver can drive

Timers 4444 Capture/Compare/PWM Modules 2 2 2 2 Serial Communications MSSP, AUSART

10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, RESET

Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions;

Packages 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP

128 (32 SEGs x 4

COMs)

Enhanced USART

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G

128 (32 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

192 (48 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

192 (48 SEGs x 4

COMs)

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

 2004 Microchip Technology Inc. Preliminary DS39629B-page 9

PIC18F6390/6490/8390/8490

FIGURE 1-1: PIC18F6X90 (64-PIN) BLOCK DIAGRAM

Table Point e r <2 1 >

inc/dec logic

Address Latch

Program Memory

(48/64Kbytes)

Data Latch

Instruction Bus <16>

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

Table Latch

Data Bus<8>

PCH PCL

Data Latch

Data Memory (3.9 Kbytes)

Address Latch

Data Address<12>

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

Access

PORTA

PORTB

PORTC

RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 RA3/AN3/VREF+/SEG17 RA4/T0CKI/SEG14 RA5/AN4/HLVDIN/SEG15 OSC2/CLKO

RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

(3)

/RA6

/SEG13

/SEG12

(1)

BOR

HLVD

Comparators

ADC

10-bit

CCP1

Instruction

Decode and

Control

MSSP

Timer2Timer1 Timer3Timer0

EUSART1

BITOP

PRODLPRODH

8 x 8 Multiply

ALU<8>

PORTD

RD7/SEG7:RD0/SEG0

Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RE7 when CCP2MX is not set.

2: RG5 is only available when MCLR 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations ” for additional information.

functionality is disabled.

DS39629B-page 10 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

FIGURE 1-2: PIC18F8X90 (80-PIN) BLOCK DIAGRAM

Data Latch

Data Memory

(3.9 Kbytes)

Address Latch

Data Address<12>

Instruction

Decode and

Control

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Access

 2004 Microchip Technology Inc. Preliminary DS39629B-page 11

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

MCLR/VPP/RG5

MCLR VPP

RG5

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

CMOS

I/O

O O

I/O

Master Clear (input) or programming voltage (input).

TTL

— —

TTL

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage inpu t. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Osc ill ato r mode . In RC mode, OSC2 pin outputs CLKO, whi ch has 1/4 the frequency of OSC1 and denotes t he instruction cycle rate. General purpose I/O pin.

DD)

DS39629B-page 12 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V SEG16

RA3/AN3/V

RA3 AN3 V SEG17

RA4/T0CKI/SEG14

RA4 T0CKI SEG14

RA5/AN4/HLVDIN/SEG15

RA5 AN4 HLVDIN SEG15

RA6 See the OSC2/CLKO/RA6 pin.

REF-/SEG16

REF-

REF+/SEG17

REF+

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

I/O

ST/OD

Analog

I/O

TTL

Analog

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (Low) input. SEG16 output for LCD.

Digital I/O. Analog input 3. A/D reference voltage (High) input. SEG17 output for LCD.

Digital I/O. Open-drain when configured as output. Timer0 external clock input. SEG14 output for LCD.

Digital I/O. Analog input 4. Low-Voltage Detect input. SEG15 output for LCD.

RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

 2004 Microchip Technology Inc. Preliminary DS39629B-page 13

DD)

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0

RB0 INT0

RB1/INT1/SEG8

RB1 INT1 SEG8

Pin Number

TQFP

Buffer

Type

I/OITTL

I/O

TTL

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull- ups on all inputs.

Digital I/O.

External interrupt 0.

Digital I/O. External interrupt 1. SEG8 output for LCD.

RB2/INT2/SEG9

RB2 INT2 SEG9

RB3/INT3/SEG10

RB3 INT3 SEG10

RB4/KBI0/SEG11

RB4 KBI0 SEG11

RB5/KBI1

RB5 KBI1

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

I/O

TTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

I/OITTL

TTL

I/O

TTL

I/O

I/O I/O

TTL

Digital I/O. External interrupt 2. SEG9 output for LCD.

Digital I/O. External interrupt 3. SEG10 output for LCD.

Digital I/O. Interrupt-on-change pin. SEG11 output for LCD.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

DS39629B-page 14 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/CCP2

RC1 T1OSI

(1)

CCP2

RC2/CCP1/SEG13

RC2 CCP1 SEG13

RC3/SCK/SCL

RC3 SCK SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO/SEG12

RC5 SDO SEG12

I/O

I/O I/O

I/O I/O I/O

I/O

O O

—

CMOS

ST ST

Analog

ST ST ST

—

Analog

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture2 input/Compare2 output/PWM2 output.

Digital I/O. Capture1 input/Compare1 output/PWM1 output. SEG13 output for LCD.

Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchron ous serial clock input/output for I

Digital I/O. SPI data in.

C data I/O.

Digital I/O. SPI data out. SEG12 output for LCD.

C™ mode.

RC6/TX1/CK1

RC6 TX1 CK1

RC7/RX1/DT1

RC7 RX1 DT1

I/O

—

ST ST ST

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1).

 2004 Microchip Technology Inc. Preliminary DS39629B-page 15

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/SEG0

RD0 SEG0

RD1/SEG1

RD1 SEG1

RD2/SEG2

RD2 SEG2

RD3/SEG3

RD3 SEG3

RD4/SEG4

RD4 SEG4

RD5/SEG5

RD5 SEG5

RD6/SEG6

RD6 SEG6

RD7/SEG7

RD7 SEG7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

Digital I/O. SEG0 output for LCD.

Digital I/O. SEG1 output for LCD.

Digital I/O. SEG2 output for LCD.

Digital I/O. SEG3 output for LCD.

Digital I/O. SEG4 output for LCD.

Digital I/O. SEG5 output for LCD.

Digital I/O. SEG6 output for LCD.

Digital I/O. SEG7 output for LCD.

DD)

DS39629B-page 16 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

LCDBIAS1

LCDBIAS2

LCDBIAS3

COM0

RE4/COM1

RE4 COM1

RE5/COM2

RE5 COM2

RE6/COM3

RE6 COM3

RE7/CCP2/SEG31

RE7

(2)

CCP2 SEG31

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

I Analog BIAS1 input for LCD.

I Analog BIAS2 input for LCD.

I Analog BIAS3 input for LCD.

O Analog COM0 out put for LC D.

I/OOST

Analog

I/OOST

Analog

I/OOST

Analog

I/O I/O

ST ST

Analog

Digital I/O. COM1 output for LCD.

Digital I/O. COM2 output for LCD.

Digital I/O. COM3 output for LCD.

Digital I/O. Capture 2 input/Compare 2 output/PWM 2 output. SEG31 output for LCD.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 17

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5/SEG18

RF0 AN5 SEG18

RF1/AN6/C2OUT/SEG19

RF1 AN6 C2OUT SEG19

RF2/AN7/C1OUT/SEG20

RF2 AN7 C1OUT SEG20

RF3/AN8/SEG21

RF3 AN8 SEG21

RF4/AN9/SEG22

RF4 AN9 SEG22

RF5/AN10/CV

RF5 AN10

REF

CV SEG23

REF/SEG23

I/O

O O

I/O

O O

I/O

O O

ST Analog Analog

ST Analog

—

Analog

ST Analog

—

Analog

ST Analog Analog

ST Analog Analog Analog

Digital I/O. Analog input 5. SEG18 output for LCD.

Digital I/O. Analog input 6. Comparator 2 output. SEG19 output for LCD.

Digital I/O. Analog input 7. Comparator 1 output. SEG20 output for LCD.

Digital I/O. Analog input 8. SEG21 output for LCD.

Digital I/O. Analog input 9. SEG22 output for LCD.

Digital I/O. Analog input 10. Comparator reference voltage output. SEG23 output for LCD.

RF6/AN11/SEG24

RF6 AN11 SEG24

RF7/SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

DS39629B-page 18 Preliminary  2004 Microchip Technology Inc.

/SEG25 RF7 SS SEG25

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

I/O

ST Analog Analog

TTL

Analog

Digital I/O. Analog input 11. SEG24 output for LCD.

Digital I/O. SPI™ slave select input. SEG25 output for LCD.

DD)

PIC18F6390/6490/8390/8490

TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/SEG30

RG0 SEG30

RG1/TX2/CK2/SEG29

RG1 TX2 CK2 SEG29

RG2/RX2/DT2/SEG28

RG2 RX2 DT2 SEG28

RG3/SEG27

RG3 SEG27

RG4/SEG26

RG4 SEG26

RG5 See MCLR VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.

SS 20 P — Ground reference for analog modules.

AV AVDD 19 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

I/OOST

Analog

I/O I/O

I/OOST

O O

—

Analog

ST ST ST

Analog

Digital I/O. SEG30 output for LCD.

Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). SEG29 output for LCD.

Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). SEG28 output for LCD.

Digital I/O. SEG27 output for LCD.

Digital I/O. SEG26 output for LCD.

/VPP/RG5 pin.

DD)

 2004 Microchip Technology Inc. Preliminary DS39629B-page 19

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

/VPP/RG5

MCLR

MCLR VPP

RG5

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

CMOS

I/O

O O

I/O

Master Clear (input) or programming voltage (input).

TTL

— —

TTL

Master Clear (Reset) input. This pin is an activ e-lo w Reset to the device. Programming voltage input. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

DD)

DS39629B-page 20 Preliminary  2004 Microchip Technology Inc.

PIC18F6390/6490/8390/8490

TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED)