MICROCHIP PIC18F6310, PIC18F6410, PIC18F8310, PIC18F8410 DATA SHEET

PIC18F6310/6410/8310/8410

Data Sheet

64/80-Pin Flash Microcontrollers

with nanoWatt Technology

 2004 Microchip Technology Inc. Preliminary DS39635A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS39635A-page ii Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

64/80-Pin Flash Microcontrollers with nanoWatt Technology

Power Managed Modes:

• Run: CPU on, peripheral s on

• Idle: CPU off, peripheral s on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 µA typical

• Sleep mode currents down to 0.1 µA typical

• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• T wo -Spe ed Os ci ll ator Start-up

Flexible Oscillator Struc ture:

• Four Crystal modes:

- LP: up to 200 kHz

- XT: up to 4 MHz

- HS: up to 40 MHz

- HSPLL: 4-10 MHz (16-40 MHz internal)

• 4x Phase Lock Loop (available for crystal and

internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shut down of dev ice if prim ary or secondary clock fails

External Memory Interface (PIC18F8310/8410 Devices only):

• Address capability of up to 2 Mbytes

• 16-bit/8-bit interface

Peripheral Highlight s:

• High current sink/source 25 mA/25 mA

• Four external interrupts

• Four input change interrupts

• Four 8-bit/16-bit Timer/Counter modules

• Up to 3 Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ (all 4 modes) and I Master and Slave modes

• Addressable USART module:

- Supports RS-485 and RS-232

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-Wake-up on Start bit

- Auto-Baud Detect

• 10-bit, up to 12-channel Analog-to-Digital Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

2

C™

Special Microcontroller Features:

• C compiler optimized architecture:

- Optional extended instruct ion set designed to

optimize re-entrant code

• 1000 erase/write cycle Flash pr ogram memory typical

• Flash Retention: 100 years typical

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

- 2% stability over V

• In-Circuit Serial Programming ™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

DD and temperature

Program Memory

Device

PIC18F6310 8K/0 4096/0 768 54 12 3 Y Y 1/1 2 1/3 N PIC18F6410 16K/0 8192/0 768 54 12 3 Y Y 1/1 2 1/3 N PIC18F8310 8K/2M 4096/1M 768 70 12 3 Y Y 1/1 2 1/3 Y PIC18F8410 16K/2M 8192/1M 768 70 12 3 Y Y 1/1 2 1/3 Y

 2004 Microchip Technology Inc. Preliminary DS39635A-page 1

(On-Board/External)

Flash

(bytes)

# Single-Word

Instructions

Data

Memory

SRAM (bytes)

I/O

10-bit

A/D (ch)

CCP

(PWM)

SPI™

MSSP

Master

I2C™

EUSART/

AUSART

Comparators

Timers

8/16-bit

Ext. Bus

PIC18F6310/6410/8310/8410

Pin Diagrams

64-Pin TQFP

(1)

RE2/CS

RE3

RE4

RE5

RE6

RE7/CCP2

RD0/PSP0

VDDVSS

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RE1/WR

RE0/RD

RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2

RG3

RG5/MCLR

RF5/AN10/CV

RF2/AN7/C1OUT

/VPP RG4

VSS

VDD

RF7/SS

RF6/AN11

REF

RF4/AN9 RF3/AN8

64

63 62 61

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26

RF0/AN5

RF1/AN6/C2OUT

DD

AV

AVSS

PIC18F6310 PIC18F6410

REF-

RA1/AN1

RA2/AN2/V

RA3/AN3/VREF+

RA0/AN0

54 53 52 5158 57 56 5560 59

27 28

SS

V

VDD

RA5/AN4/HLVDIN

29 30

(1)

RA4/T0CKI

50 49

31

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

RC6/TX1/CK1

RC7/RX1/DT1

RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC

SS

V OSC2/CLKO/RA6 OSC1/CLKI/RA7

DD

V RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

DS39635A-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

PIC18F6310/6410/8310/8410

/AD15

(1)

RH2/A18 RH3/A19

RE1/AD9/WR

RE0/AD8/RD

RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2

RG3

RG5/MCLR

RF5/AN10/CV

RF2/AN7/C1OUT

/VPP RG4

VSS VDD

RF7/SS

RF6/AN11

REF

RF4/AN9 RF3/AN8

RH7 RH6

RE2/AD10/CS

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/CCP2

RH0/A16

RH1/A17

80

79

78

77 76 75

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32

RD0/AD0/PSP0

PIC18F8310 PIC18F8410

DD

V

VSS

RD1/AD1/PSP1

RD2/AD2/PSP2

RD3/AD3/PSP3

RD4/AD4/PSP4

RD5/AD5/PSP5

RD6/AD6/PSP6

RD7/AD7/PSP7

RJ0/ALE

RJ1/OE

68 67 66 6572 71 70 6974 73

33 34

64 63 62 61

37

35 36 38

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

39

RJ2/WRL RJ3/WRH RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC

SS

V OSC2/CLKO/RA6 OSC1/CLKI/RA7

DD

V RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RJ7/UB RJ6/LB

(1)

RH5

RH4

RA1/AN1

RA0/AN0

SS

V

DD

AV

RF0/AN5

RF1/AN6/C2OUT

REF-

AVSS

RA2/AN2/V

RA3/AN3/VREF+

VDD

RA5/AN4/HLVDIN

(1)

RA4/T0CKI

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

RJ5/CE

RJ4/BA0

RC6/TX1/CK1

RC7/RX1/DT1

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

 2004 Microchip Technology Inc. Preliminary DS39635A-page 3

PIC18F6310/6410/8310/8410

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2004 Microchip Technology Inc. Preliminary DS39635A-page 5

PIC18F6310/6410/8310/8410

NOTES:

DS39635A-page 6 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the following devices:

• PIC18F6310 • PIC18LF6310

• PIC18F6410 • PIC18LF6410

• PIC18F8310 • PIC18LF8310

• PIC18F8410 • PIC18LF8410

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price. In addition to these features, the PIC18F6310/6410/8310/8410 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F6310/6410/8310/8410 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled, bu t the peripheral s still active. In these st ates, powe r consumpt ion can be reduced even further – t o as litt le as 4% of nor mal operation requirements.

• On-the-Fly Mode Switching: The power managed modes a re invo ked b y user code durin g operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 µA and 2.1 µA, respectively.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F6310/6410/8310/8410 family offer nine different oscillator options, allowing users a wide range o f choices i n develo ping applica tion hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes, with the same

pin options as the External Clock modes.

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC source (approximately 31kHz, stable over temperature and V user selectable cl oc k frequ enc ie s betw ee n 125 kHz to 4 MHz for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds from 31 kHz to 32 MHz – all without using an external crystal or clock circuit.

Besides its ava ilability as a cloc k source, the intern al oscillator block pro vid es a s t ab le re fere nce source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller i s switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset or wake-up from Sleep mode until the primary clock source is available.

DD), as well as a range of six

 2004 Microchip Technology Inc. Preliminary DS39635A-page 7

PIC18F6310/6410/8310/8410

1.2 Other Special Features

• Memory Endurance: The Flas h cells f or prog ram memory are rated to last for approximately a thousand erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 100 years.

• External Memory Interface: For those applications where mo re p r ogra m o r data storage is needed, the PIC18F 8310/8 410 dev ices provid e the ability to access external memory devices. The memory interface is configurable for both 8-bit and 16-bit data widths and uses a standard range of control signals to enable communication with a wide range of memory devices. With their 21-bit program counters, the 80-pin dev ic es can access a linear memory space of up to 2 Mbytes.

• Extended Instruction Set: The PIC18F6310/6410/8310/8410 family introduces an optional extension to th e PIC18 instr uction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as ‘C’.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation an d provides support for th e LIN bus protocol. Other enhancements include Automatic Baud Rate Detec tion an d a 16-bit Baud Rate Generator for improved resolu tion. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world, without using an external crystal (or its accompanying power requirement).

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated withou t wai ting for a sampling period and thus, reduces code overhead.

• Extended Watchdog Timer (WDT): This enhanced version in corpora tes a 1 6-bit pre scale r, allowing a time-out range from 4 ms to over 2 minutes that is stable across operating voltage and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F 6310/6410 /8310/8410 famil y are available in 64-pin (PIC18F6310/8310) and 80-pin (PIC18F6410/8410) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2, respectively.

The devices are differentiated from each other in three ways:

1. Flash Program Me mory: 8 Kbytes in PIC1 8FX310

devices, 16 Kbytes in PIC18FX410 devices.

2. I/O Ports: 7 bidirectional ports on 64-pin

devices, 9 bidirectional ports on 80-pin devices.

3. External Memory Interface: present on 80-pin

devices only.

All other features fo r device s in this family are identi cal. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

Like all Microchip PIC18 devices, members of the PIC18F6310/6410/8310/8410 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an “F” in the part number (such a s PIC18F63 10), acc ommoda te an operating V parts, designated by “LF” (such as PIC18LF6410), function over an extended V

DD range of 4.2V to 5.5V. Low-voltage

DD range of 2.0V to 5.5V.

DS39635A-page 8 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

TABLE 1-1: DEVICE FEATURES

Features PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 8K 16K 8K 16K Program Memory (Instruction s) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 External Memory Interface No No Yes Yes Interrupt Sources 22 22 22 22 I/O Ports Ports A, B, C, D, E,

F, G Timers 4444 Capture/Compare/PWM Modules 3 3 3 3 Serial Communications MSSP, AUSART

Enhanced USART Parallel Communications PSP PSP PSP PSP 10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions;

83 with Extended

Instruction Set

enabled

Packages 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP

Ports A, B, C, D, E,

F, G

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

Ports A, B, C, D, E,

F, G, H, J

MSSP, AUSART

Enhanced USART

POR, BOR, RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

 2004 Microchip Technology Inc. Preliminary DS39635A-page 9

PIC18F6310/6410/8310/8410

FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM

Instruction

Decode and

Control

Data Latch

Data Memory

(8/16 Kbytes)

Address Latc h

Data Address< 12>

BSR

12

Access

PORTA

PORTB

PORTC

RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/HLVDIN

RB0/INT0 RB1/INT1

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1

RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

(1)

DS39635A-page 10 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

FIGURE 1-2: PIC18F8310/8410 (80-PIN) BLOCK DIAGRAM

PORTA

PORTB

PORTC

PORTD

RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/HLVDIN OSC2/CLKO OSC1/CLKI

RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

(3)

/RA7

/RA6

(1)

OSC1

OSC2

T1OSI

T1OSO

MCLR

V

VDD,

8

PORTE

PRODLPRODH

8 x 8 Multiply

3

BITOP

(3)

(2)

SS

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply Programming

In-Circuit

Debugger

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

Precision Band Gap Reference

W

8

ALU<8>

8

PORTF

PORTH

RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT

RF3/AN8 RF4/AN9 RF5/AN10/CV RF6/AN11 RF7/SS

RH3/AD19:RH0/AD16 RH7:RH4

REF

Note 1: CCP2 multiplexing is determined by the settings of the CCP2MX and PM1:PM0 configuration bits.

2: RG5 is only available when MCLR 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations ” for additional information.

functionality is disabled.

 2004 Microchip Technology Inc. Preliminary DS39635A-page 11

PIC18F6310/6410/8310/8410

TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

RG5/MCLR/VPP

RG5 MCLR

VPP

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

39

40

7

I I

P

I

CMOS

I/O

O O

I/O

Master Clear (input) or programming voltage (input). ST ST

ST

TTL

— —

TTL

Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

DD)

DS39635A-page 12 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI

RA4 T0CKI

RA5/AN4/HLVDIN

RA5 AN4

HLVDIN RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

24

23

22

21

28

27

I/O

I/OIST/OD

I/O

TTL

I

Analog

TTL

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

ST

TTL

I

Analog

I

Analog

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Digital I/O. Open-drain when configured as output. Timer0 external clock input.

Digital I/O. Analog input 4. High/Low-Voltage Detect input.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 13

PIC18F6310/6410/8310/8410

TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0

RB0 INT0

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3

RB3 INT3

RB4/KBI0

RB4 KBI0

RB5/KBI1

RB5 KBI1

RB6/KBI2/PGC

RB6 KBI2 PGC

Pin Number

TQFP

48

47

46

45

44

43

42

Type

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

Buffer

Type

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0.

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

37

I/O I/O

TTL

I

TTL

ST

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

DS39635A-page 14 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI RC1/T1OSI/CCP2

RC1

T1OSI

(1)

CCP2 RC2/CCP1

RC2

CCP1 RC3/SCK/SCL

RC3

SCK

SCL RC4/SDI/SDA

RC4

SDI

SDA RC5/SDO

RC5

SDO RC6/TX1/CK1

RC6

TX1

CK1

30

29

33

34

35

36

31

I/O

O

I/O I/O

I/O I/O I/O

I/O I/O

I/O

O

I/O

O

I/O

ST

—

I

ST

CMOS

ST

ST ST

ST ST ST

ST

—

ST

—

ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output.

Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchronous serial clock input/output for I2C™ mode.

Digital I/O. SPI data in.

2

C data I/O.

I

Digital I/O. SPI data out.

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

RC7/RX1/DT1

RC7

RX1

DT1 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

 2004 Microchip Technology Inc. Preliminary DS39635A-page 15

32

I/O I/O

ST

I

ST ST

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1).

DD)

PIC18F6310/6410/8310/8410

TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/PSP0

RD0 PSP0

RD1/PSP1

RD1 PSP1

RD2/PSP2

RD2 PSP2

RD3/PSP3

RD3 PSP3

RD4/PSP4

RD4 PSP4

RD5/PSP5

RD5 PSP5

RD6/PSP6

RD6 PSP6

RD7/PSP7

RD7 PSP7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

58

55

54

53

52

51

50

49

I/O I/O

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

Digital I/O. Parallel Slave Port data.

DD)

DS39635A-page 16 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/RD

RE0

RD RE1/WR

RE1

WR RE2/CS

RE2

CS RE3 63 I/O ST Digital I/O. RE4 62 I/O ST Digital I/O. RE5 61 I/O ST Digital I/O. RE6 60 I/O ST Digital I/O. RE7/CCP2

RE7

(2)

CCP2 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

64

59

2

I/O

I

1

I/O

I

I/O

I

I/O I/O

ST

TTL

ST

TTL

ST

TTL

ST ST

Digital I/O. Read control for Parallel Slave Port.

Digital I/O. Write control for Parallel Slave Port.

Digital I/O. Chip select control for Parallel Slave Port.

Digital I/O. Capture 2 input/Compare 2 output/PWM 2 output.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 17

PIC18F6310/6410/8310/8410

TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5

RF0 AN5

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

REF

18

17

16

15

14

13

12

I/O

O

I/O

O

I/O

O

I/O

ST

I

Analog

ST

I

Analog

—

ST

I

Analog

—

ST

I

Analog

ST

I

Analog

ST

I

Analog Analog

ST

I

Analog

Digital I/O. Analog input 5.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

RF7/SS

RF7 SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

Pin Number

11

Type

I/O

ST

I

TTL

Digital I/O. SPI slave select input.

DS39635A-page 18 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/CCP3

RG0

CCP3 RG1/TX2/CK2

RG1

TX2

CK2 RG2/RX2/DT2

RG2

RX2

DT2 RG3 6 I/O ST Digital I/O. RG4 8 I/O ST Digital I/O. RG5 See RG5/MCLR

VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.

SS 20 P — Ground refer ence for analog modules.

AV AVDD 19 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.

3

I/O I/O

4

I/O

O

I/O

5

I/O

I

I/O

ST ST

ST

—

ST

ST ST ST

Digital I/O. Capture 3 input/Compare 3 output/PWM 3 output.

Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2).

Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2).

/VPP pin.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 19

PIC18F6310/6410/8310/8410

TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

RG5/MCLR/VPP

RG5 MCLR

VPP

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2 CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

49

50

9

I I

P

I

CMOS

I/O

O O

I/O

Master Clear (input) or programming voltage (input). ST ST

ST

TTL

— —

TTL

Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage inp ut.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

DD)

DS39635A-page 20 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

PORTA is a bidirectional I/O port.

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/V

RA2 AN2 V

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI

RA4 T0CKI

RA5/AN4/HLVDIN

RA5 AN4

HLVDIN RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin.

REF-

REF+

30

29

28

27

34

33

I/O

I/OIST/ODSTDigital I/O. Open-drain when configured as output.

I/O

TTL

I

Analog

TTL

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Timer0 external clock input.

Digital I/O. Analog input 4. High/Low-Voltage Detect input.

 2004 Microchip Technology Inc. Preliminary DS39635A-page 21

PIC18F6310/6410/8310/8410

TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0

RB0 INT0

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3/CCP2

RB3 INT3

(1)

CCP2

Pin Number

TQFP

58

57

56

55

Type

I/O

I

I/O

I

I/O

I

I/O

I

O

Buffer

Type

TTL

ST

TTL

ST

TTL

ST

TTL

ST

Analog

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0.

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3. Capture 2 input/Compare 2 output/PWM 2 output.

RB4/KBI0

RB4 KBI0

RB5/KBI1

RB5 KBI1

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

54

53

52

47

I/O

I/O I/O

TTL

I

TTL

I

TTL

I

TTL

ST

TTL

I

TTL

ST

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ program mi ng clo ck pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

DS39635A-page 22 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI RC1/T1OSI/CCP2

RC1

T1OSI

(2)

CCP2 RC2/CCP1

RC2

CCP1 RC3/SCK/SCL

RC3

SCK

SCL RC4/SDI/SDA

RC4

SDI

SDA RC5/SDO

RC5

SDO RC6/TX1/CK1

RC6

TX1

CK1 RC7/RX1/DT1

RC7

RX1

DT1 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

36

35

43

44

45

46

37

38

I/O

O

I/O I/O

I/O I/O I/O

I/O I/O

I/O

O

I/O

O

I/O

I/O I/O

ST

—

I

ST

CMOS

ST

ST ST

ST ST ST

ST

—

ST

—

ST

ST ST ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output.

Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in. I2C data I/O .

Digital I/O. SPI data out.

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1).

2

C™ mode.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 23

PIC18F6310/6410/8310/8410

TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTD is a bidirectional I/O port.

RD0/AD0/PSP0

RD0 AD0 PSP0

RD1/AD1/PSP1

RD1 AD1 PSP1

RD2/AD2/PSP2

RD2 AD2 PSP2

RD3/AD3/PSP3

RD3 AD3 PSP3

RD4/AD4/PSP4

RD4 AD4 PSP4

RD5/AD5/PSP5

RD5 AD5 PSP5

72

69

68

67

66

65

I/O I/O I/O

ST TTL TTL

Digital I/O. External memory address/data 0. Parallel Slave Port data.

Digital I/O. External memory address/data 1. Parallel Slave Port data.

Digital I/O. External memory address/data 2. Parallel Slave Port data.

Digital I/O. External memory address/data 3. Parallel Slave Port data.

Digital I/O. External memory address/data 4. Parallel Slave Port data.

Digital I/O. External memory address/data 5. Parallel Slave Port data.

RD6/AD6/PSP6

RD6 AD6 PSP6

RD7/AD7/PSP7

RD7 AD7 PSP7

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

64

63

I/O I/O I/O

ST TTL TTL

Digital I/O. External memory address/data 6. Parallel Slave Port data.

Digital I/O. External memory address/data 7. Parallel Slave Port data.

DD)

DS39635A-page 24 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTE is a bidirectional I/O port.

RE0/AD8/RD

RE0 AD8 RD

RE1/AD9/WR

RE1 AD9 WR

RE2/AD10/CS

RE2 AD10 CS

RE3/AD11

RE3 AD11

RE4/AD12

RE4 AD12

RE5/AD13

RE5 AD13

RE6/AD14

RE6 AD14

78

77

76

75

74

4

I/O I/O

I

3

I/O I/O

I

I/O I/O

I

I/O I/O

ST TTL TTL

ST TTL

Digital I/O. External memory address/data 8. Read control for Parallel Slave Port.

Digital I/O. External memory address/data 9. Write control for Parallel Slave Port.

Digital I/O. External memory address/data 10. Chip Select control for Parallel Slave Port.

Digital I/O. External memory address/data 11.

Digital I/O. External memory address/data 12.

Digital I/O. External memory address/data 13.

Digital I/O. External memory address/data 14.

RE7/CCP2/AD15

RE7

(3)

CCP2 AD15

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

73

I/O I/O I/O

ST

ST TTL

Digital I/O. Capture 2 input/Compare 2 output/PWM 2 output. External memory address/data 15.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 25

PIC18F6310/6410/8310/8410

TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTF is a bidirectional I/O port.

RF0/AN5

RF0 AN5

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

REF

24

23

18

17

16

15

14

I/O

ISTAnalog

I/O

I

O

I/O

I

O

I/O

ISTAnalog

I/O

ISTAnalog

I/O

I

O

I/O

ISTAnalog

ST

Analog

—

ST

Analog

—

ST Analog Analog

Digital I/O. Analog input 5.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

RF7/SS

RF7 SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

13

I/O

ST

I

TTL

Digital I/O. SPI slave select input.

DD)

DS39635A-page 26 Preliminary  2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410

T ABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/CCP3

RG0 CCP3

RG1/TX2/CK2

RG1 TX2 CK2

RG2/RX2/DT2

RG2 RX2

DT2 RG3 8 I/O ST Digital I/O. RG4 10 I/O ST Digital I/O. RG5 See RG5/MCLR

RH0/AD16

RH0

AD16 RH1/AD17

RH1

AD17 RH2/AD18

RH2

AD18

79

80

5

I/O I/O

6

I/O

O

I/O

7

I/O

I

I/O

I/O I/O

1

I/O I/O

ST ST

ST

—

ST

ST ST ST

ST

TTL

ST

TTL

ST

TTL

Digital I/O.

Capture 3 input/Compare 3 output/PWM 3 output.

Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2).

Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2).

PORTH is a bidirectional I/O port.

Digital I/O. External memory address/data 16.

Digital I/O. External memory address/data 17.

Digital I/O. External memory address/data 18.

/VPP pin.

RH3/AD19

RH3

AD19 RH4 22 I/O ST Digital I/O. RH5 21 I/O ST Digital I/O. RH6 20 I/O ST Digital I/O. RH7 19 I/O ST Digital I/O.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

2

I/O I/O

ST

TTL

Digital I/O. External memory address/data 19.

DD)

 2004 Microchip Technology Inc. Preliminary DS39635A-page 27

PIC18F6310/6410/8310/8410

TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

PORTJ is a bidirectional I/O port.

RJ0/ALE

RJ0 ALE

RJ1/OE

RJ1 OE

RJ2/WRL

RJ2 WRL

RJ3/WRH

RJ3 WRH

RJ4/BA0

RJ4 BA0

RJ5/CE

RJ4 CE

RJ6/LB

RJ6 LB

RJ7/UB

RJ7 UB

VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.

DD 12, 32, 48, 71 P — Positive supply for logic and I/O pins.

V AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except

Microcontroller mode).

2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).

62

61

60

59

39

40

41

42

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

Digital I/O. External memory address latch enable.

Digital I/O. External memory output enable.

Digital I/O. External memory write low control.

Digital I/O. External memory write high control.

Digital I/O. External memory Byte Address 0 control.

Digital I/O External memory chip enable control.

Digital I/O. External memory low byte control.

Digital I/O. External memory high byte control.

DD)

DS39635A-page 28 Preliminary  2004 Microchip Technology Inc.

MICROCHIP PIC18F6310, PIC18F6410, PIC18F8310, PIC18F8410 DATA SHEET

Power Managed Modes:

Flexible Oscillator Struc ture:

External Memory Interface (PIC18F8310/8410 Devices only):

Peripheral Highlight s:

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Continued)

Table of Contents

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES

FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F8310/8410 (80-PIN) BLOCK DIAGRAM