MICROCHIP PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523 DATA SHEET

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PIC18F2423/2523/4423/4523

Data Sheet

28/40/44-Pin, Enhanced Flash

Microcontrollers with 12-Bit A/D

and nanoWatt Technology

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEEL

code hopping devices, Serial

PIC18F2423/2523/4423/4523

28/40/44-Pin, Enhanced Flash Microcontrollers with

12-Bit A/D and nanoWatt Technology

Peripheral Highlights:

• 12-bit, up to 13-channel Analog-to-Digital

Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

• High-current sink/source 25 mA/25 mA

• Three programmable external interrupts

• Four input change interrupts

• Up to 2 Capture/Compare/PWM (CCP) modules,

one with Auto-Shutdown (28-pin devices)

• Enhanced Capture/Compare/PWM (ECCP)

module (40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPI (all 4 modes) and I Master and Slave modes

• Enhanced USART module:

- Supports RS-485, RS-232 and LIN 1.2

- RS-232 operation using internal oscillator block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect

C™

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA, typical

• Sleep mode current down to 0.1 μA, typical

• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V

• Watchdog Timer: 2.1 μA

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, up to 25 MHz

• 4x Phase Lock Loop (available for crystal and internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 25 MHz

• Internal oscillator block:

- 8 user-selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if external clock stops

Special Microcontroller Features:

• C compiler optimized architecture:

- Optional extended instruction set designed to

optimize re-entrant code

• 100,000 erase/write cycle Enhanced Flash program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory typical

• Flash/Data EEPROM Retention: 100 years typical

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply In-Circuit Serial Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Operating voltage range: 2.0V to 5.5V

• Programmable 16-level High/Low-Voltage Detection (HLVD) module:

- Supports interrupt on High/Low-Voltage Detection

• Programmable Brown-out Reset (BOR):

- With software enable option

Program Memory Data Memory

Device

PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3

PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3

PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3

PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3

Flash

(bytes)

# Single-Word

Instructions

SRAM (bytes)

EEPROM

(bytes)

I/O

12-Bit

A/D (ch)

CCP/

ECCP

(PWM)

SPI

MSSP

Master

C™

Comp.

EUSART

Timers

8/16-Bit

PIC18F2423/2523/4423/4523

Pin Diagrams

28-Pin PDIP, SOIC

28-Pin QFN

RA5/AN4/SS

(1)

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT

OSC2/CLKO

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT

OSC1/CLKI

(3)

RC2/CCP1

RC3/SCK/SCL

V /RA7 /RA6

1 2 3 4 5 6 7

(2)

8 9 10 11 12 13 14

PIC18F2423

/VPP/RE3

MCLR

RA0/AN0

RA1/AN1

28 27 26 25 24 23 22 21 20

PIC18F2523

19 18 17 16 15

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4KBI0/AN11

RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10

RB0/INT0/FLT0/AN12

V VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

(2)

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA5/AN4/SS

RA4/T0CKI/C1OUT

/HLVDIN/C2OUT

OSC1/CLKI

OSC2/CLKO

(3)

V /RA7 /RA6

232425262728

1 2 3

PIC18F2423

PIC18F2523

5 6 7

(2)

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

10 11

RC2/CCP1

12 13 14

RC3/SCK/SCL

RC5/SDO

RC4/SDI/SDA

RC6/TX/CK

21 20 19 18 17 16 15

RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 V

VSS RC7/RX/DT

(2)

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

Pin Diagrams (Cont.’d)

40-Pin PDIP

PIC18F2423/2523/4423/4523

44-Pin TQFP

RA2/AN2/V

RA5/AN4/SS

OSC2/CLKO

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

MCLR/VPP/RE3

RA0/AN0 RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

/HLVDIN/C2OUT

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

VSS

OSC1/CLKI

(2)

/RA7

(2)

/RA6

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

15 16 17 18 19 20

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

(1)

40 39 38 37 36 35 34 33 32 31 30 29

PIC18F4523

PIC18F4423

28 27 26 25 24 23 22 21

(1)

RC2/CCP1/P1A

RC1/T1OSI/CCP2

RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2 RB2/INT2/AN8

RB1/INT1/AN10 RB0/INT0/FLT0/AN12 V

VSS RD7/PSP7/P1D RD6/PSP6/P1C

RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO

RC4/SDI/SDA RD3/PSP3

RD2/PSP2

(1)

RB5/KBI1/PGM

1819202122

/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

MCLR

RA0/AN0

363435

RA1/AN1

33 32 31 30 29

28 27 26 25 24 23

REF-/CVREF

RA3/AN3/VREF+

RA2/AN2/V

NC RC0/T1OSO/T13CKI OSC2/CLKO OSC1/CLKI

V VDD RE2/CS/AN7 RE1/WR RE0/RD RA5/AN4/SS RA4/T0CKI/C1OUT

(2)

/RA6

(2)

/RA7

/AN6

/AN5

/HLVDIN/C2OUT

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2

VDD

4443424140

1 2 3

PIC18F4423

(1)

5 6 7 8 9 10 11

121314

PIC18F4523

RB4/KBI0/AN11

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F2423/2523/4423/4523

Pin Diagrams (Cont.’d)

44-Pin QFN

(1)

RC7/RX/DT

RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

V VDD VDD

(2)

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RB6/KBI2/PGC

RB5/KBI1/PGM

1819202122

/VPP/RE3

RB7/KBI3/PGD

MCLR

4443424140

1 2 3 4 5

6 7 8 9 10 11

121314

(2)

RB3/AN9/CCP2

PIC18F4423 PIC18F4523

RB4/KBI0/AN11

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2

363435

RA1/AN1

RA0/AN0

REF-/CVREF

RA2/AN2/V

RC0/T1OSO/T13CKI

33 32 31 30 29 28 27 26 25 24

REF+

RA3/AN3/V

OSC2/CLKO OSC1/CLKI

V VSS VDD VDD RE2/CS/AN7 RE1/WR RE0/RD RA5/AN4/SS RA4/T0CKI/C1OUT

(3)

/RA6

(3)

/RA7

/AN6

/AN5

/HLVDIN/C2OUT

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F2423/2523/4423/4523

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset .......................................................................................................................................................................................... 41

5.0 Memory Organization................................................................................................................................................................. 53

6.0 Flash Program Memory.............................................................................................................................................................. 73

7.0 Data EEPROM Memory ............................................................................................................................................................. 83

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89

9.0 Interrupts .................................................................................................................................................................................... 91

10.0 I/O Ports ................................................................................................................................................................................... 105

11.0 Timer0 Module ......................................................................................................................................................................... 123

12.0 Timer1 Module ......................................................................................................................................................................... 127

13.0 Timer2 Module ......................................................................................................................................................................... 133

14.0 Timer3 Module ......................................................................................................................................................................... 135

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 139

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 205

19.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 227

20.0 Comparator Module.................................................................................................................................................................. 237

21.0 Comparator Voltage Reference Module ................................................................................................................................... 243

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 247

23.0 Special Features of the CPU.................................................................................................................................................... 253

24.0 Instruction Set Summary.......................................................................................................................................................... 271

25.0 Development Support............................................................................................................................................................... 321

26.0 Electrical Characteristics.......................................................................................................................................................... 325

27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 363

28.0 Packaging Information.............................................................................................................................................................. 365

Appendix A: Revision History............................................................................................................................................................. 373

Appendix B: Device Differences ........................................................................................................................................................ 373

Appendix C: Conversion Considerations ........................................................................................................................................... 374

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 374

Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 375

Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 375

Index ................................................................................................................................................................................................. 377

The Microchip Web Site..................................................................................................................................................................... 387

Customer Change Notification Service .............................................................................................................................................. 387

Customer Support .............................................................................................................................................................................. 387

Reader Response .............................................................................................................................................................................. 388

PIC18F2423/2523/4423/4523 Product Identification System ............................................................................................................ 389

PIC18F2423/2523/4423/4523

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

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Errata

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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using.

Customer Notification System

PIC18F2423/2523/4423/4523

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices:

• PIC18F2423

• PIC18F2523

• PIC18F4423

• PIC18F4523

This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. On top of these features, the PIC18F2423/2523/4423/ 4523 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2423/2523/4423/4523 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

• On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 26.0 “Electrical Characteristics” for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2423/2523/4423/4523 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same

pin options as the External Clock modes.

• An internal oscillator block which provides an

8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40 MHz from the HS clock source. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz, all without using an external crystal or clock circuit.

Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

PIC18F2423/2523/4423/4523

1.2 Other Special Features

• 12-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead.

• Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F2423/ 2523/4423/4523 family introduces an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C.

• Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions and auto-restart, to reactivate outputs once the condition has cleared.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 26.0 “Electrical Characteristics” for time-out periods.

1.3 Details on Individual Family Members

Devices in the PIC18F2423/2523/4423/4523 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five ways:

1. Flash program memory (16 Kbytes for

PIC18F2423/4423 devices and 32 Kbytes for PIC18F2523/4523).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports on 28-pin devices,

5 bidirectional ports on 40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have 2 standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module).

5. Parallel Slave Port (present only on 40/44-pin

devices).

All other features for devices in this family are identical. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and Table 1-3.

Members of the PIC18F2423/2523/4423/4523 family are available only as low-voltage devices, designated by “LF” (such as PIC18LF2423), and function over a

DD range of 2.0V to 3.6V.

PIC18F2423/2523/4423/4523

TABLE 1-1: DEVICE FEATURES

Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 16384 32768 16384 32768

Program Memory (Instructions)

Data Memory (Bytes) 768 1536 768 1536

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/Compare/PWM Modules

Serial Communications MSSP,

Parallel Communications (PSP) No No Yes Yes

12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Resets (and Delays) POR, BOR,

Underflow (PWRT, OST),

Programmable High/Low-Voltage Detect

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

Packages 28-pin PDIP

8192 16384 8192 16384

0011

Enhanced USART

RESET Instruction,

Stack Full, Stack

MCLR

(optional), WDT

Ye s Ye s Ye s Ye s

83 with Extended

Instruction Set enabled

28-pin SOIC

28-pin QFN

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

28-pin PDIP 28-pin SOIC

28-pin QFN

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

40-pin PDIP 44-pin QFN

44-pin TQFP

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full, Stack

Underflow (PWRT, OST),

MCLR (optional), WDT

75 Instructions;

83 with Extended

Instruction Set enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

PIC18F2423/2523/4423/4523

FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Instruction Bus <16>

(3)

OSC1

(3)

OSC2

T1OSI

T1OSO

(2)

MCLR

VDD,

Table Latch

ROM Latch

Instruction

Decode and

Control

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply Programming

In-Circuit

Debugger

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

Fail-Safe

Clock Monitor

Data Bus<8>

State Machine Control Signals

Timer

Reset

Timer

Reset

Data Latch

Data Memory

( 3.9 Kbytes )

Address Latch

Data Address<12>

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address Decode

BITOP

Precision Band Gap Reference

Access

Bank

PRODLPRODH

8 x 8 Multiply

ALU<8>

PORTA

RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS OSC2/CLKO OSC1/CLKI

/HLVDIN/C2OUT

(3)

/RA6

(3)

/RA7

PORTB

RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2

(1)

RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD

PORTC

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2

(1)

RC2/CCP1 RC3/SCK/SCL

RC4/SDI/SDA RC5/SDO

RC6/TX/CK RC7/RX/DT

PORTE

MCLR/VPP/RE3

(2)

BOR

HLVD

Data

EEPROM

CCP1

CCP2

MSSP

Timer2Timer1 Tim er3Timer0

EUSARTComparator

ADC

12-Bit

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

functionality is disabled.

PIC18F2423/2523/4423/4523

FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM

Table Pointer<21>

inc/dec logic

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Instruction Bus <16>

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

ROM Latch

Instruction

Decode and

Control

Data Bus<8>

PCH PCL

State Machine Control Signals

PORTA

Data Latch

Data Memory

( 3.9 Kbytes )

Address Latch

Data Address<12>

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

Decode

Access

Bank

PORTB

PORTC

RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS OSC2/CLKO OSC1/CLKI

/HLVDIN/C2OUT

(3)

/RA6

(3)

/RA7

RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2

(1)

RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD

RC0/T1OSO/T13CKI RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA

RC5/SDO RC6/TX/CK RC7/RX/DT

PRODLPRODH

OSC1

OSC2

T1OSI

T1OSO

MCLR

VDD,

BOR

HLVD

8 x 8 Multiply

BITOP

(3)

(2)

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

Data

EEPROM

ECCP1

Start-up Timer

Clock Monitor

CCP2

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

MSSP

Precision Band Gap Reference

Timer2Timer1 Timer3Timer0

EUSARTComparator

ALU<8>

ADC

12-Bit

PORTD

RD0/PSP0 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D

PORTE

RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 MCLR/VPP/RE3

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR

functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

:RD4/PSP4

(2)

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

MCLR

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP, SOIC

126

10 7

QFN

Typ e

I/O

Buffer

Type

CMOS

TTL

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/VREF-/CVREF

RA2 AN2

REF-

V CV

REF

RA3/AN3/VREF+

RA3 AN3

REF+

RA4/T0CKI/C1OUT

RA4 T0CKI C1OUT

RA5/AN4/SS C2OUT

RA5 AN4 SS HLVDIN C2OUT

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

/HLVDIN/

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP, SOIC

227

328

QFN

Buffer

Typ e

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

I/O

TTL

Analog

TTL

Analog

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

ST ST —

—

Digital I/O. Timer0 external clock input. Comparator 1 output.

Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

Description

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RB0/INT0/FLT0/AN12

RB0 INT0 FLT0 AN12

RB1/INT1/AN10

RB1 INT1 AN10

RB2/INT2/AN8

RB2 INT2 AN8

RB3/AN9/CCP2

RB3 AN9

(1)

CCP2

RB4/KBI0/AN11

RB4 KBI0 AN11

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP, SOIC

21 18

22 19

23 20

24 21

25 22

26 23

27 24

28 25

QFN

Typ e

I/O

I I I

I/O

I I

I/O

I I

I/O

I I

I/O

Buffer

Type

TTL

ST ST

Analog

TTL

Analog

TTL

Analog

TTL

Analog

TTL TTL

Analog

TTL TTL

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. PWM Fault input for CCP1. Analog input 12.

Digital I/O. External interrupt 1. Analog input 10.

Digital I/O. External interrupt 2. Analog input 8.

Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Interrupt-on-change pin. Analog input 11.

Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/CCP2

RC1 T1OSI

(2)

CCP2

RC2/CCP1

RC2 CCP1

RC3/SCK/SCL

RC3 SCK SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO

RC5 SDO

RC6/TX/CK

RC6 TX CK

RC7/RX/DT

RC7 RX DT

RE3 — — — — See MCLR

VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

DD 20 17 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O=Output P =Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PDIP, SOIC

11 8

12 9

13 10

14 11

15 12

16 13

17 14

18 15

QFN

Buffer

Typ e

Type

I/O

Analog

I/O

I/O I/OSTST

I/O I/O I/O

I/O

I/OOST

I/O

PORTC is a bidirectional I/O port.

ST — ST

ST ST ST

—

ST — ST

ST ST ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in.

C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK).

/VPP/RE3 pin.

Description

C™ mode.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

VPP RE3

OSC1/CLKI/RA7

OSC1

CLKI

RA7

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Type

I/O

Buffer

Typ e

CMOS

TTL

—

TTL

Description

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin.

Oscillator crystal or clock output.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0 AN0

RA1/AN1

RA1 AN1

RA2/AN2/VREF-/CVREF

RA2 AN2 VREF-

REF

RA3/AN3/V

RA3 AN3 V

RA4/T0CKI/C1OUT

RA4 T0CKI C1OUT

RA5/AN4/SS C2OUT

RA5 AN4 SS HLVDIN C2OUT

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

REF+

/HLVDIN/

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Buffer

Type

Typ e

I/OITTL

Analog

I/OITTL

Analog

I/O

Analog

I/O

Analog

I/O

Analog I I

Analog

PORTA is a bidirectional I/O port.

Digital I/O. Analog input 0.

Digital I/O. Analog input 1.

TTL

ST ST

—

TTL

—

Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input. Comparator 1 output.

Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

Description

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0/AN12

RB0 INT0 FLT0 AN12

RB1/INT1/AN10

RB1 INT1 AN10

RB2/INT2/AN8

RB2 INT2 AN8

RB3/AN9/CCP2

RB3 AN9

(1)

CCP2

RB4/KBI0/AN11

RB4 KBI0 AN11

RB5/KBI1/PGM

RB5 KBI1 PGM

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Type

I/O

I I I

I/O

I I

I/O

I I

I/O

I I

I/O

Buffer

Typ e

TTL

ST ST

Analog

TTL

Analog

TTL

Analog

TTL

Analog

TTL TTL

Analog

TTL TTL

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. PWM Fault input for Enhanced CCP1. Analog input 12.

Digital I/O. External interrupt 1. Analog input 10.

Digital I/O. External interrupt 2. Analog input 8.

Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Interrupt-on-change pin. Analog input 11.

Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/CCP2

RC1 T1OSI

(2)

CCP2

RC2/CCP1/P1A

RC2 CCP1 P1A

RC3/SCK/SCL

RC3 SCK

SCL

RC4/SDI/SDA

RC4 SDI SDA

RC5/SDO

RC5 SDO

RC6/TX/CK

RC6 TX CK

RC7/RX/DT

RC7 RX DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

18 37 37

23 42 42

24 43 43

25 44 44

26 1 1

Buffer

Type

I/O

CMOS

I/O

I/O I/O

I/O

I/OOST

I/O

Typ e

PORTC is a bidirectional I/O port.

—

ST ST

—

ST ST

ST ST ST

—

ST ST ST

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output.

Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. Enhanced CCP1 output.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in.

C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK).

Description

C™ mode.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/PSP0

RD0 PSP0

RD1/PSP1

RD1 PSP1

RD2/PSP2

RD2 PSP2

RD3/PSP3

RD3 PSP3

RD4/PSP4

RD4 PSP4

RD5/PSP5/P1B

RD5 PSP5 P1B

RD6/PSP6/P1C

RD6 PSP6 P1C

RD7/PSP7/P1D

RD7 PSP7 P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Buffer

Type

Typ e

I/O I/OSTTTL

I/O I/O

TTL

I/O I/O

TTL

I/O I/O

TTL

Description

PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.

Digital I/O. Parallel Slave Port data.

—

Digital I/O. Parallel Slave Port data. Enhanced CCP1 output.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/RD

RE1/WR

RE2/CS

RE3 — — — — — See MCLR/VPP/RE3 pin.

VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins.

/AN5 RE0 RD

AN5

/AN6 RE1 WR

AN6

/AN7 RE2 CS

AN7

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

Type

I/O

Buffer

Typ e

TTL

Analog

TTL

Analog

TTL

Analog

Description

PORTE is a bidirectional I/O port.

Digital I/O. Read control for Parallel Slave Port (see also WR Analog input 5.

Digital I/O. Write control for Parallel Slave Port (see CS Analog input 6.

Digital I/O. Chip Select control for Parallel Slave Port (see related RD Analog input 7.

and CS pins).

and RD pins).

and WR).

DD 11, 32 7, 8,

28, 29

NC — 13 12, 13,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

7, 28 P — Positive supply for logic and I/O pins.

— — No connect.

33, 34

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

PIC18F2423/2523/4423/4523 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled

5. RC External Resistor/Capacitor with

OSC/4 Output on RA6

6. RCIO External Resistor/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with F

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with F

10. ECIO External Clock with I/O on RA6

OSC/4 Output

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

(1)

Note 1: See Table 2-1 and Table 2-2 for initial values of

2: A series resistor (R

3: R

OSC1

XTAL

(2)

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

Sleep

PIC18FXXXX

S) may be required for AT

Internal Logic

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq. OSC1 OSC2

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections.

The oscillator design requires the use of a parallel cut crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s specifications.

XT 3.58 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following Table 2-2 for additional information.

Note: When using resonators with frequencies

above 3.6 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any V

DD for

which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of R

S is 330Ω.

PIC18F2423/2523/4423/4523

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc. Typ e

Crystal

Freq.

LP 32 kHz 18 pF 18 pF

XT 1 MHz

4 MHz

HS 4 MHz

10 MHz 20 MHz 25 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected

DD and temperature range for the application.

See the notes following this table for additional information.

Crystals Used:

32 kHz 4 MHz

25 MHz 10 MHz

1 MHz 20 MHz

Note 1: When operating below 3V VDD, or when

using ceramic resonators above 3.6 MHz at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

S may be required to avoid overdriving

3: R

tuning fork crystals, such as those commonly used in LP mode or with the Timer1 oscillator. R crystal drive in other modes where waveform distortion could be an issue.

AN949, “Making Your Oscillator

See

Work”

4: Always verify oscillator performance over

the VDD and temperature range that is expected for the application. See

“Making Your Oscillator Work”

methods.

Typical Capacitor Values

Tested:

C1 C2

15 pF 15 pF

15 pF 15 pF 15 pF 15 pF

S may also be used to reduce

15 pF 15 pF

15 pF 15 pF 15 pF 15 pF

AN949,

for testing

An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC. CONFIGURATION)

Clock from Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.3 External Clock Input

The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK

INPUT OPERATION (EC CONFIGURATION)

Clock from Ext. System

OSC/4

The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

Clock from Ext. System

RA6

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

INPUT OPERATION (ECIO CONFIGURATION)

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

PIC18F2423/2523/4423/4523

2.4 RC Oscillator

For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors:

• supply voltage

• values of the external resistor (R

capacitor (C

EXT)

• operating temperature

Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as:

• normal manufacturing variation

• difference in lead frame capacitance between

package types (especially for low C

• variations within the tolerance of limits of R

EXT

and C

In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected.

FIGURE 2-5: RC OSCILLATOR MODE

VDD

REXT

OSC1

CEXT

VSS

Recommended values: 5K ≤ REXT ≤ 100 kΩ

OSC/4

OSC2/CLKO

EXT > 20 pF

The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

VDD

REXT

OSC1

EXT) and

EXT values)

EXT

Internal

Clock

PIC18FXXXX

Internal

Clock

2.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode.

The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 Configuration bits are programmed for HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM

(HS MODE)

HS Oscillator Enable

PLL Enable

(from Configuration Register 1H)

OSC2

OSC1

HS Mode

Crystal

Osc

FOUT

÷4

2.5.2 PLL AND INTOSC

The PLL is also available to the internal oscillator block when the INTOSC is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 “PLL in INTOSC Modes”.

Phase

Comparator

Loop Filter

VCO

SYSCLK

MUX

CEXT

VSS

RA6

Recommended values: 5K ≤ REXT ≤ 100 kΩ

I/O (OSC2)

EXT > 20 pF

PIC18FXXXX

PIC18F2423/2523/4423/4523

2.6 Internal Oscillator Block

The PIC18F2423/2523/4423/4523 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected, and can provide 31 kHz if required.

The other clock source is the internal RC oscillator (INTRC) which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

These features are discussed in greater detail in Section 23.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 30). Additionally, the 31 kHz clock can be provided by either the INTOSC, or INTRC clock sources, depending on the INTSRC bit (OSCTUNE<7>).

2.6.1 INTIO MODES

Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available:

• In INTIO1 mode, the OSC2 pin outputs F while OSC1 functions as RA7 for digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.

2.6.2 INTOSC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa.

OSC/4,

2.6.3 OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1).

When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred.

The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 2.7.1 “Oscillator Control Register”.

The PLLEN bit controls the operation of the frequency multiplier, PLL, in Internal Oscillator modes.

2.6.4 PLL IN INTOSC MODES

The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation.

The PLL is available for use with the INTOSC when:

1. The primary clock is the INTOSC clock source (selected in CONFIG1H<3:0>), and

2. The 4 or 8 MHz INTOSC output is selected.

Writes to the PLLEN bit will be ignored until both these conditions are met.

2.6.5 INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as V affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 2.6.5.1 “Compensating with the

EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques

may be used.

DD or temperature changes, which can

PIC18F2423/2523/4423/4523

R/W-0 R/W-0

INTSRC PLLEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled

bit 5 Unimplemented: Read as ‘0’

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111

• •

• • 10000 = Minimum frequency

(1)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TUN4 TUN3 TUN2 TUN1 TUN0

(1)

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

Section 2.6.4 “PLL in INTOSC Modes” for details.

2.6.5.1 Compensating with the EUSART

An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency.

2.6.5.2 Compensating with the Timers

This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator.

Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register.

2.6.5.3 Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated.

If the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register.

PIC18F2423/2523/4423/4523

2.7 Clock Sources and Oscillator Switching

Like previous PIC18 devices, the PIC18F2423/2523/ 4423/4523 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2423/2523/4423/4523 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.

Essentially, there are three clock sources for these devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC3:FOSC0 Configuration bits. The details of these modes are covered earlier in this chapter.

The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode.

PIC18F2423/2523/4423/4523 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock.

Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in Section 12.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2423/2523/4423/4523 devices are shown in Figure 2-8. See Section 23.0 “Special Features of the CPU” for Configuration register details.

FIGURE 2-8: PIC18F2423/2523/4423/4523 CLOCK DIAGRAM

PIC18F2423/2523/4423/4523

4 x PLL

OSCCON<6:4>

8 MHz

111

4 MHz

110

2 MHz

101

1 MHz

31 kHz

100

011

MUX

010

001

000

OSCTUNE<7>

500 kHz

Postscaler

250 kHz

125 kHz

1 0

HSPLL, INTOSC/PLL

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

Secondary Oscillator

T1OSCEN Enable Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

8 MHz

Source

INTRC Source

31 kHz (INTRC)

OSCTUNE<6>

8 MHz

(INTOSC)

LP, XT, HS, RC, EC

T1OSC

Internal Oscillator

FOSC3:FOSC0

Peripherals

MUX

CPU

Clock

Control

Clock Source Option for other Modules

WDT, PWRT, FSCM and Two-Speed Start-up

IDLEN

OSCCON<1:0>

PIC18F2423/2523/4423/4523

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits (IRCF2:IRCF0) select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31.25 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz.

When a nominal output frequency of 31 kHz is selected (IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source, and disables the INTOSC clock source.

This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in Primary Clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in Secondary Clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or INTOSC has just started and is not yet stable.

The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed.

The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0

“Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts.

2.7.2 OSCILLATOR TRANSITIONS

PIC18F2423/2523/4423/4523 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”.

PIC18F2423/2523/4423/4523

(1)

R-0 R/W-0 R/W-0

(2)

R/W-0 R/W-1 R/W-0 R/W-0 R

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator

(3)

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset.

PIC18F2423/2523/4423/4523

2.8 Effects of Power-Managed Modes on the Various Clock Sources

When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating.

In Secondary Clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3.

In Internal Oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the powermanaged mode (see Section 23.2 “Watchdog Timer

(WDT)”, Section 23.3 “Two-Speed Start-up” and Section 23.4 “Fail-Safe Clock Monitor” for more

information on WDT, Fail-Safe Clock Monitor and TwoSpeed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents).

Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do

not require a device clock source (i.e., MSSP slave, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in

Section 26.2 “DC Characteristics: Power-Down and Supply Current”.

2.9 Power-up Delays

Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 26-10). It is enabled by clearing (= 0) the PWRTEN

The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency.

There is a delay of interval T Table 26-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source.

Configuration bit.

CSD (parameter 38,

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)

RCIO Floating, external resistor should pull high Configured as PORTA, bit 6

INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6

ECIO Floating, pulled by external clock Configured as PORTA, bit 6

EC Floating, pulled by external clock At logic low (clock/4 output)

LP, XT and HS Feedback inverter disabled at quiescent

voltage level

Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR

Feedback inverter disabled at quiescent voltage level

Reset.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

3.0 POWER-MANAGED MODES

PIC18F2423/2523/4423/4523 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block). The Sleep mode does not use a clock source.

The power-managed modes include several powersaving features offered on previous PICmicro devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PICmicro devices, where all device clocks are stopped.

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1.

3.1.1 CLOCK SOURCES

The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC3:FOSC0 Configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit.

Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.

TABLE 3-1: POWER-MANAGED MODES

Mode

IDLEN<7>

Sleep 0 N/A Off Off None – All clocks are disabled

PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block

PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 11xOff Clocked Internal Oscillator Block

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

OSCCON Bits Module Clocking

(1)

SCS1:SCS0<1:0> CPU Peripherals

Available Clock and Oscillator Source

(2)

Internal Oscillator Block This is the normal full power execution mode.

(2)

PIC18F2423/2523/4423/4523

3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS

The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable.

Three bits indicate the current clock source and its status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable.

If the internal oscillator block is configured as the primary clock source by the FOSC3:FOSC0 Configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS bit.

Note 1: Caution should be used when modifying a

single IRCF bit. If V possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated (see Figure 26-1 and Figure 26-2).

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit.

DD is less than 3V, it is

3.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. Entry to, and exit from Idle mode, does not affect the state of the IDLEN bit.

3.2 Run Modes

In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 23.3 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”).

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source.

SEC_RUN mode is entered by setting the SCS1:SCS0 bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.

On transitions from SEC_RUN to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.

PIC18F2423/2523/4423/4523

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q4Q3Q2

Q4Q3Q2 Q1 Q3Q2

T1OSI

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

Note 1: Clock transition typically occurs within 2-4 T

123 n-1n

Clock Transition

OSC.

(1)

PC + 2PC

PC + 4

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

T1OSI

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

(1)

TOST

Q3 Q4 Q1

Q2 Q2 Q3

(1)

TPLL

12 n-1n

Clock

Transition

(2)

PC + 2

PC + 4

SCS1:SCS0 bits Changed

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 T

OSTS bit Set

OSC.

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times.

If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended.

This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed.

Note: Caution should be used when modifying a

single IRCF bit. If V

DD is less than 3V, it is

possible to select a higher clock speed than is supported by the low V

DD.

Improper device operation may result if

DD/FOSC specifications are violated

the V (see Figure 26-1 and Figure 26-2).

PIC18F2423/2523/4423/4523

If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks.

If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of

IOBST.

On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.

If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

Q4Q3Q2

123 n-1n

Clock Transition

(1)

PC + 2PC

INTRC

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 T

OSC.

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q3 Q4

INTOSC

Multiplexer

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

SCS1:SCS0 bits Changed

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 T

TOST

(1)

TPLL

OSTS bit Set

OSC.

Clock

Transition

n-1 n

(2)

PC + 2

PC + 4

PIC18F2423/2523/4423/4523

3.3 Sleep Mode

The power-managed Sleep mode in the PIC18F2423/ 2523/4423/4523 devices is identical to the legacy Sleep mode offered in all other PICmicro devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared.

Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run.

When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the TwoSpeed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 23.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run.

Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of T (parameter 38, Table 26-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits.

CSD

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q4Q3Q2

Q1Q1

OSC1

CPU

Clock

Peripheral

Clock

Sleep

Program

Counter

PC + 2PC

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

(1)

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Wake Event

Note1: T

OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST

TPLL

OSTS bit Set

(1)

Q3 Q4 Q1 Q2

PC + 2

Q3 Q4

PC + 4

Q1 Q2 Q3 Q4

PC + 6

PIC18F2423/2523/4423/4523

3.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 Configuration bits. The OSTS bit remains set (see Figure 3-7).

When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval T required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8).

CSD is

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS1:SCS0 bits to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval

CSD following the wake event, the CPU begins exe-

of T cuting code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8).

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

PC + 2

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

TCSD

Wake Event

PIC18F2423/2523/4423/4523

3.4.3 RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods.

From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared.

If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of T (parameter 39, Table 26-10). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source.

When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay

CSD following the wake event, the CPU begins exe-

of T cuting code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.

IOBST

3.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 “Run Modes”, Section 3.3 “Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”).

A fixed delay of interval T is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.

CSD following the wake event

3.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs.

If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 “Run Modes” and Section 3.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 23.2 “Watchdog Timer (WDT)”).

The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source.

3.5.3 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2.

Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 23.4 “Fail-Safe Clock Monitor”) is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.

PIC18F2423/2523/4423/4523

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DE LAY

Certain exits from power-managed modes do not invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped and

• the primary clock source is not any of the LP, XT,

In these instances, the primary clock source is either already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval

CSD following the wake event is still required when

T leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.

HS or HSPLL modes.

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Primary Device Clock

(PRI_IDLE mode)

T1OSC or INTRC

INTOSC

None

(Sleep mode)

Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

OST is the Oscillator Start-up Timer (parameter 32). t

3: T

also designated as T

4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

(1)

(2)

PLL.

Clock Source

after Wake-up

Exit Delay

LP, XT, HS

HSPLL

EC, RC

INTOSC

(2)

LP, XT, HS TOST

EC, RC TCSD

INTOSC

(1)

LP, XT, HS TOST

EC, RC TCSD

INTOSC

(1)

LP, XT, HS T

EC, RC TCSD

INTOSC

(1)

is the PLL Lock-out Timer (parameter F12); it is

Clock Ready Status

Bit (OSCCON)

CSD

TIOBST

(1)

(3)

(1)

(4)

(1)

(4)

(3)

OSTS

OSTSHSPLL TOST + t

None IOFS

(3)

OST

TIOBST

(1)

(4)

(3)

OSTSHSPLL TOST + t

IOFS

PIC18F2423/2523/4423/4523

4.0 RESET

A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1.

The PIC18F2423/2523/4423/4523 devices differentiate between various kinds of Reset:

a) Power-on Reset (POR) b) MCLR

Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset

This section discusses Resets generated by MCLR POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 23.2 “Watchdog

4.1 RCON Register

Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers”.

The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in

Section 9.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”.

Timer (WDT)”.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

MCLR

VDD

OSC1

Stack

Pointer

( )_IDLE

Sleep

WDT

Time-out

DD Rise

Detect

Brown-out

Reset

OST/PWRT

32 μs

(1)

INTRC

Stack Full/Underflow Reset

External Reset

MCLRE

POR Pulse

BOREN

OST

PWRT

1024 Cycles

10-Bit Ripple Counter

65.5 ms

11-Bit Ripple Counter

Chip_Reset

Enable PWRT

Enable OST

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 4-2 for time-out situations.

(2)

PIC18F2423/2523/4423/4523

R/W-0 R/W-1

IPEN SBOREN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit

If BOREN1:BOREN0 =

1 = BOR is enabled 0 = BOR is disabled

If BOREN1:BOREN0 = Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI

1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a

bit 3 TO

1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

bit 2 PD

1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction

bit 1 POR

1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR

1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

: RESET Instruction Flag bit

Brown-out Reset occurs)

: Watchdog Time-out Flag bit

: Power-Down Detection Flag bit

: Power-on Reset Status bit

: Brown-out Reset Status bit

U-0 R/W-1 R-1 R-1 R/W-0

—RITO PD POR BOR

01:

00, 10 or 11:

(2)

(1)

(2)

R/W-0

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR

‘1’ by software immediately after POR).

is determined by the type of device Reset. See the notes following this

is ‘0’ and POR is ‘1’ (assuming that POR was set to

PIC18F2423/2523/4423/4523

4.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR

Reset path which detects and ignores small

pulses.

The MCLR

pin is not driven low by any internal Resets,

including the WDT.

In PIC18F2423/2523/4423/4523 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR

is disabled, the pin becomes a digital

input. See Section 10.5 “PORTE, TRISE and LATE

Registers” for more information.

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip whenever V allows the device to start in the initialized state when VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for

DD is specified (parameter D004). For a slow rise

V time, see Figure 4-2.

When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

POR events are captured by the POR The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR.

DD rises above a certain threshold. This

bit (RCON<1>).

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW V

VDD

Note 1: External Power-on Reset circuit is required

only if the V The diode D helps discharge the capacitor quickly when V

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR of MCLR Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

DD power-up slope is too slow.

from external capacitor C, in the event

/VPP pin breakdown, due to

DD POW E R-U P)

MCLR

PIC18FXXXX

DD powers down.

PIC18F2423/2523/4423/4523

4.4 Brown-out Reset (BOR)

PIC18F2423/2523/4423/4523 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1.

The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled, any drop of V eter D005) for greater than T reset the device. A Reset may or may not occur if V falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until V

If the Power-up Timer is enabled, it will be invoked after

DD rises above VBOR; it then will keep the chip in

V Reset for an additional time delay, T (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT.

DD rises above VBOR, the Power-up

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’.

DD below VBOR (param-

BOR (parameter 35) will

DD rises above VBOR.

PWRT

Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications.

Note: Even when BOR is under software control,

the BOR Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It cannot be changed in software.

4.4.2 DETECTING BOR

When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR simultaneously check the state of both POR This assumes that the POR immediately after any POR event. If BOR POR

is ‘1’, it can be reliably assumed that a BOR event

has occurred.

alone. A more reliable method is to

and BOR.

bit is reset to ‘1’ in software

is ‘0’ while

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled.

This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Status of

BOREN1 BOREN0

00Ignored BOR disabled; must be enabled by reprogramming the Configuration bits.

01Available BOR enabled in software; operation controlled by SBOREN.

10Ignored BOR enabled in hardware in Run and Idle modes, disabled during

11Ignored BOR enabled in hardware.

SBOREN

(RCON<6>)

Sleep mode.

BOR Operation

PIC18F2423/2523/4423/4523

4.5 Device Reset Timers

PIC18F2423/2523/4423/4523 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

4.5.1 POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18F2423/2523/ 4423/4523 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs=65.6ms. While the PWRT is counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 for details.

The PWRT is enabled by clearing the PWRTEN Configuration bit.

4.5.2 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal or resonator oscillator has started and is stable enough to to clock the controller. More time may be required for the oscillator to meet its frequency tolerance specification.

The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes.

4.5.3 PLL LOCK TIME-OUT

With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (T oscillator start-up time-out.

PLL) is typically 2 ms and follows the

4.5.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. The POR pulse clears.

2. PWRT time-out is invoked (if enabled).

3. The OST time-out is invoked. The oscillator starts at the beginning of this period.

4. PLL lock time-out (if using HSPLL mode).

The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel.

high will begin execution immediately

TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS

(2)

Oscillator

Configuration

HSPLL 66 ms

HS, XT, LP 66 ms

EC, ECIO 66 ms

RC, RCIO 66 ms

INTIO1, INTIO2 66 ms

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

PWRTEN

(1)

+ 1024 TOSC + 2 ms

Power-up

= 0 PWRTEN = 1

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(1)

and Brown-out

(2)

1024 TOSC + 2 ms

Exit from

Power-Managed Mode

(2)

——

1024 TOSC + 2 ms

(2)

PIC18F2423/2523/4423/4523

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OSC1

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OSC1

OST TIME-OUT

RISES BEFORE TOST COMPLETES)

TOST

INTERNAL RESET

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OSC1

OST TIME-OUT

INTERNAL RESET

RISES AFTER TOST COMPLETES)

TOST

PIC18F2423/2523/4423/4523

FIGURE 4-6: SLOW VDD RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OSC1

OST TIME-OUT

INTERNAL RESET

PWRT

TOST

FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OSC1

OST TIME-OUT

PLL TIME-OUT

INTERNAL RESET

Note: TOST = 1024 OSC1 cycles. TPLL ≈ 2 ms max.

TOST

TPLL

TIED TO VDD)

PIC18F2423/2523/4423/4523

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI POR

and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset.

, TO, PD,

Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition

Power-on Reset 0000h 11100 0 0

RESET Instruction 0000h 0uuuu u u

Brown-out Reset 0000h 111u0 u u

during Power-Managed

MCLR Run Modes

MCLR during Power-Managed Idle Modes and Sleep Mode

WDT Time-out during Full Power or Power-Managed Run Mode

during Full Power Execution 0000h uuuuu u u

MCLR

Stack Full Reset (STVREN = 1) 0000h uuuuu 1 u

Stack Underflow Reset (STVREN = 1)

Stack Underflow Error (not an actual Reset, STVREN = 0)

WDT Time-out during Power-Managed Idle or Sleep Modes

Interrupt Exit from Power-Managed Modes

Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

Program

Counter

0000h u1uuu u u

0000h u10uu u u

0000h u0uuu u u

0000h uuuuu u 1

PC + 2 u00uu u u

(1)

PC + 2

RI TO PD POR BOR STKFUL STKUNF

uu0uu u u

RCON Register STKPTR Register

PIC18F2423/2523/4423/4523

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR

TOSU 2423 2523 4423 4523 ---0 0000 ---0 0000 ---0 uuuu

TOSH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TOSL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

STKPTR 2423 2523 4423 4523 00-0 0000 uu-0 0000 uu-u uuuu

PCLATU 2423 2523 4423 4523 ---0 0000 ---0 0000 ---u uuuu

PCLATH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PCL 2423 2523 4423 4523 0000 0000 0000 0000 PC + 2

TBLPTRU 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

TBLPTRH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TBLPTRL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TABLAT 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PRODH 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON 2423 2523 4423 4523 0000 000x 0000 000u uuuu uuuu

INTCON2 2423 2523 4423 4523 1111 -1-1 1111 -1-1 uuuu -u-u

INTCON3 2423 2523 4423 4523 11-0 0-00 11-0 0-00 uu-u u-uu

INDF0 2423 2523 4423 4523 N/A N/A N/A

POSTINC0 2423 2523 4423 4523 N/A N/A N/A

POSTDEC0 2423 2523 4423 4523 N/A N/A N/A

PREINC0 2423 2523 4423 4523 N/A N/A N/A

PLUSW0 2423 2523 4423 4523 N/A N/A N/A

FSR0H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR0L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

WREG 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 2423 2523 4423 4523 N/A N/A N/A

POSTINC1 2423 2523 4423 4523 N/A N/A N/A

POSTDEC1 2423 2523 4423 4523 N/A N/A N/A

PREINC1 2423 2523 4423 4523 N/A N/A N/A

PLUSW1 2423 2523 4423 4523 N/A N/A N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

Power-on Reset, Brown-out Reset

RESET Instruction,

Resets,

WDT Reset,

Stack Resets

Wake-up via WDT

or Interrupt

(3)

(2)

(1)

PIC18F2423/2523/4423/4523

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR

FSR1H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

BSR 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

INDF2 2423 2523 4423 4523 N/A N/A N/A

POSTINC2 2423 2523 4423 4523 N/A N/A N/A

POSTDEC2 2423 2523 4423 4523 N/A N/A N/A

PREINC2 2423 2523 4423 4523 N/A N/A N/A

PLUSW2 2423 2523 4423 4523 N/A N/A N/A

FSR2H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR2L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 2423 2523 4423 4523 ---x xxxx ---u uuuu ---u uuuu

TMR0H 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TMR0L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

OSCCON 2423 2523 4423 4523 0100 q000 0100 q000 uuuu uuqu

HLVDCON 2423 2523 4423 4523 0-00 0101 0-00 0101 u-uu uuuu

WDTCON 2423 2523 4423 4523 ---- ---0 ---- ---0 ---- ---u

(4)

RCON

TMR1H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 2423 2523 4423 4523 0000 0000 u0uu uuuu uuuu uuuu

TMR2 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PR2 2423 2523 4423 4523 1111 1111 1111 1111 1111 1111

T2CON 2423 2523 4423 4523 -000 0000 -000 0000 -uuu uuuu

SSPBUF 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPCON1 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPCON2 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

Shaded cells indicate conditions do not apply for the designated device.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

2423 2523 4423 4523 0q-1 11q0 0q-q qquu uq-u qquu

Power-on Reset,

Brown-out Reset

RESET Instruction,

Resets,

WDT Reset,

Stack Resets

Wake-up via WDT

or Interrupt

PIC18F2423/2523/4423/4523

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR

ADRESH 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

ADCON1 2423 2523 4423 4523 --00 0qqq --00 0qqq --uu uuuu

ADCON2 2423 2523 4423 4523 0-00 0000 0-00 0000 u-uu uuuu

CCPR1H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON

CCPR2H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

BAUDCON 2423 2523 4423 4523 01-0 0-00 01-0 0-00 --uu uuuu

ECCP1DEL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

ECCP1AS

CVRCON 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

CMCON 2423 2523 4423 4523 0000 0111 0000 0111 uuuu uuuu

TMR3H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON 2423 2523 4423 4523 0000 0000 uuuu uuuu uuuu uuuu

SPBRGH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SPBRG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

RCREG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TXREG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TXSTA 2423 2523 4423 4523 0000 0010 0000 0010 uuuu uuuu

RCSTA 2423 2523 4423 4523 0000 000x 0000 000x uuuu uuuu

EEADR 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

EEDATA 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

EECON2 2423 2523 4423 4523 0000 0000 0000 0000 0000 0000

EECON1 2423 2523 4423 4523 xx-0 x000 uu-0 u000 uu-0 u000

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523

2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523

4423 4523 --00 0000 --00 0000 --uu uuuu

4423 4523 0000 00-- 0000 00-- uuuu uu--

Power-on Reset, Brown-out Reset

RESET Instruction,

Resets,

WDT Reset,

Stack Resets

Wake-up via WDT

or Interrupt

PIC18F2423/2523/4423/4523

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR

Power-on Reset,

Brown-out Reset

RESET Instruction,

IPR2 2423 2523 4423 4523 11-1 1111 11-1 1111 uu-u uuuu

PIR2 2423 2523 4423 4523 00-0 0000 00-0 0000 uu-u uuuu

PIE2 2423 2523 4423 4523 00-0 0000 00-0 0000 uu-u uuuu

IPR1

PIR1

PIE1

2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

2423 2523

4423 4523 -111 1111 -111 1111 -uuu uuuu

2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523 4423 4523 -000 0000 -000 0000 -uuu uuuu

2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523

4423 4523 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2423 2523 4423 4523 0q-0 0000 00-0 0000 uu-u uuuu

TRISE

TRISD

2423 2523 4423 4523 0000 -111 0000 -111 uuuu -uuu

2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISC 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISB 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISA

(5)

2423 2523 4423 4523 1111 1111

(5)

LATE 2423 2523 4423 4523 ---- -xxx ---- -uuu ---- -uuu

LATD

2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATB 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATA

(5)

2423 2523 4423 4523 xxxx xxxx

(5)

PORTE 2423 2523 4423 4523 ---- xxxx ---- uuuu ---- uuuu

PORTD

2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA

(5)

2423 2523 4423 4523 xx0x 0000

(5)

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

Resets,

WDT Reset,

Stack Resets

1111 1111

uuuu uuuu

uu0u 0000

Wake-up via WDT

or Interrupt

(5)

uuuu uuuu

(1)

(5)

PIC18F2423/2523/4423/4523

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.

Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).

The PIC18F2423 and PIC18F4423 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F2523 and PIC18F4523 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h.

The program memory map for PIC18F2423/2523/ 4423/4523 devices is shown in Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR

PIC18F2423/2523/4423/4523 DEVICES

PC<20:0>

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1

•

Stack Level 31

Reset Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

On-Chip

Program Memory

3FFFh 4000h

PIC18FX423

Read ‘0’

On-Chip

Program Memory

7FFFh 8000h

PIC18FX523

Read ‘0’

0000h

0008h

0018h

User Memory Space

1FFFFFh 200000h

PIC18F2423/2523/4423/4523

5.1.1 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.4.1 “Computed GOTO”).

The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The Return Address Stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers.

A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the Return Address Stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack<20:0>

11111

Top-of-Stack Registers Stack Pointer

TOSLTOSHTOSU

34h1Ah00h

To p- o f -S ta ck

001A34h

000D58h

11110 11101

STKPTR<4:0>

00010

00011 00010 00001 00000

PIC18F2423/2523/4423/4523

5.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance.

After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR.

The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 23.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31.

When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack.

The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack.

The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit

bit 6 STKUNF: Stack Underflow Flag bit

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

(1)

STKUNF

1 = Stack became full or overflowed 0 = Stack has not become full or overflowed

1 = Stack underflow occurred 0 = Stack underflow did not occur

(1)

— SP4 SP3 SP2 SP1 SP0

(1)

PIC18F2423/2523/4423/4523

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A fast register stack is provided for the STATUS, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt.

If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low priority interrupt.

If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack.

Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER ;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY

There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2.

A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function.

The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in each instruction location and room on the Return Address Stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

MOVF OFFSET, W

CALL TABLE ORG nn00h TABLE ADDWF PCL

RETLW nnh

5.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory allows two bytes of data to be stored in each instruction location.

Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time.

Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”.

PIC18F2423/2523/4423/4523

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3.

FIGURE 5-3: CLOCK/ INSTRUCTION CYCLE

OSC1

OSC2/CLKO

(RC mode)

Q2 Q3 Q4

PC PC + 2 PC + 4

Execute INST (PC – 2)

Fetch INST (PC)

Q2 Q3 Q4

Execute INST (PC)

Fetch INST (PC + 2)

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3).

A fetch cycle begins with the Program Counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Internal Phase Clock

Execute INST (PC + 2)

Fetch INST (PC + 4)

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

PIC18F2423/2523/4423/4523

5.2.3 INSTRUCTIONS IN PROGRAM MEMORY

The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”).

Figure 5-4 shows an example of how instruction words are stored in the program memory.

The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 24.0 “Instruction Set Summary” provides further details of the instruction set.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

LSB = 1 LSB = 0 ↓

Program Memory Byte Locations

Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

→

F0h 00h 00000Ch

F4h 56h 000010h

Word Address

000000h 000002h 000004h 000006h

000012h 000014h

5.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence – immediately after the first word – the data in the second word is accessed and used by

the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works.

Note: See Section 5.6 “PIC18 Instruction

Execution and the Extended Instruction Set” for information on two-word

instructions in the extended instruction set.

EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2423/2523/4423/4523

5.3 Data Memory Organization

Note: The operation of some aspects of data

memory are changed when the PIC18 extended instruction set is enabled. See

Section 5.5 “Data Memory and the Extended Instruction Set” for more

information.

The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2423/ 2523/4423/4523 devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F2423/2523/4423/4523 devices.

The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s.

The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection.

To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM.

5.3.1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location’s address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction.

The value of the BSR indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figure 5-7.

Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter.

While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.

PIC18F2423/2523/4423/4523

FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2423/4423 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010

= 0011

= 0100

= 0101

= 0110

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

= 1111

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

Bank 14

Bank 15

Data Memory Map

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh 00h

FFh

Access RAM

Unused

Read 00h

Unused

GPR

SFR

000h 07Fh 080h 0FFh 100h

1FFh 200h

2FFh 300h

3FFh 400h

4FFh 500h

5FFh 600h

6FFh 700h

7FFh 800h

8FFh 900h

9FFh A00h

AFFh B00h

BFFh C00h

CFFh D00h

DFFh E00h

EFFh F00h F7Fh

F80h FFFh

When ‘a’ = 0:

The BSR is ignored and the Access Bank is used.

The first 128 bytes are general purpose RAM (from Bank 0).

The second 128 bytes are Special Function Registers (from Bank 15).

When ‘a’ = 1:

The BSR specifies the Bank used by the instruction.

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h

7Fh 80h

FFh

PIC18F2423/2523/4423/4523

FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2523/4523 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010

= 0011

= 0100

= 0101

= 0110

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

= 1111

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

Bank 14

Bank 15

Data Memory Map

00h

FFh 00h

Access RAM

Unused

Read 00h

FFh 00h

FFh

Unused

GPR

SFR

000h 07Fh 080h 0FFh 100h

1FFh 200h

2FFh 300h

3FFh 400h

4FFh 500h

5FFh 600h

6FFh 700h

7FFh 800h

8FFh 900h

9FFh A00h

AFFh B00h

BFFh C00h

CFFh D00h

DFFh E00h

EFFh F00h F7Fh

F80h FFFh

When ‘a’ = 0:

The BSR is ignored and the Access Bank is used.

The first 128 bytes are general purpose RAM (from Bank 0).

The second 128 bytes are Special Function Registers (from Bank 15).

When ‘a’ = 1:

The BSR specifies the Bank used by the instruction.

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h

7Fh 80h

FFh

PIC18F2423/2523/4423/4523

FIGURE 5-7: USE OF THE BANK SELECT REGISTER

(DIRECT ADDRESSING POINTS TO 0x02FF)

Memory

BSR

0000

Bank Select

(2)

(1)

0010

000h

100h

200h

300h

Data

Bank 0

Bank 1

Bank 2

Bank 3

through

Bank 13

00h

FFh 00h

From Opcode

(2)

11111111

E00h

F00h

FFFh

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Bank 14

Bank 15

5.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient.

To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs. This

FFh 00h

FFh

however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely.

Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables.

The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.

upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-5).

The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’,

5.3.3 GENERAL PURPOSE REGISTER FILE

PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow downwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets.

PIC18F2423/2523/4423/4523

5.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral.

The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2423/2523/4423/4523 DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2

FFEh TOSH FDEh POSTINC2

FFDh TOSL FDDh POSTDEC2

FFCh STKPTR FDCh PREINC2

FFBh PCLATU FDBh PLUSW2

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —

FF9h PCL FD9h FSR2L FB9h —

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD

FF4h PRODH FD4h —

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —

FEFh INDF0

FEEh POSTINC0

FEDh POSTDEC0

FECh PREINC0

FEBh PLUSW0

(1)

FCFh TMR1H FAFh SPBRG F8Fh —

(1)

FCEh TMR1L FAEh RCREG F8Eh —

FCDh T1CON FADh TXREG F8Dh LATE

FCCh TMR2 FACh TXSTA F8Ch LATD

FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h

FE7h INDF1

FE6h POSTINC1

FE5h POSTDEC1

FE4h PREINC1

FE3h PLUSW1

(1)

FC7h SSPSTAT FA7h EECON2

FC6h SSPCON1 FA6h EECON1 F86h —

FC5h SSPCON2 FA5h —

FC4h ADRESH FA4h —

FC3h ADRESL FA3h —

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

(1)

FBFh CCPR1H F9Fh IPR1

(1)

(2)

FBEh CCPR1L F9Eh PIR1

FBDh CCP1CON F9Dh PIE1

FBCh CCPR2H F9Ch —

FBBh CCPR2L F9Bh OSCTUNE

(2)

(3)

F99h —

F97h —

F96h TRISE

FB4h CMCON F94h TRISC

(2)

—

(1)

(2)

F8Ah LATB

F87h —

F85h —

F84h PORTE

F83h PORTD

—

(2)

(3)

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices.

PIC18F2423/2523/4423/4523

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 54

TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 54

STKPTR STKFUL STKUNF

PCLATU

PCLATH Holding Register for PC<15:8> 0000 0000 49, 54

PCL PC Low Byte (PC<7:0>) 0000 0000 49, 54

TBLPTRU

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 76

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 76

TABLAT Program Memory Table Latch 0000 0000 49, 76

PRODH Product Register High Byte xxxx xxxx 49, 89

PRODL Product Register Low Byte xxxx xxxx 49, 89

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 93

INTCON2 RBPU

INTCON3 INT2IP INT1IP

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 69

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 69

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 69

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

FSR0H

FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 69

WREG Working Register xxxx xxxx 49

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 69

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 69

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 69

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 69

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

FSR1H

FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50, 69

BSR

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 69

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 69

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 69

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 69

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

FSR2H

FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50, 69

STATUS

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See

2: These registers and/or bits are not implemented on 28-pin devices and are read as

3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as

4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as

5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54

— SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55

— — — Holding Register for PC<20:16> ---0 0000 49, 54

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 76

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 49, 94

—INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 49, 95

value of FSR0 offset by W

— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 49, 69

value of FSR1 offset by W

— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50, 69

— — — — Bank Select Register ---- 0000 50, 59

value of FSR2 offset by W

— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50, 69

— — —NOVZDCC---x xxxx 50, 67

Section 4.4 “Brown-out Reset (BOR)”.

‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

‘0’. See Section 2.6.4 “PLL in

INTOSC Modes”.

read-only.

When disabled, these bits read as ‘0’.

Value on

POR, BOR

N/A 49, 69

N/A 50, 69

Details

on page:

‘0’. This bit is

PIC18F2423/2523/4423/4523

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMR0H Timer0 Register High Byte 0000 0000 50, 125

TMR0L Timer0 Register Low Byte xxxx xxxx 50, 125

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 123

OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50

HLVDCON VDIRMAG

WDTCON

RCON IPEN SBOREN

TMR1H Timer1 Register High Byte xxxx xxxx 50, 131

TMR1L Timer1 Register Low Bytes xxxx xxxx 50, 131

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR2 Timer2 Register 0000 0000 50, 134

PR2 Timer2 Period Register 1111 1111 50, 134

T2CON

SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 50, 169,

SSPADD MSSP Address Register in I

SSPSTAT SMP CKE D/A

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 163,

SSPCON2 GCEN ACKSTAT ACKDT/

ADRESH A/D Result Register High Byte xxxx xxxx 51, 236

ADRESL A/D Result Register Low Byte xxxx xxxx 51, 236

ADCON0

ADCON1

ADCON2 ADFM

CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 51, 140

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 51, 140

CCP1CON P1M1

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 51, 140

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 51, 140

CCP2CON

BAUDCON ABDOVF RCIDL

ECCP1DEL PRSEN PDC6

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 243

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51, 237

TMR3H Timer3 Register High Byte xxxx xxxx 51, 137

TMR3L Timer3 Register Low Byte xxxx xxxx 51, 137

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC

2: These registers and/or bits are not implemented on 28-pin devices and are read as

3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as

4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as

5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

— — — — — — —SWDTEN--- ---0 50, 263

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 51, 227

— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 51, 228

(2)

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 51, 139

Section 4.4 “Brown-out Reset (BOR)”.

individual unimplemented bits should be interpreted as ‘-’.

INTOSC Modes”.

read-only.

When disabled, these bits read as ‘0’.

— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 245

(1)

—RITO PD POR BOR 0q-1 11q0 42, 48,

TMR1CS TMR1ON 0000 0000 50, 127

C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 50, 170

PSR/WUA BF 0000 0000 50, 162,

ADMSK5

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 229

P1M0

(2)

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 139,

(2)

—SCKPBRG16— WUE ABDEN 01-0 0-00 51, 208

PDC5

ACKEN/

ADMSK4

(2)

PDC4

RCEN/

ADMSK3

(2)

PDC3

PEN/

ADMSK2

(2)

PDC2

RSEN/

ADMSK1

(2)

PDC1

TMR3CS TMR3ON 0000 0000 51, 135

SEN 0000 0000 50, 173

PDC0

(2)

PSSBD0

‘0’. Reset values are shown for 40/44-pin devices;

‘0’. See Section 2.6.4 “PLL in

Value on

POR, BOR

(2)

0000 0000 51, 157

(2)

0000 0000 51, 157

Details

on page:

102

170

171

172

147

‘0’. This bit is

PIC18F2423/2523/4423/4523

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 210

SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51, 210

RCREG EUSART Receive Register 0000 0000 51, 217

TXREG EUSART Transmit Register 0000 0000 51, 215

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 206

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 207

EEADR EEPROM Address Register 0000 0000 51, 74, 83

EEDATA EEPROM Data Register 0000 0000 51, 74, 83

EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 74, 83

EECON1 EEPGD CFGS

IPR2 OSCFIP CMIP

PIR2 OSCFIF CMIF

PIE2 OSCFIE CMIE

IPR1 PSPIP

PIR1 PSPIF

PIE1 PSPIE

(2)

ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 100

(2)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 96

(2)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 98

OSCTUNE INTSRC PLLEN

(2)

TRISE

TRISD

(2)

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 118

PORTD Data Direction Control Register 1111 1111 52, 114

(3)

— FREE WRERR WREN WR RD xx-0 x000 51, 75, 84

— EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 101

— EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 97

— EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 99

— TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52

TRISC PORTC Data Direction Control Register 1111 1111 52, 111

TRISB PORTB Data Direction Control Register 1111 1111 52, 108

TRISA TRISA7

(2)

LATE

— — — — — PORTE Data Latch Register

(5)

TRISA6

(5)

PORTA Data Direction Control Register 1111 1111 52, 105

---- -xxx 52, 117

(Read and Write to Data Latch)

(2)

LATD

PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 114

LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52 , 111

LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 108

LATA LATA7

PORTE

PORTD

(2)

— — — —RE3

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 114

(5)

LATA6

(5)

PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 105

(4)

RE2

(2)

RE1

(2)

RE0

(2)

---- xxxx 52, 117

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 111

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 108

PORTA RA7

(5)

RA6

(5)

RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 105

Section 4.4 “Brown-out Reset (BOR)”.

2: These registers and/or bits are not implemented on 28-pin devices and are read as

‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as

‘0’. See Section 2.6.4 “PLL in

INTOSC Modes”.

4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as

read-only.

5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

Details

on page:

‘0’. This bit is

PIC18F2423/2523/4423/4523

5.3.5 STATUS REGISTER

The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction.

If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register.

For other instructions that do not affect Status bits, see the instruction set summaries in Table 24-2 and Table 24-3.

Note: The C and DC bits operate as the borrow

and digit borrow bits, respectively, in subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(2)

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1).

1 = Result was negative 0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

(1)

bit

(2)

bit

bit 1 DC: Digit Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.

2: For borrow

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.

, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

PIC18F2423/2523/4423/4523

5.4 Data Addressing Modes

Note: The execution of some instructions in the

core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information.

While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 5.5.1 “Indexed Addressing with Literal Offset”.

5.4.1 INHERENT AND LITERAL ADDRESSING

Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW.

Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address.

5.4.2 DIRECT ADDRESSING

Direct Addressing mode specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction.

The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register.

5.4.3 INDIRECT ADDRESSING

Indirect Addressing mode allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory.

The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING INDIRECT ADDRESSING

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then ; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

PIC18F2423/2523/4423/4523

5.4.3.1 FSR Registers and the INDF Operand

At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.

Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer.

Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address.

5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by 1 afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by 1 afterwards

• PREINC: increments the FSR value by 1, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses the new value in the operation.

In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.).

FIGURE 5-8: INDIRECT ADDRESSING

Using an instruction with one of the indirect addressing registers as the

operand....

...uses the 12-bit address stored in the FSR pair associated with that

xxxx1110 11001100

...to determine the data memory location to be used in that operation.

In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh.

ADDWF, INDF1, 1

FSR1H:FSR1L

000h

Bank 0

100h

200h

300h

E00h

F00h

FFFh

Bank 1

Bank 2

Bank 3

through

Bank 13

Bank 14

Bank 15

Data Memory

PIC18F2423/2523/4423/4523

The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory.

5.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP.

On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing.

Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device.

5.5 Data Memory and the Extended Instruction Set

Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space.

What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remain unchanged.

5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET

Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation.

5.5.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5-9.

Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 24.2.1 “Extended Instruction Syntax”.

PIC18F2423/2523/4423/4523

FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When ‘a’ = 0 and f ≥ 60h:

The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory.

Locations below 60h are not available in this addressing mode.

When ‘a’ = 0 and f ≤ 5Fh:

The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space.

Note that in this mode, the correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

000h

060h 080h

100h

F00h

F80h

FFFh

000h

080h

100h

F00h

F80h

FFFh

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

Data Memory

00h

60h 80h

Access RAM

FSR2H FSR2L

FFh

ffffffff001001da

Valid range

for ‘f’

BSR

00000000

ffffffff001001da

When ‘a’ = 1 (all values of f):

The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select

000h

080h

100h

Bank 0

Bank 1

through

Bank 14

F00h

F80h

FFFh

Bank 15

SFRs

Data Memory

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5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure 5-10.

FIGURE 5-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING

Example Situation:

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh).

Locations in Bank 0 from 060h to 07Fh are mapped, as usual, to the middle half of the Access Bank.

Special Function Registers at F80h through FFFh are mapped to 80h through FFh, as usual.

Bank 0 addresses below 5Fh can still be addressed by using the BSR.

000h 05Fh 07Fh

100h 120h 17Fh

200h

F00h

F80h

FFFh

Bank 0

Bank 1

Window

Bank 1

Bank 2

through

Bank 14

Bank 15

SFRs

Data Memory

Remapping of the Access Bank applies tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before.

5.6 PIC18 Instruction Execution and the Extended Instruction Set

Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in

Section 24.2 “Extended Instruction Set”.

Bank 1 “Window”

Bank 0

SFRs

Access Bank

only

to opera-

00h

5Fh

7Fh 80h

FFh

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6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and erasable during normal operation over the entire V range.

A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 32 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code.

Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases.

A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT).

Table read operations retrieve data from program memory and places it into the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM.

Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM.

Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned.

FIGURE 6-1: TABLE READ OPERATION

Table Pointer

TBLPTRU

Note 1: Table Pointer register points to a byte in program memory.

TBLPTRH TBLPTRL

(1)

Program Memory (TBLPTR)

Instruction: TBLRD*

Program Memory

Table Latch (8-bit)

TAB LAT

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FIGURE 6-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Table Pointer

TBLPTRU

Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by

TBLPTRH TBLPTRL

TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

(1)

Program Memory (TBLPTR)

Holding Registers

Table Latch (8-bit)

TAB LAT

6.2 Control Registers

Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s.

The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory.

The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 23.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled.

The WREN bit, when set, will allow setting the WR bit and beginning a write operation. On power-up, the WREN bit is clear. WREN must be set by code before WR can be set. WREN remains set until cleared by code.

The WRERR bit is set in hardware when the WR bit is set, and cleared when the internal programming timer expires and the write operation is complete. If the write is interrupted for any reason, the WRERR bit remains set.

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly.

The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be cleared in software.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory 0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

(1)

WREN WR RD

(1)

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

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6.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM.

6.2.3 TBLPTR – TABLE POINTER REGISTER

The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.

When a TBLWT is executed, the five LSbs of the Table Pointer register (TBLPTR<4:0>) determine which of the 32 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 17 MSbs of the TBLPTR (TBLPTR<21:5>) determine which program memory block of 32 bytes is written to. For more detail, see Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example Operation on Table Pointer

TBLRD* TBLWT*

TBLRD*+ TBLWT*+

TBLRD*TBLWT*-

TBLRD+* TBLWT+*

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLPTR is not modified

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 16 15 87 0

TBLPTRU

TABLE ERASE – TBLPTR<21:6>

TABLE WRITE – TBLPTR<21:5>

TABLE READ – TBLPTR<21:0>

TBLPTRH

TBLPTRL

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6.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time.

TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation.

The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

Instruction Register

(IR)

FETCH

TBLRD

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD

TBLPTR = xxxxx0

TAB LAT

Read Register

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6.4 Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported.

When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation.

For protection, the write initiate sequence for EECON2 must be used.

A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write

6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internal program memory location is:

1. Load Table Pointer register with address of row

being erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

cycle. The long write will be terminated by the internal programming timer.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW

ERASE_ROW

Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts

MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts

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6.5 Writing to Flash Program Memory

The minimum programming block is 16 words or 32 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding registers needed to program the Flash memory. There are 32 holding registers used by the table writes for programming.

Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 32 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 32 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write.

The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.

The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device.

Note: The default value of the holding registers on

device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ‘0’ to a ‘1’. When modifying individual bytes, it is not necessary to load all 32 holding registers before executing a write operation.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

Holding Register Holding Register Holding Register Holding Register

8 8 8

Program Memory

6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internal program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execute the row erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Decrement Table Pointer.

7. Write the 32 bytes into the holding registers with

pre-increment.

8. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

TBLPTR = xxxxx2

9. Disable interrupts.

10. Write 55h to EECON2.

11. Write 0AAh to EECON2.

12. Set the WR bit. This will begin the write cycle.

13. The CPU will stall for duration of the write (about 2 ms using internal timer).

14. Re-enable interrupts.

15. Repeat from step 6 for the remaining 32 bytes.

16. Verify the memory (table read).

This procedure will require about 6 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3.

Note: Before setting the WR bit, the Table

TBLPTR = xxxx1FTBLPTR = xxxxx1TBLPTR = xxxxx0

Pointer address needs to be within the intended address range of the 32 bytes in the holding register.

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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D’64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = '0' MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER, F ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h

Req MOVWF EECON2 ; write 55h Seq MOVLW 0AAh

MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read - decrement pointer MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L

WRITE_BUFFER_BACK1 ; write first 32 bytes to Flash MOVLW D’32’ ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS1 MOVFF POSTINC0,WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; short write to holding ; register using pre-increment DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS1

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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY1 BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h

Req MOVWF EECON2 ; write 55h Seq MOVLW 0Aah

MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory WRITE_BUFFER_BACK2 ; write remaining 32 bytes to Flash MOVLW D’32’ ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS2 MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; short write to holding ; register using pre-increment DECFSZ COUNTER, F ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS2 PROGRAM_MEMORY2 BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h

Req MOVWF EECON2 ; write 55h Seq MOVLW 0AAh

MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.

6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed.

6.5.4 PROTECTION AGAINST SPURIOUS WRITES

To protect against unintended and spurious writes to Flash program memory, the write initiate sequence must be followed. In Example 6-3, the “Required Sequence” acts to protect memory from unintended writes by requiring this very specific sequence of five instructions. This sequence must be executed exactly as shown or the write will not occur.

6.6 Flash Program Operation During

Code Protection

Additional protection may be implemented using the code protection features described in Section 23.5 “Program Verification and Code Protection”.

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TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49

TABLAT Program Memory Table Latch 49

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

EECON2 EEPROM Control Register 2 (not a physical register) 51

EECON1 EEPGD CFGS

IPR2

PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52

PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52

— FREE WRERR WREN WR RD 51

Values on

page

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7.0 DATA EEPROM MEMORY

The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire V

Five SFRs are used to read and write to the data EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADR register holds the address of the EEPROM location being accessed.

The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chip to chip. Please refer to parameter D122 (Table 26-1 in Section 26.0 “Electrical Characteristics”) for exact limits.

DD range.

The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program Flash or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program Flash memory is accessed.

Control bit, CFGS, determines if the access will be to the Configuration registers or to program Flash memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete.

Note: During normal operation, the WRERR

may read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly.

The WR control bit initiates write operations. The bit can be set but not cleared in software. It is only cleared in hardware at the completion of the write operation.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be cleared in software.

7.1 EEADR Register

The EEADR register is used to address the data EEPROM for read and write operations. The 8-bit range of the register can address a memory range of 256 bytes (00h to FFh).

7.2 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM.

Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation.

The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory 0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

— FREE WRERR

(1)

WREN WR RD

(1)

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

PIC18F2423/2523/4423/4523

7.3 Reading the Data EEPROM Memory

To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).

The basic process is shown in Example 7-1.

7.4 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction.

At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software.

7.5 Write Verify

EXAMPLE 7-1: DATA EEPROM READ

MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes

Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ;

BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ;

MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

PIC18F2423/2523/4423/4523

7.6 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled.

The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “Special Features of the CPU” for additional information.

7.7 Protection Against Spurious Write

7.8 Using the Data EEPROM

The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

There are conditions when the user may not want to

Example 7-3.

write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have

Note: If data EEPROM is only used to store

been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (T

PWRT,

parameter 33).

The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again

constants and/or data that changes rarely, an array refresh is likely not required. See specification D124.

BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts

PIC18F2423/2523/4423/4523

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

EEADR EEPROM Address Register 51

EEDATA EEPROM Data Register 51

EECON2 EEPROM Control Register 2 (not a physical register) 51

EECON1 EEPGD CFGS

IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52

PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52

PIE2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52

— FREE WRERR WREN WR RD 51

Values

on page

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.

Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH

; - ARG1 MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine Multiply Method

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

Without hardware multiply 13 69 8.63 μs27.6 μs69 μs

Hardware multiply 1 1 125 ns 400 ns 1 μs

Without hardware multiply 33 91 11.4 μs36.4 μs91 μs

Hardware multiply 6 6 750 ns 2.4 μs6 μs

Without hardware multiply 21 242 30.3 μs96.8 μs 242 μs

Hardware multiply 28 28 3.5 μs 11.2 μs28 μs

Without hardware multiply 52 254 31.8 μs 102.6 μs 254 μs

Hardware multiply 35 40 5.0 μs16.0 μs40 μs

Program

Memory (Words)

Cycles

(Max)

@ 32 MHz @ 10 MHz @ 4 MHz

Time

PIC18F2423/2523/4423/4523

Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ARG2L)

) +

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L->

MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H->

MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.

; PRODH:PRODL

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 2 (-1 • ARG1H<7> • ARG2H:ARG2L • 2

) +

EXAMPLE 8-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ;

SUBWFB RES3 ; SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3 ; CONT_CODE :

; PRODH:PRODL

) +

)

PIC18F2423/2523/4423/4523

9.0 INTERRUPTS

The PIC18F2423/2523/4423/4523 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress.

There are ten registers which are used to control interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

It is recommended that the Microchip header files supplied with MPLAB names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register.

In general, interrupt sources have three bits to control their operation. They are:

• Flag bit to indicate that an interrupt event occurred

• Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.

IDE be used for the symbolic bit

When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro patibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.

mid-range devices. In Com-

PIC18F2423/2523/4423/4523

FIGURE 9-1: PIC18 INTERRUPT LOGIC

TMR0IF TMR0IE TMR0IP

RBIF RBIE RBIP

INT0IF

INT0IE

INT1IF

INT1IE SSPIF SSPIE SSPIP

ADIF ADIE ADIP

RCIF RCIE RCIP

High Priority Interrupt Generation

Low Priority Interrupt Generation

SSPIF SSPIE SSPIP

ADIF ADIE ADIP

RCIF RCIE RCIP

Additional Peripheral Interrupts

IPEN

TMR0IF TMR0IE

TMR0IP

RBIF RBIE

RBIP

INT1IF INT1IE

INT1IP

INT2IF INT2IE

INT2IP

INT1IP

INT2IF INT2IE INT2IP

IPEN

PEIE/GIEL

IPEN

GIE/GIEH PEIE/GIEL

Wake-up if in

Idle or Sleep modes

Interrupt to CPU Vector to Location

0008h

GIE/GIEH

Interrupt to CPU Vector to Location 0018h

PIC18F2423/2523/4423/4523

9.1 INTCON Registers

The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. This feature allows for software polling.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN =

1 = Enables all unmasked interrupts 0 = Disables all interrupts

When IPEN =

1 = Enables all high priority interrupts 0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN =

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

When IPEN =

1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

(1)

PIC18F2423/2523/4423/4523

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP

bit 7 RBPU

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. This feature allows for software polling.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled.

: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge 0 = Interrupt on falling edge

1 = High priority 0 = Low priority

PIC18F2423/2523/4423/4523

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority 0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority 0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. This feature allows for software polling.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled.

PIC18F2423/2523/4423/4523

9.2 PIR Registers

The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request Flag registers (PIR1 and PIR2).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit

bit 6 ADIF: A/D Converter Interrupt Flag bit

bit 5 RCIF: EUSART Receive Interrupt Flag bit

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

bit 2 CCP1IF: CCP1 Interrupt Flag bit

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

(1)

1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred

1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full

1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode: Unused in this mode.

1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred

1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow

Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIF CMIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred

bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit

1 = A high/low-voltage condition occurred (direction determined by VDIRMAG bit, HLVDCON<7>) 0 = A high/low-voltage condition has not occurred

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode: Unused in this mode.

— EEIF BCLIF HLVDIF TMR3IF CCP2IF

PIC18F2423/2523/4423/4523

9.3 PIE Registers

The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

PSPIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt

(1)

Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.

MICROCHIP PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

Peripheral Highlights:

Power-Managed Modes:

Flexible Oscillator Structure:

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Cont.’d)

Pin Diagrams (Cont.’d)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES

FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

2.2 Crystal Oscillator/Ceramic Resonators

2.3 External Clock Input

2.4 RC Oscillator

FIGURE 2-5: RC OSCILLATOR MODE

FIGURE 2-6: RCIO OSCILLATOR MODE

2.5 PLL Frequency Multiplier

2.5.1 HSPLL OSCILLATOR MODE

2.5.2 PLL AND INTOSC

2.6 Internal Oscillator Block

2.6.1 INTIO MODES

2.6.2 INTOSC OUTPUT FREQUENCY

2.6.3 OSCTUNE REGISTER

2.6.4 PLL IN INTOSC MODES

2.6.5 INTOSC FREQUENCY DRIFT

2.7 Clock Sources and Oscillator Switching

FIGURE 2-8: PIC18F2423/2523/4423/4523 CLOCK DIAGRAM

2.7.1 OSCILLATOR CONTROL REGISTER

2.7.2 OSCILLATOR TRANSITIONS

2.8 Effects of Power-Managed Modes on the Various Clock Sources

2.9 Power-up Delays

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

3.0 POWER-MANAGED MODES

3.1 Selecting Power-Managed Modes

3.1.1 CLOCK SOURCES

TABLE 3-1: POWER-MANAGED MODES

3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS

3.1.4 MULTIPLE SLEEP COMMANDS

3.2 Run Modes

3.2.1 PRI_RUN MODE

3.2.2 SEC_RUN MODE

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODE

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

3.3 Sleep Mode

3.4 Idle Modes

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

3.4.1 PRI_IDLE MODE

3.4.2 SEC_IDLE MODE

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

3.4.3 RC_IDLE MODE

3.5 Exiting Idle and Sleep Modes

3.5.1 EXIT BY INTERRUPT

3.5.2 EXIT BY WDT TIME-OUT

3.5.3 EXIT BY RESET

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DE LAY

4.0 RESET

4.1 RCON Register

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

4.2 Master Clear (MCLR)

4.3 Power-on Reset (POR)