Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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Microchip disclaims all liability arising from this information and
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life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programmin g, IC SP, ICEPI C, M PASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartT el and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39632B-page iiPreliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
28/40/44-Pin High-Performance, Enhanced Flash USB
Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control , Interr upt, Isochro nous and Bu lk
Transfers
• Supports up to 32 endpoints (16 bidirectional)
• 1-Kbyte dual access RAM for USB
• On-chip USB transceiver with on-chip voltage
regulator
• Interface for off-chip USB transceiver
• Streaming Parallel Port (SPP) for USB streaming
transfers (40/44-pin devices only)
Power-Managed Modes:
• Run: CPU on , peripherals on
• Idle: CPU off, peripherals on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 µA typical
• Sleep mode currents down to 0.1 µA typical
• Timer1 oscillator: 1.1 µA typical, 32 kHz, 2V
• Watchdog Timer: 2.1 µA typical
• Two -Spe ed Os ci ll ator Start-up
Flexible Oscillator Struc ture:
• Four Crystal modes including High Precision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal oscillator block:
- 8 user-selectable frequencies, from
31 kHz to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Dual oscillator options allow microcontroller and
USB module to run at different clock speeds
• Fail-Safe Clock Monitor
- Allows for safe shutdown if any clock stops
Peripheral Highlight s:
• High-current sink/source 25 mA/25 mA
• Three external interrupts
• Four Timer modules (Timer0 to Timer3)
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (T
- Compare is 16-bit, max. resolution 100 ns (T
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Enhanced USART module:
- LIN bus support
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I
Master and Slave modes
• 10-bit, up to 13-channels Analog-to-Digital Converter
module (A/D) with programmable acquisition time
• Dual analog comparators with input multiplexing
CY/16)
CY)
2
C™
Special Microcontroller Features:
• C compiler optimized architecture with optional
extended instruction set
• 100,000 erase/write cycl e Enhan ced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Programmable Code Protection
• Single-Supply 5V In -Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Optional dedicated ICD/ICSP port (44-pin devices only)
8.08 x 8 Hardware Multiplier............................................................................................................................................................95
17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 163
18.0 Streaming Parallel Port ............................................................................................................................................................ 187
19.0 Master Synchronous Serial Port (MSSP) Module ....................................................................................................................193
25.0 Special Features of the CPU........................................................ ..................... ....................................................................... 279
26.0 Instruction Set Summary..........................................................................................................................................................301
27.0 Development Support............................................................................................................................................................... 351
29.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 395
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 406
Appendix E: Migration From Mid-Range to Enhanced Devices......................................................................................................... 407
Appendix F: Migration From High-End to Enhanced Devices............................................................ .... .. .... .. ....................................407
Index .................................................................................................................................................................................................. 409
Systems Information and Upgrade Hot Line...................................................................................................................................... 421
PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 423
DS39632B-page 4Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS39632B-page 6Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
1.0DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F2455• PIC18LF2455
• PIC18F2550• PIC18LF2550
• PIC18F4455• PIC18LF4455
• PIC18F4550• PIC18LF4550
This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition
of high endurance, Enhanced Flash program memory.
Inaddition to these features, the
PIC18F2455/2550/445 5/4550 family introd uces desig n
enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive
applications.
1.1New Core Features
1.1.1nanoWatt TECHNOLOGY
All of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can significantly reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these st ates, powe r consumpt ion can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The
power-managed mod es are invo ked b y use r code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 28.0 “Electrical Characteristics” for
values.
1.1.3MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range o f choices i n develo ping applica tion
hardware. These include:
• Four Crystal modes using crystals or ceramic
resonators.
• Four External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31kHz, stable over
temperature and V
6 user selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This optio n frees an osc illator pi n for
use as an additional general purp ose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and
external oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.
• Asynchronous dual clock operation, allowing the
USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.
Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller i s
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
DD), as well as a range of
1.1.2UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a fully featured Universal Serial Bus
communications module that is c omplian t with the USB
Specification Revision 2.0. The module supports both
low-speed and full speed communication for all supported data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of external transcei vers and volt age regula tors.
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, located in the p rote cte d Bo ot Blo ck at th e
top of program memory, it becomes possible to
create an application that can update itself in the
field.
• Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an optional extension to th e PIC18 instr uction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
application code originally developed in high-lev el
languages such as C.
• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto- sh ut d ow n for
disabling PWM output s on interrup t or other selec t
conditions and auto-restart to reactivate outputs
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detec tion an d a 16-bit Baud
Rate Generator for improved resolu tion. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without wa iting for a sampling pe riod and
thus, reducing code overhead.
• Dedicated ICD/ICSP Port: These dev ices
introduce the use of debugger and programming
pins that are not multiplexed with other microcontroller features. Offered as an option in select
packages, this fe ature allo ws users to d evelop I/O
intensive applications while retaining the ability to
program and debug in the circuit.
1.3Details on Individual Family
Members
Devices in the PIC18F 2455/2550 /4455/4550 famil y are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in six
ways:
1.Flash program memory (24Kbytes for
PIC18FX455 devices, 32Kbytes for
PIC18FX550).
2.A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3.I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).
4.CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP modules,
40/44-pin devices have one standard CCP
module and one ECCP module).
5.Streaming Parallel Port (present only on
40/44-pin devices).
All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available as
both standard and low-voltage devices. Standard
devices with Enhan ced Flas h memory, designated with
an “F” in the part number (such as PIC18F2550),
accommodate an ope rati ng V
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), func tion over an e xtended V
of 2.0V to 5.5V.
DD range of 4.2V to 5.5V.
DD range
DS39632B-page 8Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
TABLE 1-1:DEVICE FEATURES
FeaturesPIC18F2455PIC18F2550PIC18F4455PIC18F4550
Operating FrequencyDC – 48 MHzDC – 48 MHzDC – 48 MHzDC – 48 MHz
Program Memory (Bytes)24576327682457632768
Program Memory (Instruction s)12288163841228816384
Data Memory (Bytes)2048204820482048
Data EEPROM Memory (Bytes)256256256256
Interrupt Sources19192020
I/O PortsPorts A, B, C, (E)Ports A, B, C, (E)Ports A, B, C, D, E Ports A, B, C, D, E
Timers4444
Capture/Compare/PWM Modules2211
Enhanced Capture/
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
Note 1:Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
Number
PDIP,
SOIC
10
Pin
Buffer
Type
1
9
Type
ST
I
P
I
ST
IIAnalog
Analog
O
O
I/O
—
—
TTL
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pins.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OS C2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Description
DS39632B-page 12Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
T ABLE 1-2:PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
11818
133230
143331
Pin
Buffer
Type
I
P
I
IIAnalog
Analog
O
O
I/O
Type
Master Clear (input) or programming voltage (input).
ST
ST
—
—
TTL
configuration bit is cleared.
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pins.)
Oscillator cryst al or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Description
DS39632B-page 16Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
T ABLE 1-3:PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
REF+
REF+
/
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
21919
32020
42121
52222
62323
72424
Pin
Buffer
Type
Type
I/OITTL
Analog
I/OITTL
Analog
I/O
I
Analog
I
Analog
O
Analog
I/O
I
Analog
I
Analog
I/O
I
O
I
I/O
I
Analog
I
I
Analog
O
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
TTL
TTL
ST
ST
—
TTL
TTL
TTL
—
configuration bit is cleared.
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
Digital I/O.
Analog input 4.
SPI™ slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
3398
34109
351110
361211
371414
381515
391616
401717
Pin
Type
I/O
I
I
I
I
I/O
I/O
I
I
I/O
I/O
I/O
I
I
O
I/O
I
I/O
O
I/O
I
I
O
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
Buffer
Type
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
TTL
Analog
ST
ST
ST
ST
TTL
Analog
ST
ST
ST
TTL
Analog
ST
—
TTL
Analog
ST
—
TTL
Analog
TTL
—
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
configuration bit is cleared.
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI™ data in.
2
C™ data I/O.
I
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Description
2
C mode.
DS39632B-page 18Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
T ABLE 1-3:PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
153432
163535
173636
234242
244343
254444
2611
Pin
Type
I/O
O
I
I/O
I
I/O
O
I/O
I/O
O
I
I/O
I
I
I/O
I
I/O
O
I/O
I/O
I
I/O
O
Buffer
Type
PORTC is a bidirectional I/O port.
ST
—
ST
ST
CMOS
ST
—
ST
ST
TTL
TTL
—
TTL
TTL
—
TTL
ST
—
ST
ST
ST
ST
—
configuration bit is cleared.
Digital I/O.
Timer1 oscillat or outpu t.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillat or inpu t.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 PWM output, channel A.
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
Digital I/O.
EUSART asynchronous tran smit.
EUSART synchronous clock (see RX/DT).
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI™ data out.
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
193838
203939
214040
224141
2722
2833
2944
3055
Pin
Buffer
Type
Type
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
Description
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.
Digital I/O.
Streaming Parallel Port data.
Digital I/O.
Streaming Parallel Port data.
Digital I/O.
Streaming Parallel Port data.
Digital I/O.
Streaming Parallel Port data.
Digital I/O.
Streaming Parallel Port data.
ST
TTL
—
ST
TTL
—
ST
TTL
—
configuration bit is cleared.
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.
DS39632B-page 20Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
T ABLE 1-3:PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
RE2/AN7/OESPP
RE2
AN7
OESPP
RE3—————See MCLR
VSS12, 31 6, 30, 316, 29P—Ground reference for logic and I/O pins.
V
DD11, 32 7, 8,
USB183737O—Internal USB 3.3V voltage regulator output.
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
/ICVPP
ICRST
ICVPP
ICPORTS
ST = Schmitt Trigger input with CMOS levels I= Input
O= Output P= Power
2:Default assignment for CCP2 when CCP2MX configuration bit is set.
3:These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Pin Number
PDIP QFN TQFP
82525
92626
102727
7, 28P—Positive supply for logic and I/O pins.
28, 29
——12
——13
——33
——34P—No Connect or 28-pin device emulation.
Pin
Buffer
Type
I/O
I
Analog
O
I/O
I
Analog
O
I/O
I
Analog
O
I/O
I/OSTST
I/O
I/OSTST
I
P
Type
PORTE is a bidirectional I/O port.
ST
—
ST
—
ST
—
—
—
configuration bit is cleared.
Digital I/O.
Analog input 5.
SPP clock 1 output.
Digital I/O.
Analog input 6.
SPP clock 2 output.
Digital I/O.
Analog input 7.
SPP output enable output.
DS39632B-page 22Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
2.0OSCILLATOR
CONFIGURATIONS
2.1Overview
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock system than previous PIC18F devices. The add ition of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full speed specifications.
To accommodate these requirements, PIC18F245 5/
2550/4455/4550 de vices in clude a new c lock bran ch to
provide a 48 MHz clock for full speed USB oper ation.
Since it is driven from the primary clock source, an
additional system of prescalers and postscalers has
been added to accomm odate a wide r ange of oscilla tor
frequencies. An overview of the oscillator structure is
shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1OSCILLATOR CONTROL
The operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two c onfiguration registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator ControlRegister”.
The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2
“OSCTUNE Register”.
2.2Oscillator Types
PIC18F2455/2550/445 5/4550 devices can be operated
in twelve distinct oscillator modes. In contrast with previous PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 configuration
bits to select one of these modes:
1.XTCrystal/Resonator
2.XTPLL Crystal/Resonator with PLL enabled
3.HSHigh-Speed Crystal/Resonator
4.HSPLL High-Speed Crystal/Resonator
with PLL enabled
5.ECExternal Clock with F
6.ECIOExternal Clock with I/O on RA6
7.ECPLL External Clock with PLL enabled
and F
OSC/4 output on RA6
8.ECPIO External Clock with PLL enabled,
I/O on RA6
9.INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source
10. INTXTInternal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source
11. INTIOInternal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digital I/O on RA6
12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
OSC/4 output on RA6
F
OSC/4 output
2.2.1OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PICmicro
clocks were driven by a single oscillator source; the
usual sources were primary, secondary or the internal
oscillator. With PIC18F2455/2550/4455/4550 devices,
the primary oscillator becomes part of the USB module
and cannot be associated to any other clock source.
Thus, the USB module must be cl ocked from the primary
clock source; however, the microcontroller core and
other peripherals can be separately clocked from the
secondary or internal oscillators as before.
Because of the timing requirements imposed by USB,
an internal clock of eit her 6MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock re quirement and sti ll provide fl exibility for cloc king th e rest of the de vice from the pr imary
oscillator source. These are detailed in Section 2.3“Oscillator Settings for USB”.
DS39632B-page 24Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
2.2.2CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note:Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
FIGURE 2-2:CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)
(1)
C1
(1)
C2
Note 1: See T able 2-1 and T able 2-2 for initial values of
2: A series resistor (R
3: R
OSC1
XTAL
(2)
RS
OSC2
C1 and C2.
strip cut crystals.
F varies with the oscillator mode chosen.
(3)
RF
Sleep
PIC18FXXXX
S) may be required for AT
To
Internal
Logic
TABLE 2-1:CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
ModeFreqOSC1OSC2
XT4.0 MHz33 pF33 pF
HS8.0 MHz
16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. Thesevalues are not optimized.
Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following Table 2-2 for additional
information.
Resonators Used:
16.0 MHz
4.0 MHz
8.0 MHz
27 pF
22 pF
27 pF
22 pF
T ABLE 2-2:CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq
XT4 MHz27 pF27 pF
HS4 MHz27 pF27 pF
8 MHz22 pF22 pF
20 MHz15 pF15 pF
Capacitor values are for design guidance only.
These capacit ors wer e tested with th e crystal s listed
below for basi c st a r t-up a nd ope rati on. These values
are not optimized.
Different cap acitor valu es may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following this table for additional
information.
Crystals Used:
Note 1: Higher capac itance inc reases th e stabilit y
of oscillator but also increases the
start-up time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
DD and temperature range that is
the V
expected for the application.
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.
An external clock may also be used when the microcontroller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external cl ock source to b e connecte d to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
FIGURE 2-4:EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
2.2.4PLL FREQUENCY MULTIPLIER
PIC18F2455/2550/425 5/4550 dev ices include a Ph ase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
There is a lso a separ at e pos tscal er opt ion f or deri ving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the pos tscaler fo r XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler div id es the os ci ll ator inp ut by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.
Clock from
Ext. System
OSC/4
F
OSC1/CLKI
PIC18FXXXX
OSC2/CLKO
The ECIO and ECPIO Oscillator modes function like
the EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/
O pin becomes bit 6 of PORTA (RA6). Figure 2-5
shows the pin connections for the ECIO Oscillator
mode.
FIGURE 2-5:EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
Clock from
Ext. System
RA6
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
FIGURE 2-6:PLL BLOCK DIAGRAM
(HS MODE)
HS/EC/ECIO/XT Oscillator Enable
(from CONFIG1H Register)
OSC2
Oscillator
OSC1
and
Prescaler
PLL Enable
Phase
Comparator
IN
F
FOUT
÷24
Loop
Filter
VCO
SYSCLK
MUX
DS39632B-page 26Preliminary 2004 Microchip Technology Inc.
PIC18F2455/2550/4455/4550
2.2.5INTERNAL OSCILLATOR BLOCK
The PIC18F2455/2550/4455/4550 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. If the USB peripheral is not used, the
internal oscillator may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INT OSC postsca ler which can provide a
range of clock frequencies from 31 kHz to 4 MHz. The
INTOSC output is enabled when a clock frequency
from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also ena bled autom atically when an y of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Spe ed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).
2.2.5.1Internal Oscillator Modes
When the internal oscillator is used as the microcontroller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
USB clock source is determined by the particular
internal oscillator mode.
There are four distinct modes available:
1.INTHS mode: The USB clock is provided by the
oscillator in HS mode.
2.INTXT mode: The USB clock is provided by the
oscillator in XT mode.
3.INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs F
4.INTIO mode: The U SB clock i s provid ed by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).
Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.
OSC/4.
2.2.5.2OSCTUNE Register
The internal oscillator ’s output has been calibrated at
the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately,
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues du ring this shift.
There is no indication that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator pr ovides the clock sourc e when the 31 kHz
frequency option is se lected . This is c overed in greater
detail in Section 2.4.1 “Oscillator Control Register”.
2.2.5.3Internal Oscillator Output Frequency
and Drift
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or temperature changes, which can affect the controller operation
in a variety of ways.
The low-frequency IN TRC o sc il lat or o pe rates i nd ependently of the INTOSC so urce. Any ch anges in INTO SC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
bit 6-5Unimplemented: Read as ‘0’
bit 4-0TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
——TUN4TUN3TUN2TUN1TUN0
2.2.5.4Compensating for INTOSC Drift
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be req uired when it beg ins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate,
increment OSCTUNE to increase t he clo ck freque nc y.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
Finally, a CCP module can use free runnin g Timer1 (or
Timer3), cl oc ked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The ti me of the first ev ent is capt ured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is su btra cte d fro m the time of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculate d
time, the internal oscillator block is r unning to o slow ; t o
compensate, increment the OSCTUNE register.
DS39632B-page 28Preliminary 2004 Microchip Technology Inc.
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