MICROCHIP PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550 DATA SHEET

PIC18F2455/2550/4455/4550

Data Sheet

28/40/44-Pin High-Performance,

Enhanced Flash USB Microcontrollers

with nanoWatt Technology

 2004 Microchip Technology Inc. Preliminary DS39632B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR­RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
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written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programmin g, IC SP, ICEPI C, M PASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartT el and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS39632B-page ii Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

28/40/44-Pin High-Performance, Enhanced Flash USB

Microcontrollers with nanoWatt Technology

Universal Serial Bus Features:

• USB V2.0 Compliant

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Supports Control , Interr upt, Isochro nous and Bu lk

Transfers

• Supports up to 32 endpoints (16 bidirectional)

• 1-Kbyte dual access RAM for USB

• On-chip USB transceiver with on-chip voltage

regulator

• Interface for off-chip USB transceiver

• Streaming Parallel Port (SPP) for USB streaming

transfers (40/44-pin devices only)

Power-Managed Modes:

• Run: CPU on , peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 µA typical

• Sleep mode currents down to 0.1 µA typical

• Timer1 oscillator: 1.1 µA typical, 32 kHz, 2V

• Watchdog Timer: 2.1 µA typical

• Two -Spe ed Os ci ll ator Start-up

Flexible Oscillator Struc ture:

• Four Crystal modes including High Precision PLL

for USB

• Two External Clock modes, up to 48 MHz

• Internal oscillator block:

- 8 user-selectable frequencies, from
31 kHz to 8 MHz

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Dual oscillator options allow microcontroller and
USB module to run at different clock speeds

• Fail-Safe Clock Monitor

- Allows for safe shutdown if any clock stops

Peripheral Highlight s:

• High-current sink/source 25 mA/25 mA

• Three external interrupts

• Four Timer modules (Timer0 to Timer3)

• Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (T

- Compare is 16-bit, max. resolution 100 ns (T

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- Multiple output modes

- Selectable polarity

- Programmable dead time

- Auto-Shutdown and Auto-Restart

• Enhanced USART module:

- LIN bus support

• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I
Master and Slave modes

• 10-bit, up to 13-channels Analog-to-Digital Converter
module (A/D) with programmable acquisition time

• Dual analog comparators with input multiplexing

CY/16)

CY)

2

C™

Special Microcontroller Features:

• C compiler optimized architecture with optional
extended instruction set

• 100,000 erase/write cycl e Enhan ced Flash
program memory typical

• 1,000,000 erase/write cycle Data EEPROM
memory typical

• Flash/Data EEPROM Retention: > 40 years

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Programmable Code Protection

• Single-Supply 5V In -Circuit Serial
Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Optional dedicated ICD/ICSP port (44-pin devices only)

• Wide operating voltage range (2.0V to 5.5V)

Program Memory Data Memory

10-bit

Device

PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3
PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

 2004 Microchip Technology Inc. Preliminary DS39632B-page 1

Flash

(bytes)

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

I/O

A/D (ch)

CCP/ECCP

(PWM)

SPP

SPI™

MSSP

Master

Timers

2

C™

I

EAUSART

8/16-bit

Comparators

PIC18F2455/2550/4455/4550

Pin Diagrams

28-Pin PDIP, SOIC

RA5/AN4/SS

40-Pin PDIP

MCLR/VPP/RE3

RA0/AN0

RA2/AN2/V

RA4/T0CKI/C1OUT/RCV

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RA1/AN1

REF-/CVREF

RA3/AN3/VREF+

/HLVDIN/C2OUT

OSC1/CLKI

OSC2/CLKO/RA6

(1)

/UOE

RC2/CCP1

V

V

USB

PIC18F2550

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM

(1)

/VPO

1
2
3
4
5
6
7

SS

8
9

10
11

12
13
14

PIC18F2455

MCLR/VPP/RE3

RA2/AN2/V

RA3/AN3/VREF+

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS

/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP

RE2/AN7/OESPP

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RC2/CCP1/P1A

RA0/AN0
RA1/AN1

REF-/CVREF

V

VSS

OSC1/CLKI

(1)

/UOE

V

USB

RD0/SPP0
RD1/SPP1

DD

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2
RB2/AN8/INT2/VMO

RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
V

DD

VSS
RD7/SPP7/P1D
RD6/SPP6/P1C

RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2

(1)

/VPO

DS39632B-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

PIC18F2455/2550/4455/4550

/UOE

(1)

(2)

RC7/RX/DT/SDO

RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C

V

(1)

VDD

/VPO

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2

44-Pin QFN

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

4443424140

1
2
3

SS

6
7
8
9
10
11

121314

(2)

(2)

/ICPGC

(2)

(2)

NC/ICCK

PIC18F4455
PIC18F4550

15

/ICPGD

RB5/KBI1/PGM

NC/ICDT

RB4/AN11/KBI0/CSSPP

RD2/SPP2

RD1/SPP1

39

38

16

17

1819202122

RB7/KBI3/PGD

RB6/KBI2/PGC

USB

RD0/SPP0

V

RC2/CCP1/P1A

RC1/T1OSI/CCP2

NC/ICPORTS

363435

37

33
32
31
30
29
28
27
26
25
24
23

RA1/AN1

RA0/AN0

/VPP/RE3

REF-/CVREF

MCLR

RA3/AN3/VREF+

RA2/AN2/V

NC/ICRST
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
V
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS
RA4/T0CKI/C1OUT/RCV

(2)

(2)

/ICVPP

SS

/HLVDIN/C2OUT

PIC18F4455
PIC18F4550

 2004 Microchip Technology Inc. Preliminary DS39632B-page 3

PIC18F2455/2550/4455/4550

Table of Contents

1.0 Device Overview..........................................................................................................................................................................7

2.0 Oscillator Configurations............................................................................................................................................................ 23

3.0 Power-Managed Modes .................................................................................................. .. ..... .................................................... 35

4.0 Reset.......................................................................................................................................................................................... 43

5.0 Memory Organization.................................................................................................................................................................57

6.0 Flash Program Memory............... ..................... ..................... ..................... ..................... ...........................................................79

7.0 Data EEPROM Memory............................................................... ..................... ..................... .................................................... 89

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................95

9.0 Interrupts....................................................................................................................................................................................97

10.0 I/O Ports......... ............................................................. ..................... ........................................................................................ 111

11.0 Timer0 Module ......................................................................................................................................................................... 125

12.0 Timer1 Module ......................................................................................................................................................................... 129

13.0 Timer2 Module ......................................................................................................................................................................... 135

14.0 Timer3 Module ......................................................................................................................................................................... 137

15.0 Capture/Compare/PWM (CCP) Modules .................................................................................................................................141

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 149

17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 163

18.0 Streaming Parallel Port ............................................................................................................................................................ 187

19.0 Master Synchronous Serial Port (MSSP) Module ....................................................................................................................193

20.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART).......................................................................................233

21.0 10-Bit Analog-to-Digital Converter (A/D) Module .....................................................................................................................253

22.0 Comparator Module...................................................................................... ....... .... .... .. ...........................................................263

23.0 Comparator Voltage Reference Module................................................. .... .. ....... .... .. .... .. ....... .... .. ............................................ 269

24.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................273

25.0 Special Features of the CPU........................................................ ..................... ....................................................................... 279

26.0 Instruction Set Summary..........................................................................................................................................................301

27.0 Development Support............................................................................................................................................................... 351

28.0 Electrical Characteristics..........................................................................................................................................................357

29.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 395

30.0 Packaging Information.......................... ..................... ..................... ..................... ..................................................................... 397

Appendix A: Revision History.............................................................................................................................................................405

Appendix B: Device Differences.........................................................................................................................................................405

Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 406

Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 406

Appendix E: Migration From Mid-Range to Enhanced Devices......................................................................................................... 407

Appendix F: Migration From High-End to Enhanced Devices............................................................ .... .. .... .. ....................................407

Index .................................................................................................................................................................................................. 409

On-Line Support........................................................................ .. .... .. ......... .... .. .... ......... .. ................................................................... 421

Systems Information and Upgrade Hot Line...................................................................................................................................... 421

Reader Response.............................................................................................................................................................................. 422

PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 423

DS39632B-page 4 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 5

PIC18F2455/2550/4455/4550

NOTES:

DS39632B-page 6 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F2455 • PIC18LF2455

• PIC18F2550 • PIC18LF2550

• PIC18F4455 • PIC18LF4455

• PIC18F4550 • PIC18LF4550

This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition
of high endurance, Enhanced Flash program memory.
In addition to these features, the
PIC18F2455/2550/445 5/4550 family introd uces desig n
enhancements that make these microcontrollers a log­ical choice for many high-performance, power sensitive
applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can signifi­cantly reduce power consumption during operation.
Key items include:

• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these st ates, powe r consumpt ion can be
reduced even further, to as little as 4% of normal
operation requirements.

• On-the-fly Mode Switching: The
power-managed mod es are invo ked b y use r code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.

• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 28.0 “Electrical Characteristics” for
values.

1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range o f choices i n develo ping applica tion
hardware. These include:

• Four Crystal modes using crystals or ceramic

resonators.

• Four External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31kHz, stable over
temperature and V
6 user selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This optio n frees an osc illator pi n for
use as an additional general purp ose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and
external oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.

• Asynchronous dual clock operation, allowing the

USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.

Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller i s
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

DD), as well as a range of

1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a fully featured Universal Serial Bus
communications module that is c omplian t with the USB
Specification Revision 2.0. The module supports both
low-speed and full speed communication for all sup­ported data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of external transcei vers and volt age regula tors.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 7

PIC18F2455/2550/4455/4550

1.2 Other Special Features

• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.

• Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, located in the p rote cte d Bo ot Blo ck at th e
top of program memory, it becomes possible to
create an application that can update itself in the
field.

• Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an optional extension to th e PIC18 instr uction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
application code originally developed in high-lev el
languages such as C.

• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto- sh ut d ow n for
disabling PWM output s on interrup t or other selec t
conditions and auto-restart to reactivate outputs
once the condition has cleared.

• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detec tion an d a 16-bit Baud
Rate Generator for improved resolu tion. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).

• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without wa iting for a sampling pe riod and
thus, reducing code overhead.

• Dedicated ICD/ICSP Port: These dev ices
introduce the use of debugger and programming
pins that are not multiplexed with other micro­controller features. Offered as an option in select
packages, this fe ature allo ws users to d evelop I/O
intensive applications while retaining the ability to
program and debug in the circuit.

1.3 Details on Individual Family Members

Devices in the PIC18F 2455/2550 /4455/4550 famil y are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.

The devices are differentiated from each other in six
ways:

1. Flash program memory (24Kbytes for

PIC18FX455 devices, 32Kbytes for
PIC18FX550).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have 2 standard CCP modules,
40/44-pin devices have one standard CCP
module and one ECCP module).

5. Streaming Parallel Port (present only on

40/44-pin devices).

All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and
Table 1-3.

Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available as
both standard and low-voltage devices. Standard
devices with Enhan ced Flas h memory, designated with
an “F” in the part number (such as PIC18F2550),
accommodate an ope rati ng V
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), func tion over an e xtended V
of 2.0V to 5.5V.

DD range of 4.2V to 5.5V.

DD range

DS39632B-page 8 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-1: DEVICE FEATURES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory (Instruction s) 12288 16384 12288 16384
Data Memory (Bytes) 2048 2048 2048 2048
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/

Compare/PWM Modules
Serial Communications MSSP,

Enhanced USART

Universal Serial Bus (USB)
Module

Streaming Parallel Port (SPP) No No Yes Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators 2 2 2 2
Resets (and Delays) POR, BOR,

RESET Instruction,

MCLR

Programmable Low-Voltage
Detect

Programmable Brown-out Reset Yes Yes Y es Yes
Instruction Set 75 Instructions;

83 with Extended

Packages 28-pin PDIP

0011

MSSP,

Enhanced USART

1111

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

WDT

Yes Yes Yes Yes

Instruction Set

enabled

28-pin SOIC

Stack Full,

Stack Underflow

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

28-pin PDIP
28-pin SOIC

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

MSSP,

Enhanced USART

POR, BOR,

RESET Instruction,

Stack Full,

Stac k U nde rflo w

(PWRT, OST),

(optional),

MCLR

WDT

75 Instructions;

83 with Extended

Instruction Set

enabled

40-pin PDIP

44-pin QFN

44-pin TQFP

 2004 Microchip Technology Inc. Preliminary DS39632B-page 9

PIC18F2455/2550/4455/4550

FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOC K DIAGR AM

T able Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Instruction Bus <16>

(2)

OSC1

(2)

OSC2

T1OSI

T1OSO

(1)

MCLR

VDD,

SS

V

USB

V

20

8

Table Latch

Instruction

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

ROM Latch

IR

Decode &

Control

Start-up Timer

Clock Monitor

USB Voltage

Regulator

Data Bus<8>

8

8

State Machine
Control Signals

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Data Latch

Data Memory

(2Kbytes)

Address Latch

12

Data Address< 12>

44

12

FSR0
FSR1
FSR2

logic

8 x 8 Multiply

W

8

ALU<8>

Access

Bank

PRODLPRODH

8

8

12

8

BSR

3

BITOP

Band Gap
Reference

8

inc/dec

Address

Decode

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

PORTB

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

PORTC

8

8

8

PORTE

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

MCLR/VPP/RE3

(3)

/VPO

(3)

(1)

/UOE

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: RB3 is the alternate pin for CCP2 multiplexing.

Data

EEPROM

CCP1

CCP2

MSSP

Timer2Timer1 Timer3Timer0

EUSART

ADC

10-bit

USB

DS39632B-page 10 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM

T able Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

20

8

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

Data Bus<8>

8

PCH PCL

8

Data Latch

Data Memory

(2 Kbytes)

Address Latch

12

Data Address< 12>

12

44

BSR

FSR0
FSR1
FSR2

inc/de c

logic

Access

Bank

12

PORTA

PORTB

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS /HL VDIN/C2OUT
OSC2/CLKO/RA6

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2

(4)

/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

Instruction Bus <16>

VDD,

SS

V

(2)

OSC1

(2)

OSC2
T1OSI
T1OSO

(3)

ICPGC

(3)

ICPGD
ICPORTS
ICRST
MCLR

V

(3)

(3)

(1)

USB

ROM Latch

IR

Instruction
Decode &

Internal

Oscillator

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply
Programming

In-Circuit

Debugger

Control

USB Voltage

Regulator

State Machine
Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Fail-Safe

Clock Monitor

3

BITOP

8

Band Gap
Reference

Address

Decode

8 x 8 Multiply

8

ALU<8>

PORTC

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

(4)

/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP

8

RC6/TX/CK
RC7/RX/DT/SDO

PRODLPRODH

PORTD

8

W

8

8

RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

8

8

PORTE

RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3

(1)

BOR

HLVD

Comparator

Note 1: RE3 is multiplexed with MCLR

Data

EEPROM

ECCP1

Timer2Timer1 Timer3Timer0

CCP2

MSSP

EUSART

ADC

10-bit

and is only av ailable when the MCLR Resets are disabled.

USB

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 25.9 “Special ICPORT Features ( Designated

Packages Only)” for additional information.

4: RB3 is the alternate pin for CCP2 multiplexing.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 11

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS

Pin

Pin Name

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2
CLKO
RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.

Number

PDIP,
SOIC

10

Pin

Buffer

Type

1

9

Type

ST

I

P

I

ST

IIAnalog

Analog

O
O

I/O

—
—

TTL

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage inpu t.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pins.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OS C2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

Description

DS39632B-page 12 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS
HL VDIN/C2OUT

RA6 — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

REF-/CVREF

RA2
AN2
VREF-

REF

CV

REF+

RA3
AN3

REF+

V

RA4
T0CKI
C1OUT
RCV

/

RA5
AN4
SS
HLVDIN
C2OUT

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX configuration bit is set.

Number

PDIP,
SOIC

2

3

4

5

6

7

Pin

Buffer

Type

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I/O

I/O

I/O

TTL

I

Analog

I

Analog

O

Analog

TTL

I

Analog

I

Analog

I

O

I

TTL

TTL

I

Analog

I

TTL

I

Analog

O

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

ST
ST

—

—

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
SPI™ slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

Description

 2004 Microchip Technology Inc. Preliminary DS39632B-page 13

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RB0/AN12/INT0/FLT0/
SDI/SDA

RB0
AN12
INT0
FLT0
SDI
SDA

RB1/AN10/INT1/SCK/
SCL

RB1
AN10
INT1
SCK
SCL

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/CCP2/VPO

RB3
AN9

(1)

CCP2
VPO

RB4/AN11/KBI0

RB4
AN1 1
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.

Number

PDIP,
SOIC

21

22

23

24

25

26

27

28

Pin

Type

I/O

I
I
I
I

I/O

I/O

I

I
I/O
I/O

I/O

I

I

O

I/O

I
I/O

O

I/O

I

I

I/O

I
I/O

I/O

I
I/O

I/O

I
I/O

Buffer

Type

TTL

Analog

ST
ST
ST
ST

TTL

Analog

ST
ST
ST

TTL

Analog

ST

—

TTL

Analog

ST

—

TTL

Analog

TTL

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI™ data in.

2

C™ data I/O.

I

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

2

C mode.

DS39632B-page 14 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/UOE

RC1
T1OSI

(2)

CCP2
UOE

RC2/CCP1

RC2
CCP1

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT/SDO

RC7
RX
DT

SDO
RE3 — — — See MCLR
VUSB 14 O — Internal USB 3.3V voltage regulator.
VSS 8, 19 P — Ground reference for logic and I/O pins.

DD 20 P — Positive supply for logic and I/O pins.

V
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.

Number

PDIP,
SOIC

11

12

13

15

16

17

18

Pin

Type

I/O

O

I

I/O

I

I/O

—

I/O
I/O

I

I/O

I

I

I/O

O

I/O

O

I/O

I/O

I

I/O

O

Buffer

Type

ST

—

ST

ST

CMOS

ST

—

ST
ST

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

—

Description

PORTC is a bidirectional I/O port.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous trans mit.
EUSART synchronous clock (se e RX/DT) .

Digital I/O.
EUSART asynchronous rece iv e.
EUSART synchronous dat a (se e TX/CK).
SPI™ data out.

/VPP/RE3 pin.

output.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 15

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS

Pin Name

/VPP/RE3

MCLR

MCLR
VPP

RE3

OSC1/CLKI

OSC1
CLKI

OSC2/CLKO/RA6

OSC2
CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

11818

13 32 30

14 33 31

Pin

Buffer

Type

I

P

I

IIAnalog

Analog

O
O

I/O

Type

Master Clear (input) or programming voltage (input).

ST

ST

—
—

TTL

configuration bit is cleared.

Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pins.)

Oscillator cryst al or clock output.

Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

Description

DS39632B-page 16 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/VREF-/

REF

CV

RA2
AN2

REF-

V
CV

REF

RA3/AN3/V

RA3
AN3
V

RA4/T0CKI/C1OUT/
RCV

RA4
T0CKI
C1OUT
RCV

RA5/AN4/SS
HLVDIN/C2OUT

RA5
AN4
SS
HLVDIN
C2OUT

RA6 — — — — — See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

REF+

REF+

/

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

21919

32020

42121

52222

62323

72424

Pin

Buffer

Type

Type

I/OITTL

Analog

I/OITTL

Analog

I/O

I

Analog

I

Analog

O

Analog

I/O

I

Analog

I

Analog

I/O

I

O

I

I/O

I

Analog
I
I

Analog

O

PORTA is a bidirectional I/O port.

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

TTL

TTL

ST
ST

—

TTL

TTL
TTL

—

configuration bit is cleared.

Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

Digital I/O.
Analog input 3.
A/D reference voltage (high) input.

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

Digital I/O.
Analog input 4.
SPI™ slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

Description

 2004 Microchip Technology Inc. Preliminary DS39632B-page 17

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/AN12/INT0/
FLT0/SDI/SDA

RB0
AN12
INT0
FLT0
SDI
SDA

RB1/AN10/INT1/SCK/
SCL

RB1
AN10
INT1
SCK
SCL

RB2/AN8/INT2/VMO

RB2
AN8
INT2
VMO

RB3/AN9/CCP2/VPO

RB3
AN9

(1)

CCP2
VPO

RB4/AN11/KBI0/CSSPP

RB4
AN11
KBI0
CSSPP

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

33 9 8

34 10 9

35 11 10

36 12 11

37 14 14

38 15 15

39 16 16

40 17 17

Pin

Type

I/O

I
I
I
I

I/O

I/O

I

I
I/O
I/O

I/O

I

I

O

I/O

I
I/O

O

I/O

I

I

O

I/O

I
I/O

I/O

I
I/O

I/O

I
I/O

Buffer

Type

PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.

TTL

Analog

ST
ST
ST
ST

TTL

Analog

ST
ST
ST

TTL

Analog

ST

—

TTL

Analog

ST

—

TTL

Analog

TTL

—

TTL
TTL

ST

TTL
TTL

ST

TTL
TTL

ST

configuration bit is cleared.

Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI™ data in.

2

C™ data I/O.

I

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

Description

2

C mode.

DS39632B-page 18 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2/
UOE

RC1
T1OSI

(2)

CCP2
UOE

RC2/CCP1/P1A

RC2
CCP1
P1A

RC4/D-/VM

RC4
D­VM

RC5/D+/VP

RC5
D+
VP

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT/SDO

RC7
RX
DT
SDO

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

15 34 32

16 35 35

17 36 36

23 42 42

24 43 43

25 44 44

26 1 1

Pin

Type

I/O

O

I

I/O

I

I/O

O

I/O
I/O

O

I

I/O

I

I

I/O

I

I/O

O

I/O

I/O

I

I/O

O

Buffer

Type

PORTC is a bidirectional I/O port.

ST

—

ST

ST

CMOS

ST

—

ST
ST

TTL

TTL

—

TTL

TTL

—

TTL

ST

—

ST

ST
ST
ST

—

configuration bit is cleared.

Digital I/O.
Timer1 oscillat or outpu t.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillat or inpu t.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 PWM output, channel A.

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

Digital I/O.
EUSART asynchronous tran smit.
EUSART synchronous clock (see RX/DT).

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI™ data out.

Description

output.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 19

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/SPP0

RD0
SPP0

RD1/SPP1

RD1
SPP1

RD2/SPP2

RD2
SPP2

RD3/SPP3

RD3
SPP3

RD4/SPP4

RD4
SPP4

RD5/SPP5/P1B

RD5
SPP5
P1B

RD6/SPP6/P1C

RD6
SPP6
P1C

RD7/SPP7/P1D

RD7
SPP7
P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

19 38 38

20 39 39

21 40 40

22 41 41

27 2 2

28 3 3

29 4 4

30 5 5

Pin

Buffer

Type

Type

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/OSTTTL

I/O
I/O

O

I/O
I/O

O

I/O
I/O

O

Description

PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

Digital I/O.
Streaming Parallel Port data.

ST

TTL

—

ST

TTL

—

ST

TTL

—

configuration bit is cleared.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.

DS39632B-page 20 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/AN5/CK1SPP

RE0
AN5
CK1SPP

RE1/AN6/CK2SPP

RE1
AN6
CK2SPP

RE2/AN7/OESPP

RE2
AN7

OESPP
RE3 — — — — — See MCLR
VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins.

V

DD 11, 32 7, 8,

USB 18 37 37 O — Internal USB 3.3V voltage regulator output.

V
NC/ICCK/ICPGC

ICCK

ICPGC
NC/ICDT/ICPGD

ICDT

ICPGD
NC/ICRST

NC/ICPORTS

NC — 13 — — — No Connect.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.

/ICVPP
ICRST
ICVPP

ICPORTS

ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power

2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG

Pin Number

PDIP QFN TQFP

82525

92626

10 27 27

7, 28 P — Positive supply for logic and I/O pins.

28, 29

——12

——13

——33

— — 34 P — No Connect or 28-pin device emulation.

Pin

Buffer

Type

I/O

I

Analog

O

I/O

I

Analog

O

I/O

I

Analog

O

I/O
I/OSTST

I/O
I/OSTST

I

P

Type

PORTE is a bidirectional I/O port.

ST

—

ST

—

ST

—

—
—

configuration bit is cleared.

Digital I/O.
Analog input 5.
SPP clock 1 output.

Digital I/O.
Analog input 6.
SPP clock 2 output.

Digital I/O.
Analog input 7.
SPP output enable output.

/VPP/RE3 pin.

No Connect or dedicated ICD/ICSP™ port clock.

In-Circuit Debugger clock.
ICSP programming clock.

No Connect or dedicated ICD/ICSP port clock.

In-Circuit Debugger data.
ICSP programming data.

No Connect or dedicated ICD/ICSP port Reset.

Master Clear (Reset) input.
Programming voltage input.

Enable 28-pin device emulation when connected

SS.

to V

Description

(3)

(3)

(3)

(3)

 2004 Microchip Technology Inc. Preliminary DS39632B-page 21

PIC18F2455/2550/4455/4550

NOTES:

DS39632B-page 22 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.0 OSCILLATOR CONFIGURATIONS

2.1 Overview

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock system than previous PIC18F devices. The add i­tion of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full speed specifications.

To accommodate these requirements, PIC18F245 5/
2550/4455/4550 de vices in clude a new c lock bran ch to
provide a 48 MHz clock for full speed USB oper ation.
Since it is driven from the primary clock source, an
additional system of prescalers and postscalers has
been added to accomm odate a wide r ange of oscilla tor
frequencies. An overview of the oscillator structure is
shown in Figure 2-1.

Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.

2.1.1 OSCILLATOR CONTROL

The operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two c onfigura­tion registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.

The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.

The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2

“OSCTUNE Register”.

2.2 Oscillator Types

PIC18F2455/2550/445 5/4550 devices can be operated
in twelve distinct oscillator modes. In contrast with pre­vious PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 configuration
bits to select one of these modes:

1. XT Crystal/Resonator

2. XTPLL Crystal/Resonator with PLL enabled

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator
with PLL enabled

5. EC External Clock with F

6. ECIO External Clock with I/O on RA6

7. ECPLL External Clock with PLL enabled
and F

OSC/4 output on RA6

8. ECPIO External Clock with PLL enabled,
I/O on RA6

9. INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source

10. INTXT Internal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source

11. INTIO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digital I/O on RA6

12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,

OSC/4 output on RA6

F

OSC/4 output

2.2.1 OSCILLATOR MODES AND

USB OPERATION

Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PICmicro
clocks were driven by a single oscillator source; the
usual sources were primary, secondary or the internal
oscillator. With PIC18F2455/2550/4455/4550 devices,
the primary oscillator becomes part of the USB module
and cannot be associated to any other clock source.
Thus, the USB module must be cl ocked from the primary
clock source; however, the microcontroller core and
other peripherals can be separately clocked from the
secondary or internal oscillators as before.

Because of the timing requirements imposed by USB,
an internal clock of eit her 6MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock re quirement and sti ll provide fl exibil­ity for cloc king th e rest of the de vice from the pr imary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.

®

devices, all core and peripheral

 2004 Microchip Technology Inc. Preliminary DS39632B-page 23

PIC18F2455/2550/4455/4550

FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F4550

OSC2

OSC1

T1OSO

T1OSI

Primary Oscillator

Sleep

XT, HS, EC, ECIO

Secondary Oscillator

T1OSCEN
Enable
Oscillator

OSCCON<6:4>

Internal

Oscillator

Block

8 MHz

Source
INTRC

Source

31 kHz (INTRC)

8 MHz

(INTOSC)

PLLDIV

÷ 12

111

÷ 10

110

÷ 6

101

100

MUX

011

010

001

000

HSPLL, ECPLL,

8 MHz
4 MHz

2 MHz

1 MHz
500 kHz
250 kHz

125 kHz

1

31 kHz

0

XTPLL, ECPIO

(4 MHz input only)

96 MHz

PLL

CPUDIV

÷ 6

11

÷ 4

10

÷ 3

01

÷ 2

PLL Postscaler

OSCCON<6:4>

111

110

101

100

011

010

001

000

OSCTUNE<7>

00

MUX

÷ 2

FOSC3:FOSC0

Internal Oscillator

÷ 5
÷ 4
÷ 3

PLL Prescaler

÷ 2
÷ 1

CPUDIV

÷ 4

11

÷ 3

10

÷ 2

01

÷ 1

00

Oscillator Postscaler

INTOSC Postscaler

USB Clock Source

USBDIV

0
1

÷ 4

1
0

Primary
Clock

T1OSC

FOSC3:FOSC0

Clock Source Option
for other Modules

WDT, PWRT, FSCM
and Two-Speed Start-up

MUX

Clock

Control

FSEN

1

0

IDLEN

Peripherals

OSCCON<1:0>

USB

Peripheral

CPU

DS39632B-page 24 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.

The oscillator design requires the use of a parallel cut
crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s
specifications.

FIGURE 2-2: CRYSTAL/CERAMIC

RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See T able 2-1 and T able 2-2 for initial values of

2: A series resistor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXXXX

S) may be required for AT

To

Internal
Logic

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pF
HS 8.0 MHz

16.0 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the resonators

listed below for basic start-up and operation. These
values are not optimized.

Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following Table 2-2 for additional

information.

Resonators Used:

16.0 MHz

4.0 MHz

8.0 MHz

27 pF
22 pF

27 pF
22 pF

T ABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc Type

Crystal

Freq

XT 4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacit ors wer e tested with th e crystal s listed

below for basi c st a r t-up a nd ope rati on. These values

are not optimized.

Different cap acitor valu es may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected

DD and temperature range for the application.

V
See the notes following this table for additional

information.

Crystals Used:

Note 1: Higher capac itance inc reases th e stabilit y

of oscillator but also increases the
start-up time.

2: When operating below 3V V

using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.

An external clock may also be used when the micro­controller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).

T ypical Ca pac itor Values

Tested:

C1 C2

4 MHz
8 MHz

20 MHz

DD, or when

 2004 Microchip Technology Inc. Preliminary DS39632B-page 25

PIC18F2455/2550/4455/4550

FIGURE 2-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC
CONFIGURATION)

Clock from
Ext. System

Open

OSC1

OSC2

PIC18FXXXX

(HS Mode)

2.2.3 EXTERNAL CLOCK INPUT

The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external cl ock source to b e connecte d to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.

In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/425 5/4550 dev ices include a Ph ase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.

There is a lso a separ at e pos tscal er opt ion f or deri ving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the pos tscaler fo r XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler div id es the os ci ll ator inp ut by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.

Clock from
Ext. System

OSC/4

F

OSC1/CLKI

PIC18FXXXX

OSC2/CLKO

The ECIO and ECPIO Oscillator modes function like
the EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/
O pin becomes bit 6 of PORTA (RA6). Figure 2-5
shows the pin connections for the ECIO Oscillator
mode.

FIGURE 2-5: EXTERNAL CLOCK

INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)

Clock from
Ext. System

RA6

The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

FIGURE 2-6: PLL BLOCK DIAGRAM

(HS MODE)

HS/EC/ECIO/XT Oscillator Enable

(from CONFIG1H Register)

OSC2

Oscillator

OSC1

and

Prescaler

PLL Enable

Phase

Comparator

IN

F
FOUT

÷24

Loop
Filter

VCO

SYSCLK

MUX

DS39632B-page 26 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.2.5 INTERNAL OSCILLATOR BLOCK

The PIC18F2455/2550/4455/4550 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. If the USB peripheral is not used, the
internal oscillator may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INT OSC postsca ler which can provide a
range of clock frequencies from 31 kHz to 4 MHz. The
INTOSC output is enabled when a clock frequency
from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also ena bled autom atically when an y of the
following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Spe ed Start-up
These features are discussed in greater detail in

Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).

2.2.5.1 Internal Oscillator Modes

When the internal oscillator is used as the micro­controller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
USB clock source is determined by the particular
internal oscillator mode.

There are four distinct modes available:

1. INTHS mode: The USB clock is provided by the
oscillator in HS mode.

2. INTXT mode: The USB clock is provided by the
oscillator in XT mode.

3. INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs F

4. INTIO mode: The U SB clock i s provid ed by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.

OSC/4.

2.2.5.2 OSCTUNE Register

The internal oscillator ’s output has been calibrated at
the factory but can be adjusted in the user’s applica­tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

When the OSCTUNE regis ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately,
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues du ring this shift.
There is no indication that the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator pr ovides the clock sourc e when the 31 kHz
frequency option is se lected . This is c overed in greater
detail in Section 2.4.1 “Oscillator Control Register”.

2.2.5.3 Internal Oscillator Output Frequency
and Drift

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or tempera­ture changes, which can affect the controller operation
in a variety of ways.

The low-frequency IN TRC o sc il lat or o pe rates i nd epen­dently of the INTOSC so urce. Any ch anges in INTO SC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 27

PIC18F2455/2550/4455/4550

REGISTER 2-1: OSCTUNE: OSCILLATOR T UNING REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC

bit 7 bit 0

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

• •

00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111

• •

• •
10000 = Minimum frequency

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— — TUN4 TUN3 TUN2 TUN1 TUN0

2.2.5.4 Compensating for INTOSC Drift

It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be req uired when it beg ins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may sug­gest that the clock speed is too low; to compensate,
increment OSCTUNE to increase t he clo ck freque nc y.

It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.

Finally, a CCP module can use free runnin g Timer1 (or
Timer3), cl oc ked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The ti me of the first ev ent is capt ured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is su btra cte d fro m the time of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.

If the measured time is much greater than the calcu­lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculate d
time, the internal oscillator block is r unning to o slow ; t o
compensate, increment the OSCTUNE register.

DS39632B-page 28 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.3 Oscillator Settings for USB

When the PIC18F4550 is used for USB connectivity, it

 2004 Microchip Technology Inc. Preliminary DS39632B-page 29

PIC18F2455/2550/4455/4550

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)

Input Oscillator

Frequency

20 MHz ÷5 (100) HS, EC, ECIO None (00)20MHz

16 MHz ÷4 (011) HS, EC, ECIO None (00)16MHz

12 MHz ÷3 (010) HS, EC, ECIO None (00)12MHz

8MHz ÷2 (001) HS, EC, ECIO None (00)8MHz

4MHz ÷1 (000) XT, HS, EC, ECIO None (00)4MHz

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full speed USB operation (USB clock of 48 MHz).

Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,

USB clock of 6 MHz).

Note 1: Only valid when the USBDIV configuration bit is cleared.

PLL Division

(PLLDIV2:PLLDIV0)

Clock Mode

(FOSC3:FOSC0)

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

HSPLL, ECPLL, XTPLL,

ECPIO

MCU Clock Division
(CPUDIV1:CPUDIV0)

÷2 (01)10MHz
÷3 (10)6.67MHz
÷4 (11)5MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)8MHz
÷3 (10)5.33MHz
÷4 (11)4MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)6MHz
÷3 (10)4MHz
÷4 (11)3MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)4MHz
÷3 (10)2.67MHz
÷4 (11)2MHz

÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

÷2 (01)2MHz
÷3 (10)1.33MHz
÷4 (11)1MHz
÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10) 24 MHz
÷6 (11)16MHz

Microcontroller

Clock Frequency

DS39632B-page 30 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.4 Clock Sources and Oscillator Switching

Like previous PIC18 enhanced devices, the
PIC18F2455/2550/445 5/4550 f amily inclu des a featu re
that allows the devic e clock so urce to be swit ched fro m
the main oscillator to an alternate low-frequency clock
source. PIC18F2455/2550/4455/4550 devices offer
two alternate clock sources. When an alternate clock
source is enabled, the various power-managed
operating modes are avail abl e.

Essentially, there are three clock sources for these
devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the Ex ternal Crystal
and Resonator modes, the External Clock modes and
the internal oscillator block. The particular mode is
defined by the FOSC3 :FOSC0 c onfigurat ion bits. The
details of these modes are covered earlier in this
chapter.

The s econdary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.

PIC18F2455/2550/445 5/45 50 devices offer the Time r1
oscillator as a seco ndary oscilla tor . This oscil lator , in all
power-managed modes, is often the time base for
functions such as a real-time clock. Most often, a

32.768 kHz watch crystal is connected between the

RC0/T1OSO/T13CKI and RC1/T1OSI/UOE
the XT and HS mode oscillator circuits, loading
capacitors are als o connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.

In addition to being a p rimary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

2.4.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-ma nag ed mo des .

The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 configu­ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.

pins. Like

The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the internal
oscillator block to drive the de vice clock. The choices are
the INTRC source, the INTOSC source (8 MHz) or one
of the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the internal oscillator block is
supplying the device clock, changing the states of these
bits will have an immediate change on the internal oscil­lator’s output. On device Resets, the default output
frequency of the internal oscillator block is set at 1 MHz.

When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which inter­nal oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (O SCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.

This option allo ws users t o select the tunabl e and more
precise INTOSC as a clock source, while maintaining
power savings with a ve ry low clock speed. R egardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The OSTS
bit indicates that the Oscillator Start-up Timer has timed
out and the primary clock is providing the device clock in
primary clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized and is providing
the device clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock mod es. In
power-managed modes, only one of these three bit s w ill
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stab le.

The IDLEN bit dete rmines if th e dev ice go es in to Slee p
mode, or one of the Idle modes, when the SLEEP
instruction is executed.

The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0

“Power-Managed Modes” .

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis­ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable prior to
switching to it as the clock source; other­wise, a very l ong delay may occ ur while
the Timer1 oscillator starts.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 31

PIC18F2455/2550/4455/4550

2.4.2 OSCILLATOR TRANSITIONS

PIC18F2455/2550/4455/4550 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short p ause in the device cl ock occurs
during the clock switch. The length of this pause is the

sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block
01 = Timer1 oscillator
00 = Primary oscillator

Note 1: Depends on the state of the IESO configuration bit.

(3)

(1)

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.

(1)

(2)

R-0 R/W-0 R/W-0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39632B-page 32 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.5 Effects of Power-Managed Modes on the Various Clock Sources

When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31kHz INTRC output can be used direc tly
to provide the clock and may be enabled to support
various special features regardless of the
power-managed mode (see Sect io n 2 5. 2 “Watchdo g
Timer (WDT)”, Section 25.3 “Two-Speed Start-up”
and Section 25.4 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directly from the INTRC
output.

Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module;
the core and all other modules will switch to the new
clock source.

If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).

Sleep mode should never be invoked while the USB
module is operating and co nnected. The only exceptio n
is when the device has been issued a “Suspend” com-

mand over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.

Enabling any on-chip feature that will operate during
Sleep will increase the current co nsumed duri ng Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in

Section 28.2 “DC Characteristic s: Power-Down and
Supply Current”.

2.6 Power-up Delays

Power-up delays are controlled by two timers, s o that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum­stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-12). It is enabled by clearing (= 0) the
PWRTEN

The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the
device is kept in Res et for an add iti onal 2ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequ enc y.

There is a delay of interval, T
Table 28-12), following POR, while the controller
becomes ready to execute instruc tions. This delay runs
concurrently with any other delays. This may be the
only delay th at occurs wh en any of the E C or internal
oscillator modes are us ed a s th e pri ma ry c lo ck so urc e.

configuration bit.

CSD (parameter 38,

TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

INTCKO Floating, pulled by external clock At logic low (clock/4 output)
INTIO Floating, pulled by external clock Configured as PORTA, bit 6
ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
XT and HS Feedback inverter disabled at quiescent

voltage level

Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR

 2004 Microchip Technology Inc. Preliminary DS39632B-page 33

Feedback inverter disabled at quiescent
voltage level

Reset.

PIC18F2455/2550/4455/4550

NOTES:

DS39632B-page 34 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

3.0 POWER-MANAGED MODES

PIC18F2455/2550/4455/4550 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective p ower conservation i n applications
where resources may be limited (i.e., battery-powered
devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device
are clocked and some times , what sp eed. The R un and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.

The power-managed modes include several
power-saving features offered on previous PICmicro
devices. On e is th e clock switchin g featu re, offer ed in
other PIC18 devices, allowing the controller to use the
Timer1 os cil la tor in pl ac e of the prim ary osc il lato r. Also
included is the Sleep mode, offered by all PICmicro
devices, where all device clocks are stopped.

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summariz ed in Table 3-1.

3.1.1 CLOCK SOURCES

The SCS1:SCS0 bits allow the sele ction of one o f three
clock sources for power-managed modes. They are:

• the primary clock, as defined by the
FOSC3:FOSC0 configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits selec t the clock sourc e and determin e
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be sub ject to clock tr ansition delays. These are

®

discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.

Entry to the Power-Managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.

Depending on the current mode and the mode being
switched to, a chan ge to a powe r-manag ed mode doe s
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or ch angin g the IDLEN b it, pri or to i ssuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.

TABLE 3-1: POWER-MANAGED MODES

Mode

Sleep 0 N/A Off Off None – all clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes.

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 oscillator
RC_RUN N/A 1x Clocked Clocked Internal oscillator block
PRI_IDLE 100Off Clocked Primary – all oscillator modes
SEC_IDLE 101Off Clocked Secondary – Timer1 oscillator
RC_IDLE 11xOff Clocked Internal oscillator block

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 35

OSCCON Bits Module Clocking

(1)

IDLEN

SCS1:SCS0 CPU Peripherals

Available Clock and Oscillator Source

This is the normal full power execution mode.

(2)

(2)

PIC18F2455/2550/4455/4550

3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS

The length of the transition between clock sources is
the sum of two cycles o f the old clo ck so urce an d three
to four cycl es of the new clock so urce. This formula
assumes that the new clock source is stable.

Three bits indicate the current clock source and its
status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is s et, the I NTOSC output is provid­ing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is cloc ki ng t he dev ic e, o r th e INTOSC source is
not yet stable.

If the internal oscillator block is configured as the
primary clock source by the FOSC3:FOSC0 con­figuration bits, then both the OSTS and IOFS bits may
be set when in PRI_RUN or PRI_IDLE modes. This
indicates that the primary clock (INTOSC output) is
generating a sta ble 8 MHz output. Entering a nother RC
power-managed mode at the same frequency would
clear the OSTS bit.

Note 1: Caution should be used when m odifying a

single IRCF bit. I f V
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.

DD is less than 3V, it is

3.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-ma nag ed mo de s pe ci fie d by ID L EN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.

3.2 Run Modes

In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset un less Two-Speed St art-u p
is enabled (see Section 25.3 “Two-Speed Start-up”
for details). In this m ode, the OSTS bi t is set. Th e IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.4.1 “Oscillator
Control Register”).

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the T imer1 os cillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.

SEC_RUN mode is en tered by sett ing th e SCS1:SCS 0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RU N mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, devic e cloc ks will be de layed u ntil
the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.

On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clo ck bec omes r eady, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.

DS39632B-page 36 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q4Q3Q2

Q1

Q1

Q4Q3Q2 Q1 Q3Q2

T1OSI

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

Note 1: Clock transition typically occurs within 2-4 T

123

Clock Transition

OSC.

n-1

n

(1)

PC + 2PC

PC + 4

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

T1OSI

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

(1)

TOST

PC

Q3 Q4 Q1

Q2 Q2 Q3

(1)

TPLL

12 n-1n

(2)

Clock

Transition

PC + 2

Q1

Q2

PC + 4

SCS1:SCS0 bits Changed

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 T

OSTS bit Set

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC sourc e, this mo de provides the
best power cons ervation of all the R un modes w hile stil l
executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.

If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin­guishable differences between PRI_RUN and
RC_RUN modes during execution. Howeve r, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.

OSC.

This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.

Note: Caution should be used whe n m odi fy ing a

single IRCF bit. If V

DD is less than 3V, it is

possible to select a higher clock speed
than is supported by the low V

DD.

Improper device operation may result if
the VDD/FOSC specifications are violated.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 37

PIC18F2455/2550/4455/4550

If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.

If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of

IOBST.

T

On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer whil e the prim ary clock is st arted. W hen the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not af fe cte d by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.

If the IRCF b its w ere pr e vi o us ly at a no n - zer o v al u e o r
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bi t will
remain set.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

Q4Q3Q2

Q1

123 n-1n

Clock Transition

(1)

PC + 2PC

INTRC

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

Q1

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock trans ition typi ca lly occurs withi n 2-4 T

OSC.

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q2

Q3 Q4

Q1

INTOSC

Multiplexer

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

SCS1:SCS0 bits Changed

Note 1 : TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock trans iti on typica ll y occurs withi n 2-4 T

TOST

Q2

(1)

PC

Q3

(1)

TPLL

OSTS bit Set

OSC.

12 n-1n

(2)

Clock

Transition

PC + 2

Q1

Q4

Q1

PC + 4

Q2

Q3

DS39632B-page 38 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

3.3 Sleep Mode

The Power-Managed Sleep mode in the
PIC18F2455/2550/4455/4550 devices is identical to
the legacy Sleep mode offered in all other PICmicro
devices. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator ( Figure 3-5) . All clock source sta tus bits are
cleared.

Entering the Sleep m ode from any other mo de does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.

When a wake ev ent occurs i n Sleep mo de (by int errupt,
Reset or WDT time-out), the device wil l not be clocke d
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator block if either the
Two-Speed Start-up or the Fail-Safe Clock Monitor are
enabled (s ee Section 25.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The
IDLEN and SCS bits are not affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.

If the IDLEN bit i s set to a ‘1’ when a SLEEP inst ruction is
executed, the periph erals will be cl ocked fro m the cloc k
source selected us ing the SCS1:SCS 0 bits; howev er , the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction pr ovides a quick method of switchi ng from a
given Run mo de to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue
to operate. If the T imer1 oscill ator is enable d, it will also
continue to run.

Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wak e even t occur s, CPU
execution is delayed by an interval of T
(parameter 38, Table 28-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT
time-out will resul t i n a WD T wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.

CSD

FIGURE 3-5: TRANSITION TI MING FOR ENTRY TO SLEEP MODE

Q4Q3Q2

Q1Q1

OSC1

CPU

Clock

Peripheral

Clock
Sleep

Program

Counter

PC + 2PC

FIGURE 3-6: TRANSITION TI MING FOR WAKE FROM SLEEP (HSPLL)

OSC1

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

Note 1: T

Q1 Q2 Q3 Q4 Q1 Q2

(1)

TOST

Wake Event

OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

(1)

TPLL

PC

OSTS bit Set

Q3 Q4 Q1 Q2

PC + 2

Q3 Q4

PC + 4

Q1 Q2 Q3 Q4

PC + 6

 2004 Microchip Technology Inc. Preliminary DS39632B-page 39

PIC18F2455/2550/4455/4550

3.4.1 PRI_IDLE MODE

This mode is unique among the three Low-Power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accura te primary clock sour ce, since the clock
source does not have to “warm up” or transition from
another oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc­tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disab led, th e peri pherals c ontinu e
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 config uration bit s. The OSTS bit
remains set (see Figure3-7).

When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allo w the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).

CSD is

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set­ting the IDLEN bit and executi ng a SLEEP instruction. If
the device is in anoth er Run mode, se t IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.

When a wake event occ urs, the pe ripherals continue to
be clocked from the Timer1 oscillator. After an interval

CSD following the wake event, the CPU begi ns ex e-

of T
cuting code being cloc ked by the T im er1 oscil lator . Th e
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mod e.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q1

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1

Q4

Q2

Q3

PC PC + 2

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

Q1 Q3 Q4

TCSD

PC

Q2

Wake Event

DS39632B-page 40 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

3.4.3 RC_IDLE MODE

In RC_IDLE mode, t he C PU is d isabled but the periph­erals continue to b e c loc ke d fro m t he internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power cons ervation during Idl e periods .

From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in a nother Run mode, first s et IDLEN, th en set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is reco mmended that SCS0 also be cle ared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before exec uti ng th e SLEEP instruction. When the
clock source is switched to the IN TOSC mult iplexer , the
primary oscillator is shut down and the OSTS bit is
cleared.

If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of T
(parameter 39, Table 28-12). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOF S bit will remain c lear and t here will b e
no indication of the current clock source.

When a wake event occ urs, the pe ripherals co ntinue to
be clocked from the INTOSC multiplexer. After a delay

CSD following the wake event, the CPU begins

of T
executing code being clocked by the INTOSC multi­plexer . The IDLEN and SCS bit s are not affect ed by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.

IOBST

3.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is
triggered b y an interrupt , a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the
device to exit from an Id le mod e, or the Sleep mo de , to
a Run mode. To enable this functionality, an interrupt
source must be enab led by s etti ng i t s en able bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the c orresponding interrupt flag bit is set.

On all exits from Idl e or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).

A fixed delay of interval T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instructio n execution r esumes on th e first clock c ycle
following this delay.

CSD following th e wak e ev en t

3.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.

If the device i s not exec uti ng code (al l Idle mode s and
Sleep mode), the time-out will res ul t in a n ex it fro m the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).

The WDT timer and postscaler are cleared by execut­ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.

3.5.3 EXIT BY RESET

Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator bloc k i s
the new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.

Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 25.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 25.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source ha s cle are d. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 41

PIC18F2455/2550/4455/4550

3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY

Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:

• PRI_IDLE mode where the primary clock source

is not stopped; and

• the primary clock source is not any of the XT or

HS modes.

In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator s tart-up d elay (EC and any internal
oscillator modes). However, a fixed delay of interval

CSD following the wake event is still required when

T

DS39632B-page 42 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

4.0 RESET

The PIC18F2455/2550/4455/4550 devices differentiate
between various kinds of Reset:

a) Power-on Reset (POR)
b) MCLR
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during

e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset

This section discusses Resets generated by MCLR
POR and BOR and covers the ope rati on o f the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are co v ere d i n Section 25.2 “Watchdog
Timer (WDT)”.

Reset during normal operation

execution)

,

A simplified block di agram of the On-Chip Reset Circu it
is shown in Figure 4-1.

4.1 RCON Register

Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis­ter indicate that a specif ic Reset eve nt has occu rred. In
most cases, thes e bits c an only be cl eared by the e vent
and must be set by the app lication after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Sect ion 4.6 “R eset State
of Registers”.

The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in

Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

 2004 Microchip Technology Inc. Preliminary DS39632B-page 43

PIC18F2455/2550/4455/4550

REGISTER 4-1: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1

IPEN SBOREN

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit

If BOREN1:BOREN0 = 01:

1 = BOR is enabled
0 = BOR is disabled

If BOREN1:BOREN0 =

Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after

a Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD

bit 1 POR

bit 0 BOR

: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction

0 = Set by execution of the SLEEP instruction

: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

00, 10 or 11:

U-0 R/W-1 R-1 R-1 R/W-0

—RITO PD POR BOR

(1)

(2)

(2)

R/W-0

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR

notes following this table and Section 4.6 “Reset State of Registers” for
additional information.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been

detected so that subsequent Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming

that POR

DS39632B-page 44 Preliminary  2004 Microchip Technology Inc.

was set to ‘1’ by software immediately after POR).

is determined by the t ype of device Reset. See the

PIC18F2455/2550/4455/4550

4.2 Master Clear Reset (MCLR)

The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices h ave a nois e filter in
the MCLR

Reset path which detects and ignores small

pulses.
The MCLR

pin is not drive n low by any inter nal Reset s,

including the WDT.
In PIC18F2455/2550/4455/4550 devices, the MCLR

input can be disabl ed with the MCL RE configuratio n bit.
When MCLR

is disabled, the pin becomes a digital

input. See Section 10.5 “PORTE, TRISE and LATE

Registers” for more information.

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
VDD is adequate for operation.

T o t ake advantage o f the POR circuitry , tie the MCLR
through a resistor (1 kΩ to 10 kΩ) to V
eliminate external RC components usually needed to
create a Power-on Reset delay . A minimu m rise rate for

DD is specified (parameter D004, Section 28.1 “DC

V
Characteristics”). For a slow rise time, see Figure 4-2.

When the device st arts normal operation (i.e., exits the
Reset condition), device operating parameters (volt­age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.

POR events are captured by the POR
The state of the bit is set to ‘0’ whe never a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.

DD rises above a certain threshold. This

pin

DD. This will

bit (RCON<1>).

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR
SLOW V

DD

V

VDD

D

R

C

Note 1: External Power-on Reset circuit is required

only if the V
The diode D helps discharge the capacitor
quickly when V

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate
the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR
of MCLR
static Discharge (ESD) or Electrical
Overstress (EOS).

DD power-up slope is too slow.

from external capacitor C, in the event

/VPP pin breakdown, due to Electro-

DD POWER-UP)

R1

MCLR

PIC18FXXXX

DD powers down.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 45

PIC18F2455/2550/4455/4550

4.4 Brown-out Reset (BOR)

PIC18F2455/2550/4455/4550 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR
is controlled by the BORV1:BORV0 and
BOREN1:BOREN0 configura tion b its . There are a tota l
of four BOR configurations which are summarized in
Table 4-1.

The BOR threshold is set by t he BOR V1:BOR V0 bit s. If
BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of V
D005, Section 28.1 “DC Characteristics”) for
greater than TBOR (parameter 35, Table 28-12) will
reset the device. A Reset may or may not occur if V
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset u ntil V

If the Power-up T imer is enabl ed, it will be inv oked after

DD rises above VBOR; it then will keep the chip in

V
Reset for an additional time delay, T
(parameter 33, Table 28-12). If VDD drops below VBOR
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises above VBOR, the
Power-up Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise, it is r ead as ‘0’.

DD below VBOR (parameter

DD

DD rises above VBOR.

PWRT

Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment withou t ha vi ng to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi­nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.

Note: Even when BOR is under s oftware contro l,

the BOR Reset voltage level is still set by
the BORV1:BORV0 configuration bits. It
cannot be changed in software.

4.4.2 DETECTING BOR

When BOR is enab led, the BO R bit always resets to ‘0’
on any BOR or P OR event. This makes it diff icult to
determine if a BOR event has occurre d jus t by rea ding
the state of BOR
simultaneously check the state of both POR
This assumes th at the POR
immediately after any POR event. IF BOR
POR

is ‘1’, it can be reliably assum ed that a BOR event

has occurred.

alone. A more reliable method is to

and BOR.

bit is reset to ‘1’ in softwa re

is ‘0’ while

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however , the BOR is au tom ati ca lly dis abl ed . When the
device returns to any other operating mode, BOR is
automatically re-enabled.

This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it save s additional po wer in Sleep mod e
by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Status of

BOREN1 BOREN0

00Unavailable BOR disabled; must be enabled by reprogramming the configuration bits.
01Available BOR enabled in software; operation controlled by SBOREN.
10Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep

11Unavailable BOR enabled in hardware; must be disabled by reprogramming the

DS39632B-page 46 Preliminary  2004 Microchip Technology Inc.

SBOREN

(RCON<6>)

mode.

configuration bits.

BOR Operation

PIC18F2455/2550/4455/4550

4.5 Device Reset Timers

PIC18F2455/2550/4455/4550 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time -out

4.5.1 POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18F2455/2550/
4455/4550 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 µs=65.6ms.
While the PWRT is counting, the device is held in
Reset.

The power-up time delay depe nd s on the INTRC cl oc k
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 28-12)
for details.

The PWRT is enabled by clearing the PWRTEN
configuration bit.

4.5.2 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 28-12). This
ensures that the crystal oscillator or resonator has
started and stabilized.

The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-manag ed mod e s.

4.5.3 PLL LOCK TIME-OUT

With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ­ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is suf fi ci ent fo r th e
PLL to lock to the main oscillator frequency. This PLL
lock time-o ut (T

PLL) is typically 2 ms and follows the

oscillator start-up time-out.

4.5.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. After the POR condition has cleared, PWRT
time-out is invoked (if enabled).

2. Then, the OST is activated.

The total time-out will vary based on oscillator configu­ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figure s 4-3 through 4-6 also apply
to devices operating in XT mode. For devices in RC
mode and with the PWRT disabled, on the other hand,
there will be no time-out at all.

Since the time-outs occur from the POR pulse, if MC LR
is kept low long e nough, all ti me -out s will e xpire. Brin g­ing MCLR
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.

high will begin execution immediately

TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS

(2)

(2)

and Brown-out

(2)

1024 TOSC + 2 ms

Exit from

Power-Managed Mode

(2)

1024 TOSC + 2 ms

(2)

——

2 ms

(2)

2 ms

(2)

——

Oscillator

Configuration

PWRTEN = 0 PWRTEN = 1

HS, XT 66 ms
HSPLL, XTPLL 66 ms

(1)

+ 1024 TOSC + 2 ms
EC, ECIO 66 ms
ECPLL, ECPIO 66 ms
INTIO, INTCKO 66 ms
INTHS, INTXT 66 ms

Power-up

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

(1)

(1)

+ 2 ms

(1)

(1)

+ 1024 TOSC 1024 TOSC 1024 TOSC

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 47

PIC18F2455/2550/4455/4550

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

PWRT TI ME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

NOT TIED TO VDD): CASE 1

TOST

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

DS39632B-page 48 Preliminary  2004 Microchip Technology Inc.

NOT TIED TO VDD): CASE 2

TOST

PIC18F2455/2550/4455/4550

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)

 2004 Microchip Technology Inc. Preliminary DS39632B-page 49

PIC18F2455/2550/4455/4550

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other

Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.

Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper­ation. Status bits from the RCON register, RI
POR

and BOR, are set or cleare d dif ferently i n differe nt

, TO, PD,

Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition

Program

Counter

SBOREN RI

Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u

Brown-out 0000h u

during Power-Managed

MCLR

0000h u

(2)
(2)
(2)

Run modes
MCLR

during Power-Managed

0000h u

(2)

Idle modes and Sleep mode
WDT Time-ou t during Full Power

0000h u

(2)

or Power-Managed Run modes
MCLR

during Full Power

0000h u

(2)

Execution
Stack Full Reset (STVREN = 1) 0000h u
Stack Underflow Reset

0000h u

(2)
(2)

(STVREN = 1)
Stack Underflow Error (not an

0000h u

(2)

actual Reset, STVREN = 0)
WDT Time-out during

PC + 2 u

(2)

Power-Managed Idle or Sleep
modes

Interrupt Exit from

PC + 2 u

(2)

Power-Managed modes

Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

RCON Register STKPTR Register

TO PD POR BOR STKFUL STKUNF

0uuuu u u

111u0 u u

u1uuu u u

u10uu u u

u0uuu u u

uuuuu u u

uuuuu 1 u

uuuuu u 1

uuuuu u 1

u00uu u u

uu0uu u u

DS39632B-page 50 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR

Resets,

Register Applicable Devices

Power-on Reset,
Brown-o ut Reset

TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu
TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu
PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2
TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu
INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u
INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu
INDF0 2455 2550 4455 4550 N/A N/A N/A
POSTINC0 2455 2550 4455 4550 N/A N/A N/A
POSTDEC0 2455 2550 4455 4550 N/A N/A N/A
PREINC0 2455 2550 4455 4550 N/A N/A N/A
PLUSW0 2455 2550 4455 4550 N/A N/A N/A
FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2455 2550 4455 4550 N/A N/A N/A
POSTINC1 2455 2550 4455 4550 N/A N/A N/A
POSTDEC1 2455 2550 4455 4550 N/A N/A N/A
PREINC1 2455 2550 4455 4550 N/A N/A N/A
PLUSW1 2455 2550 4455 4550 N/A N/A N/A
FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: When the wake-up is due to an int errup t and the G IEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake -up is due to an interru pt and the GIEL or GIEH bit is set, the PC is loaded w ith the interru pt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

(1)
(1)
(1)
(1)

(2)

(3)
(3)
(3)

 2004 Microchip Technology Inc. Preliminary DS39632B-page 51

PIC18F2455/2550/4455/4550

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register Applicable Devices

INDF2 2455 2550 4455 4550 N/A N/A N/A
POSTINC2 2455 2550 4455 4550 N/A N/A N/A
POSTDEC2 2455 2550 4455 4550 N/A N/A N/A
PREINC2 2455 2550 4455 4550 N/A N/A N/A
PLUSW2 2455 2550 4455 4550 N/A N/A N/A
FSR2H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2455 2550 4455 4550 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TMR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
OSCCON 2455 2550 4455 4550 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 2455 2550 4455 4550 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 2455 2550 4455 4550 ---- ---0 ---- ---0 ---- ---u

(4)

RCON
TMR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2455 2550 4455 4550 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PR2 2455 2550 4455 4550 1111 1111 1111 1111 1111 1111
T2CON 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ADRESH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
ADCON1 2455 2550 4455 4550 --00 0qqq --00 0qqq --uu uuuu
ADCON2 2455 2550 4455 4550 0-00 0000 0-00 0000 u-uu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: When the wake-up is due to an int errup t and the G IEL or GIEH bit is set, th e TOSU, TOSH and TOSL are

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake -up is due to an interru pt and the GIEL or GIEH bit is set, the PC is loaded w ith the interru pt

4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

2455 2550 4455 4550 0q-1 11q0 0q-q qquu uq-u qquu

Shaded cells indicate condi tions do not apply for the designated device.

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

vector (0008h or 0018h).

enabled as PORTA pins, they are disabled and read ‘0’.

Power-on Reset,

Brown-o ut Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

DS39632B-page 52 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register Applicable Devices

CCPR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2455 2550

2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CCPR2H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
BAUDCON 2455 2550 4455 4550 01-0 0-00 01-0 0-00 uu-u u-uu
ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu
TMR3H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu
RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu
EEADR 2455 2 550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000
EECON1 2455 2550 4455 4550 xx-0 x000 uu-0 u000 uu-0 u000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: When the wake-up is due to an int errup t and the G IEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake -up is due to an interru pt and the GIEL or GIEH bit is set, the PC is loaded w ith the interru pt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

4455 4550 --00 0000 --00 0000 --uu uuuu

Power-on Reset,
Brown-o ut Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

 2004 Microchip Technology Inc. Preliminary DS39632B-page 53

PIC18F2455/2550/4455/4550

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Resets,

MCLR

Register Applicable Devices

Power-on Reset,

Brown-o ut Reset

IPR2 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
IPR1 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

2455 2550 4455 4550 -111 1111 -111 1111 -uuu uuuu

PIR1

2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

2455 2550

4455 4550 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
TRISE 2455 2550 4455 4550 ---- -111 ---- -111 uuuu -uuu
TRISD

2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISC 2455 2550 4455 4550 11-- -111 11-- -111 uu-- -uuu
TRISB 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISA

(5)

2455 2550 4455 4550 -111 1111

(5)

LATE 2455 2550 4455 4550 ---- -xxx ---- -uuu ---- -uuu
LATD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2455 2550 4455 4550 xx-- -xxx uu-- -uuu uu-- -uuu
LATB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATA

(5)

2455 2550 4455 4550 -xxx xxxx

(5)

PORTE 2455 2550 4455 4550 0--- x000 0--- x000 u--- uuuu
PORTD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2455 2550 4455 4550 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA

(5)

2455 2550 4455 4550 -x0x 0000

(5)

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate condi tions do not apply for the designated device.

Note 1: When the wake-up is due to an int errup t and the G IEL or GIEH bit is set, th e TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake -up is due to an interru pt and the GIEL or GIEH bit is set, the PC is loaded w ith the interru pt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

WDT Reset,

RESET Instruction,

Stack Resets

-111 1111

-uuu uuuu

-u0u 0000

(5)

(5)

(5)

Wake-up via WDT

or Interrupt

(3)

(3)

-uuu uuuu

-uuu uuuu

-uuu uuuu

(5)

(5)

(5)

DS39632B-page 54 Preliminary  2004 Microchip Technology Inc.



PIC18F2455/2550/4455/4550

NOTES:

DS39632B-page 56 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 enhanced
microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM
As Harvard architecture dev ices, the dat a and progra m

memories use separate busses; this allows for con­current access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addresse d and accessed
through a set of control registers.

Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed s eparately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory sp ace. Accessi ng a loca tion betwee n
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).

The PIC18F2455 and PIC18F4455 each have
24 Kbytes of Flash memory an d can store up to 12,288
single-word instructions. The PIC18F2550 and
PIC18F4550 each have 32 Kbytes of Flash memory
and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.

The program memory maps for PIC18FX455 and
PIC18FX550 devices are shown in Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2455/2550/4455/ 4550 DEVICES

PIC18FX455

CALL,RCALL,RETURN,
RETFIE,RETLW,
CALLW,
ADDULNK,
SUBULNK

High Priority Interrupt Vector

Low Priori ty In t e r r u pt Vector

PC<20:0>

Stack Level 1

Stack Level 31

Reset Vector

21

•

•

•

0000h
0008h

0018h

CALL,RCALL,RETURN,
RETFIE,RETLW,
CALLW,
ADDULNK,
SUBULNK

PIC18FX550

PC<20:0>

Stack Level 1

Stack Level 31

Reset Vector

High Priority Interrupt Vector 0008h

Low Priori ty In t e r r u pt Vector

21

•

•

•

0000h

0018h

On-Chip

Program Memory

5FFFh
6000h

Read ‘0’

1FFFFFh
200000h

 2004 Microchip Technology Inc. Preliminary DS39632B-page 57

User Memory Space

On-Chip

Program Memory

Read ‘0’

7FFFh
8000h

User Memory S pace

1FFFFFh
200000h

PIC18F2455/2550/4455/4550

5.1.1 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the
instruction to fetch for execu tion. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byt e, or PCH re gister, contains
the PC<15:8> bits; i t is not directly re adable or writ able.
Updates to the PCH register are perfo rmed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.

The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to P CLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).

The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.

The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The return address s tack allows any combinatio n of up
to 31 program calls and interrupts to occur. The PC is
pushed onto th e stac k when a CALL or RCALL instruc­tion is executed or an interrupt is Acknowledged. The
PC value is pulled of f the stack o n a RETURN, RETLW or
a RETFIE ins truction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or da ta sp ace. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
top-of-stack Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.

A CALL type instru ctio n caus es a pus h ont o the stac k.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN ty pe ins truc ti on c au se s
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits in dic ate if th e s t ac k i s
full, has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is

readable and writable. A set of three registers,

TOSU:TOSH:TOSL, hold th e contents of the stack loca­tion pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a use r defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>

11111

T op -of-Stack Registers Stack Pointer

TOSLTOSHTOSU

34h1Ah00h

Top-of-Stack

DS39632B-page 58 Preliminary  2004 Microchip Technology Inc.

001A34h
000D58h

11110
11101

STKPTR<4:0>

00010

00011
00010
00001
00000

PIC18F2455/2550/4455/4550

5.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Reg ister 5-1) contains the S t ack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.

After the PC is pus hed o nto the st ack 31 times (wi thout
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.

The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack
Overflow Reset Enable) configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a de scription of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.

If STVREN is cleared, the STKFUL bi t will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.

When the stack has been popped enough times to
unload the stac k, the next pop will ret urn a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the
ability to push value s on to the st ac k an d pul l va lues off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and T OS L can be m odifie d to plac e dat a
or a return address on the stack.

The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.

The POP instruction discards the current TOS by decre­menting the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.

REGISTER 5-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL
bit 7 bit 0

bit 7 STKFUL: Stack Full Flag bit

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred
0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

STKUNF

Note 1: Bit 7 and bi t 6 are clea red by user software or by a POR.

(1)

— SP4 SP3 SP2 SP1 SP0

(1)

(1)

 2004 Microchip Technology Inc. Preliminary DS39632B-page 59

PIC18F2455/2550/4455/4550

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Regist er 4L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and th en cause a devic e Reset . When
STVREN is cleared, a full or underflow condi tion will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A fast register stack is provided for the Status, WREG
and BSR registers to provide a “fast return” option for
interrupts. Each stack is only one level deep and is
neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push val ues into t he s tack re gist ers. The v alue s in
the registers ar e then load ed ba ck i nto th eir a ssoc iated
registers if the RETFIE, FAST instruction is used to
return from the interrupt.

If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priori ty interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.

If interrupt priority is not used, all interrupts ma y use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label, FAST instruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.

Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER
;STACK

•

•

SUB1 •

•
RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY

There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.

A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an of fs et into the table before
executing a call to tha t t a ble . The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions, that returns the value ‘nn’ to the calling
function.

The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

MOVF OFFSET, W

CALL TABLE
ORG nn00h
TABLE ADDWF PCL

RETLW nnh

RETLW nnh

RETLW nnh

.

.

.

5.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory
allows two bytes of dat a to be stored in each instruction
location.

Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the da ta that is read from o r written to program
memory. Data is transferred to or from program
memory one byte at a time.

Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.

DS39632B-page 60 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q 4). Internall y, the program counter i s
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruc­tion register during Q4. The ins truc tion is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.

FIGURE 5-3: CLOCK/ INSTRUCTION CYCLE

OSC1

Q1
Q2
Q3
Q4

PC

OSC2/CLKO

(RC mode)

Q2 Q3 Q4

Q1

PC PC + 2 PC + 4

Execute INST (PC – 2)

Fetch INST (PC)

Q2 Q3 Q4

Q1

Execute INST (PC)

Fetch INST (PC + 2)

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instructio n fetch and execute ar e pipe­lined in such a m anner that a fetc h takes one i nstruction
cycle, while the decode and execute takes another
instructio n cy cle. H owe ver, due to the pip elini ng, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to chan ge (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example5-3).

A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.

In the execution cy cle, the fetch ed instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

Q1

Internal
Phase
Clock

Execute INST (PC + 2)

Fetch INST (PC + 4)

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

Note: All instructions are single cycl e, ex ce pt fo r any prog ram bran ch es . Thes e t a ke tw o cy c les si nce the fetc h

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 61

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

PIC18F2455/2550/4455/4550

5.2.3 INSTRUCTIONS IN PROGRAM MEMORY

The program memory is addressed in bytes. Instruc­tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction bo undaries , the PC incr ements in step s
of 2 and the LSb wi ll always read ‘0’ (see Section 5.1.1
“Program Counter”).

Figure 5-4 shows an exam ple of h ow in st ruc tion w ord s
are stored in the program memory.

The CALL and GOTO instructions have the absolute

program memory address embedded into the instruc-

tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same ma nner. The
offset value stored in a br anch instruction represent s the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

LSB = 1 LSB = 0 ↓

F0h 00h 00000Ch

F4h 56h 000010h

Instruction 1:
Instruction 2:

Instruction 3:

Program Memory
Byte Locations

MOVLW 055h 0Fh 55h 000008h
GOTO 0006h EFh 03h 00000Ah

MOVFF 123h, 456h C1h 23h 00000Eh

→

Word Address

000000h
000002h
000004h
000006h

000012h
000014h

5.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the in struc tion s always has
‘1111’ as its four M ost Si gnifican t bit s; the other 12 bit s
are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the dat a in t he se cond word is acc essed and

used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for case s when the two-word ins truction is
preceded by a co nd i ti ona l in st ru ct i on t h at c han ge s t he
PC. Example 5-4 shows how this works.

Note: See Section 5.5 “Program Memory and

the Extended Instruction Set” for

information on two-word instruction in the
extended instruction set.

EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:
Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

DS39632B-page 62 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

5.3 Data Memory Organization

Note: The operation of some aspects of data

memory are changed when the PIC18
extended instruction set is enabled. See

Section 5.6 “Data Memory and the
Extended Instruction Set” for more

information.

The data memory in PIC 18 devices is implem ented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each.
PIC18F2455/255 0/4455/4550 devices impleme nt 8 com­plete banks, for a total of 2048 bytes. Figure5-5 shows
the data memory organization for the devices.

The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functio ns, while GPRs are us ed for data
storage and scratchpad operations in the user’s
application. Any re ad of an unimpl emented location will
read as ‘0’s.

The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.

To ensure that commonly used registers (SFRs and
select GPRs) c an b e ac cess ed i n a si ngle cycle, PI C18
devices impl em ent an Ac ce ss Ba nk . Th is i s a 256-byte
memory space that pr ovid es fa st acces s to SFRs a nd
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.3 “Access Bank” provides a
detailed description of the Access RAM.

5.3.1 USB RAM

Banks 4 through 7 of the data memory are actually
mapped to special dual port RAM. When the USB
module is disabled, the GPRs in these banks are used
like any other GPR in the data memory space.

When the USB module i s enabled, the m emory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.

It is theoretically poss ible to use the ar eas of USB RAM
that are not allocated as USB buffers for normal
scratchpad mem ory or o ther vari able sto rage . In p rac ­tice, the dynamic nature of b uffer allocation makes this
risky at best. Additional ly , Bank 4 is used for USB buf fer
management when the module is enabled and should
not be used for any other purposes during that time.

Additional information on USB RAM and buffer
operation is provided in Section 17.0 “Universal
Serial Bus (USB)”.

5.3.2 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom­plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.

Most instruct ions in th e PIC18 in struct ion set ma ke use
of the bank poin ter, known as the Bank Select Reg ister
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; the y will always read ‘ 0’ and cannot be
written to. The BSR can be l oaded direc tly by using the
MOVLB instruction.

The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an of fs et from th e
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-6.

Since up to 16 regis ters m ay share the s ame l ow-order
address, the user must alway s be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit addre ss of F9 h, while the BSR
is 0Fh, will end up resetting the prog ram counter.

While any bank can be s el ec ted, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the Status register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This i nstruction ig nores the
BSR completely when it ex ecutes. All o ther instruction s
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 63

PIC18F2455/2550/4455/4550

FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2455/2550/4455/4550 DEVICES

BSR<3:0>

= 0000

= 0001

= 0010

= 0011

= 0100

= 0101

= 0110

= 0111

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Data Memory Map

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

Access RAM

GPR

GPR

GPR

GPR

GPR

GPR

GPR

GPR

(1)

(1)

(1)

(1)

000h
05Fh
060h
0FFh
100h

1FFh
200h

2FFh
300h

3FFh
400h

4FFh
500h

5FFh
600h

6FFh
700h

7FFh
800h

When a = 0:

The BSR is ignored and the
Access Bank is used.

The first 96 bytes are
general purpose RAM
(from Bank 0).

The remaining 160 bytes are
Special Function Registers
(from Bank 15).

When a = 1:

The BSR specifies the bank
used by the instruction.

Access Bank

Access RAM Low

Access RAM High

(SFRs)

00h

5Fh

60h

FFh

= 1000

= 1110

= 1111

Note 1: These banks also serve as RAM buf fer for USB operati on. See Section 5.3.1 “USB RAM” for more

information.

DS39632B-page 64 Preliminary  2004 Microchip Technology Inc.

Bank 8

to

Bank 14

Bank 15

FFh

00h

FFh

Unused

Read as 00h

Unused

SFR

EFFh
F00h
F5Fh

F60h
FFFh

PIC18F2455/2550/4455/4550

FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

(1)

7

0000

Bank Select

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

BSR

0

0011

(2)

E00h

F00h

FFFh

the registers of the Access Bank.

000h

100h

200h

300h

Data Memory

Bank 0
Bank 1

Bank 2

Bank 3

through

Bank 13

Bank 14

Bank 15

00h
FFh

00h
FFh

00h
FFh

00h

FFh
00h

FFh
00h

FFh

7

From Opcode

11111111

(2)

0

5.3.3 ACCESS BANK

While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means th at the user must a lways
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.

T o stre amline acces s for the most commonl y used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Block 15 . The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 5-5).

The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, t he in st ru ct ion
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.

Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means th at use rs can ev aluate an d operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for da ta values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.

The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.

5.3.4 GENERAL PURPOSE REGISTER FILE

PIC18 devices may have banked memory in the GPR
area. This is dat a R AM whi ch is ava il able for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 65

PIC18F2455/2550/4455/4550

5.3.5 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and p eripheral modul es for controllin g
the desired operation of the device. These reg isters are
implemented as st atic RAM in th e dat a me mory sp ac e.
SFRs start at th e top of dat a memory an d extend do wn­ward to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.

The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s Status register is described later in this section.
Registers related to the operation of a peripheral
feature are described in the chapter for that perip heral.

The SFRs are typically distributed among the
peripherals whose fun cti ons th ey c ontr ol. U nus ed SFR
locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455/2550/4455/4550 DEVICES

Address Name Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2

FFEh TOSH FDEh POSTINC2
FFDh TOSL FDDh POSTDEC2
FFCh STKPTR FDCh PREINC2
FFBh P CLATU FDBh PLUSW2

FFAh PCLATH FDAh FSR2H FBAh

FF9h PCL FD9h FSR2L FB9h

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE

FF5h TABLAT FD5h T 0CON FB5h CVRCON F95h TRISD

FF4h PRODH FD4h

FF3h PRO DL FD3h OS CCO N FB3h TMR3H F93h TRISB F73h UEP 3

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h UEP2

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h
FEFh INDF0

(1)

FEEh POSTINC0

FEDh POSTDEC0
FECh PREINC0

FEBh PLUSW0

(1)

(1)

FCFh TMR1H FAFh SPBRG F8Fh —

(1)

FCEh TMR1L FAEh RCREG F8Eh —

(1)

FCDh T1CON FADh TXREG F8Dh LATE
FCCh TMR2 FACh TXSTA F8Ch LATD
FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE

FEAh FSR0H FCAh T2CON FAAh

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h UIE

FE8h WREG FC8h SSPADD FA8h EEDATA F88h

FE7h INDF1

FE6h POSTINC1

FE5h POSTDEC1

FE4h PREINC1

FE3h PLUSW1

(1)

(1)

(1)

FC7h SSPSTAT FA7h EECON2

(1)

FC6h SSPCON1 FA6h EECON1 F86h —

(1)

FC5h SSPCON2 FA5h —
FC4h ADRESH FA4h —

FC3h ADRESL FA3h —
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SPPDATA
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —

(1)

(1)

(1)

(2)

—

FBFh CCPR1H F9Fh IPR1 F7Fh U EP15

(1)

FBEh CCPR1L F9Eh PIR1 F7Eh UEP14

(1)

FBDh CCP1CON F9Dh PIE1 F7Dh UEP13
FBCh CCPR2H F9Ch —

(2)

FBBh CCPR2L F9Bh OSCTUNE F7Bh UEP11

CCP2CON

(2)

—

F9Ah —

F99h —

(2)
(2)
(2)

—

(2)

—

(3)
(3)

FB4h CMCON F 94h TRISC F74h UEP4

(2)

—

(2)

—

(2)
(2)

(3)

(3)

(2)

—

(1)

(2)
(2)
(2)

F8Ah LATB F6Ah UEIR

(2)

—

F87h —

F85h —

(2)
(2)
(2)

F84h PORTE F64h SPPEPS
F83h PORTD

(3)

F7Ch UEP12

F7Ah UEP10

F79h UEP9
F78h UEP8
F77h UEP7
F76h UEP6
F75h UEP5

F71h UEP1

F70h UEP0
F6Fh UCFG
F6Eh UADDR
F6Dh UCON
F6Ch USTAT

F68h UIR

F67h UFRMH

F66h UFRML

F65h SPPCON

F63h SPPCFG

(2)
(2)

(3)
(3)
(3)

(3)

Note 1: Not a physical register.

2: Unimplemented registers are read as ‘0’.
3: These registers are implemented only on 40/44-pin devices.

DS39632B-page 66 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TOSU
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 51, 58
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 51, 58
STKPTR STKFUL STKUNF
PCLATU
PCLATH Holding Register for PC<15:8> 0000 0000 51, 58
PCL PC Low Byte (PC<7:0>) 0000 0000 51, 58
TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 51, 82
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 51, 82
TABLAT Program Memory Table Latch 0000 0000 51, 82
PRODH Product Register High Byte xxxx xxxx 51, 95
PRODL Product Register Low Byte xxxx xxxx 51, 95
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 51, 99
INTCON2 RBPU
INTCON3 INT2IP INT1IP
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 51, 73
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 51, 74
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 51, 74
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 51, 74
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

FSR0H
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 51, 73
WREG Working Register xxxx xxxx 51
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 51, 73
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 51, 74
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 51, 74
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 51, 74
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

FSR1H
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 51, 73
BSR
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 52, 73
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 52, 74
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 52, 74
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 52, 74
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

FSR2H
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 52, 73
STATUS
TMR0H Timer0 Register High Byte 0000 0000 52, 127
TMR0L Timer0 Register Low Byte xxxx xxxx 52, 127
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 52, 125

Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: Bit 21 of the TBLPTRU allows access to the device configuration bits.

2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 51, 58

— Return Stack Pointer 00-0 0000 51, 59

— — — Holding Register for PC<20:16> ---0 0000 51, 58

— —bit 21

INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 51, 100

value of FSR0 offset by W

— — — — Indirect Data Memory Address Pointer 0 High ---- 0000 51, 73

value of FSR1 offset by W

— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 51, 73

— — — — Bank Select Register ---- 0000 52, 63

value of FSR2 offset by W

— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 52, 73

— — —NOVZDCC---x xxxx 52, 71

individual unimplemented bits should be interpreted as ‘-’.

(1)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 51, 82

— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 51, 101

Value on

POR, BOR

N/A 51, 74

N/A 51, 74

N/A 52, 74

Details

on page

 2004 Microchip Technology Inc. Preliminary DS39632B-page 67

PIC18F2455/2550/4455/4550

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 52, 32
HLVDCON VDIRMAG
WDTCON
RCON IPEN SBOREN
TMR1H Timer1 Register High Byte xxxx xxxx 52, 133
TMR1L Timer1 Register Low Byte xxxx xxxx 52, 133
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR2 Timer2 Register 0000 0000 52, 136
PR2 Timer2 Period Register 1111 1111 52, 136
T2CON
SSPBUF SSP Receive Buffer/Transm i t Register xxxx xxxx 52, 194,

SSPADD SSP Address Register in I
SSPSTAT SMP CKE D/A

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 195,

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 52, 205
ADRESH A/D Result Register High Byte xxxx xxxx 52, 262
ADRESL A/D Result Register Low Byte xxxx xxxx 52, 262
ADCON0
ADCON1
ADCON2 ADFM
CCPR1H Capture/Compare/PWM Register 1 High Byt e xxxx xxxx 53, 142
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 53, 142
CCP1CON P1M1

CCPR2H Capture/Compare/PWM Register 2 High Byt e xxxx xxxx 53, 142
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 53, 142
CCP2CON
BAUDCON ABDOVF RCIDL
ECCP1DEL PRSEN PDC6
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 269
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 53, 263
TMR3H Timer3 Register High Byte xxxx xxxx 53, 139
TMR3L Timer3 Register Low Byte xxxx xxxx 53, 139
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53, 237
SPBRG EUSART Baud Rate Generator Register Lo w Byte 0000 0000 53, 237
RCREG EUSART Receive Register 0000 0000 53, 244
TXREG EUSART Transmit Register 0000 0000 53, 242
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 234
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 53, 235

Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: Bit 21 of the TBLPTRU allows access to the device configuration bits.

2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

— — — — — — —SWDTEN--- ---0 52, 292

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 135

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 5 2, 253
— — V CFG 1 VCFG 0 P CFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 52, 254

(3)

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 53, 141

individual unimplemented bits should be interpreted as ‘-’.

— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 52, 273

(2)

—RITO PD POR BOR 0q-1 11q0 52, 44

TMR1CS TMR1ON 0000 0000 52, 129

2

C™ Slave Mode. SSP Baud Rate Reload Register in I2C™ Master Mode. 0000 0000 52, 202

PSR/WUA BF 0000 0000 52, 194,

— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 52, 255

(3)

P1M0

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 141,

(3)

— SCKP BRG16 — WUE ABDEN 01-0 0-00 5 3, 236

PDC5

(3)

PDC4

(3)

PDC3

(3)

PDC2

(3)

(3)

PDC1

TMR3CS TMR3ON 0000 0000 53, 137

(3)

PDC0

PSSBD0

Value on

POR, BOR

(3)

0000 0000 53, 158

(3)

0000 0000 53, 159

Details

on page

202

203

204

149

DS39632B-page 68 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

T ABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

EEADR EEPROM Address Register 0000 0000 53, 89
EEDATA EEPROM Data Register 0000 0000 53, 89
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 53, 80
EECON1 EEPGD CFGS

— FREE WRERR WREN WR RD xx-0 x000 53, 81
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 54, 107
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 54, 103
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 54, 105
IPR1 SPPIP
PIR1 SPPIF
PIE1 SPPIE
OSCTUNE INTSRC

(3)

TRISE

(3)

TRISD
TRISC TRISC7 TRISC6

(3)

ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 54, 106

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 54, 102

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54, 104

— — TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 54, 28

— — — — — TRISE2 TRISE1 TRISE0 ---- -111 54, 124

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 54, 122

— — — TRISC2 TRISC1 TRISC0 11-- -111 54, 119
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54, 116
TRISA
LATE
LATD

(3)
(3)

— TRISA6
— — — — — LATE2 LATE1 LATE0 ---- -xxx 54, 124

LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 54, 122

LATC LATC7 LATC6

(4)

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 54, 113

— — — LATC2 LATC1 LATC0 xx-- -xxx 54, 119
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 54, 116
LATA
PORTE RDPU

(3)

PORTD

—LATA6

(3)

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 5 4, 122

PORTC RC7 RC6 RC5

(4)

LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 54, 113

— — —RE3

(6)

RC4

(6)

(5)

— RC2 RC1 RC0 xxxx -xxx 54, 119

RE2

(3)

RE1

(3)

RE0

(3)

0--- x000 54, 123

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 116
PORTA
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0

—RA6
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169

(4)

RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 54, 113

Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: Bit 21 of the TBLPTRU allows access to the device configuration bits.

2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

Details

on page

 2004 Microchip Technology Inc. Preliminary DS39632B-page 69

PIC18F2455/2550/4455/4550

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 55, 166
UADDR
UCON
USTAT
UEIE BTSEE
UEIR BTSEF
UIE
UIR
UFRMH
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 55, 170

(3)

SPPCON

(3)

SPPEPS

(3)

SPPCFG
SPPDATA

Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: Bit 21 of the TBLPTRU allows access to the device configuration bits.

(3)

2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

— ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 55, 170
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 5 5, 164
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 55, 168

— — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 55, 181

— — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 55, 180
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 55, 179
— SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 55, 178
— — — — — FRM10 FRM9 FRM8 ---- -xxx 55, 170

— — — — — — SPPOWN SPPEN ---- --00 55, 187

RDSPP WRSPP — SSPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 55, 191

CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 55, 188

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 55, 192

individual unimplemented bits should be interpreted as ‘-’.

Value on

POR, BOR

Details

on page

DS39632B-page 70 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

5.3.6 STATUS REGISTER

The St atus register , sho wn in Register5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any instruction.

If the St atus regis ter is the dest ination for an instructio n
that affect s the Z, DC, C, OV or N bit s, the re sults of the
instruction are not written; instead, the status is
updated according to t he i nstruc tion pe rformed . There­fore, the result of an instru cti on w i th the Status register
as its destinatio n may be dif ferent than intended . As an
example, CLRF STATUS will set the Z bit and leave the
remaining Status bits unchanged (‘000u u1uu’).

REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDCC

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1 = Result was negative

0 = Result was positive

bit 3 OV: Overf low bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit

magnitude which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

Note: For Borrow,

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.

bit 0 C: Carry/Borrow

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For Borrow,

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.

bit

the polarity is reversed. A subtraction is executed by adding the two’s

bit

the polarity is reversed. A subtraction is executed by adding the two’s

It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status
register , b ecaus e thes e ins tructi ons d o not af fect t he Z,
C, DC, OV or N bits in the Status register.

For other instructions that do not affect S tatus bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.

Note: The C and DC bits operate as the Borrow

and Digit Borrow bits, respectively, in
subtraction.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS39632B-page 71

PIC18F2455/2550/4455/4550

5.4 Data Addressing Modes

Note: The ex ecution o f some ins truct ions in t he

core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data

Memory and the Extended Instruction
Set” for more information.

While the program memory can be addressed in only
one way – through the program counter – information
in the data memory sp ace c an be a ddress ed in severa l
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on whic h operands are used and whe ther or
not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect
An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.

5.4.1 INHERENT AND LITERAL ADDRESSING

Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Exa mp les includ e SLEEP, RESET
and DAW.

Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.

5.4.2 DIRECT ADDRESSING

Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address spec ifies either a re gister address in
one of the banks of d ata RAM ( Section 5.3.4 “General

Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.

The Access RAM bit ‘a’ de term in es ho w the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register (BSR)”) are
used with the address t o determin e the comple te 12-bit
address of the reg ister. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.

The destination of the operati on’s results is determine d
by the destination bit ‘d ’. Wh en ‘d’ is ‘1’, the results are
stored back in t he s o ur c e re g is ter, over wr iti n g i ts or i gi ­nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destin ation th at is i mplicit in the instruc tion; the ir
destination is either the target register being operated
on or the W register.

5.4.3 INDIRECT ADDRESSING

Indirect addressi ng allows the user to acces s a locatio n
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the location s to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.

The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic mani pulati on of the poi nter value with
auto-incrementing, auto-decrementing or offsetting
with another va lue . Th is al lo ws f or e fficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING
INDIRECT ADDRESSING

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then
; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

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5.4.3.1 FSR Registers and the
INDF Operand

At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, s o each
FSR pair holds a 12-bi t va lue. T his repre sen ts a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.

Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers; they are

FIGURE 5-7: INDIRECT ADDRESSING

mapped in the SFR spa ce but are not physic ally im ple­mented. Reading or writing to a parti cular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of th eir corr espon ding FSR as a poin ter to th e
instruction’s target. The INDF operand is just a
convenient way of using the pointer.

Because indirect addres sing uses a full 1 2-bit a ddress ,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.

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5.4.3.2 FSR Registers and POSTIN C,
POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each F SR register p air
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by ‘1’ afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by ‘1’ afterwards

• PREINC: increment s the FSR valu e by ‘1’, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses
the new value in the operation.

In this context, accessing an INDF register uses the
value in the FSR registers with out changing the m. Sim­ilarly , accessing a PLUSW reg ister gives the FSR value
offset by t hat in th e W register; neither value is ac tu all y
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register from FFh to 00h carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the Status register (e.g., Z, N, OV, etc.).

The PLUSW register can be used to implement a form
of indexed addressing in t he data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as softw are stacks, inside of data memory.

5.4.3.3 Operations by FSRs on FSRs

Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam­ple, using an FSR to point to one of the virtual regis ters
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attemp ts to read the va lue of INDF1,
using INDF0 as an operand, will return 00h. Attempts
to write to INDF1, using INDF0 as the operand, will
result in a NOP.

On the other hand, using the virtua l registers to write to
an FSR pair may not occu r as p lanned . In t hese cases,
the value will be written to the FSR p air bu t without an y
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.

Similarly, operations by indirect addressing are gener­ally permitted on all other SFRs . Users sho uld exerc ise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.

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5.5 Program Memory and the Extended Instruction Set

The operation of progra m m emory is un affected by the
use of the extended instruction set.

Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These
instructions are executed as described in

Section 5.2.4 “Two-Word Instructions”.

5.6 Data Memory and the Extended Instruction Set

Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically , t he use of the Ac cess Bank for ma ny of the
core PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space. This mode also alters the behavior of
indirect addressing using FSR2 and its associated
operands.

What does not change is just as im po rtant. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.

5.6.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair a nd its a ssociated fil e operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented –
instructions – can invoke a form of indexed addressing
using an offse t spe ci fied in the instruction. This special
addressing mode is know n as I ndexed A ddressing with
Literal Offset or Indexed Literal Offset mode.

When using the extended instruction set, this
addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);
and

• The file address argument is less than or equal
to 5Fh.

Under these conditions, the file address of the instruc­tion is not interpreted as the lower byte of an address
(used with the BSR in direct addre ssing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an address pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.

5.6.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed Literal
Offset Addressing mode. This includes all byte-oriented
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only use
Inherent or Literal Addressing modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file addres s of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different
possible addressing modes when the extended
instruction set is enabled in shown in Figure 5-8.

Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.

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FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When a = 0 and f ≥ 60h:

The instruction executes in
Direct Forced mode. ‘f’ is inter­preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.

Locations below 60h are not
available in this addressing
mode.

When a = 0 and f ≤ 5Fh:

The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.

Note that in this mode, the
correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

000h

060h
080h

100h

F00h

F60h

FFFh

000h

080h

100h

F00h
F60h

FFFh

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

Data Memory

00h
60h

Access RAM

FSR2H FSR2L

FFh

ffffffff001001da

Valid range

for ‘f’

BSR

00000000

ffffffff001001da

When a = 1 (all values of f):

The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter­preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Sel ect

000h

080h

100h

Bank 0

Bank 1

through

Bank 14

Register (BSR). The address
can be in any implemented
bank in the data memory
space.

DS39632B-page 76 Preliminary  2004 Microchip Technology Inc.

F00h
F60h

FFFh

Bank 15

SFRs

Data Memory

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5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode
effectively changes how the lower portion of Access
RAM (00h to 5Fh) is mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.3 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-9.

Remapping of the Access Bank applies only to opera­tions using the I ndexed Lite ral Offs et mode. Ope rations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before. Any indirect or
indexed operation tha t explicitly uses an y of the indirect
file operands (including FSR2) will continue to operate
as standard indirect addressing. Any instruction that
uses the Access Bank, but includes a register address
of greater than 05Fh, w ill use di rect address ing and th e
normal Access Bank map.

5.6.4 BSR IN INDEXED LITERAL OFFSET MODE

Although the Access Bank is remapped when the
extended instruct ion set is enable d, the operation o f the
BSR remains unchanged. Direct addressing using the
BSR to select the data memory bank operates in the
same manner as previously described.

FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL

OFFSET ADDRESSING

Example Situation:

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).

Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh as usual.

Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.

000h

100h
120h

17Fh

200h

F00h
F60h

FFFh

Bank 0

Window

Bank 1

Bank 2

through

Bank 14

Bank 15

SFRs

Data Memory

00h

Bank 1 “Window”

5Fh
60h

SFRs

FFh

Access Bank

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NOTES:

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6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and
erasable, during normal operation over the entire V
range.

A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 32 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.

Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.

A value written to progra m memory does not nee d to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.

DD

6.1 Table Reads and Table Writes

In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory sp ace and the dat a RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).

Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.

Table wri te oper at ions s tore d ata fr om t he data me mor y
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.

Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a t able write is being
used to write executable code into program memory,
program instructions will need to be word aligned.

FIGURE 6-1: TABLE READ OPERATION

Table Pointer

TBLPTRU

Note 1: Table Pointer register points to a byte in program memory.

TBLPTRH TBLPTRL

(1)

Program Memory
(TBLPTR)

Instruction: TBLRD*

Program Memory

Table Latch (8-bit)

TABLAT

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FIGURE 6-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Table Pointer

TBLPTRU

Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by

TBLPTRH TBLPTRL

TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

(1)

Program Memory
(TBLPTR)

Holding Registers

Table Latch (8-bit)

TABLAT

6.2 Control Registers

Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control
register for memory acce sses. The EECO N2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.

The EEPGD control bit determines if th e access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.

The CFGS control bit determines if the access will be
to the configuration/calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on configuration
registers regardless of EEPGD (see Section 25.0
“Special Features o f the CPU”). Wh en clear , memory
selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear , only wr ite s are enab led .

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is c lear . T he WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.

The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be
cleared in software.

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REGISTER 6-1: EECON1: DATA EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access configuration registers
0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPT R on the next WR command (cleared

by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in

normal operation or an improper write attempt)

0 = The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.

This allows tracing of the error condition.

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read t akes one cycle. RD is cleared in ha rdware. The RD bit can

only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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6.2.2 TABLE LATCH REGISTER (TABLAT)

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.

6.2.3 TABLE POINTER REGISTER (TBLPTR)

The Table Pointer (TBLPTR) reg is ter ad dre ss es a by te
within the program memory. The TBLPTR is comprised
of three SFR registers : Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis­ters join to form a 22-bit wide po inter. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory sp ace. Th e 22nd b it allow s acce ss to
the device ID, the user ID and the configuration bits.

The table pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table opera­tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the
Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABL AT.

When a TBLWT is executed, the five LSbs of the Table
Pointer register (TBLP TR<4:0>) determine which of the
32 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 17 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 32 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased . The Least
Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example Operation on Table Pointer

TBLRD*
TBLWT*

TBLRD*+
TBLWT*+

TBLRD*­TBLWT*-

TBLRD+*
TBLWT+*

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read /write

TBLPTR is not modified

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 16 15 87 0

DS39632B-page 82 Preliminary  2004 Microchip Technology Inc.

TBLPTRU

TABLE ERASE
TBLPTR<21:6>

TABLE WRITE – TBLPTR<21:5>

TABLE READ – TBLPTR<21:0>

TBLPTRLTBLPTRH

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6.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are pe rformed one by te at
a time.

TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.

The internal program memory is typically organize d by
words. The Least Significant b it of th e address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

Instruction Register

(IR)

FETCH

TBLRD

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVF WORD_ODD

TBLPTR = xxxxx0

TABLAT

Read Register

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6.4 Erasing Flash Program Memory

The minimum eras e block is 32 wo rds or 64 b ytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word Erase in the Flash array is not
supported.

When initiating an erase sequence from the micro­controller itself, a blo ck of 64 bytes of program memo ry
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.

The EECON1 register comma nds the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The F REE bit is set to select an erase
operation.

For protection, the wri te i ni tiat e s equ enc e f or EECO N2
must be used.

A long write is nec essa ry for erasin g the i nternal Flash.
Instruction execution is halted while in a long write

6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internal
program memory location is:

1. Load Table Pointer register with address of row

being erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the Row Erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

cycle. The long write will be terminated by the internal
programming timer.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW

ERASE_ROW

Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts

MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

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6.5 Writing to Flash Program Memory

The minimum programming block is 16 words or
32 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 32 holding registers used by the table writes for
programming.

Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 32
times for each programming operation. All of the table
write operations will essential ly be short writes because
only the holding registers are written. At the end of
updating the 32 holding reg isters, the EECON1 regis ter
must be written to in order to start the programming
operation with a long write.

The long write is necessary for programming the
internal Flash. Instructio n execu tion is halted wh ile in a
long write cycle. The long write will be terminated by
the internal programming timer.

The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.

Note: The default value of the holding registers on

device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte . This mea ns that
individual bytes of program memory may be
modified, provided that the change does not
attempt to chang e any bi t from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 32 holding registers
before executing a write operation.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

Holding Register Holding Register Holding Register Holding Register

8 8 8

6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internal
program memory location should b e:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execu te the Row Erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Write 32 bytes into the holding registers with

auto-increment.

7. Set the EECON1 register for the w rite operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

TBLPTR = xxxx1FTBLPTR = xxxxx1TBLPTR = xxxxx0 TBLPTR = xxxxx2

Program Memory

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.
1 1. Set the WR bit. This will beg in the write cy cle.

12. The CPU will stall for dura tion of t he write (about
2 ms using internal timer).

13. Re-enable interrupts.

14. Repeat steps 6 through 14 once more to write
64 bytes.

15. Verify the memory (table read).

This procedure will require about 8 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.

Note: Before setting the WR bit, the Table

Pointer address needs to be within the
intended address range of the 32 bytes in
the holdin g register.

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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW

READ_BLOCK

MODIFY_WORD

ERASE_BLOCK

Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh

WRITE_BUFFER_BACK

WRITE_BYTE_TO_HREGS

MOVWF TBLPTRL

TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat

MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h

MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW D’2’
MOVWF COUNTER1

MOVLW D’32’ ; number of bytes in holding register
MOVWF COUNTER

MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS

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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh

BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h

MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DECFSZ COUNTER1
BRA WRITE_BUFFER_BACK
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

If a write is termin ate d b y a n u npl anned event, such as
loss of power or an unexpected Reset, the memory
location just pr ogrammed shou ld be verifi ed and rep ro­grammed if needed. If the wr ite operatio n is interrupte d
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.

6.5.4 PROTECTION AGAINST SPURIOUS WRITES

To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Sp eci al F eatu res of the

CPU” for more detail.

6.6 Flash Program Operation During

Code Protection

See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash

program memory.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TBLPTR U
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 51
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 51
TABLAT Program Memory Table Latch 51
INTCON GIE/GIEH PEIE/GIEL
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 51

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51

— FREE WRERR WREN WR RD 53

USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54

Values

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7.0 DATA EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,
separate from the dat a RAM and program memory, that
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space, but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writab le during no rmal operati on over the
entire V

Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR
The data EEPROM allows byte read and write. When

interfaci ng to the data mem ory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
holds the address of the EEPROM location being
accessed.

The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip
to chip. Please refer to parameter D122 (Table 28-1 in
Section 28.0 “Electrical Characteristics”) for exact
limits.

7.1 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two
registers: EECON1 and EECO N2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.

The EECON1 register (Register 7-1) is the control
register for data and program memory access. Control
bit, EEPGD, determines if the acc ess will be to progra m
or data EEPROM memory. When clear, operations will
access the data EEPROM memory . Whe n set, program
memory is accessed.

DD range.

Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is c lear . Th e WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.

The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be
cleared in software.

Control bits, RD and WR, start read and erase/write
operations, respec tively . These bits a re set by firmwa re
and cleared by hardware at the completion of the
operation.

The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Read s
and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.

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REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access configuration registers
0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPT R on the next WR command (cleared

by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in

normal operation or an improper write attempt)

0 = The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.

This allows tracing of the error condition.

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read

(Read takes one cyc le. RD is cleared in ha rdware. The RD bit can only be set (not cleare d)
in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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7.2 Reading the Data EEPROM Memory

T o read a d ata memory loca tion, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another re ad opera tion o r unt il it is writ ten to
by the user (during a write operation).

The basic process is shown in Example 7-1.

7.3 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be fol lowed to initiate the write cycl e.

The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.

Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe­cution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc­tion. Both WR and WREN c an not be se t with th e s am e
instruction.

At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag b it
(EEIF) is set. The user ma y either e nable this interrup t,
or poll this bit. EEIF must be cleared by software.

7.4 Write Verify

Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

EXAMPLE 7-1: DATA EEPROM READ

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes

Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;

BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;

MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

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7.5 Operation During Code-Protect

Data EEPROM memory has its own code-protect bit s in
Configuration Words. External read and write
operations are disabled if code protection is enabled.

The microcontroller i tself can both re ad and wr ite to the
internal data EEPROM regardless of the state of the
code-protect configuration bit. Refer to Section 25.0
“Special Features of the CPU” for additional
information.

7.6 Protection Against Spurious Write

7.7 Using the Data EEPROM

The data EEPROM is a hi gh en dura nc e, byt e address­able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124 or D124A. If this is
not the case, an ar ray r efr esh m ust be pe rfor med . For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.

A simple data EEPROM refresh routine is shown in

There are conditions when the device may not want to

Example 7-3.

write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are b locked
during the Power-up Timer period (T

PWRT,

parameter 33, Table 28-12).
The write initiate se quence and the WREN bit together

help prevent an accidental write during brown-out,
power glitch or software malfunction.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;

BSF EECON1, RD ; Read current address
MOVLW 55h ;

MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again

Note: If data EEPROM is only used to store

constants an d/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.

BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts

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TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Reset

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
EEADR EEPRO M Address Register 53
EEDATA EEPROM Data Register 53
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

— FREE WRERR WREN WR RD 53

USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54

Values

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8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier pe rforms an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the Status
register.

Making multiplication a hardware operation allows it to
be completed in a s ingle instruction cycle. This has th e
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica­tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.

Example 8-2 shows the s equence to d o an 8 x 8 si gned
multiplication. To account for the sign bits of the
arguments, eac h argume nt’s Most Signi ficant b it (MSb)
is tested and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine Multiply Method

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

Without hardware multiply 13 69 6.9 µs27.6 µs69 µs

Hardware multiply 1 1 100 ns 400 ns 1 µs

Without hardware multiply 33 91 9.1 µs36.4 µs91 µs

Hardware multiply 6 6 600 ns 2.4 µs6 µs

Without hardware multiply 21 242 24.2 µs96.8 µs 242 µs

Hardware multiply 28 28 2.8 µs 11.2 µs28 µs

Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs

Hardware multiply 35 40 4.0 µs16.0 µs40 µs

Program

Memory

(Words)

Cycles

(Max)

@ 40 MHz @ 10 MHz @ 4 MHz

Time

 2004 Microchip Technology Inc. Preliminary DS39632B-page 95

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Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used . The 32-bit re sult is st ored in four
registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0 = ARG1 H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L)

16

) +

8

) +

8

) +

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION
ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2

16

) +

8

) +

8

) +

EXAMPLE 8-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->

MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->

MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;

;

MOVF ARG1L,W
MULWF ARG2H ; ARG1L * ARG2H ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->

MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;

SUBWFB RES3
;
SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3
;
CONT_CODE
:

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

; PRODH:PRODL

16

) +

16

)

DS39632B-page 96 Preliminary  2004 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

9.0 INTERRUPTS

The PIC18F2455/2550/4455/4550 devices have
multiple interrupt sources and an interrupt priority
feature that allows each interrupt so urce to be assigne d
a high priority level or a low priority level. The high
priority interrupt vector is at 000008h and the low
priority interrupt vector is at 000018h. High priority
interrupt events will interrupt any low priority interrupts
that may be in progress.

There are ten registers which are used to control
interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2
It is recommended that the Microchip header files

supplied with MPLAB
names in these registers. This allows the assembler/
compiler to automatical ly ta ke care of the pla ceme nt of
these bits within the specified register.

Each interrupt source has three bits to control its
operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event
occurred

• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally . Setti ng the GIEH bit (INTC ON<7>) enable s all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the prio rity bit cleared ( low priority ).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual inter­rupts can be disabled through their corresponding
enable bits.

When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/dis ables all pe ripheral interru pt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.

®

IDE be used for the symb olic bit

®

mid-range devices. In

When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interru pt priority
levels are used, this wi ll be either the GIEH or G IEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter­mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in s oftware be fore re-enab ling
interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and set s the GIE bit (GIEH or GI EL
if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or
the PORTB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.

9.1 USB Interrupts

Unlike other perip herals , the USB modu le is cap abl e of
generating a wide range of interrupt s for m any types of
events. These incl ude se veral t ypes of no rmal com mu­nication and status events and several module level
error events.

To handle these events, the USB module is equipped
with its own interrupt logic. The logic functions in a
manner similar to the micr ocontroller level interrupt fun­nel, with each interru pt source havin g separate fla g and
enable bits. All events are funneled to a single device
level interrupt, USBIF (PIR2<5>). Unlike the device
level interrupt log ic, the in divid ual U SB inte rrupt ev ent s
cannot be individually assigned their own priority. This
is determined at the device level interrupt funnel for all
USB events by the USBIP bit.

For additional details on USB interrupt logic, refer to
Section 17.5 “USB Interrupts”.

 2004 Microchip Technology Inc. Preliminary DS39632B-page 97

PIC18F2455/2550/4455/4550

FIGURE 9-1: INTERRUPT LOGIC

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

From USB
Interrupt Logic

High Priority Interrupt Generation

Low Priority Interrupt Generation

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

TMR1IF
TMR1IE
TMR1IP

From USB
Interrupt Logic

USBIF
USBIE
USBIP

TMR1IF
TMR1IE
TMR1IP

USBIF
USBIE
USBIP

Additional Peripheral Interrupts

Additional Peripheral Interrupts

IPEN

TMR0IF
TMR0IE

TMR0IP

RBIF
RBIE

RBIP

INT1IF
INT1IE

INT1IP
INT2IF

INT2IE
INT2IP

TMR0IF
TMR0IE
TMR0IP

INT0IF
INT0IE

INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP

IPEN

GIEL/PEIE

RBIF
RBIE
RBIP

IPEN

Wake-up if in Sleep Mode

GIEL/PEIE

GIE/GEIH

Interrupt to CPU
Vector to Location

0008h

GIEH/GIE

Interrupt to CPU
Vector to Location
0018h

DS39632B-page 98 Preliminary  2004 Microchip Technology Inc.