MICROCHIP PIC18F2420, PIC18F2520, PIC18F4420, PIC18F4520 DATA SHEET
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PIC18F2420/2520/4420/4520
Data Sheet
28/40/44-Pin
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
2004 Microchip Technology Inc. Preliminary DS39631A
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39631A-page ii Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
28/40/44-Pin Enhanced Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
Power Managed Modes:
• Run: CPU on, peripheral s on
• Idle: CPU off, peripheral s on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 µA typical
• Sleep mode current down to 0.1 µA typical
• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V
• Watchdog Timer: 2.1 µA
• T wo -Spe ed Os ci ll ator Start-up
Peripheral Highlights:
• High-current sink/source 25 mA/25 mA
• Three programmable external interrupts
• Four input change interrupts
• Up to 2 Capture/Compare/PWM (CCP) modules,
one with Auto-Shutdown (28-pin devices)
• Enhanced Capture/Compare/PWM (ECCP)
module (40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I
Master and Slave Modes
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- RS-232 operation using internal oscillator
block (no external cryst a l requi red)
- Auto-Wake-up on Start bit
- Auto-Baud Detect
• 10-bit, up to 13-channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Dual analog comparators with input multiplexing)
2
C™
Flexible Oscillator Structure:
• Four Crystal modes, up to 40 MHz
• 4X Phase Lock Loop (available for crystal and
internal oscillators)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal oscillat or bloc k:
- 8 user selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User tunable to c o mp en sa te for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
• C compiler optimized architecture:
- Optional extended instruct ion set designed to
optimize re-entrant code
• 100,000 erase/write cy cl e Enhan ced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: 100 years typical
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
• Programmable 16-level High/Low-Voltage
Detection (HLVD) module:
- Supports interrupt on High/Low-Voltage
Detection
• Programmable Brown-out Reset (BOR
- With software enable option
2004 Microchip Technology Inc. Preliminary DS39631A-page 1
PIC18F2420/2520/4420/4520
-
Program Memory Data Memory
Device
PIC18F2420 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3
PIC18F2520 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3
PIC18F4420 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3
PIC18F4520 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
10-bit
A/D (ch)
CCP/
ECCP
(PWM)
SPI
MSSP
Master
2
I
C
Comp.
EUSART
Timers
8/16-bit
DS39631A-page 2 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams
28-pin PDIP, SOIC
PIC18F2420/2520/4420/4520
RA5/AN4/SS
40-pin PDIP
RA5/AN4/SS
MCLR/VPP/RE3
RA0/AN0
RA2/AN2/V
RA4/T0CKI/C1OUT
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RA2/AN2/V
RA4/T0CKI/C1OUT
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RA1/AN1
REF-/CVREF
RA3/AN3/VREF+
/HLVDIN/C2OUT
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC2/CCP1
RC3/SCK/SCL
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
REF-/CVREF
RA3/AN3/VREF+
/HLVDIN/C2OUT
RE0/RD
RE1/WR
RE2/CS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
V
/AN5
/AN6
/AN7
V
VSS
PIC18F2520
PIC18F4520
28
27
26
25
24
23
22
21
20
19
18
17
16
15
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
DD
V
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
(1)
(1)
1
2
3
4
5
6
7
SS
(1)
DD
(1)
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F2420
PIC18F4420
28-pin QFN
/VPP/RE3
MCLR
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
22
232425262728
1213 14
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RB4KBI0/AN11
21
20
19
18
17
16
15
RC6/TX/CK
RB3/AN9/CCP2
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RC7/RX/DT
(1)
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA5/AN4/SS
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
RA4/T0CKI/C1OUT
/HLVDIN/C2OUT
V
OSC1/CLKI/RA7
OSC2/CLKO/RA6
SS
1
2
3
PIC18F2420
4
PIC18F2520
5
6
7
8
9
(1)
RC1/T1OSI/CCP2
RC0/T1OSO/T13CKI
1011
RC2/CCP1
2004 Microchip Technology Inc. Preliminary DS39631A-page 3
PIC18F2420/2520/4420/4520
Pin Diagrams (Cont.’d)
44-pin TQFP
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB3/AN9/CCP2
RC7/RX/DT
RD4/PSP4
V
VDD
RB2/INT2/AN8
(1)
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2
NC
15
16
RB6/KBI2/PGC
RB5/KBI1/PGM
38
39
37
1819202122
17
RA0/AN0
/VPP/RE3
RB7/KBI3/PGD
MCLR
363435
RA1/AN1
33
32
31
30
29
28
27
26
25
24
23
REF-/CVREF
RA3/AN3/VREF+
NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
SS
V
VDD
RE2/CS/AN7
/AN6
RE1/WR
/AN5
RE0/RD
RA5/AN4/SS
RA4/T0CKI/C1OUT
/HLVDIN/C2OUT
4443424140
1
2
3
4
5
SS
(1)
PIC18F4420
6
PIC18F4520
7
8
9
10
11
121314
NC
NC
RB4/KBI0/AN11
44-pin QFN
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
V
VDD
VDD
SS
1
2
3
4
5
6
7
8
9
10
11
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
4443424140
PIC18F4420
PIC18F4520
121314
15
16
(1)
NC
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
38
39
37
1819202122
17
RA0/AN0
/VPP/RE3
RB7/KBI3/PGD
MCLR
(1)
RC2/CCP1/P1A
RC1/T1OSI/CCP2
363435
RA1/AN1
REF-/CVREF
RA2/AN2/V
RA2/AN2/V
RC0/T1OSO/T13CKI
33
32
31
30
29
28
27
26
25
24
23
REF+
RA3/AN3/V
OSC2/CLKO/RA6
OSC1/CLKI/RA7
SS
V
VSS
VDD
VDD
RE2/CS/AN7
/AN6
RE1/WR
/AN5
RE0/RD
RA5/AN4/SS
RA4/T0CKI/C1OUT
/HLVDIN/C2OUT
DS39631A-page 4 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
Table of Contents
1.0 Device Overview.......................................................................................................................................................................... 7
2.0 Oscillator Configurations............................................................................................................................................................ 23
3.0 Power Managed Modes ...................................... .. .. .... .. .. ..... .. .. .... .. .. .. .. ....... .. .. .. .. .. .. ....... .. .. .. ...................................................... 33
4.0 Reset..........................................................................................................................................................................................41
5.0 Memory Organization.................................................................................................................................................................53
6.0 Flash Program Memory............ ................ ................. ................. ................................................................................................73
7.0 Data EEPROM Memory.................................. ................................................ ........................................................................... 83
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89
9.0 Interrupts.................................................................................................................................................................................... 91
10.0 I/O Ports................................ ................................................................................................................................................... 105
11.0 Timer0 Module ......................................................................................................................................................................... 123
12.0 Timer1 Module ......................................................................................................................................................................... 127
13.0 Timer2 Module ......................................................................................................................................................................... 133
14.0 Timer3 Module ......................................................................................................................................................................... 135
15.0 Capture/Compare/P w m (CCP) Modules.............................................. ................. ................. .................................................. 139
16.0 Enhanced Capture/Compare/PWM (ECCP) Module ................................................................................................................ 147
17.0 Master Synchronous Serial Port (MSSP) Module ............................................................................... .....................................161
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 201
19.0 10-Bit Analog-to-Digital Converter (A/D) Module .....................................................................................................................223
20.0 Comparator Module.......................................................................................................... ........................................................ 233
21.0 Comparator Voltage Reference Module................................................................................................................................... 239
22.0 High/Low-Voltage Detect (HLVD).......................................................................... .... ......... .... ..................................................243
23.0 Special Features of the CPU.......... ................. ................ ................. ................. ....................................................................... 249
24.0 Instruction Set Summary.......................................................................................................................................................... 267
25.0 Development Support............................................................................................................................................................... 317
26.0 Electrical Characteristics.......................................................................................................................................................... 323
27.0 DC and AC Characteristics Graphs and Tables................................................................... .... .... .. .......................................... 361
28.0 Packaging Informa tio n. ................................................ ................. ............................................................................................ 363
Appendix A: Revision History............................................................................................................................................................. 371
Appendix B: Device Differences ........................................................................................................................................................ 371
Appendix C: Conversion Considerations ...........................................................................................................................................372
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 372
Appendix E: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 373
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 373
Index .................................................................................................................................................................................................. 375
On-Line Support.................................................................................................................................................................................385
Systems Information and Upgrade Hot Line...................................................................................................................................... 385
Reader Response.............................................................................................................................................................................. 386
PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................387
2004 Microchip Technology Inc. Preliminary DS39631A-page 5
PIC18F2420/2520/4420/4520
TO OUR VALUED CUSTOMERS
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We welcome your feedback.
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DS39631A-page 6 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F2420 • PIC18LF2420
• PIC18F2520 • PIC18LF2520
• PIC18F4420 • PIC18LF4420
• PIC18F4520 • PIC18LF4520
This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance
at an economical price – with the addition of highendurance, Enhanced Flash program memory. On top
of these features, the PIC18F2420/2520/4420/4520
family introduces design enhancements that make
these microcontrollers a logical choice for many highperformance, power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2420/2520/4420/4520
family incorporate a range of features that can significantly reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these st ates, powe r consumpt ion can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power
managed modes a re invo ked b y user code durin g
operation, allowing the user to incorporate powersaving ideas into their application’s software
design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 26.0 “Electrical Characteristics”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2420/2520/4420/4520
family offer ten different oscillator options, allowing
users a wide range o f choices i n develo ping applica tion
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which provides an
8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of 6 user
selectable cl ock fre quenc ies, be tween 125 kHz to
4 MHz, for a total of 8 clock frequencies. This
option frees the two oscillator pins for use as
additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and inte rnal oscillator m odes, which a llows clo ck speeds o f
up to 40 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 32 MHz – all without usin g
an external crystal or clock circuit.
Besides its ava ilability as a cloc k source, the intern al
oscillator block pro vid es a s t ab le re fere nce source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference signal provi ded by the i nte rnal os ci llator. If a
clock failure occurs, the controller is switched to
the internal oscillato r block, al lowing f or continue d
low-speed operation or a safe application
shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
2004 Microchip Technology Inc. Preliminary DS39631A-page 7
PIC18F2420/2520/4420/4520
1.2 Other Special Features
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-programmability: These devices can write
to their own program memory spaces under internal software control. By us ing a bootloader routi ne
located in the protecte d Boot Block a t the top of
program memory, it becomes possible to create
an application that can update itself in the field.
• Extended Instruction Set: The PIC18F2420/
2520/4420/4520 family introduces an opti onal
extension to the PIC18 inst ruction set, whic h adds
8 new instructions and an Indexed Addressing
mode. This extension, enabled as a device configuration option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include Auto-S hutdown, for disabling PWM outputs on interrupt or other select
conditions and Auto-Rest art, to re activ ate outpu ts
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolu tion. When the
microcontroller is using the internal oscillator
block, the USART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated withou t wai ting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version in corpora tes a 1 6-bit pre scale r,
allowing an extende d tim e-out range that is st able
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F 2420/2520 /4420/4520 famil y are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure1-1
and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (16Kbytes for
PIC18F2420/4420 devices and 32 Kbytes for
PIC18F2520/4520).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectio nal ports on 28-pin devices,
5 bidirectional ports on 40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP modules, 40/44-pin devic es hav e one st and ard CCP
module and one ECCP module).
5. Parallel Slave Port (present only on 40/44-pin
devices).
All other features fo r device s in this family are identi cal.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2420/2520/4420/4520 family are available as
both standard and low-voltage devices. Standard
devices with Enhan ced Flas h memory, designated with
an “F” in the part number (such as PIC18F2420),
accommodate an ope rati ng V
Low-voltage parts, designated by “LF” (such as
PIC18LF2420), func tion over an e xtended VDD range
of 2.0V to 5.5V.
DD range of 4.2V to 5.5V.
DS39631A-page 8 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
TABLE 1-1: DEVICE FEATURES
Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (B y tes) 16384 32768 16384 32768
Program Memory
(Instructions)
Data Memory (Bytes) 768 1536 768 1536
Data EEPROM Memory ( Byt es ) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced
Capture/Compare/PWM Modules
Serial Communica ti ons MSSP,
Parallel Communicati ons (P SP) No No Y es Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,
Underflow (PWRT , OST),
Programmable
High/Low-V ol t ag e De tect
Programmable B ro wn- ou t Res et Yes Ye s Yes Yes
Instruction Set 75 Instructions;
Packages 28-pin PDIP
8192 16384 8192 16384
0011
Enhanced USART
RESET Instruction,
Stack Full, Stack
MCLR
(optional), WDT
Yes Yes Yes Yes
83 with Extend ed
Instruction S et en ab led
28-pin SOIC
28-pin QFN
MSSP,
Enhanced USAR T
POR, BOR,
RESET Instruction,
Stack Full, S t ack
Underflow (PWRT, OST),
MCLR (optional), WDT
75 Instructions;
83 with Extended
Instruction Set enabled
28-pin PDIP
28-pin SOIC
28-pin QFN
MSSP,
Enhanced USART
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WD T
75 Instructions;
83 with Extended
Instruction Set enabled
40-pin PDIP
44-pin QFN
44-pin TQFP
MSSP ,
Enhanced USART
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
75 Instructions;
83 with Extend ed
Instruction Set enabled
40-pin PDIP
44-pin QFN
44-pin TQFP
2004 Microchip Technology Inc. Preliminary DS39631A-page 9
PIC18F2420/2520/4420/4520
FIGURE 1-1: PIC18F2420/252 0 (28-PI N) BLOC K DIAGR AM
T able Pointer<21>
inc/dec logic
21
20
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
8
Instruction Bus <16>
PCLATH
PCLATU
PCU
Program Counter
31 Level Stack
STKPTR
Table Latch
ROM Latch
IR
Data Bus<8>
8
PCH PCL
8
Data Latch
Data Memory
( 3.9Kbytes )
Address Latch
12
Data Address< 12>
BSR
4
FSR0
FSR1
FSR2
inc/dec
logic
Address
Decode
4
12
Access
Bank
12
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
OSC2/CLKO
OSC1/CLKI
/HLVDIN/C2OUT
(3)
/RA6
(3)
/RA7
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1
OSC2
T1OSI
T1OSO
MCLR
VDD,
V
BOR
HLVD
8
8
ADC
10-bit
8
PRODLPRODH
PORTC
8
8
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
RC6/TX/CK
RC7/RX/DT
PORTE
MCLR/VPP/RE3
(2)
Instruction
Decode and
Control
State machine
control signals
3
BITOP
8 x 8 Multiply
W
8
(3)
(3)
(2)
SS
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Data
EEPROM
CCP1
CCP2
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
MSSP
Precision
Band Gap
Reference
Timer2Timer1 Timer3Timer0
EUSARTComparator
8
ALU<8>
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR
functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39631A-page 10 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
FIGURE 1-2: PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM
T able Pointer<21>
inc/dec logic
21
Address Latch
Program Memory
(16/32Kbytes)
Data Latch
20
8
PCLATH
PCLATU
PCU
Program Counter
31 Level Stack
STKPTR
Table Latch
Data Bus<8>
8
PCH PCL
8
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latc h
12
Data Address< 12>
BSR
4
FSR0
FSR1
FSR2
inc/dec
logic
4
12
Access
Bank
12
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS
OSC2/CLKO
OSC1/CLKI
/HLVDIN/C2OUT
(3)
/RA6
(3)
/RA7
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Instruction Bus <16>
(3)
OSC1
(3)
OSC2
T1OSI
T1OSO
(2)
MCLR
VDD,
SS
V
BOR
HLVD
ROM Latch
IR
Instruction
Decode and
Control
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Data
EEPROM
State machine
control signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
3
BITOP
8
Precision
Band Gap
Reference
Timer2Timer1 Timer3Timer0
Address
Decode
8 x 8 Multiply
8
ALU<8>
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
8
RC5/SDO
RC6/TX/CK
RC7/RX/DT
PRODLPRODH
PORTD
8
W
8
8
RD0/PSP0
RD5/PSP5/P1B
RD6/PSP6/P1C
:RD4/PSP4
RD7/PSP7/P1D
8
8
PORTE
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/VPP/RE3
(2)
ECCP1
CCP2
MSSP
EUSARTComparator
ADC
10-bit
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR
functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations ” for additional information.
2004 Microchip Technology Inc. Preliminary DS39631A-page 11
PIC18F2420/2520/4420/4520
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
MCLR
/VPP/RE3
MCLR
VPP
RE3
OSC1/CLKI/RA7
OSC1
CLKI
RA7
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PDIP,
SOIC
126
96
10 7
QFN
Pin
Type
I
P
I
I
I
I/O
O
O
I/O
Buffer
Type
ST
ST
ST
CMOS
TTL
—
—
TTL
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programmin g voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator i n Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
DS39631A-page 12 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
T ABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA2
AN2
V
CV
RA3/AN3/V
RA3
AN3
V
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
RA5/AN4/SS
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
REF-/CVREF
REF-
REF
REF+
REF+
/HLVDIN/
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PDIP,
SOIC
QFN
227
328
41
52
63
74
Pin
Buffer
Type
Type
I/OITTL
Analog
I/OITTL
Analog
I/O
TTL
I
Analog
I
Analog
O
Analog
I/O
TTL
I
Analog
I
Analog
I/O
I
O
I/O
TTL
I
Analog
I
TTL
I
Analog
O
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
ST
ST
—
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
Digital I/O.
Analog input 4.
SPI™ slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
Description
2004 Microchip Technology Inc. Preliminary DS39631A-page 13
PIC18F2420/2520/4420/4520
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
RB1/INT1/AN10
RB1
INT1
AN10
RB2/INT2/AN8
RB2
INT2
AN8
RB3/AN9/CCP2
RB3
AN9
(1)
CCP2
RB4/KBI0/AN11
RB4
KBI0
AN11
RB5/KBI1/PGM
RB5
KBI1
PGM
RB6/KBI2/PGC
RB6
KBI2
PGC
RB7/KBI3/PGD
RB7
KBI3
PGD
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PDIP,
SOIC
21 18
22 19
23 20
24 21
25 22
26 23
27 24
28 25
QFN
Pin
Type
I/O
I
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I/O
I
I
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
Buffer
Type
TTL
ST
ST
Analog
TTL
ST
Analog
TTL
ST
Analog
TTL
Analog
ST
TTL
TTL
Analog
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
Digital I/O.
External interrupt 0.
PWM Fault input for CCP1.
Analog input 12.
Digital I/O.
External interrupt 1.
Analog input 10.
Digital I/O.
External interrupt 2.
Analog input 8.
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
DS39631A-page 14 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
T ABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
T1OSI
(2)
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
RE3 — — — — See MCLR
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PDIP,
SOIC
11 8
12 9
13 10
14 11
15 12
16 13
17 14
18 15
QFN
Pin
Buffer
Type
Type
I/O
O
I
I/O
I
Analog
I/O
I/O
I/OSTST
I/O
I/O
I/O
I/O
I
I/O
I/OOST
I/O
O
I/O
I/O
I
I/O
PORTC is a bidirectional I/O port.
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Digital I/O.
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI data in.
I2C data I/O.
Digital I/O.
SPI data out.
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
/VPP/RE3 pin.
Description
2
C™ mode.
2004 Microchip Technology Inc. Preliminary DS39631A-page 15
PIC18F2420/2520/4420/4520
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS
Pin Name
/VPP/RE3
MCLR
MCLR
VPP
RE3
OSC1/CLKI/RA7
OSC1
CLKI
RA7
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Pin Number
PDIP QFN TQFP
11818
13 32 30
14 33 31
Pin
Type
I
P
I
I
I
I/O
O
O
I/O
Buffer
Type
ST
ST
ST
CMOS
TTL
—
—
TTL
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an ac tive-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
analog otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
General purpose I/O pin.
DS39631A-page 16 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
T ABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI/C1OUT
RA5/AN4/SS
C2OUT
RA6 See the OSC2/CLKO/RA6 pin .
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
REF-/CVREF
RA2
AN2
VREF-
REF
CV
REF+
RA3
AN3
REF+
V
RA4
T0CKI
C1OUT
/HLVDIN/
RA5
AN4
SS
HLVDIN
C2OUT
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Pin Number
PDIP QFN TQFP
21919
32020
42121
52222
62323
72424
Pin
Buffer
Type
Type
I/OITTL
Analog
I/OITTL
Analog
I/O
I
Analog
I
Analog
O
Analog
I/O
I
Analog
I
Analog
I/O
I
O
I/O
I
Analog
I
I
Analog
O
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
TTL
TTL
ST
ST
—
TTL
TTL
—
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
Description
2004 Microchip Technology Inc. Preliminary DS39631A-page 17
PIC18F2420/2520/4420/4520
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
RB1/INT1/AN10
RB1
INT1
AN10
RB2/INT2/AN8
RB2
INT2
AN8
RB3/AN9/CCP2
RB3
AN9
(1)
CCP2
RB4/KBI0/AN11
RB4
KBI0
AN11
RB5/KBI1/PGM
RB5
KBI1
PGM
RB6/KBI2/PGC
RB6
KBI2
PGC
RB7/KBI3/PGD
RB7
KBI3
PGD
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Pin Number
PDIP QFN TQFP
33 9 8
34 10 9
35 11 10
36 12 11
37 14 14
38 15 15
39 16 16
40 17 17
Pin
Type
I/O
I
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I/O
I
I
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
Buffer
Type
TTL
ST
ST
Analog
TTL
ST
Analog
TTL
ST
Analog
TTL
Analog
ST
TTL
TTL
Analog
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-u p s on a ll
inputs.
Digital I/O.
External interrupt 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
Digital I/O.
External interrupt 1.
Analog input 10.
Digital I/O.
External interrupt 2.
Analog input 8.
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
clock pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
DS39631A-page 18 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
T ABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
T1OSI
(2)
CCP2
RC2/CCP1/P1A
RC2
CCP1
P1A
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Pin Number
PDIP QFN TQFP
15 34 32
16 35 35
17 36 36
18 37 37
23 42 42
24 43 43
25 44 44
26 1 1
Pin
Buffer
Type
I/O
O
I
I/O
I
CMOS
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I
I/O
I/OOST
I/O
O
I/O
I/O
I
I/O
Type
PORTC is a bidirectional I/O port.
ST
—
ST
ST
ST
ST
ST
—
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 output.
Digital I/O.
Synchronous serial clock input/output for
SPI™ mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
Description
2
C™ mode.
2004 Microchip Technology Inc. Preliminary DS39631A-page 19
PIC18F2420/2520/4420/4520
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RD0/PSP0
RD0
PSP0
RD1/PSP1
RD1
PSP1
RD2/PSP2
RD2
PSP2
RD3/PSP3
RD3
PSP3
RD4/PSP4
RD4
PSP4
RD5/PSP5/P1B
RD5
PSP5
P1B
RD6/PSP6/P1C
RD6
PSP6
P1C
RD7/PSP7/P1D
RD7
PSP7
P1D
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Pin Number
PDIP QFN TQFP
19 38 38
20 39 39
21 40 40
22 41 41
27 2 2
28 3 3
29 4 4
30 5 5
Pin
Buffer
Type
Type
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/OSTTTL
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
Description
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
ST
TTL
—
ST
TTL
—
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
DS39631A-page 20 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
T ABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RE0/RD
RE1/WR/AN6
RE2/CS/AN7
RE3 — — — — — See MCLR
VSS 12, 31 6, 30, 316, 29 P — Ground reference for logic and I/O pins.
/AN5
RE0
RD
AN5
RE1
WR
AN6
RE2
CS
AN7
Pin Number
PDIP QFN TQFP
82525
92626
10 27 27
Pin
Type
I/O
I
I
I/O
I
I
I/O
I
I
Buffer
Type
ST
TTL
Analog
ST
TTL
Analog
ST
TTL
Analog
Description
PORTE is a bidirectional I/O port.
Digital I/O.
Read control for Parallel Slave Port
(see also WR
Analog input 5.
Digital I/O.
Write control for Parallel Slave Port
(see CS
Analog input 6.
Digital I/O.
Chip Select control for Parallel Slave Port
(see related RD
Analog input 7.
and CS pins).
and RD pins).
and WR).
/VPP/RE3 pin.
V
DD 11, 32 7, 8,
28, 29
NC — 13 12, 13,
Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
7, 28 P — Positive supply for logic and I/O pins.
— — No conne ct.
33, 34
2004 Microchip Technology Inc. Preliminary DS39631A-page 21
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 22 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
PIC18F2420/2520/442 0/4520 devices can be operated
in ten different osc illato r modes . The us er can pro gram
the configuration bi ts, FOSC3:FOSC 0, in Configuratio n
Register 1H to select one of these ten modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
F
OSC/4 output on RA6
6. RCIO External Resistor/Capacitor with I/O
on RA6
7. INTIO1 Internal Oscillator with F
on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
9. EC External Clock with F
10. ECIO External Clock with I/O on RA6
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
OSC/4 output
OSC/4 output
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
(1)
C1
(1)
C2
Note 1: See T able 2-1 and Table2-2 for initial values of
2: A series resistor (R
3: R
OSC1
XTAL
(2)
RS
OSC2
C1 and C2.
strip cut crystals.
F varies with the oscillator mode chosen.
(3)
RF
Sleep
PIC18FXXXX
S) may be required for AT
To
Internal
Logic
T ABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 3.58 MHz
4.19 MHz
4 MHz
4 MHz
Capacitor values are for design guidance only.
Different cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following Table 2-2 for additional
information.
Note: When using resonators with frequencies
above 3.5 MHz, the use of HS mode,
rather than XT mode, is recommended.
HS mode may be used at any V
which the controller is rated. If HS is
selected, it is possible that the gain of the
oscillator will overdrive the resonator.
Therefore, a series resistor should be
placed between the OSC2 pin and the
resonator. As a good starting point, the
recommended value of R
15 pF
15 pF
30 pF
50 pF
15 pF
15 pF
30 pF
50 pF
DD for
S is 330Ω.
2004 Microchip Technology Inc. Preliminary DS39631A-page 23
PIC18F2420/2520/4420/4520
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc T y pe
Crystal
Freq
LP 32 kHz 30 pF 30 pF
XT 1 MHz
4 MHz
HS 4 MHz
10 MHz
20 MHz
25 MHz
25 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation . These values
are not optimized.
Different capa citor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
DD and temperature range for the application.
V
See the notes following this table for additional
information.
32 kHz 4 MHz
25 MHz 10 MHz
1 MHz 20 MHz
Note 1: Higher capacitanc e increases th e stabilit y
of the oscillator but also increases the
start-up time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be r equired to av oid overdr iving
crystals with low driv e lev e l spe ci fic ati on.
5: Always verify oscillator perform an ce over
DD and temperature range that is
the V
expected for the application.
T ypical Cap acitor V alues
Tested:
C1 C2
15 pF
15 pF
15 pF
15 pF
15 pF
0 pF
15 pF
Crystals Used:
15 pF
15 pF
15 pF
15 pF
15 pF
5 pF
15 pF
DD, or when
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
Open
OSC1
OSC2
PIC18FXXXX
(HS Mode)
2.3 External Clock Input
The EC and ECIO Oscillator mode s require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
F
OSC/4
The ECIO Oscillator mo de func tio ns lik e t he EC mod e,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK
Clock from
Ext. System
RA6
OSC1/CLKI
PIC18FXXXX
OSC2/CLKO
INPUT OPERATION
(ECIO CONFIGURATION)
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
DS39631A-page 24 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
2.4 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:
• supply voltage
• values of the external resistor (R
capacitor (C
EXT)
• operating temperature
Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
• normal manufacturing variation
• difference in lead frame capacitance between
package types (especially for low C
• variations within the t olerance of limits of REXT
EXT
and C
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-5 shows how the R/C combination is
connected.
FIGURE 2-5: RC OSCILLATOR MODE
VDD
REXT
OSC1
CEXT
VSS
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
OSC/4
OSC2/CLKO
EXT > 20 pF
C
The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-6: RCIO OSCILLATOR MODE
VDD
REXT
OSC1
EXT) and
EXT values)
Internal
Clock
PIC18FXXXX
Internal
Clock
2.5 PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
2.5.1 HSPLL OSCILLATOR MODE
The HSPLL mode make s use of the HS mode osc illator
for frequencies up t o 10 MHz. A PLL then multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz. The PLLEN bit is not
available in this oscillator mode.
The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 configu r ati on bi t s are prog ram med
for HSPLL mode (= 0110).
FIGURE 2-7: PLL BLOCK DIAGRAM
(HS MODE)
HS Oscillator Enable
PLL Enable
(from Configuration Register 1H)
OSC2
OSC1
HS Mode
Crystal
Osc
IN
F
FOUT
÷4
2.5.2 PLL AND INTOSC
The PLL is also ava ilabl e to th e inte rnal os cill ator bl ock
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the
PLL is described in Section 2.6.4 “PLL in INTOSC
Modes”.
Phase
Comparator
Loop
Filter
VCO
SYSCLK
MUX
CEXT
VSS
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
2004 Microchip Technology Inc. Preliminary DS39631A-page 25
I/O (OSC2)
C
EXT > 20 pF
PIC18FXXXX
PIC18F2420/2520/4420/4520
2.6 Internal Oscillator Block
The PIC18F2420/2520/4420/4520 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for
external oscillator circuits on the OSC1 and/or OSC2
pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock fre quency from 12 5 kHz
to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also ena bled autom atically when an y of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• T wo-Spe ed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page30).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs F
while OSC1 functions as RA 7 fo r dig it a l in put a nd
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.2 INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application. This is do ne by writi ng to the OSC TUNE regi ster
(Register 2-1).
OSC/4,
When the OSCTUNE regis ter is mo di fied , the IN T O SC
frequency will begin shifting to the new frequency. The
INTRC clock will reach the new frequency within
8 clock cy cles (approximately 8 * 32 µs=256µs). The
INTOSC clock will stabilize within 1ms. Code execution conti nues during t his shift. There is no indication
that the shift has occurred.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.
2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
2.6.5 INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discus sed
in Section 2.6.5.1 “Compensating with the USART”,
Section 2.6.5.2 “Compensating with the Timers” and
Section 2.6.5.3 “Compensating with the CCP Mo dule
in Capture Mode”, but other techniques may be used.
DS39631A-page 26 Preliminary 2004 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
REGISTER 2-1: OSCTUNE: OSCILLATOR T UNING REGISTER
R/W-0 R/W-0
INTSRC PLLEN
bit 7 bit 0
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit
1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable
bit 5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
(1)
and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
— TUN4 TUN3 TUN2 TUN1 TUN0
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2.6.5.1 Compensating with the USART
An adjustment may be required when the USART
begins to generate frami ng errors or rec eive s dat a with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.
2.6.5.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillat or.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is ru nning too fast. To adjust for t his, decr ement
the OSCTUNE register.
2.6.5.3 Compensating with the CCP Module
in Capture Mode
A CCP module can use free running Timer1 (or
Timer3), cl oc ked by the internal oscillator bl ock and an
external event with a known period (i.e., AC power frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is su btra cte d fro m the tim e of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculate d
time, the internal oscillator block is runn ing t oo slow; to
compensate, increment the OSCTUNE register.
2004 Microchip Technology Inc. Preliminary DS39631A-page 27
PIC18F2420/2520/4420/4520
2.7 Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F2420/2520/
4420/4520 family includes a feature that allows the
device clock so urc e to be s w itc hed fro m t he main osci llator to an alternate low-frequency clock source.
PIC18F2420/2520/4420/4520 devices offer two alternate
clock sources. When an alternate clock source is enabled,
the various power managed operating modes are available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the Ex ternal Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.
The s econdary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F2420/2520/442 0/45 20 d ev ic es o f fe r the Timer1
oscillator as a secon dary oscilla tor . This osc illator , in all
power managed modes, is often the time base for
functions such as a real-time cloc k.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP mode oscillator circuit, loading
capacitors are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.
In addition to being a prim ary clock source, the internal
oscillator block is available as a power managed
mode clock source. T he IN TR C s ource is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F2420/2520/4420/4520
devices are shown in Figure 2-8. See Section 23.0
“Special Features of the CPU” for Configuration
register details.
FIGURE 2-8: PIC18F2420/2520/4420/4520 CLOCK DIAGRAM
PIC18F2420/2520/4420/4520
4 x PLL
OSCCON<6:4>
8 MHz
111
4 MHz
110
2 MHz
101
1 MHz
31 kHz
100
MUX
011
010
001
000
OSCTUNE<7>
500 kHz
Postscaler
250 kHz
125 kHz
1
0
HSPLL, INTOSC/PLL
OSC2
OSC1
T1OSO
T1OSI
Primary Oscillator
Sleep
Secondary Oscillator
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
Internal
Oscillator
Block
8 MHz
Source
INTRC
Source
31 kHz (INTRC)
OSCTUNE<6>
8 MHz
(INTOSC)
LP, XT, HS, RC, EC
T1OSC
Internal Oscillator
FOSC3:FOSC0
Peripherals
MUX
CPU
Clock
Control
Clock Source Option
for other Modules
WDT, PWRT, FSCM
and Two-Speed Start-up
IDLEN
OSCCON<1:0>
DS39631A-page 28 Preliminary 2004 Microchip Technology Inc.
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