MICROCHIP PIC17C7XX Technical data
PIC17C7XX
High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
Microcontroller Core Features:
• Only 58 single word instructions to learn
• All single cycle instructions (121 ns) except for
program branches and table reads/writes which
are two-cycle
• Operating speed:
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
• 8 x 8 Single-Cycle Hardware Multiplier
• Interrupt capability
• 16 level deep hardware stack
• Direct, indirect, and relative addressing modes
• Internal/external program memory execution,
Capable of addressing 64K x 16 program memory
space
Device
Program (x16) Data (x8)
Memory
PIC17C752 8K 678
PIC17C756A 16K 902
PIC17C762 8K 678
PIC17C766 16K 902
Peripheral Features:
• Up to 66 I/O pins with individual direction control
• 10-bit, multi-channel analog-to-digital converter
• High current sink/source for direct LED drive
• Four capture input pins
- Captures are 16-bit, max resolution 121 ns
• Three PWM outputs (resolution is 1- to 10-bits)
• TMR0: 16-bit timer/counter with
8-bit programmable prescaler
• TMR1: 8-bit timer/counter
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Two Universal Synchronous Asynchronous
Receiver Transmitters (USART/SCI) with Independent baud rate generators
• Synchronous Serial Port (SSP) with SPI™ and
2
I
C™ modes (including I2C master mode)
Pin Diagrams
84 LCC
VDDNC
VSSRC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RJ7
RH2
RH3
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR
/VPP
TEST
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
NC
V
SS
VDD
RH1
RD2/AD10
RD3/AD11
RH0
11
9876 54321
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3435 36 37 38 39 40 41 42 43
33
DD
AV
RF1/AN5
RF0/AN4
RH6/AN14
RH7/AN15
RC0/AD0
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
84
PIC17C76X
44
SS
NC
V
REF-
AVSS
RG1/AN2
RG0/AN3
RG2/AN1/V
RG3/AN0/VREF+
83 82 81
45
VDD
46
47
RG4/CAP3
80
7978 77
4948
RG5/PWM3
RA5/TX1/CK1
RG7/TX2/CK2
RG6/RX2/DT2
RJ6
75
76
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53525150
RJ1
RJ0
RA4/RX1/DT1
RJ5
RJ4
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
V
SS
NC
OSC2/CLKOUT
OSC1/CLKIN
V
DD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS
/SCL
RA1/T0CKI
RJ3
RJ2
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out Reset
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
CMOS Technology:
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range (3.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
- < 5 mA @ 5V, 4 MHz
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
1998 Microchip Technology Inc. DS30289A-page 1
PIC17C7XX
Pin Diagrams cont.’d
68-Pin LCC
64-Pin TQFP
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
/VPP
MCLR
TEST
NC
V
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
VDDNC
VSSRC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
987654321
10
11
12
13
14
15
16
17
18
19
SS
20
21
22
23
24
25
26
2728293031323334353637383940414243
RF1/AN5
RD2/AD10
DD
AVSS
AV
RF0/AN4
RD3/AD11
RD4/AD12
RD5/AD13
PIC17C75X
RG3/AN0/VREF+
RD6/AD14
NC
REF-
RG1/AN2
RG0/AN3
RG2/AN1/V
RD7/AD15
RC0/AD0
VDDVSS
68676665646362
SS
V
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RA5/TX1/CK1
RA4/RX1/DT1
RC6/AD6
RC7/AD7
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
V
SS
NC
OSC2/CLKOUT
OSC1/CLKIN
V
DD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS
/SCL
RA1/T0CKI
DS30289A-page 2
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR
/VPP
TEST
V
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
SS
10
11
12
13
14
15
16
171819202122232425262728293031
RF1/AN5
DD
AV
RF0/AN4
PIC17C75X
REF-
AVSS
RG1/AN2
RG2/AN1/V
RG3/AN0/VREF+
SS
V
VDD
RG0/AN3
RG4/CAP3
RG5/PWM3
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
RA5/TX1/CK1
RA4/RX1/DT1
RG7/TX2/CK2
RG6/RX2/DT2
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
V
SS
OSC2/CLKOUT
OSC1/CLKIN
DD
V
RB7/SDO
RB6/SCK
RA3/SDI/SDA
/SCL
RA2/SS
RA1/T0CKI
1998 Microchip Technology Inc.
PIN DIAGRAMS cont.’d
84-pin LCC
RH2
RH3
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
/VPP
MCLR
TEST
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
PIC17C7XX
DD
V
NC
VSSRC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RJ7
797877
4948
RJ6
75
76
53525150
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
RJ5
RJ4
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
V
SS
NC
OSC2/CLKOUT
OSC1/CLKIN
V
DD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
/SCL
RA2/SS
RA1/T0CKI
RJ3
RJ2
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
PIC17C76X
RC0/AD0
RD7/AD15
44
84
838281
45
46
80
47
RH1
RD2/AD10
RH0
11
987654321
10
12
13
14
15
16
17
18
19
20
21
NC
22
23
24
25
26
27
28
29
30
31
32
34353637383940414243
33
80-Pin QFP
RH2
RH3
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR
/VPP
TEST
V
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
RH0
RH1
80
79
1
2
3
4
5
6
7
8
9
10
11
SS
12
13
14
15
16
17
18
19
20
2122 23 24252627 2829303132
RH6/AN14
RH7/AN15
RF1/AN5
RF0/AN4
RD2/AD10
RD3/AD11
78
7776 75
RF1/AN5
RF0/AN4
DD
REF-
AVSS
AV
RG1/AN2
RG2/AN1/V
RG3/AN0/VREF+
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
PIC17C76X
DD
REF-
AVSS
AV
RG2/AN1/V
RG3/AN0/VREF+
SS
NC
V
RG0/AN3
RC0/AD0
VDDVSS
SS
V
RG1/AN2
RG0/AN3
VDD
RG4/CAP3
RG5/PWM3
RC1/AD1
RC2/AD2
RC3/AD3
6867 66657271 70697473
3334
VDD
RG4/CAP3
RG5/PWM3
RA5/TX1/CK1
RA4/RX1/DT1
RG7/TX2/CK2
RG6/RX2/DT2
RC4/AD4
RC5/AD5
RC6/AD6
6463 6261
37
3536
38
RA5/TX1/CK1
RG7/TX2/CK2
RG6/RX2/DT2
RJ1
RJ0
RC7/AD7
RJ7
RJ6
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
RJ1
RJ0
RA4/RX1/DT1
RJ5
RJ4
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
SS
V
OSC2/CLKOUT
OSC1/CLKIN
DD
V
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS
/SCL
RA1/T0CKI
RJ3
RJ2
1998 Microchip Technology Inc. DS30289A-page 3
PIC17C7XX
Table of Contents
1.0 Overview...........................................................................................................................................................5
2.0 Device Varieties................................................................................................................................................7
3.0 Architectural Overview......................................................................................................................................9
4.0 On-chip Oscillator Circuit................................................................................................................................15
5.0 Reset...............................................................................................................................................................21
6.0 Interrupts.........................................................................................................................................................31
7.0 Memory Organization......................................................................................................................................41
8.0 Table Reads and Table Writes .......................................................................................................................57
9.0 Hardware Multiplier.........................................................................................................................................65
10.0 I/O Ports..........................................................................................................................................................69
11.0 Overview of Timer Resources.........................................................................................................................93
12.0 Timer0.............................................................................................................................................................95
13.0 Timer1, Timer2, Timer3, PWMs and Captures...............................................................................................99
14.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules.........................................115
15.0 Master Synchronous Serial Port (MSSP) Module.........................................................................................131
16.0 Analog-to-Digital Converter (A/D) Module ....................................................................................................177
17.0 Special Features of the CPU ........................................................................................................................189
18.0 Instruction Set Summary...............................................................................................................................195
19.0 Development Support...................................................................................................................................231
20.0 PIC17C7XX Electrical Characteristics..........................................................................................................235
21.0 PIC17C7XX DC and AC Characteristics.......................................................................................................265
22.0 Packaging Information..................................................................................................................................277
Appendix A: Modifications..........................................................................................................................................283
Appendix B: Compatibility..........................................................................................................................................283
Appendix C: What’s New............................................................................................................................................284
Appendix D: What’s Changed....................................................................................................................................284
Appendix E: I
Appendix F: Status and Control Registers.................................................................................................................291
On-Line Support..........................................................................................................................................................321
Reader Response .......................................................................................................................................................322
PIC17C7XX Product Identification System .................................................................................................................323
2
C Overview.......................................................................................................................................285
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become kno wn to us, we will pub lish an errata sheet. The errata will specify the re vision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip .com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
erature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. Howe ver, we realize that we ma y ha v e missed a few things. If y ou find an y inf ormation that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
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We appreciate your assistance in making this a better document.
DS30289A-page 4
1998 Microchip Technology Inc.
PIC17C7XX
1.0 OVERVIEW
This data sheet covers the PIC17C7XX group of the
PIC17CXXX family of microcontrollers. The following
devices are discussed in this data sheet:
• PIC17C752
• PIC17C756A
• PIC17C762
• PIC17C766
The PIC17C7XX devices are 68/84-pin,
EPROM-based members of the versatile PIC17CXXX
family of low-cost, high-performance, CMOS,
fully-static, 8-bit microcontrollers.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC17CXXX has enhanced
core features, 16-lev el deep stack, and multiple internal
and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a
16-bit wide instruction word with a separate 8-bit wide
data path. The two stage instruction pipeline allows all
instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 58
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance. For mathematical intensive applications
all devices have a single cycle 8 x 8 Hardware Multiplier.
PIC17CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC17C7XX devices have up to 902 b ytes of RAM and
66
pins. In addition, the PIC17C7XX adds several
I/O
peripheral features useful in many high performance
applications including:
• Four timer/counters
• Four capture inputs
• Three PWM outputs
• Two independent Universal Synchronous Asynchronous Receiver Transmitters (USARTs)
• An A/D converter (multi-channel, 10-bit resolution)
• A Synchronous Serial Port
(SPI and I
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LF oscillator is for low frequency crystals and minimizes power
consumption, XT is a standard crystal, and the EC is for
external clock input.
The SLEEP (power-down) mode offers additional
power saving. Wake-up from SLEEP can occur
through several external and internal interrupts and
device resets.
2
C w/ Master mode)
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software malfunction.
There are four configuration options for the device
operational mode:
• Microprocessor
• Microcontroller
• Extended microcontroller
• Protected microcontroller
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
The device also has Brown-out Reset circuitry. This
allows a device reset to occur if the device V
below the Brown-out voltage trip point (BVDD). The
chip will remain in Brown-out Reset until VDD rises
above BV
A UV-erasable CERQUAD-packaged version (compatible with PLCC) is ideal for code dev elopment while the
cost-effective One-Time Programmable (OTP) version
is suitable for production in any volume.
The PIC17C7XX fits perfectly in applications that
require extremely fast execution of complex software
programs. These include applications ranging from
precise motor control and industrial process control to
automotive, instrumentation, and telecom applications.
The EPROM technology makes customization of application programs (with unique security codes, combinations, model numbers, parameter storage, etc.) f ast and
convenient. Small footprint package options (including
die sales) make the PIC17C7XX ideal for applications
with space limitations that require high performance.
High speed execution, powerful peripheral features,
flexible I/O, and low power consumption all at low cost
make the PIC17C7XX ideal for a wide range of embedded control applications.
1.1 F
The PIC17CXXX family of microcontrollers have architectural enhancements over the PIC16C5X and
PIC16CXX families. These enhancements allow the
device to be more efficient in software and hardware
requirements. Ref er to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXXX devices (Appendix B).
1.2 De
The PIC17CXXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler, and
fuzzy logic support tools. For additional information
see Section 19.0.
DD
.
amily and Upward Compatibility
velopment Support
DD
falls
1998 Microchip Technology Inc. DS30289A-page 5
PIC17C7XX
TABLE 1-1: PIC17CXXX FAMILY OF DEVICES
Features PIC17C42A PIC17C43 PIC17C44 PIC17C752 PIC17C756A PIC17C762 PIC17C766
Maximum Frequency
of Operation
Operating Voltage Range 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V
Program
Memory ( x16)
Data Memory (bytes) 232 454 454 678 902 678 902
Hardware Multiplier (8 x 8) Yes Yes Yes Yes Yes Ye s Yes
Timer0
(16-bit + 8-bit postscaler)
Timer1 (8-bit) Yes Yes Yes Yes Yes Ye s Yes
Timer2 (8-bit) Yes Yes Yes Yes Yes Ye s Yes
Timer3 (16-bit) Yes Yes Yes Yes Yes Ye s Yes
Capture inputs (16-bit) 2 2 24444
PWM outputs (up to 10-bit) 2 2 23333
USART/SCI 1 1 12222
A/D channels (10-bit) — — —12121616
SSP (SPI/I
mode)
Power-on Reset
Watchdog Timer Yes Yes Yes Yes Yes Ye s Yes
External Interrupts Yes Yes Yes Yes Yes Yes Yes
Interrupt Sources 11 11 11 18 18 18 18
Code Protect Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset — — — Yes Yes Yes Yes
In-circuit Serial Program-
ming
I/O Pins 33 33 33 50 50 66 66
I/O High Cur-
rent Capability
Package Types
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
(EPROM) 2K 4K 8K 8K 16K 8K 16K
(ROM) — — — — — — —
2
C w/Master
Source 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA
Sink
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
Yes Yes Yes Yes Yes Ye s Yes
— — — Yes Yes Yes Yes
Yes Yes Yes Yes Yes Ye s Yes
— — — Yes Yes Yes Yes
(1)
25 mA
40-pin DIP
44-pin PLCC
44-pin
MQFP
44-pin TQFP
(1)
25 mA
40-pin DIP
44-pin PLCC
44-pin
MQFP
44-pin TQFP
(1)
25 mA
40-pin DIP
44-pin PLCC
44-pin
MQFP
44-pin TQFP
(1)
25 mA
64-pin DIP
68-pin LCC
68-pin TQFP
(1)
25 mA
64-pin DIP
68-pin LCC
68-pin TQFP
(1)
25 mA
80-pin QFP
84-pin
PLCC
80-pin QFP
25 mA
84-pin
PLCC
(1)
DS30289A-page 6
1998 Microchip Technology Inc.
PIC17C7XX
2.0 DEVICE V ARIETIES
Each device has a variety of frequency ranges and
packaging options. Depending on application and production requirements, the proper device option can be
selected using the information in the PIC17C7XX Product Selection System section at the end of this data
sheet. When placing orders, please use the
“PIC17C7XX Product Identification System” at the back
of this data sheet to specify the correct part number.
When discussing the functionality of the device, memory technology and voltage range does not matter.
There are three memory type options. These are specified in the middle characters of the part number.
1.C, as in PIC17C756A. These devices have
EPROM type memory.
2.CR, as in PIC17CR756A. These devices have
ROM type memory.
3.F, as in PIC17F756A. These devices have Flash
type memory.
All these devices operate over the standard voltage
range. Devices are also offered which operate over an
extended voltage range (and reduced frequency
range). Table 2-1 shows all possible memory types
and voltage range designators for a particular device.
These designators are in
TABLE 2-1: DEVICE MEMORY
Memory Type
EPROM PIC17CXXX PIC17LCXXX
ROM
Flash
Note:
Not all memory technologies are available
for a particular device.
bold
typeface.
VARIETIES
Voltage Range
Standard Extended
PIC17CRXXX PIC17
PIC17FXXX PIC17LFXXX
LCR
XXX
2.1 UV Erasab
The UV erasable version, offered in CERQUAD package, is optimal for prototype dev elopment and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes. Third
party programmers also are available; ref er to the
Party Guide
for a list of sources.
2.2 One-Time-Pr
le Devices
Third
ogrammable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must be programmed.
2.3 Quic
k-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP de vices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serializ
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
ed Quick-Turnaround
Production (SQTP
SM
vices
) De
1998 Microchip Technology Inc. DS30289A-page 7
PIC17C7XX
2.5 Read Onl
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
ROM devices do not allow serialization information in
the program memory space.
For information on submitting ROM code, please contact your regional sales office.
Note:
2.6 Flash Memor
These devices are electrically erasable and, therefore,
can be offered in the low cost plastic package. Being
electrically erasable, these devices can be erased and
reprogrammed in-circuit. These devices are the same
for prototype development, pilot programs, as well as
production.
Note:
y Memory (ROM) Devices
Presently, NO ROM versions of the
PIC17C7XX devices are available.
y Devices
Presently, NO Flash versions of the
PIC17C7XX devices are available.
DS30289A-page 8
1998 Microchip Technology Inc.
PIC17C7XX
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC17CXXX can be attributed to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC17CXXX uses a modified Harvard architecture.
This architecture has the program and data accessed
from separate memories. So , the device has a progr am
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word.
PIC17CXXX opcodes are 16-bits wide, enabling single
word instructions. The full 16-bit wide program memory bus fetches a 16-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions execute in a
single cycle (121 ns @ 33 MHz), except for program
branches and two special instructions that transfer data
between program and data memory.
The PIC17CXXX can address up to 64K x 16 of program memory space.
The
PIC17C752
EPROM program memory on-chip.
The
PIC17C756A
EPROM program memory on-chip.
A simplified block diagram is shown in Figure 3-1. The
descriptions of the device pins are listed in Table 3-1.
Program execution can be internal only (microcontrol-
ler or protected microcontroller mode), external only
(microprocessor mode) or both (extended microcontroller mode). Extended microcontroller mode does not
allow code protection.
The PIC17CXXX can directly or indirectly address its
register files or data memory. All special function registers, including the Program Counter (PC) and Working Register (WREG), are mapped in data memory.
The PIC17CXXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC17CXXX simple yet efficient. In addition, the learning curve is
reduced significantly.
One of the PIC17CXXX family architectural enhancements from the PIC16CXX family allows two file registers to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register. Thus
increasing performance and decreasing program
memory usage.
The PIC17CXXX devices contain an 8-bit ALU and
working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any
register file.
and
and
PIC17C762
PIC17C766
integrate 8K x 16 of
integrate 16K x 16
The WREG register is an 8-bit working register used for
ALU operations.
All PIC17CXXX devices have an 8 x 8 hardware multiplier. This multiplier generates a 16-bit result in a single
cycle.
The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
Zero (Z) and overflow (O V) bits in the ALUSTA register.
The C and DC bits operate as a borro
out bit, respectively, in subtraction. See the
SUBWF
instructions for examples.
w and digit borrow
SUBLW
and
Signed arithmetic is comprised of a magnitude and a
sign bit. The overflow bit indicates if the magnitude
overflows and causes the sign bit to change state. That
is if the result of 8-bit signed operations is greater than
127 (7Fh) or less than -128 (80h).
Signed math can have greater than 7-bit values (magnitude), if more than one byte is used. The overflow bit
only operates on bit6 (MSb of magnitude) and bit7 (sign
bit) of each byte value in the ALU. That is, the overflow
bit is not useful if trying to implement signed math
where the magnitude, for example, is 11-bits.
If the signed math values are greater than 7-bits (such
as 15-, 24- or 31-bit), the algorithm must ensure that
the low order bytes of the signed value ignore the ov erflow status bit.
Example 3-1 shows an two cases of doing signed arith-
metic. The Carry (C) bit and the Overflow (OV) bit are
the most important status bits for signed math operations.
EXAMPLE 3-1: 8-BIT MATH ADDITION
Hex Value Signed Values Unsigned Values
FFh
01h
+
= 00h
C bit = 1
OV bit = 0
DC bit = 1
Z bit = 1
Hex Value Signed Values Unsigned Values
7Fh
+ 01h
= 80h
C bit = 0
OV bit = 1
DC bit = 1
Z bit = 0
-1
+ 1
= 0 (FEh)
C bit = 1
OV bit = 0
DC bit = 1
Z bit = 1
127
+ 1
= 128 → 00h
C bit = 0
OV bit = 1
DC bit = 1
Z bit = 0
255
+ 1
= 256 → 00h
C bit = 1
OV bit = 0
DC bit = 1
Z bit = 1
127
+ 1
= 128
C bit = 0
OV bit = 1
DC bit = 1
Z bit = 0
1998 Microchip Technology Inc. DS30289A-page 9
PIC17C7XX
FIGURE 3-1: PIC17C752/756A BLOCK DIAGRAM
PORTA
RA0/INT
RA1/T0CKI
RA2/SS
/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
RB7/SDO
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
PORTB
PORTC
PORTD
PORTE
PORTF
8 x 8 mult
PRODH PRODL
8
BSR <7:4>
Address
Buffer
Data RAM
17C756A
902 x 8
17C752
678 x 8
Data Latch
BSR
Timer0
WREG<8>
IR <7:0>
12
RAM
Literal
PCLATH<8>
PCH
Timer2 PWM1
BITOP
ALU
Shifter
16
Instruction
Decode
Control Outputs
Table
Latch <16>
PCL
16
USART1
Table Pointer<16>
Data Bus<8>
IR<16>
Read/write
Decode
for
Registers
Mapped
in Data
Space
Stack
16 x 16
16
Chip_reset
IR Latch <16>
8
ROM Latch <16>
PWM3
Q1, Q2,
Q3, Q4
& Other
Control
Signals
16
Capture2
8
Data Latch
Program
Memory
(EPROM)
17C756A
16K x 16
17C752
8K x 16
Address
Latch
16
10-bit
A/D
Clock
Generator
Power-on
Reset
Brown-out
Reset
Watchdog
Timer
Test Mode
Select
F1
F9
8
VDD, VSS
MCLR, VPP
Decode
AD<15:0>
PORTC,
PORTD
System Bus Interface
ALE,
WR
OE
PORTE
SSP
OSC1,
OSC2
Test
,
,
RG0/AN3
RG1/AN2
RG2/AN1/V
RG3/AN0/V
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
REF-
REF+
PORTG
Timer1 Timer3
USART2
PWM2
Capture1 Capture3
Capture4
Interrupt
Module
DS30289A-page 10 1998 Microchip Technology Inc.
FIGURE 3-2: PIC17C762/766 BLOCK DIAGRAM
PORTA
RA0/INT
RA1/T0CKI
/SCL
RA2/SS
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
RB7/SDO
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
RG0/AN3
RG1/AN2
RG2/AN1/V
RG3/AN0/V
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
REF-
REF+
RH0
RH1
RH2
RH3
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
8 x 8 mult
PRODH PRODL
BSR <7:4>
8
IR <7:0>
12
RAM
Address
Buffer
Data RAM
17C766
902 x 8
and
17C762
678 x 8
Data Latch
BSR
PCLATH<8>
Timer0
Timer1 Timer3
WREG<8>
Literal
PCH
Timer2 PWM1
BITOP
ALU
Shifter
16
Instruction
Decode
Control Outputs
Table
Latch <16>
PCL
16
USART1
USART2
IR<16>
Read/write
Decode
for
Registers
Mapped
in Data
Space
Table Pointer<16>
Stack
16 x 16
16
Data Bus<8>
PWM2
IR Latch <16>
8
ROM Latch <16>
PWM3
Capture1
PIC17C7XX
Clock
Test Mode
Brown-out
8
FSR0
FSR1
Data Latch
Program
Memory
(EPROM)
17C766
16K x 16,
and
17C762
8K x 16
Address
Latch
16
PORTJ
Generator
Power-on
Reset
Watchdog
Timer
Select
Reset
8
System Bus Interface
Q1, Q2,
Q3, Q4
Chip_reset
& Other
Control
Signals
16
OSC1,
OSC2
VDD, VSS
MCLR, VPP
Test
AVDD, AVSS
Decode
AD<15:0>
PORTC,
PORTD
ALE,
WR
,
OE
,
PORTE
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
Interrupt
Module
SSP
10-bit
A/D
Capture2
Capture3
Capture4
1998 Microchip Technology Inc. DS30289A-page 11
PIC17C7XX
TABLE 3-1: PINOUT DESCRIPTIONS
PIC17C75X PIC17C76X
Name
OSC1/CLKIN 47 50 39 62 49 I ST Oscillator input in crystal/resonator or RC oscillator
OSC2/CLKOUT 48 51 40 63 50 O — Oscillator output. Connects to crystal or resonator in
MCLR/VPP 15 16 7 20 9 I/P ST Master clear (reset) input or Programming Voltage
RA0/INT 56 60 48 72 58 I ST RA0 can also be selected as an external inter-
RA1/T0CKI 41 44 33 56 43 I ST RA1 can also be selected as an external inter-
RA2/SS/SCL 42 45 34 57 44
RA3/SDI/SDA 43 46 35 58 45
RA4/RX1/DT1 40 43 32 51 38
RA5/TX1/CK1 39 42 31 50 37
RB0/CAP1 55 59 47 71 57 I/O ST RB0 can also be the Capture1 input pin.
RB1/CAP2 54 58 46 70 56 I/O ST RB1 can also be the Capture2 input pin.
RB2/PWM1 50 54 42 66 52 I/O ST RB2 can also be the PWM1 output pin.
RB3/PWM2 53 57 45 69 55 I/O ST RB3 can also be the PWM2 output pin.
RB4/TCLK12 52 56 44 68 54 I/O ST RB4 can also be the external clock input to
RB5/TCLK3 51 55 43 67 53 I/O ST RB5 can also be the external clock input to
RB6/SCK 44 47 36 59 46 I/O ST RB6 can also be used as the master/slave clock
RB7/SDO 45 48 37 60 47 I/O ST RB7 can also be used as the data output for the
Legend: I = Input only; O = Output only; I/O = Input/Output;
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
DIP
PLCC
TQFP
PLCC
QFP
I/O/P
No.
No.
No.
No.
No.
P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input.
Buffer
Type
Type
mode. External clock input in external clock mode.
crystal oscillator mode. In RC oscillator or external
clock modes OSC2 pin outputs CLKOUT which has
one fourth the frequency (F
denotes the instruction cycle rate.
(VPP) input. This is the active low reset input to the
device.
PORTA pins have individual differentiations that are
listed in the following descriptions:
rupt input. Interrupt can be configured to be on
positive or negative edge. Input only pin.
rupt input, and the interrupt can be configured
to be on positive or negative edge. RA1 can
also be selected to be the clock input to the
(2)
ST RA2 can also be used as the slave select input
I/O
(2)
ST RA3 can also be used as the data input for the
I/O
(1)
ST RA4 can also be selected as the USART1 (SCI)
I/O
(1)
ST RA5 can also be selected as the USART1 (SCI)
I/O
Timer0 timer/counter. Input only pin.
for the SPI or the clock input for the I
High voltage, high current, open drain port pin.
SPI or the data for the I
High voltage, high current, open drain port pin.
Asynchronous Receive or USART1 (SCI)
Synchronous Data.
Output available from USART only.
Asynchronous Transmit or USART1 (SCI)
Synchronous Clock.
Output available from USART only.
PORTB is a bi-directional I/O Port with software
configurable weak pull-ups.
Timer1 and Timer2.
Timer3.
for the SPI.
SPI.
Description
OSC/4) of OSC1 and
2
C bus.
2
C bus.
DS30289A-page 12 1998 Microchip Technology Inc.
PIC17C7XX
TABLE 3-1: PINOUT DESCRIPTIONS
PIC17C75X PIC17C76X
Name
RC0/AD0 2 3 58 3 72 I/O TTL This is also the least significant byte (LSB) of
RC1/AD1 63 67 55 83 69 I/O TTL
RC2/AD2 62 66 54 82 68 I/O TTL
RC3/AD3 61 65 53 81 67 I/O TTL
RC4/AD4 60 64 52 80 66 I/O TTL
RC5/AD5 58 63 51 79 65 I/O TTL
RC6/AD6 58 62 50 78 64 I/O TTL
RC7/AD7 57 61 49 77 63 I/O TTL
RD0/AD8 10 11 2 15 4 I/O TTL This is also the most significant byte (MSB) of
RD1/AD9 9 10 1 14 3 I/O TTL
RD2/AD10 8 9 64 9 78 I/O TTL
RD3/AD11 7 8 63 8 77 I/O TTL
RD4/AD12 6 7 62 7 76 I/O TTL
RD5/AD13 5 6 61 6 75 I/O TTL
RD6/AD14 4 5 60 5 74 I/O TTL
RD7/AD15 3 4 59 4 73 I/O TTL
RE0/ALE 11 12 3 16 5 I/O TTL In microprocessor mode or extended microcon-
RE1/OE 12 13 4 17 6 I/O TTL In microprocessor or extended microcontroller
RE2/WR
RE3/CAP4 14 15 6 19 8 I/O ST RE3 can also be the Capture4 input pin.
RF0/AN4 26 28 18 36 24 I/O ST RF0 can also be analog input 4.
RF1/AN5 25 27 17 35 23 I/O ST RF1 can also be analog input 5.
RF2/AN6 24 26 16 30 18 I/O ST RF2 can also be analog input 6.
RF3/AN7 23 25 15 29 17 I/O ST RF3 can also be analog input 7.
RF4/AN8 22 24 14 28 16 I/O ST RF4 can also be analog input 8.
RF5/AN9 21 23 13 27 15 I/O ST RF5 can also be analog input 9.
RF6/AN10 20 22 12 26 14 I/O ST RF6 can also be analog input 10.
RF7/AN11 19 21 11 25 13 I/O ST RF7 can also be analog input 11.
Legend: I = Input only; O = Output only; I/O = Input/Output;
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
DIP
PLCC
TQFP
PLCC
QFP
I/O/P
No.
No.
No.
No.
No.
13 14 5 18 7 I/O TTL In microprocessor or extended microcontroller
P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input.
Type
Buffer
Type
PORTC is a bi-directional I/O Port.
the 16-bit wide system bus in microprocessor
mode or extended microcontroller mode. In
multiplexed system bus configuration, these
pins are address output as well as data input or
output.
PORTD is a bi-directional I/O Port.
the 16-bit system bus in microprocessor mode
or extended microcontroller mode. In multiplexed system bus configuration these pins are
address output as well as data input or output.
PORTE is a bi-directional I/O Port.
troller mode, RE0 is the Address Latch Enable
(ALE) output. Address should be latched on the
falling edge of ALE output.
mode, RE1 is the Output Enable (OE) control
output (active low).
mode, RE2 is the Write Enable (WR) control
output (active low).
PORTF is a bi-directional I/O Port.
Description
1998 Microchip Technology Inc. DS30289A-page 13
PIC17C7XX
TABLE 3-1: PINOUT DESCRIPTIONS
PIC17C75X PIC17C76X
Name
RG0/AN3 32 34 24 42 30 I/O ST RG0 can also be analog input 3.
RG1/AN2 31 33 23 41 29 I/O ST RG1 can also be analog input 2.
RG2/AN1/VREF- 30 32 22 40 28 I/O ST RG2 can also be analog input 1, or
RG3/AN0/VREF+ 29 31 21 39 27 I/O ST RG3 can also be analog input 0, or
RG4/CAP3 35 38 27 46 33 I/O ST RG4 can also be the Capture3 input pin.
RG5/PWM3 36 39 28 47 34 I/O ST RG5 can also be the PWM3 output pin.
RG6/RX2/DT2 38 41 30 49 36 I/O ST RG6 can also be selected as the USART2 (SCI)
RG7/TX2/CK2 37 40 29 48 35 I/O ST RG7 can also be selected as the USART2 (SCI)
RH0 — — — 10 79 I/O ST
RH1 — — — 11 80 I/O ST
RH2 — — — 12 1 I/O ST
RH3 — — — 13 2 I/O ST
RH4/AN12 — — — 31 19 I/O ST RH4 can also be analog input 12.
RH5/AN13 — — — 32 20 I/O ST RH5 can also be analog input 13.
RH6/AN14 — — — 33 21 I/O ST RH6 can also be analog input 14.
RH7/AN15 — — — 34 22 I/O ST RH7 can also be analog input 15.
RJ0 — — — 52 39 I/O ST
RJ1 — — — 53 40 I/O ST
RJ2 — — — 54 41 I/O ST
RJ3 — — — 55 42 I/O ST
RJ4 — — — 73 59 I/O ST
RJ5 — — — 74 60 I/O ST
RJ6 — — — 75 61 I/O ST
RJ7 — — — 76 62 I/O ST
TEST 16 17 8 21 10 I ST Test mode selection control input. Always tie to V
VSS 17, 33,
VDD 1, 18,
AVSS 28 30 20 38 26 P Ground reference for A/D converter.
AVDD 27 29 19 37 25 P Positive supply for A/D converter.
NC — 1, 18,
Legend: I = Input only; O = Output only; I/O = Input/Output;
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
DIP
PLCC
TQFP
PLCC
QFP
I/O/P
No.
No.
No.
No.
No.
19, 36,
9, 25,
23, 44,
49, 64
53, 68
41, 56
2, 20,
37, 49,
35, 52
10, 26,
38, 57
— 1, 22,
34, 46
P = Power; — = Not Used; TTL = TTL input; ST = Schmitt Trigger input.
65, 84
24, 45,
61, 2
43, 64
11, 31,
51, 70
12, 32,
48, 71
— No Connect. Leave these pins unconnected.
Buffer
Type
Type
PORTG is a bi-directional I/O Port.
the ground reference voltage
the positive reference voltage
Asynchronous Receive or USART2 (SCI)
Synchronous Data.
Asynchronous Transmit or USART2 (SCI)
Synchronous Clock.
PORTH is a bi-directional I/O Port. PORTH is only
available on the PIC17C76X devices
PORTJ is a bi-directional I/O Port. PORTJ is only
available on the PIC17C76X devices.
P Ground reference for logic and I/O pins.
P Positive supply for logic and I/O pins.
for normal operation.
This pin MUST be at the same potential as VSS.
This pin MUST be at the same potential as VDD.
Description
SS
DS30289A-page 14 1998 Microchip Technology Inc.
PIC17C7XX
4.0 ON-CHIP OSCILLATOR CIRCUIT
The internal oscillator circuit is used to generate the
device clock. Four device clock periods generate an
internal instruction clock (T
There are four modes that the oscillator can operate in.
They are selected by the device configuration bits during device programming. These modes are:
• LF Low Frequency (F
• XT Standard Crystal/Resonator Frequency
(2 MHz <= F
• EC External Clock Input
(Default oscillator configuration)
• RC External Resistor/Capacitor
(F
OSC <= 4 MHz)
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 96 ms (nominal) on POR and BOR. The PWR T is designed to keep
the part in RESET while the power supply stabilizes.
With these two timers on-chip, most applications need
no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interrupt.
Several oscillator options are made available to allow
the part to better fit the application. The RC oscillator
option saves system cost while the LF crystal option
saves power. Configuration bits are used to select various options.
4.1 Oscillator Configurations
4.1.1 OSCILLATOR TYPES
The PIC17CXXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF Low Power Crystal
• XT Crystal/Resonator
• EC External Clock Input
• RC Resistor/Capacitor
The main difference between the LF and XT modes is
the gain of the internal inverter of the oscillator circuit
which allows the different frequency ranges.
For more details on the device configuration bits, see
Section 17.0.
CY).
OSC <= 2 MHz)
OSC <= 33 MHz)
4.1.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT or LF modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 4-2). The
PIC17CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications.
For frequencies above 20 MHz, it is common for the
crystal to be an overtone mode crystal. Use of overtone mode crystals require a tank circuit to attenuate
the gain at the fundamental frequency. Figure 4-3
shows an example circuit.
4.1.2.1 OSCILLATOR / RESONATOR START-UP
As the device voltage increases from Vss, the oscillator
will start its oscillations. The time required f or the oscillator to start oscillating depends on many factors.
These include:
• Crystal / resonator frequency
• Capacitor values used (C1 and C2)
• Device V
• System temperature
• Series resistor value (and type) if used
• Oscillator mode selection of device (which selects
Figure 4-1 shows an example of a typical oscillator/
resonator start-up. The peak-to-peak voltage of the
oscillator waveform can be quite low (less than 50% of
device V
(refer to parameter #D033 and parameter #D043 in the
electrical specification section).
DD rise time.
the gain of the internal oscillator inverter)
DD) when the waveform is centered at VDD/2
FIGURE 4-1: OSCILLATOR / RESONATOR
START-UP
CHARACTERISTICS
VDD
Crystal Start-up Time
Time
1998 Microchip Technology Inc. DS30289A-page 15
PIC17C7XX
FIGURE 4-2: CRYSTAL OR CERAMIC
RESONATOR OPERATION (XT
OR LF OSC CONFIGURATION)
OSC1
C1
XTAL
OSC2
Note1
C2
PIC17CXXX
See Table 4-1 and Table 4-2 for recommended values of
C1 and C2.
SLEEP
RF
To internal
logic
Note 1: A series resistor (Rs) may be required for
AT strip cut crystals.
TABLE 4-1: CAPACITOR SELECTION
FOR CERAMIC
RESONATORS
Oscillator
Type
Resonator
Frequency
LF 455 kHz
2.0 MHz
XT 4.0 MHz
8.0 MHz
16.0 MHz
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
Note 1: These values include all board capacitances
on this pin. Actual capacitor value depends
on board capacitance
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
Resonators used did not have built-in capacitors.
Capacitor Range
(1)
C1 = C2
15 - 68 pF
10 - 33 pF
22 - 68 pF
33 - 100 pF
33 - 100 pF
FIGURE 4-3: CRYSTAL OPERATION,
OVERTONE CRYSTALS (XT
OSC CONFIGURATION)
C1
C2
C3
0.1 µF
To filter the fundamental frequency
L*C2
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
C3 handles current during charging of tank circuit.
OSC1
SLEEP
OSC2
PIC17CXXX
1
2
=
(2πf)
TAB LE 4-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc
Type
LF 32 kHz
Freq
(1)
1 MHz
2 MHz
XT 2 MHz
4 MHz
(2)
8 MHz
16 MHz
25 MHz
(3)
32 MHz
Higher capacitance increases the stability of the oscillator
but also increases the start-up time and the oscillator current. These values are for design guidance only. RS may be
required in XT mode to avoid overdriving the crystals with
low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal manufacturer for appropriate values for external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
2: R
S of 330Ω is required for a capacitor com-
bination of 15/15 pF.
3: These v alues include all board capacitances
on this pin. Actual capacitor value depends
on board capacitance
Crystals Used:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
1.0 MHz ECS-10-13-1 ± 50 PPM
2.0 MHz ECS-20-20-1 ± 50 PPM
4.0 MHz ECS-40-20-1 ± 50 PPM
8.0 MHz ECS ECS-80-S-4
ECS-80-18-1
16.0 MHz ECS-160-20-1 TBD
25 MHz CTS CTS25M ± 50 PPM
32 MHz CRYSTEK HF-2 ± 50 PPM
(3)
C1
100-150 pF
10-33 pF
10-33 pF
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10 pF
(3)
C2
100-150 pF
10-33 pF
10-33 pF
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10 pF
± 50 PPM
DS30289A-page 16 1998 Microchip Technology Inc.
PIC17C7XX
4.1.3 EXTERNAL CLOCK OSCILLATOR
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the
OSC1/CLKIN pin is hi-impedance and the
OSC2/CLKOUT pin is the CLKOUT output (4 T
OSC).
FIGURE 4-4: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
CLKOUT
(F
OSC/4)
OSC1
PIC17CXXX
OSC2
4.1.4 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 4-5 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 4-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
10kΩ
+5V
10 kΩ
4.7 kΩ
74AS04
XTAL
74AS04
10 kΩ
To Other
Devices
PIC17CXXX
OSC1
20 pF
20 pF
Figure 4-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 4-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
74AS04
Devices
PIC17CXXX
OSC1
330 Ω
74AS04
1998 Microchip Technology Inc. DS30289A-page 17
330 Ω
74AS04
0.1 µF
XTAL
PIC17C7XX
4.1.5 RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, oscillator frequency
will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead
frame capacitance between package types will also
affect oscillation frequency, especially for low Cext values. The user also needs to tak e into account v ariation
due to tolerance of external R and C components used.
Figure 4-7 shows how the R/C combination is con-
nected to the PIC17CXXX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values (e.g.
1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package
lead frame capacitance.
See Section 21.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation
will affect RC frequency more for large R) and for
smaller C (since variation of input capacitance will
affect RC frequency more).
See Section 21.0 for variation of oscillator frequency
due to V
DD for given Rext/Cext values as well as fre-
quency variation due to operating temperature for given
R, C, and V
DD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 4-8 for
waveform).
FIGURE 4-7: RC OSCILLATOR MODE
VDD
Rext
OSC1
PIC17CXXX
Internal
clock
4.1.5.1 RC START-UP
As the device voltage increases, the RC will immedi-
ately start its oscillations once the pin voltage levels
meet the input threshold specifications (parameter
#D032 and parameter #D042 in the electrical specifica-
tion section). The time required for the RC to start
oscillating depends on many factors. These include:
• Resistor value used
• Capacitor value used
• Device V
DD rise time
• System temperature
Cext
V
SS
DS30289A-page 18 1998 Microchip Technology Inc.
Fosc/4
OSC2/CLKOUT
PIC17C7XX
4.2 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
FIGURE 4-8: CLOCK/INSTRUCTION CYCLE
OSC1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
Q2 Q3 Q4
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q2 Q3 Q4
Q1
Execute INST (PC) Fetch INST (PC+2)
4.3 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and e xecute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 4-1).
A fetch cycle begins with the program counter incrementing in Q1.
In the execution cycle, the f etched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during
Q2 (operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Q1
Internal
phase
clock
Execute INST (PC+1)
EXAMPLE 4-1: INSTRUCTION PIPELINE FLOW
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1998 Microchip Technology Inc. DS30289A-page 19
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC17C7XX
NOTES:
DS30289A-page 20 1998 Microchip Technology Inc.
PIC17C7XX
5.0 RESET
The PIC17CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR
Reset
• WDT Reset
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state”. The T
in different reset situations as indicated in Table 5-3.
These bits, in conjunction with the POR
O and PD bits are set or cleared differently
and BOR bits,
When the device enters the "reset state" the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impendance inputs. The reset state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
Note: While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE
pins as high outputs.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 5-1.
are used in software to determine the nature of the
reset. See Table 5-4 for a full description of the reset
states of all registers.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR
Module
Brown-out
Reset
and RE2/WR
WDT
Module
V
DD rise
detect
VDD
OST/PWRT
OSC1
1998 Microchip Technology Inc. DS30289A-page 21
On-chip
RC OSC†
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
WDT
Time_Out
Reset
Power_On_Reset
OST
10-bit Ripple counter
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
S
R
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
Chip_Reset
Q
PIC17C7XX
5.1 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST), and Brown-out Reset
(BOR)
5.1.1 POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in reset
until V
DD is above the trip point (in the range of 1.4V -
2.3V). The devices produce an internal reset for both
rising and falling V
just tie the MCLR/
to V
DD. This will eliminate external RC components
DD. To take advantage of the POR,
VPP pin directly (or through a resistor)
usually needed to create Power-on Reset. A minimum
rise time for V
DD is required. See Electrical Specifica-
tions for details.
Figure 5-2 and Figure 5-3 show two possible POR cir-
cuits.
FIGURE 5-2: USING ON-CHIP POR
VDD
VDD
MCLR
PIC17CXXX
FIGURE 5-3: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
DD POWER-UP)
V
V
DD
VDD
D
R
R1
MCLR
C
PIC17CXXX
5.1.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the internal POR signal if V
tied, or after the first rising edge of MCLR
DD and MCLR are
(detected
high). The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as the
PWRT is active. In most cases the PWRT delay allows
V
DD to rise to an acceptable level.
The power-up time delay will vary from chip to chip and
DD and temperature. See DC parameters for
with V
details.
5.1.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024T
OSC) delay whenever the PWRT
is invoked or a wak e-up from SLEEP event occurs in XT
or LF mode. The PWRT and OST operate in parallel.
The OST counts the oscillator pulses on the
OSC1/CLKIN pin. The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds. This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of the time-out is a function of the crystal/resonator frequency.
Figure 5-4 shows the operation of the OST circuit. In
this figure the oscillator is of such a low frequency that
although enabled simultaneously, the OST does not
time-out until after the Power-up Timer time-out.
FIGURE 5-4: OSCILLATOR START-UP
TIME (LOW FREQ)
POR or BOR Trip Point
VDD
MCLR
OSC2
OSC1
Note 1: An external Power-on Reset circuit is
required only if V
DD power-up time is too
OST TIME_OUT
T
T
OST
slow. The diode D helps discharge the
capacitor quickly when V
down.
2: R < 40 kΩ is recommended to ensure
that the voltage drop across R does not
exceed 0.2V (max. leakage current spec.
on the MCLR/
VPP pin is 5 µA). A larger
voltage drop will degrade V
MCLR/
VPP pin.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR
tor C in the event of MCLR/
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
DS30289A-page 22 1998 Microchip Technology Inc.
DD powers
IH level on the
from external capaci-
VPP pin break-
PWRT TIME_OUT
TPWRT
INTERNAL RESET
This figure shows in greater detail the timings
involved with the oscillator start-up timer. In this
example the low frequency crystal start-up time is
larger than power-up time (T
PWRT).
Tosc1 = time for the crystal oscillator to react to an
oscillation level detectable by the Oscillator
Start-up Timer (OST).
TOST = 1024TOSC.
PIC17C7XX
5.1.4 TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR
is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resonators. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/
VPP pin must be
held low until the voltage is within the device specification. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR
.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization condi-
tions for all the registers.
TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
XT, LF Greater of: 96 ms or 1024TOSC 1024TOSC —
EC, RC Greater of: 96 ms or 1024T
POR, BOR Wake up from
SLEEP
OSC ——
MCLR Reset
TABLE 5-2: STATUS BITS AND THEIR SIGNIFICANCE
BOR
(1)
TO PD
Event
Power-on Reset
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wak e-up during SLEEP
MCLR Reset during normal operation
Brown-out Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
CLRWDT instruction executed
POR
0011
1110
1101
1100
1111
1011
000x
00x0
xx11
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
TAB LE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUST A REGISTER
Event PCH:PCL CPUSTA
(4)
Power-on Reset 0000h --11 1100 Ye s
Brown-out Reset 0000h --11 1110 Ye s
Reset during normal operation 0000h --11 1111 No
MCLR
Reset during SLEEP 0000h --11 1011
MCLR
WDT Reset during normal operation 0000h --11 0111 No
WDT Wake-up during SLEEP
(3)
0000h --11 0011
Interrupt wake-up from SLEEP GLINTD is set PC + 1 --11 1011
GLINTD is clear
PC + 1
(1)
--10 1011
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active (on wake-up) when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
mid-range devices.
4: When BODEN is enabled, else the BOR
status bit is unknown.
OST Active
(2)
Yes
(2)
Yes
(2)
Yes
(2)
Yes
1998 Microchip Technology Inc. DS30289A-page 23
PIC17C7XX
In Figure 5-5, Figure 5-6 and Figure 5-7, the TPWRT
timer timeout is greater then the TOST timer timeout, as
would be the case in higher frequency crystals. For
lower frequency crystals, (i.e., 32 kHz) T
greater.
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
OST may be
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TOST
FIGURE 5-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 5-7: SLOW RISE TIME (MCLR
VDD
MCLR
INTERNAL POR
T TIME-OUT
PWR
OST TIME-OUT
INTERNAL RESET
TIED TO VDD)
Minimum VDD operating voltage
0V
PWRT
T
TOST
5V
1V
TOST
NOT TIED TO VDD)
DS30289A-page 24 1998 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Register Address
Power-on Reset
Brown-out Reset
Reset
MCLR
WDT Reset
Wake-up from SLEEP
through interrupt
Unbanked
INDF0 00h N.A. N.A. N.A.
FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000h 0000h
PC + 1
(2)
PCLATH 03h 0000 0000 uuuu uuuu uuuu uuuu
ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu
T0STA 05h 0000 000- 0000 000- 0000 000-
(3)
CPUSTA
INTSTA 07h 0000 0000 0000 0000
06h --11 11qq --11 qquu --uu qquu
uuuu uuuu
(1)
INDF1 08h N.A. N.A. N.A.
FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu
WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu
TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu
TBLPTRL 0Dh 0000 0000 0000 0000 uuuu uuuu
TBLPTRH 0Eh 0000 0000 0000 0000 uuuu uuuu
BSR 0Fh 0000 0000 0000 0000 uuuu uuuu
Bank 0
PORTA
(4,6)
10h 0-xx 11xx 0-uu 11uu u-uu uuuu
DDRB 11h 1111 1111 1111 1111 uuuu uuuu
PORTB
(4)
12h xxxx xxxx uuuu uuuu uuuu uuuu
RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu
TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG1 17h 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
1998 Microchip Technology Inc. DS30289A-page 25
PIC17C7XX
TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Register Address
Power-on Reset
Brown-out Reset
Reset
MCLR
WDT Reset
Wake-up from SLEEP
through interrupt
Bank 1
(5)
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
(5)
(5)
(4, 5)
(4, 5)
(4, 5)
PIR1 16h x000 0010 u000 0010
10h 1111 1111 1111 1111 uuuu uuuu
11h xxxx xxxx uuuu uuuu uuuu uuuu
12h 1111 1111 1111 1111 uuuu uuuu
13h xxxx xxxx uuuu uuuu uuuu uuuu
14h ---- 1111 ---- 1111 ---- uuuu
15h ---- xxxx ---- uuuu ---- uuuu
uuuu uuuu
(1)
PIE1 17h 0000 0000 0000 0000 uuuu uuuu
Bank 2
TMR1 10h xxxx xxxx uuuu uuuu uuuu uuuu
TMR2 11h xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 12h xxxx xxxx uuuu uuuu uuuu uuuu
TMR3H 13h xxxx xxxx uuuu uuuu uuuu uuuu
PR1 14h xxxx xxxx uuuu uuuu uuuu uuuu
PR2 15h xxxx xxxx uuuu uuuu uuuu uuuu
PR3/CA1L 16h xxxx xxxx uuuu uuuu uuuu uuuu
PR3/CA1H 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 3
PW1DCL 10h xx-- ---- uu-- ---- uu-- ---PW2DCL 11h xx0- ---- uu0- ---- uuu- ---PW1DCH 12h xxxx xxxx uuuu uuuu uuuu uuuu
PW2DCH 13h xxxx xxxx uuuu uuuu uuuu uuuu
CA2L 14h xxxx xxxx uuuu uuuu uuuu uuuu
CA2H 15h xxxx xxxx uuuu uuuu uuuu uuuu
TCON1 16h 0000 0000 0000 0000 uuuu uuuu
TCON2 17h 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
DS30289A-page 26 1998 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Register Address
Bank 4
PIR2 10h 000- 0010 000- 0010
PIE2 11h 000- 0000 000- 0000 uuu- uuuu
Unimplemented
RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu
TXREG2 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG2 17h 0000 0000 0000 0000 uuuu uuuu
Bank 5
DDRF 10h 1111 1111 1111 1111 uuuu uuuu
(4)
PORTF
DDRG 12h 1111 1111 1111 1111 uuuu uuuu
PORTG
ADCON0 14h 0000 -0-0 0000 -0-0 uuuu uuuu
ADCON1 15h 000- 0000 000- 0000 uuuu uuuu
ADRESL 16h xxxx xxxx uuuu uuuu uuuu uuuu
ADRESH 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 6
SSPADD 10h 0000 0000 0000 0000 uuuu uuuu
SSPCON1 11h 0000 0000 0000 0000 uuuu uuuu
SSPCON2 12h 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 13h 0000 0000 0000 0000 uuuu uuuu
SSPBUF 14h xxxx xxxx uuuu uuuu uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
(4)
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
12h ---- ---- ---- ---- ---- ----
11h 0000 0000 0000 0000 uuuu uuuu
13h xxxx 0000 uuuu 0000 uuuu uuuu
15h ---- ---- ---- ---- ---- ---16h ---- ---- ---- ---- ---- ---17h ---- ---- ---- ---- ---- ----
Power-on Reset
Brown-out Reset
Reset
MCLR
WDT Reset
Wake-up from SLEEP
through interrupt
(1)
uuu- uuuu
1998 Microchip Technology Inc. DS30289A-page 27
PIC17C7XX
TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Register Address
Bank 7
PW3DCL 10h xx0- ---- uu0- ---- uuu- ---PW3DCH 11h xxxx xxxx uuuu uuuu uuuu uuuu
CA3L 12h xxxx xxxx uuuu uuuu uuuu uuuu
CA3H 13h xxxx xxxx uuuu uuuu uuuu uuuu
CA4L 14h xxxx xxxx uuuu uuuu uuuu uuuu
CA4H 15h xxxx xxxx uuuu uuuu uuuu uuuu
TCON3 16h -000 0000 -000 0000 -uuu uuuu
Unimplemented
Bank 8
DDRH
(4)
PORTH
DDRJ
PORTJ
Unbanked
PRODL 18h xxxx xxxx uuuu uuuu uuuu uuuu
PRODH 19h xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
(4)
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
17h ---- ---- ---- ---- ---- ----
10h 1111 1111 1111 1111 uuuu uuuu
11h xxxx xxxx uuuu uuuu uuuu uuuu
12h 1111 1111 1111 1111 uuuu uuuu
13h xxxx xxxx uuuu uuuu uuuu uuuu
Power-on Reset
Brown-out Reset
Reset
MCLR
WDT Reset
Wake-up from SLEEP
through interrupt
DS30289A-page 28 1998 Microchip Technology Inc.
PIC17C7XX
5.1.5 BROWN-OUT RESET (BOR)
PIC17C7XX devices have on-chip Brown-out Reset cir-
cuitry. This circuitry places the device into a reset when
the device voltage falls below a trip point (BV
DD). This
ensures that the device does not continue program
execution outside the valid operation range of the
device. Brown-out resets are typically used in AC line
applications or large battery applications where large
loads may be switched in (such as automotive).
Note: Before using the on-chip brown-out for a
voltage supervisory function, please
review the electrical specifications to
ensure that they meet your requirements.
The BODEN configuration bit can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V
DD falls below BVDD (Typically 4.0V,
parameter #D005 in electrical specification section), for
greater than parameter #35, the brown-out situation will
reset the chip. A reset is not guaranteed to occur if V
DD
falls below BVDD for less than parameter #35. The chip
will remain in Brown-out Reset until V
BV
DD. The Power-up Timer and Oscillator Start-up
DD rises above
Timer will then be invoked. This will keep the chip in
reset the greater of 96 ms and 1024 T
below BV
DD while the Power-up Timer/Oscillator
OSC. If VDD drops
Start-up Timer is running, the chip will go back into a
Brown-out Reset. The Power-up Timer/Oscillator
Start-up Timer will be initialized. Once V
BV
DD, the Power-up Timer/Oscillator Start-up Timer
DD rises above
will start their time delays. Figure 5-10 shows typical
Brown-out situations.
In some applications, the Brown-out reset trip point of
the device may not be at the desired level. Figure 5-8
and Figure 5-9 are two examples of external circuitry
that may be implemented. Each needs to be e v aluated
to determine if they match the requirements of the
application.
FIGURE 5-8: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
DD
33k
10kΩ
40 kΩ
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
V
MCLR
PIC17CXXX
FIGURE 5-9: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
DD
V
Q1
R1
VDD
MCLR
PIC17CXXX
= 0.7V
R1
R2
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
VDD •
40 kΩ
R1 + R2
FIGURE 5-10: BROWN-OUT SITUATIONS
V
DD
Internal
Reset
V
DD
Internal
Reset
V
DD
Internal
Reset
1998 Microchip Technology Inc. DS30289A-page 29
Greater of 96 ms
< 96 ms
and 1024 Tosc
Greater of 96 ms
and 1024 Tosc
Greater of 96 ms
and 1024 Tosc
BV
DD Max.
DD Min.
BV
BVDD Max.
DD Min.
BV
BVDD Max.
DD Min.
BV
PIC17C7XX
NOTES:
DS30289A-page 30 1998 Microchip Technology Inc.
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