MICROCHIP PIC16C7X Technical data
•
•
•
PIC16C7X
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
• PIC16C72 • PIC16C74A
• PIC16C73 • PIC16C76
• PIC16C73A • PIC16C77
• PIC16C74
PIC16C7X Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of Program Memory,
up to 368 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range: 2.5V to 6.0V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
< 2 mA @ 5V, 4 MHz
15 µ A typical @ 3V, 32 kHz
< 1 µ A typical standby current
PIC16C7X Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module(s)
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit
• 8-bit multichannel analog-to-digital converter
• Synchronous Serial Port (SSP) with
2
SPI
and I
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD
• Brown-out detection circuitry for
Brown-out Reset (BOR)
C
, WR and CS controls
PIC16C7X Features 72 73 73A 74 74A 76 77
Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K
Data Memory (Bytes) x 8 128 192 192 192 192 368 368
I/O Pins 22 22 22 33 33 22 33
Parallel Slave Port — — — Yes Yes — Yes
Capture/Compare/PWM Modules 1 222222
Timer Modules 3 333333
A/D Channels 5 558858
2
Serial Communication SPI/I
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes — Yes Yes Yes
Interrupt Sources 8 11 11 12 12 11 12
1997 Microchip Technology Inc. DS30390E-page 1
C SPI/I
2
USART
C,
2
SPI/I
USART
C,
2
SPI/I
USART
C,
2
SPI/I
USART
C,
2
SPI/I
USART
C,
2
SPI/I
USART
C,
PIC16C7X
Pin Diagrams
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
V
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
• 1
2
3
4
5
6
SS
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
PIC16C72
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
V
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
• 1
2
3
4
5
6
SS
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PIC16C73
PIC16C73A
PIC16C76
RA3/AN3/VREF
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC3/SCK/SCL
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
RA4/T0CKI
/AN4
RA5/SS
RE0/RD
/AN5
RE1/WR/AN6
/AN7
RE2/CS
V
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
SSOP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA4/T0CKI
RA5/SS/AN4
V
RC1/T1OSI
RC2/CCP1
SS
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C72
PDIP , Windowed CERDIP
1
2
3
REF
DD
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C74
PIC16C74A
PIC16C77
28
27
26
25
24
23
22
21
20
19
18
17
16
15
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
DS30390E-page 2
1997 Microchip Technology Inc.
Pin Diagrams (Cont.’d)
MQFP
PIC16C7X
PLCC
RA3/AN3/VREF
RA2/AN2
/VPP
RA1/AN1
RA0/AN0
MCLR
NC
RB7
RB6
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3
RB5
RB4
NC
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RB7
/VPP
RA0/AN0
MCLR
NC
RC2/CCP1
RC1/T1OSI/CCP2
33
32
31
30
29
28
27
26
25
24
23
2221201918171615141312
REF
RA2/AN2
RA1/AN1
RA3/AN3/V
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
SS
V
VDD
RE2/CS/AN7
RE1/WR
/AN6
/AN5
RE0/RD
/AN4
RA5/SS
RA4/T0CKI
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO
RD3/PSP3
RD2/PSP2
4443424140393837363534
1
2
3
4
5
6
SS
PIC16C74
7
8
9
10
11
NC
NC
RB4
RB5
RB6
MQFP
TQFP
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
NC
RC2/CCP1
RC1/T1OSI/CCP2
RA4/T0CKI
/AN4
RA5/SS
/AN5
RE0/RD
/AN6
RE1/WR
RE2/CS/AN7
V
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
65432
1
RD0/PSP0
RC2/CCP1
RC3/SCK/SCL
4443424140
RD3/PSP3
RD2/PSP2
RD1/PSP1
RC5/SDO
RC4/SDI/SDA
2827262524232221201918
NC
RC6/TX/CK
7
8
9
10
PIC16C74
11
DD
12
PIC16C74A
13
14
PIC16C77
15
16
NC
17
RC1/T1OSI/CCP2
RB3
39
RB2
38
RB1
37
RB0/INT
36
35
34
33
32
31
30
29
DD
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3
SS
4443424140393837363534
1
2
3
4
5
PIC16C74A
6
7
PIC16C77
8
9
10
11
NC
NC
RB7
RB6
RB5
RB4
/VPP
MCLR
RA2/AN2
RA1/AN1
RA0/AN0
NC
33
32
RC0/T1OSO/T1CKI
31
OSC2/CLKOUT
30
OSC1/CLKIN
29
28
27
26
25
24
23
2221201918171615141312
RA3/AN3/VREF
SS
V
VDD
RE2/CS/AN7
RE1/WR
/AN6
/AN5
RE0/RD
/AN4
RA5/SS
RA4/T0CKI
1997 Microchip Technology Inc. DS30390E-page 3
PIC16C7X
Table of Contents
1.0 General Description....................................................................................................................................................................... 5
2.0 PIC16C7X Device Varieties...........................................................................................................................................................7
3.0 Architectural Overview................................................................................................................................................................... 9
4.0 Memory Organization................................................................................................................................................................... 19
5.0 I/O Ports....................................................................................................................................................................................... 43
6.0 Overview of Timer Modules......................................................................................................................................................... 57
7.0 Timer0 Module............................................................................................................................................................................. 59
8.0 Timer1 Module............................................................................................................................................................................. 65
9.0 Timer2 Module............................................................................................................................................................................. 69
10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71
11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)...................................................................................... 99
13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117
14.0 Special Features of the CPU ..................................................................................................................................................... 129
15.0 Instruction Set Summary............................................................................................................................................................ 147
16.0 Development Support................................................................................................................................................................ 163
17.0 Electrical Characteristics for PIC16C72..................................................................................................................................... 167
18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183
19.0 Electrical Characteristics for PIC16C73A/74A........................................................................................................................... 201
20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219
21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241
22.0 Packaging Information............................................................................................................................................................... 251
Appendix A: ................................................................................................................................................................................... 263
Appendix B: Compatibility............................................................................................................................................................. 263
Appendix C: What’s New............................................................................................................................................................... 264
Appendix D: What’s Changed....................................................................................................................................................... 264
Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265
Pin Compatibility ................................................................................................................................................................................ 271
Index .................................................................................................................................................................................................. 273
List of Examples................................................................................................................................................................................. 279
List of Figures..................................................................................................................................................................................... 280
List of Tables...................................................................................................................................................................................... 283
Reader Response.............................................................................................................................................................................. 286
PIC16C7X Product Identification System........................................................................................................................................... 287
For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As
an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and
PIC16C74A devices.
Applicable Devices
73 73A 74 74A 76 77
72
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30390E-page 4
1997 Microchip Technology Inc.
PIC16C7X
1.0 GENERAL DESCRIPTION
The PIC16C7X is a family of
mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the
PIC16CXX mid-range family.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller f amily has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are available . Additionally, a large register set gives
some of the architectural innovations used to achie v e a
very high performance.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C72 has 128 bytes of RAM and 22 I/O pins.
In addition several peripheral features are available
including: three timer/counters, one Capture/Compare/
PWM module and one serial port. The Synchronous
Serial Port can be configured as either a 3-wire Serial
Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I
8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.
The PIC16C73/73A devices have 192 bytes of RAM,
while the PIC16C76 has 368 byes of RAM. Each de vice
has 22 I/O pins. In addition, several peripheral features
are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
Inter-Integrated Circuit (I
chronous Asynchronous Receiver Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. Also a 5-channel high-speed 8-bit A/
D is provided.The 8-bit resolution is ideally suited for
applications requiring low-cost analog interface, e.g.
thermostat control, pressure sensing, etc.
The PIC16C74/74A devices have 192 bytes of RAM,
while the PIC16C77 has 368 bytes of RAM. Each
device has 33 I/O pins. In addition several peripheral
features are available including: three timer/counters,
two Capture/Compare/PWM modules and two serial
ports. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I
versal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial
Communications Interface or SCI. An 8-bit Parallel
Slave Port is provided. Also an 8-channel high-speed
2
C) bus. Also a 5-channel high-speed
low-cost, high-perfor-
2
C) bus. The Universal Syn-
2
C) bus. The Uni-
8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.
The PIC16C7X family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard
crystal, and the HS is for High Speed crystals. The
SLEEP (power-down) feature provides a power saving
mode. The user can wake up the chip from SLEEP
through several external and internal interrupts and
resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
A UV erasable CERDIP packaged version is ideal for
code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume.
The PIC16C7X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes
customization of application programs (transmitter
codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power , high perf ormance, ease of use and I/O fle xibility
make the PIC16C7X very versatile ev en in areas where
no microcontroller use has been considered before
(e.g. timer functions, serial communication, capture
and compare, PWM functions and coprocessor applications).
1.1 F
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).
1.2 De
PIC16C7X devices are supported by the complete line
of Microchip Development tools.
Please refer to Section 16.0 for more details about
Microchip’s development tools.
amily and Upward Compatibility
velopment Support
1997 Microchip Technology Inc. DS30390E-page 5
PIC16C7X
TABLE 1-1: PIC16C7XX FAMILY OF DEVCES
PIC16C710
Clock
Memory
Peripherals
Features
Maximum Frequency
of Operation (MHz)
EPROM Program Memory
(x14 words)
ROM Program Memory
(14K words)
Data Memory (bytes) 36 36 68 128 128 128
Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0,
Capture/Compare/
PWM Module(s)
Serial Port(s)
2
(SPI/I
C, USART)
Parallel Slave Port — — — — — —
A/D Converter (8-bit) Channels 4 4 4 4 5 5
Interrupt Sources 4 4 4 4 8 8
I/O Pins 13 13 13 13 22 22
Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Yes Yes Yes
Packages 18-pin DIP,
20 20 20 20 20 20
512 1K 1K 2K 2K —
—————2K
————1 1
— — — — SPI/I
18-pin DIP,
SOIC;
SOIC
20-pin SSOP
PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72
TMR0,
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
TMR1,
TMR2
2
C SPI/I
28-pin SDIP,
SOIC, SSOP
TMR1,
TMR2
2
C
28-pin SDIP,
SOIC, SSOP
(1)
PIC16C74A PIC16C76 PIC16C77
Clock
Memory
Maximum Frequency of Operation (MHz)
EPROM Program Memory
(x14 words)
PIC16C73A
20 20 20 20
4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
Peripherals
Timer Module(s) TMR0,
TMR1,
TMR2
Capture/Compare/PWM Mod-
2222
ule(s)
2
Serial Port(s) (SPI/I
C, US-
SPI/I
2
C, USART SPI/I
TMR0,
TMR1,
TMR2
2
C, USART SPI/I
TMR0,
TMR1,
TMR2
2
C, USART SPI/I
TMR0,
TMR1,
TMR2
2
C, USART
ART)
Parallel Slave Port — Yes — Yes
A/D Converter (8-bit) Channels 5858
Interrupt Sources 11 12 11 12
I/O Pins 22 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Features
In-Circuit Serial Programming Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes
Packages 28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
All PIC16/17 Family devices ha ve Pow er-on Reset, selectab le Watchdog Timer, selectab le code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
DS30390E-page 6
1997 Microchip Technology Inc.
PIC16C7X
2.0 PIC16C7X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available . Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C7X Product Identification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1. C , as in PIC16 C 74. These devices have
EPROM type memory and operate over the
standard voltage range.
2. LC , as in PIC16 LC 74. These devices have
EPROM type memory and operate over an
extended voltage range.
2.1 UV Erasab
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
programmers both support programming of the
PIC16C7X.
le Devices
Plus and PRO MATE
2.3 Q
uick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serializ
Production (SQTP
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
II
ed Quick-Turnaround
SM
Devices
)
2.2 O
ne-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1997 Microchip Technology Inc. DS30390E-page 7
PIC16C7X
NOTES:
DS30390E-page 8
1997 Microchip Technology Inc.
PIC16C7X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional v on Neumann architecture in which program and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (200 ns @ 20 MHz) e xcept f or
program branches.
The table below lists program memory (EPROM) and
data memory (RAM) for each PIC16C7X device.
Device
PIC16C72 2K x 14 128 x 8
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
PIC16C77 8K x 14 386 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function registers, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
Program
Memory
Data Memory
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borro
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
w bit and a digit borrow out bit,
1997 Microchip Technology Inc. DS30390E-page 9
PIC16C7X
FIGURE 3-1: PIC16C72 BLOCK DIAGRAM
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
2K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Reset
Timer
Reset
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
128 x 8
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS
/AN4
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
MCLR
VDD, VSS
Timer0
A/D
Timer1 Timer2
Synchronous
Serial Port
CCP1
Note 1: Higher order bits are from the STATUS register.
DS30390E-page 10 1997 Microchip Technology Inc.
FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM
Device Program Memory Data Memory (RAM)
PIC16C73
PIC16C73A
PIC16C76
4K x 14
4K x 14
8K x 14
192 x 8
192 x 8
368 x 8
PIC16C7X
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Reset
Timer
Reset
9
8
FSR reg
MUX
8
Indirect
Addr
Data Bus
RAM
File
Registers
RAM Addr
7
(2)
(1)
Addr MUX
STATUS reg
3
ALU
8
W reg
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS
/AN4
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR
VDD, VSS
CCP1 CCP2
Synchronous
Serial Port
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C73.
A/DTimer0 Timer1 Timer2
USART
1997 Microchip Technology Inc. DS30390E-page 11
PIC16C7X
FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM
Device Program Memory Data Memory (RAM)
PIC16C74
PIC16C74A
PIC16C77
4K x 14
4K x 14
8K x 14
192 x 8
192 x 8
368 x 8
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
(13-bit)
Timer
Reset
Timer
Reset
(2)
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
(1)
Addr MUX
FSR reg
STATUS reg
ALU
W reg
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
PORTD
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
MCLR
VDD, VSS
CCP1 CCP2
Synchronous
Serial Port
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C74.
Parallel Slave Port
A/DTimer0 Timer1 Timer2
USART
PORTE
RE0/RD
RE1/WR
RE2/CS
/AN5
/AN6
/AN7
DS30390E-page 12 1997 Microchip Technology Inc.
PIC16C7X
TABLE 3-1: PIC16C72 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKIN 9 9 9 I
OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
MCLR
/VPP
RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
RB0/INT 21 21 21 I/O TTL/ST
RB1 22 22 22 I/O TTL
RB2 23 23 23 I/O TTL
RB3 24 24 24 I/O TTL
RB4 25 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 27 I/O TTL/ST
RB7 28 28 28 I/O TTL/ST
RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 17 I/O ST
RC7 18 18 18 I/O ST
VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
SSOP
Pin#
Pin#
1 1 1 I/P ST Master clear (reset) input or programming voltage input. This
— = Not used TTL = TTL input ST = Schmitt Trigger input
SOIC
Pin#
I/O/P
Type
Buffer
Type
ST/CMOS
Description
(3)
Oscillator crystal input/external clock source input.
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
Output is open drain type.
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
clock input.
PWM1 output.
2
for both SPI and I
data I/O (I2C mode).
C modes.
1997 Microchip Technology Inc. DS30390E-page 13
PIC16C7X
TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION
Pin Name
OSC1/CLKIN 9 9 I
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
MCLR
/VPP
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
RB0/INT 21 21 I/O TTL/ST
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST
RB7 28 28 I/O TTL/ST
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DIP
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
SOIC
Pin#
1 1 I/P ST Master clear (reset) input or programming voltage input. This
I/O/P
Type
Buffer
Type
ST/CMOS
Description
(3)
Oscillator crystal input/external clock source input.
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
Output is open drain type.
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
clock input.
input/Compare2 output/PWM2 output.
PWM1 output.
2
for both SPI and I
data I/O (I2C mode).
Synchronous Clock.
Synchronous Data.
C modes.
DS30390E-page 14 1997 Microchip Technology Inc.
PIC16C7X
TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKIN 13 14 30 I ST/CMOS
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for
RB0/INT 33 36 8 I/O TTL/ST
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST
RB7 40 44 17 I/O TTL/ST
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PLCC
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
(4)
Oscillator crystal input/external clock source input.
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
voltage
counter. Output is open drain type.
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
1997 Microchip Technology Inc. DS30390E-page 15
PIC16C7X
TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d)
DIP
Pin Name
Pin#
PLCC
Pin#
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
RD0/PSP0 19 21 38 I/O ST/TTL
RD1/PSP1 20 22 39 I/O ST/TTL
RD2/PSP2 21 23 40 I/O ST/TTL
RD3/PSP3 22 24 41 I/O ST/TTL
RD4/PSP4 27 30 2 I/O ST/TTL
RD5/PSP5 28 31 3 I/O ST/TTL
RD6/PSP6 29 32 4 I/O ST/TTL
RD7/PSP7 30 33 5 I/O ST/TTL
RE0/RD/AN5 8 9 25 I/O ST/TTL
RE1/WR/AN6 9 10 26 I/O ST/TTL
RE2/CS/AN7 10 11 27 I/O ST/TTL
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,4012,13,
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
QFP
Pin#
33,34
I/O/P
Type
Buffer
Type
Description
PORTC is a bi-directional I/O port.
Timer1 clock input.
Capture2 input/Compare2 output/PWM2 output.
PWM1 output.
output for both SPI and I2C modes.
data I/O (I2C mode).
(SPI mode).
Synchronous Clock.
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PORTE is a bi-directional I/O port.
(3)
RE0 can also be read control for the parallel slav e port,
or analog input5.
(3)
RE1 can also be write control for the parallel slave port,
or analog input6.
(3)
RE2 can also be select control for the parallel slave
port, or analog input7.
— These pins are not internally connected. These pins should
be left unconnected.
DS30390E-page 16 1997 Microchip Technology Inc.
PIC16C7X
3.1 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-4.
FIGURE 3-4: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q1
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instr uction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle , the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Execute INST (PC) Fetch INST (PC+2)
Q2 Q3 Q4
Q1
Execute INST (PC+1)
Internal
phase
clock
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1997 Microchip Technology Inc. DS30390E-page 17
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16C7X
NOTES:
DS30390E-page 18 1997 Microchip Technology Inc.
PIC16C7X
4.0 MEMORY ORGANIZATION
Applicable Devices
72 73 73A 74 74A 76 77
4.1 Program Memory Organization
The PIC16C7X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:
Device
PIC16C72 2K x 14 0000h-07FFh
PIC16C73 4K x 14 0000h-0FFFh
PIC16C73A 4K x 14 0000h-0FFFh
PIC16C74 4K x 14 0000h-0FFFh
PIC16C74A 4K x 14 0000h-0FFFh
PIC16C76 8K x 14 0000h-1FFFh
PIC16C77 8K x 14 0000h-1FFFh
For those devices with less than 8K program memory,
accessing a location above the physically implemented
address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC16C72 PROGRAM
CALL, RETURN
RETFIE, RETLW
Program
Memory
Address Range
MEMORY MAP AND STACK
PC<12:0>
13
FIGURE 4-2: PIC16C73/73A/74/74A
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-chip Program
Memory (Page 0)
Space
User Memory
On-chip Program
Memory (Page 1)
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
User Memory
Space
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-chip Program
Memory
0000h
0004h
0005h
07FFh
0800h
1FFFh
1997 Microchip Technology Inc. DS30390E-page 19
PIC16C7X
FIGURE 4-3: PIC16C76/77 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Space
User Memory
Stack Level 1
Stack Level 2
Stack Level 8
Reset V ector
Interrupt Vector
On-Chip
On-Chip
On-Chip
On-Chip
13
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
4.2 Data Memory Organization
Applicable Devices
72 73 73A 74 74A 76 77
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly , or indi-
rectly through the File Select Register FSR
(Section 4.5).
DS30390E-page 20 1997 Microchip Technology Inc.
PIC16C7X
FIGURE 4-4: PIC16C72 REGISTER FILE
MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
General
Purpose
Register
(1)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
General
Purpose
Register
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FIGURE 4-5: PIC16C73/73A/74/74A
REGISTER FILE MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(2)
(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
20h A0h
General
Purpose
Register
(1)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(2)
TRISD
(2)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
General
Purpose
Register
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
7Fh
FFh
Bank 0 Bank 1
7Fh
Note 1: Not a physical register.
1997 Microchip Technology Inc. DS30390E-page 21
Bank 0 Bank 1
Unimplemented data memory locations, read as
'0'.
FFh
Unimplemented data memory locations, read as
'0'.
Note 1: Not a physical register.
2: These registers are not physically imple-
mented on the PIC16C73/73A, read as '0'.
PIC16C7X
FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP
PCL
FSR
PIE1
PIE2
PR2
(*)
80h
81h
82h
83h
84h
85h
86h
87h
(1)
88h
(1)
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
(*)
00h
01h
Indirect addr.
OPTION
02h
03h
STATUS
04h
05h
06h
07h
(1)
08h
(1)
09h
0Ah
0Bh
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
0Ch
0Dh
0Eh
PCON
0Fh
10h
11h
12h
13h
14h
SSPADD
SSPSTAT
15h
16h
17h
18h
19h
TXSTA
SPBRG
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
ADCON1
20h
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
General
Purpose
Register
16 Bytes
File
Address
PCL
FSR
(*)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
(*)
100h
101h
Indirect addr.
OPTION
102h
103h
STATUS
104h
105h
106h
TRISB
107h
108h
109h
10Ah
10Bh
PCLATH
INTCON
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
General
Purpose
Register
16 Bytes
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
80 Bytes 80 Bytes 80 Bytes
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
accesses
70h - 7Fh
Bank 3
1EFh
1F0h
1FFh
Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require
relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.
DS30390E-page 22 1997 Microchip Technology Inc.
PIC16C7X
4.2.2 SPECIAL FUNCTION REGISTERS
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
with the “core” functions are described in this section,
and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Bank 0
(1)
00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h
03h
04h
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —
0Ah
0Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1)
STATUS IRP
(1)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(1)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(4)
RP1
(4)
RP0 TO PD ZDCC0001 1xxx 000q quuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
Value on all
other resets
(3)
1997 Microchip Technology Inc. DS30390E-page 23
PIC16C7X
TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(1)
80h
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
83h
84h
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —
8Ah
8Bh
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1)
STATUS IRP
(1)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
(1)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(4)
RP1
(4)
RP0 TO PD ZDCC0001 1xxx 000q quuu
Value on:
POR,
BOR
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
Value on all
other resets
(3)
DS30390E-page 24 1997 Microchip Technology Inc.
PIC16C7X
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Bank 0
(4)
00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h
03h
04h
05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h
09h
0Ah
0Bh
0Ch PIR1 PSPIF
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(5)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
(5)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(7)
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
(3)
(7)
RP1
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RP0 TO PD ZDCC0001 1xxx 000q quuu
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
Value on all
other resets
(2)
1997 Microchip Technology Inc. DS30390E-page 25
PIC16C7X
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(4)
80h
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
83h
84h
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h
89h
8Ah
8Bh
8Ch PIE1 PSPIE
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(5)
TRISD PORTD Data Direction Register 1111 1111 1111 1111
(5)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(7)
(3)
(7)
RP1
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
RP0 TO PD ZDCC0001 1xxx 000q quuu
Value on:
POR,
BOR
(6)
---- --qq ---- --uu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
Value on all
other resets
(2)
DS30390E-page 26 1997 Microchip Technology Inc.
PIC16C7X
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Bank 0
(4)
00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h
03h
04h
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h
09h
0Ah
0Bh
0Ch PIR1 PSPIF
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(5)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
(5)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
Value on all
other resets
(2)
1997 Microchip Technology Inc. DS30390E-page 27
PIC16C7X
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
(4)
80h
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
83h
84h
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h
89h
8Ah
8Bh
8Ch PIE1 PSPIE
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(5)
TRISD PORTD Data Direction Register 1111 1111 1111 1111
(5)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Value on:
POR,
BOR
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
Value on all
other resets
(2)
DS30390E-page 28 1997 Microchip Technology Inc.
PIC16C7X
TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 2
(4)
100h
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
102h
103h
104h
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
10Bh
10Ch10Fh
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
— Unimplemented — —
Value on:
POR,
BOR
Bank 3
(4)
180h
181h OPTION RBPU
182h
183h
184h
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
18Bh
18Ch18Fh
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(1,4)
PCLATH — — —
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
— Unimplemented — —
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
Value on all
other resets
(2)
1997 Microchip Technology Inc. DS30390E-page 29
PIC16C7X
4.2.2.1 STATUS REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
The ST ATUS register, shown in Figure 4-7, contains the
arithmetic status of the ALU, the RESET status and the
bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
O and PD bits are not
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STA TUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1: For those devices that do not use bits IRP
and RP1 (STATUS<7:6>), maintain these
bits clear to ensure upward compatibility
with future products.
Note 2: The C and DC bits operate as a borro
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: T
bit 3: PD
bit 2: Z: Zero bit
bit 1: DC: Digit carry/borro
bit 0: C: Carry/borro
O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borro
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
w the polarity is reversed. A subtraction is executed by adding the two’s complement of the
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
w
DS30390E-page 30 1997 Microchip Technology Inc.
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