MICROCHIP PIC16C745, PIC16C765 Technical data

PIC16C745/765

8-Bit CMOS Microcontrollers with USB

Devices included in this data sheet:

• PIC16C745 • PIC16C765

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions

Memory

Device

PIC16C745 8K 256 28 8 5 PIC16C765 8K 256 40 8 8

Program

x14

Data

Pins

• All single cycle instructions except for program branches which are two cycle

• Interrupt capability (up to 12 internal/external interrupt sources)

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Brown-out detection circuitry for Brown-out Reset (BOR)

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

- EC - External clock (24 MHz)

- E4 - External clock with PLL (6 MHz)

- HS - Crystal/Resonator (24 MHz)

- H4 - Crystal/Resonator with PLL (6 MHz)

• Processor clock of 24 MHz derived from 6 MHz crystal or resonator

• Fully static low-power, high-speed CMOS

• In-Circuit Serial Programming (ICSP)

• Operating voltage range

- 4.35 to 5.25V

• High Sink/Source Current 25/25 mA

• Wide temperature range

- Industrial (-40°C - 85°C)

• Low-power consumption:

- ~ 16 mA @ 5V, 24 MHz

-100 µA typical standby current

A/D

Resolution

Channels

A/D

Pin Diagrams

28-Pin DIP, SOIC

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

RA5/AN4

Vss

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

USB

• 1

2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20

PIC16C745

19 18 17 16 15

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V

Vss RC7/RX/DT RC6/TX/CK D+ D-

Peripheral Features:

• Universal Serial Bus (USB 1.1)

- Soft attach/detach

• 64 bytes of USB dual port RAM

• 22 (PIC16C745) or 33 (PIC16C765) I/O pins

- Individual direction control

- 1 high voltage open drain (RA4)

- 8 PORTB pins with:

- Interrupt-on-change control (RB<7:4> only)

- Weak pull-up control

- 3 pins dedicated to USB

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler can be incremented during SLEEP via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• 2 Capture, Compare and PWM modules

- Capture is 16-bit, max. resolution is 10.4 ns

- Compare is 16-bit, max. resolution is 167 ns

- PWM maximum resolution is 10-bit

• 8-bit multi-channel Analog-to-Digital converter

• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with external RD

, WR and CS controls (PIC16C765 only)

 2000 Microchip Technology Inc. Preliminary DS41124C-page 1

PIC16C745/765

REF

44-Pin PLCC

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

V VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

40-Pin DIP

MCLR/VPP

RA0/AN0 RA1/AN1

RA2/AN2

RA3/AN3/V

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RD0/PSP0 RD1/PSP1

7 8 9 10 11

12 13 14 15 16 17

REF

VSS

USB

MCLR

RA3/AN3/V

RA2/AN2

RA1/AN1

RA0/AN0

65432

PIC16C765

USB

RD1/PSP1

RD0/PSP0

RC2/CCP1

RC1/T1OSI/CCP2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

RB7

RB6

4443424140

D-

RD3/PSP3

RD2/PSP2

PIC16C765

44-Pin TQFP

RB5

RB4

RC6/TX/CK

RB3

RB2

RB1

RB0/INT

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

2827262524232221201918

D+

RC6/TX/CK

RB7 RB6

39 38

RB5

RB4 RB3

RB2

35 34

RB1

RB0/INT V

32 31 30 29 28 27 26 25 24 23 22 21

VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK D+ DRD3/PSP3 RD2/PSP2

RC7/RX/DT

RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

V VDD

RB0/INT

RB1 RB2 RB3

4443424140393837363534

1 2 3 4 5 6 7 8 9 10 11

USB

D+D-RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

PIC16C765

RB7

RB6

RB5

RB4

RA0/AN0

MCLR

RC2/CCP1

RC1/T1OSI/CCP2

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4

RA4/T0CKI

2221201918171615141312

REF

RA2/AN2

RA1/AN1

RA3/AN3/V

Key Features

PICmicro

Mid-Range Reference Manual

PIC16C745 PIC16C765

(DS33023)

Operating Frequency 6 MHz or 24 MHz 6 MHz or 24 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) Program Memory (14-bit words) 8K 8K Data Memory (bytes) 256 256 Dual Port Ram 64 64 Interrupt Sources 11 12 I/O Ports 22 (Ports A, B, C) 33 (Ports A, B, C, D, E) Timers 3 3 Capture/Compare/PWM modules 2 2 Analog-to-Digital Converter Module 5 channel x 8 bit 8 channel x 8 bit Parallel Slave Port — Yes Serial Communication USB, USART/SCI USB, USART/SCI Brown-out Detect Reset Yes Yes

DS41124C-page 2 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

Table of Contents

1.0 General Description .............................................................................................................................................. 5

2.0 PIC16C745/765 Device Varieties .................................... ............. .............. ............. .............. ...............................7

3.0 Architectural Overview.......................................................................................................................................... 9

4.0 Memory Organization.......................................................................................................................................... 15

5.0 I/O Ports....... .............. ............. .............. ............. .............. ............. .............. ........................................................ 31

6.0 Timer0 Module.................................................................................................................................................... 43

7.0 Timer1 Module.................................................................................................................................................... 45

8.0 Timer2 Module.................................................................................................................................................... 49

9.0 Capture/Compare/PWM Modules.......................................................................................................................51

10.0 Universal Serial Bus................ .............. ............. .............. ............. .............. ............. ........................................... 57

11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) .............................................................77

12.0 Analog-to-Digital Converter (A/D) Module .......................................................................................................... 91

13.0 Special Features of the CPU .............................................................................................................................. 99

14.0 Instruction Set Summary................................................................................................................................... 113

15.0 Development Support ....................................................................................................................................... 121

16.0 Electrical Characteristics................................................................................................................................... 127

17.0 DC and AC Characteristics Graphs and Tables ............................................................................................... 145

18.0 Packaging Information...................................................................................................................................... 147

Index .......................................................................................................................................................................... 157

On-Line Support.......................................................................................................................................................... 161

Reader Response ....................................................................................................................................................... 162

Product Identification System ..................................................................................................................................... 163

To Our Valued Customers

Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

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An errata sheet may exist fo r current devic es, describin g minor opera tional difference s (from the data sheet) and reco mmended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

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Corrections to this Data Sheet

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We appreciate your assistance in making this a better document.

 2000 Microchip Technology Inc. Preliminary DS41124C-page 3

PIC16C745/765

NOTES:

DS41124C-page 4 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

1.0 GENERAL DESCRIPTION

The PIC16C745/765 devices are low cost, high-perfor-

mance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX mid-range family.

All PICmicro RISC architecture. The PIC16C745 /765 microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources. The separate instruction and data bu ses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructio ns to exec ute in a single cycle, except for program branches, which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.

The PIC16C745 device has 22 I/O pins. The PIC16C765 device has 33 I/O pins. Ea ch device has 256 bytes of RAM. In addition, sev eral peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Universal Serial Bus (USB 1.1) low speed peripheral provides bus communications. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also, a 5- channel high-speed 8-bit A/D is provided on the PIC16C745, while the PIC16C765 offers 8 channels. The 8-bit res olution is ideally sui t ed f or ap pl i c at i on s r e qu i ri n g a lo w c o s t an alog interface (e.g. , thermosta t control, press ure sensing, etc.).

The PIC16C745/765 devices have special features to reduce external components, thus reducing cost, enhancing system reliability and r educing power consumption. There are 4 oscillator options, of which EC is for the external regulated clock source, E4 is for the external regulated clock source with the PLL enabled, HS is for the high speed crystal s/resona tors an d H 4 is for high speed crystals/resonators with the PLL enabled. The SLEEP (power-down) feature provides a power-saving mode. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESETS.

microcontrollers employ an advanced

A highly reliable Watchdog Timer (WDT), with a dedicated on-chip RC oscillator, provides protection against software lock-up, and also provides one way of waking the device from SLEEP.

A UV erasable CERDIP packaged version is ideal for code development, while the cost-effective One- TimeProgrammable (OTP) version is suitable for production in any volume.

The PIC16C745/765 devices fit nicely in many applications ranging from security and re mote sensors to appl iance controls and automotives. The EPROM technology makes customization of application programs (data loggers, industrial controls, UPS) extremely fast and conveni ent. The small footp rint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, lowpower, high-per fo rmanc e, ease of us e and I/O fl exibility make the PIC16C745/765 devices very versatile, even in areas where no microcontroll er use ha s been consid ered before (e.g., timer functions , serial communicati on, capture and compare, PWM fun ct ions a nd c oproc esso r applications).

1.1 Family and Upward Compatibility

Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Code written for the PIC16C5X can be easily ported to the PIC16C745/765 family of devices.

1.2 Development Support

PICmicro® devices are supported by the comp lete l ine of Microchip Development tools.

Please refer to Section 15.0 for more details about Microchip’s development tools.

 2000 Microchip Technology Inc. Preliminary DS41124C-page 5

PIC16C745/765

NOTES:

DS41124C-page 6 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

2.0 PIC16C745/765 DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C7 45/765 Product Identification System section at the end o f this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in windowed CERDIP packages, is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the supported oscillator modes.

Microchip’s PICSTART programmers both support programming of the PIC16C745/765.

2.2 One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications.

The OTP devices, packaged in plastic pack ages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.



Plus and PRO MATEII

2.3 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patter ns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before pr oduction shipments are available. Please contact your local Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry-code, password or ID number.

 2000 Microchip Technology Inc. Preliminary DS41124C-page 7

PIC16C745/765

NOTES:

DS41124C-page 8 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C745/765 family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C745/765 uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating pr ogram and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all sing le word instructions. A 14-bit wide program memory access bus fetches a 14-bit instr uction in a single cycl e. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, most instructions execute in a sin gle cycle (166.6667 ns @ 24 MHz) except for program branches.

Memory

Device

PIC16C745 8K 256 28 8 5 PIC16C765 8K 256 40 8 8

Program

x14

Data

The PIC16C745/765 can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C745/765 has an orthogonal (symmetrical ) instructi on set that make s it possibl e to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C745/765 simple yet efficient. In addition, the learning curve is reduced significantly.

Pins

A/D

Resolution

A/D

Channels

PIC16C745/765 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file.

The ALU is 8-bits wide and ca pable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typi cally one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STA TUS register . The C and DC bits operate as a borrow

bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

 2000 Microchip Technology Inc. Preliminary DS41124C-page 9

PIC16C745/765

FIGURE 3-1: PIC16C745/765 BLOCK DIAGRAM

OSC1/ CLKIN

OSC2/

CLKOUT

Program

Bus

EPROM

Program

Memory

8K x 14

Instruction reg

Instruction Decode &

Control

Timing

Generation

x4 PLL

Program Counter

Direct Addr

Start-up Timer

MCLR

8 Level Stack

(13 bit)

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VDD, VSS

RAM Addr(1)

Data Bus

RAM

File

Registers

256 x 8

Addr MUX

STATUS reg

ALU

W reg

Parallel Slave Port

8-bit A/DTimer0 Timer1 Timer2

FSR reg

MUX

Indirect

Addr

PORTA

RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4

PORTB

RB0/INT

RB<7:1>

PORTC

PORTD

(2)

PORTE

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC6/TX/CK RC7/RX/DT

RD3:0/PSP3:0 RD4/PSP4

RD5/PSP5 RD6/PSP6 RD7/PSP7

RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS

(2)

(2) (2) (2) (2)

(2)

CCP2

CCP1

USART

Dual Port

RAM

64 x 8

USB

XCVR

USB

DD+

Note 1: Higher order bits are from the STATUS register.

2: Not available on PIC16C745.

DS41124C-page 10 Preliminary  2000 Microchip Technology Inc.

TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION

Name Function

/VPP

MCLR

OSC1/CLKIN

OSC2/CLKOUT

Input Type

MCLR ST — Master Clear

PP Power — Programming Voltage

OSC1 Xtal — Crystal/Resonator CLKIN ST — Exter nal Clo ck Inpu t OSC2 — Xtal Crystal/Resonator

CLKOUT — CMOS Internal Clock (F

Output

Type

PIC16C745/765

Description

INT/4) Output

RA0/AN0

RA1/AN1

RA2/AN2

RA0 ST CMOS Bi-directional I/O AN0 AN — A/D Input RA1 ST CMOS Bi-directional I/O AN1 AN — A/D Input RA2 ST CMOS Bi-directional I/O AN2 AN — A/D Input RA3 ST CMOS Bi-directional I/O

RA3/AN3/V

RA4/T0CKI

RA5/AN4

RB0/INT

REF

AN3 AN — A/D Input

REF AN — A/D Positive Reference

RA4 ST OD Bi-directional I/O

T0CKI ST — Timer 0 Clock Input

RA5 ST Bi-directional I/O AN4 AN — A/D Input

RB0 TTL CMOS Bi-directional I/O

INT ST — Interrupt RB1 RB1 TTL CMOS Bi-directional I/O RB2 RB2 TTL CMOS Bi-directional I/O RB3 RB3 TTL CMOS Bi-directional I/O RB4 RB4 TTL CMOS Bi-directional I/O with Interrupt-on-Change RB5 RB5 TTL CMOS Bi-directional I/O with Interrupt-on-Change

RB6/ICSPC

RB7/ICSPD

RB6 TTL CMOS Bi-directional I/O with Interrupt-on-Change

ICSPC ST In-Circuit Serial Programming Clock Input

RB7 TTL CMOS Bi-directional I/O with Interrupt-on-Change

ICSPD ST CMOS In-Circuit Serial Programming Data I/O

RC0 ST CMOS Bi-directional I/O

RC0/T1OSO/T1CKI

T1OSO — Xtal T1 Oscillator Output

T1CKI ST — T1 Clock Input

RC1 ST CMOS Bi-directional I/O

RC1/T1OSI/CCP2

(1)

T1OSI Xtal — T1 Oscillator Input CCP2 Capture In/Compare Out/PWM Out 2

RC2/CCP1

USB VUSB Power Regulator Output Voltage

RC2 ST CMOS Bi-directional I/O

CCP1 Capture In/Compare Out/PWM Out 1

D- D- USB USB U SB Differentia l Bus

D+ D+ USB USB USB Differential Bus

Legend: OD = open drain, ST = Schmitt Trigger

Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable.

2: PIC16C765 only.

(1)

(1) (1) (1)

(1)

 2000 Microchip Technology Inc. Preliminary DS41124C-page 11

PIC16C745/765

TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION (CONTINUED)

Name Function

RC6/TX/CK

RC7/RX/DT

Input Type

RC6 ST CMOS Bi-directional I/O

TX — CMOS USART Async Transmit CK ST CMOS USART Master Out/Slave In Clock

RC7 ST CMOS Bi-directional I/O

RX ST — USART Async Receive DT ST CMOS USART Data I/O

Output

Type

Description

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

RD0 TTL CMOS Bi-directional I/O

(2)

PSP0 TTL — Parallel Slave Port Data Input

RD1 TTL CMOS Bi-directional I/O

(2)

PSP1 TTL — Parallel Slave Port Data Input

RD2 TTL CMOS Bi-directional I/O

(2)

PSP2 TTL — Parallel Slave Port Data Input

RD3 TTL CMOS Bi-directional I/O

(2)

PSP3 TTL — Parallel Slave Port Data Input

RD4 TTL CMOS Bi-directional I/O

(2)

PSP4 TTL — Parallel Slave Port Data Input

RD5 TTL CMOS Bi-directional I/O

(2)

PSP5 TTL — Parallel Slave Port Data Input

RD6 TTL CMOS Bi-directional I/O

(2)

PSP6 TTL — Parallel Slave Port Data Input

RD7 TTL CMOS Bi-directional I/O

(2)

PSP7 TTL — Parallel Slave Port Data Input

RE0 ST CMOS Bi-directional I/O

(2)

RD TTL — Parallel Slave Port Control Input AN5 AN — A/D Input RE1 ST CMOS Bi-directional I/O

(2)

WR TTL — Parallel Slave Port Control Input AN6 AN — A/D Input RE2 ST CMOS Bi-directional I/O

(2)

CS TTL — Parallel Slave Port Data Input

AN7 AN — A/D Input

(2)

VDD VDD Power — Power V

SS VSS Power — Ground

Legend: OD = open drain, ST = Schmitt Trigger

Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable.

2: PIC16C765 only.

DS41124C-page 12 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

3.1 Clocking Scheme/Instruction Cycle

The clock input feeds either an on-chip PLL, or directly

INT). The clock output from either the PLL or

drives (F direct drive (F

INT) is internally divided by four to gener-

ate four non-overlapping quadrature clocks namely, Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC2/CLKOUT

(EC mode)

FINT

Q1 Q2 Q3 Q4

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC- 1) Fetch INST (PC+1)

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to c hange (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the pr ogram counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC ) Fetch INST (PC+2)

Q2 Q3 Q4

Execute INST (PC+1)

Internal phase clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch

instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

 2000 Microchip Technology Inc. Preliminary DS41124C-page 13

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Exe cute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16C745/765

NOTES:

DS41124C-page 14 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C745/765 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. All devices covered by this data sheet have 8K x 14 bits of program memory. The address range is 0000h - 1FFFh for all devices.

The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 4-1: PIC16C745/765 PROGRAM

CALL, RETURN RETFIE, RETLW

On-chip

Program

Memory

MEMORY MAP AND ST ACK

PC<12:0>

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

Page 0

Page 1

Page 2

Page 3

0000h

0004h 0005h

07FFh 0800h

0FFFh 1000h

17FFh 1800h

4.2 Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits.

RP<1:0> (STATUS<6:5>) = 00 → Bank0 = 01 → Bank1 = 10 → Bank2 = 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the SFRs. Above the SFRs are GPRs, implemented as static RAM.

All implemented banks contain SFRs. Some “high use” SFRs from one bank may be mirrored in another bank for code reduction and quicker access.

4.2.1 GEN ERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi-

rectly through the File Select Register (FSR) (Section 4.5).

1FFFh

 2000 Microchip Technology Inc. Preliminary DS41124C-page 15

PIC16C745/765

FIGURE 4-2: DATA MEMORY MAP FOR PIC16C745/765

Bank 0 File

Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect add r.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h

(2)

PORTD

(2)

PORTE PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch PIR2 0Dh PIE2 8Dh TMR1L 0Eh PCON 8Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h PR2 92h

CCPR1L 15h CCPR1H 16h CCP1CON 17h

RCSTA 18h TXSTA 98h TXREG 19h SPBRG 99h RCREG 1Ah CCPR2L 1Bh

CCPR2H 1Ch 9Ch 11Ch CCP2CON 1Dh 9Dh 11Dh ADRES 1Eh 9Eh 11Eh ADCON0 1Fh ADCON1 9Fh 11Fh General

Purpose Register 96 Bytes

Address

08h 09h

13h 93h 113h UEIE 193h 14h 94h 114h USTAT 194h

20h General

Bank 1 File

(2)

TRISD

(2)

TRISE

Purpose Register 80 Bytes

Address

88h 108h 188h 89h 109h 189h

8Fh 10Fh 18Fh 90h 110h UIR 190h 91h 111h UIE 191h

95h 115h UCTRL 195h 96h 116h UADDR 196h 97h 117h

9Ah 11Ah UEP2 19Ah 9Bh 11Bh

A0h General

Bank 2 File

Address

105h 185h

107h 187h

10Ch 18Ch 10Dh 18Dh 10Eh 18Eh

112h UEIR 192h

118h UEP0 198h 119h UEP1 199h

120h USB Dual Port Purpose Register 80 Bytes

Bank 3 File

USWSTAT

Memory 64 Bytes

(1)

Address

197h

(1)

19Bh

(1)

19Ch

(1)

19Dh

(1)

19Eh

(1)

19Fh 1A0h

1DFh

accesses

7Fh FFh 17Fh 1FFh

Unimplemented data memory locations, read as ‘0’. *Not a physical register.

Note 1: Reserved registers may contain USB state information.

2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745; always maintain these bits clear.

DS41124C-page 16 Preliminary  2000 Microchip Technology Inc.

70h-7Fh

EFh 16Fh 1EFh F0h accesses

70h-7Fh

170h accesses

70h-7Fh

1E0h

1F0h

PIC16C745/765

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the devic e. These registers are implemented as static RAM.

The Special Function Registers can be classified into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that p eripher al feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

Bank 0

(3)

00h INDF 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC 08h PORTD 09h PORTE 0Ah PCLATH 0Bh INTCON 0Ch PIR1 PSPIF 0Dh PIR2 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON 13h — Unimplemented — — 14h — Unimplemented — — 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON 18h RCSTA SPEN RX9 SREN CREN 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

Addressing th is location u ses contents of FSR to address d ata memory (not a physical register) 0000 0000 0000 0000

(3)

Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(3)

(2)

IRP

(3)

Indirect data memory address pointer xxxx xxxx uuuu uuuu

— — PORTA Data Latch when written: POR TA pins when read --0x 0000 --0u 0000

RC7 RC6

(4)

PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

(4)

— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

(1,3)

— — — Write Buffer for the upper 5 bits of the Program Co unter ---0 0000 ---0 0000

(3)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— — — – — — — CCP2IF ---- ---0 ---- ---0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

— — DC2B1 DC2B1 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

(2)

RP1

(4)

ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RP0 TO PD ZDCC0001 1xxx 000q quuu

— — —

— FERR OERR RX9D 0000 -00x 0000 -00x

RC2 RC1 RC0

— ADON 0000 00-0 0000 00-0

xx-- -xxx uu-- -uuu

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.

POR, BOR

Value on all other resets

(2)

 2000 Microchip Technology Inc. Preliminary DS41124C-page 17

PIC16C745/765

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

80h INDF 81h OPTION RBPU 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC 88h TRISD 89h TRISE 8Ah PCLATH 8Bh INTCON 8Ch PIE1 PSPIE 8Dh PIE2 8Eh PCON 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1

(3)

Addressing th is location u ses contents of FSR to address d ata memory (not a physical register) 0000 0000 0000 0000

(3)

Program Counte r’s (PC) Least Significant Byte 0000 0000 0000 0000

(3)

Indirect data memory address pointer xxxx xxxx uuuu uuuu

TRISC7 TRISC8

(4)

PORTD Data Direction Regi s ter 1111 1111 1111 1111

(4)

(1,3)

(3)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

— — PORTA Data Direction Register --11 1111 --11 1111

— — —

IBF OBF IBOV PSPMODE — PORTE Data Directio n Bits 0000 -111 0000 -111

— — — Write Buffer for the upper 5 bits of the Program Co unter ---0 0000 ---0 0000

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(4)

ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

— — — — — — — CCP2IE ---- ---0 ---- ---0 — — — — — — POR BOR ---- --qq ---- --uu

— BRGH TRMT TX9D 0000 -010 0000 -010

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TRISC2 TRISC1 TRISC0

Value on:

11-- -111 11-- -111

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.

POR, BOR

Value on all other resets

(2)

DS41124C-page 18 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

100h 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h 103h 104h 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah 10Bh 10Ch-

11Fh

(3)

INDF

PCL STATUS FSR

PCLATH INTCON

Addressing th is location u ses contents of FSR to address d ata memory (not a physical register) 0000 0000 0000 0000

(3)

Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(3)

IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(3)

Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,3)

— — — Write Buffer for the upper 5 bits of the Program Co unter ---0 0000 ---0 0000

(3)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented — —

Value on:

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.

POR, BOR

Value on all other resets

(2)

 2000 Microchip Technology Inc. Preliminary DS41124C-page 19

PIC16C745/765

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

(3)

180h

INDF 181h OPTION_REG RBPU 182h

PCL 183h

STATUS 184h

FSR 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah

PCLATH 18Bh

INTCON 18Ch-

18Fh 190h UIR 191h UIE 192h UEIR BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 193h UEIE BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 194h USTAT 195h UCTRL 196h UADDR 197h USWSTAT SWSTAT7 SWSTAT6 SWSTAT5 SWSTAT4 SWSTAT 3 SWSTAT2 SWSTAT1 SWSTAT0 0000 0000 0000 0000 198h UEP0 199h UEP1 19Ah UEP2 19Bh-

Reserved Reserved, do not use. 0000 0000 0000 0000

19Fh

Addressing th is location u ses contents of FSR to address d ata memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(3)

Program Counte r’s (PC) Least Significant Byte 0000 0000 0000 0000

(3)

IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(3)

Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,3)

— — —

(3)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented — —

— — STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST --00 0000 --00 0000 — — STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST --00 0000 --00 0000

— — — ENDP1 ENDP0 IN — — ---x xx-- ---u uu-- — — SEO PKT_DIS DEV_ATT RESUME SUSPND — --x0 000- --xq qqq- — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 -000 0000

— — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000 — — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000 — — — — EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000

Write Buffer for the upper 5 bits of the Program Counter

Value on:

---0 0000 ---0 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.

POR, BOR

Value on all other resets

(2)

DS41124C-page 20 Preliminary  2000 Microchip Technology Inc.

PIC16C745/765

TABLE 4-2: USB DUAL PORT RAM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

UOWN

1A0h BD0OST

1A1h BD0OBC 1A2h BD0OAL Buffer Address Low xxxx xxxx uuuu uuuu 1A3h

1A4h BD0IST

1A5h BD0IBC 1A6h BD0IAL Buffer Address Low xxxx xxxx uuuu uuuu 1A7h

1A8h BD1OST

1A9h BD1OBC 1AAh BD1OAL Buffer Address Low xxxx xxxx uuuu uuuu 1ABh

1ACh BD1IST

1ADh BD1IBC 1AEh BD1IAL Buffer Address Low xxxx xxxx uuuu uuuu 1AFh

1B0h BD2OST

1B1h BD2OBC 1B2h BD2OAL Buffer Address Low xxxx xxxx uuuu uuuu 1B3h

1B4h BD2IST

1B5h BD2IBC 1B6h BD2IAL Buffer Address Low xxxx xxxx uuuu uuuu 1B7h 1B8h-

1DFh

— Reserved — —

40 byte USB Buffer xxxx xxxx uuuu uuuu

DATA0/1

UOWN

DATA0/1