MICROCHIP PIC16C72 Technical data

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PIC16C72 SERIES

8-Bit CMOS Microcontrollers with A/D Converter

Devices included:

• PIC16C72

• PIC16CR72

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock input

• 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS technology

• Fully static design

• Wide operating voltage range:

- 2.5V to 6.0V (PIC16C72)

- 2.5V to 5.5V (PIC16CR72)

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 15 µ A typical @ 3V, 32 kHz

- < 1 µ A typical standby current

DC - 200 ns instruction cycle

Pin Diagrams

SDIP, SOIC, SSOP, Windowed Side Brazed Ceramic

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI RC2/CCP1

RC3/SCK/SCL

• 1 2 3 4 5 6 7

8 9 10 11 12 13 14

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7

RC6

RC5/SDO

RC4/SDI/SDA

PIC16C72

PIC16CR72

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Capture, Compare, PWM (CCP) module

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 8-bit 5-channel analog-to-digital converter

• Synchronous Serial Port (SSP) with



and I



SPI

• Brown-out detection circuitry for Brown-out Reset (BOR)

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 1



PIC16C72 Series

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 3

2.0 Memory Organization................................................................................................................................................................... 5

3.0 I/O Ports..................................................................................................................................................................................... 19

4.0 Timer0 Module ........................................................................................................................................................................... 25

5.0 Timer1 Module ........................................................................................................................................................................... 27

6.0 Timer2 Module ........................................................................................................................................................................... 31

7.0 Capture/Compare/PWM (CCP) Module..................................................................................................................................... 33

8.0 Synchronous Serial Port (SSP) Module..................................................................................................................................... 39

9.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 53

10.0 Special Features of the CPU...................................................................................................................................................... 59

11.0 Instruction Set Summary............................................................................................................................................................ 73

12.0 Development Support................................................................................................................................................................. 75

13.0 Electrical Characteristics - PIC16C72 Series............................................................................................................................. 77

14.0 DC and AC Characteristics Graphs and Tables - PIC16C72..................................................................................................... 97

15.0 DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ 107

16.0 Packaging Information.............................................................................................................................................................. 109

Appendix A: What’s New in this Data Sheet .................................................................................................................................. 115

Appendix B: What’s Changed in this Data Sheet........................................................................................................................... 115

Appendix C: Device Differences..................................................................................................................................................... 115

Index .................................................................................................................................................................................................. 117

On-Line Support................................................................................................................................................................................. 121

Reader Response.............................................................................................................................................................................. 122

PIC16C72 Series Product Identification System................................................................................................................................ 125

Sales and Support.............................................................................................................................................................................. 125

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

Key Reference Manual Features PIC16C72 PIC16CR72

Operating Frequency DC - 20MHz DC - 20MHz Resets POR, PWRT, OST, BOR POR, PWRT, OST, BOR Program Memory - (14-bit words) 2K (EPROM) 2K (ROM) Data Memory - RAM (8-bit bytes) 128 128 Interrupts 8 8 I/O Ports PortA, PortB, PortC PortA, PortB, PortC Timers Timer0, Timer1, Timer2 Timer0, Timer1, Timer2 Capture/Compare/PWM Modules 1 1 Serial Communications Basic SSP SSP 8-Bit A/D Converter 5 channels 5 channels Instruction Set (No. of Instructions) 35 35

DS39016A-page 2

Preliminary

1998 Microchip Technology Inc.



PIC16C72 Series

1.0 DEVICE OVERVIEW

This document contains device-speciﬁc information for the operation of the PIC16C72 device. Additional information may be found in the PICmicro™ Mid-Range MCU Reference Manual (DS33023) which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

The PIC16C72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1.

FIGURE 1-1: PIC16C72/CR72 BLOCK DIAGRAM

Program Counter

Direct Addr

Start-up Timer

8 Level Stack

(13-bit)

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

RAM Addr

Program

Bus

OSC1/CLKIN OSC2/CLKOUT

EPROM/

ROM

Program Memory

2K x 14

Instruction reg

Instruction Decode &

Control

Timing

Generation

The program memory contains 2K words which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes.

There are also 22 I/O pins that are user-conﬁgurable on a pin-to-pin basis. Some pins are multiplex ed with other device functions. These functions include:

• External interrupt

• Change on PORTB interrupt

• Timer0 clock input

• Timer1 clock/oscillator

• Capture/Compare/PWM

• A/D converter

• SPI/I

Table 1-1 details the pinout of the device with descriptions and details for each pin.

Data Bus

RAM

File

Registers

128 x 8

(1)

Addr MUX

FSR reg

STATUS reg

ALU

W reg

MUX

Indirect

Addr

PORTA

PORTB

PORTC

RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS

/AN4

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7

MCLR

VDD, VSS

Timer0

A/D

Timer1 Timer2

Synchronous

Serial Port

Note 1: Higher order bits are from the STATUS register.

1998 Microchip Technology Inc.

CCP1

Preliminary

DS39016A-page 3



PIC16C72 Series

TABLE 1-1 PIC16C72/CR72 PINOUT DESCRIPTION

Pin Name Pin#

OSC1/CLKIN 9 I OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal

MCLR

RA0/AN0 2 I/O TTL RA0 can also be analog input0. RA1/AN1 3 I/O TTL RA1 can also be analog input1. RA2/AN2 4 I/O TTL RA2 can also be analog input2. RA3/AN3/V RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is

RA5/SS/AN4

RB0/INT 21 I/O TTL/ST RB1 22 I/O TTL RB2 23 I/O TTL RB3 24 I/O TTL RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O TTL/ST RB7 28 I/O TTL/ST

RC0/T1OSO/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock

RC1/T1OSI 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1

RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both

RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 I/O ST RC7 18 I/O ST V V Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

REF

SS DD

— = Not used TTL = TTL input ST = Schmitt Trigger input

This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise

I/O/P Type

1 I/P ST Master clear (reset) input or programming voltage input. This pin is an

5 I/O TTL RA3 can also be analog input3 or analog reference voltage

7 I/O TTL RA5 can also be analog input4 or the slave select for the

8, 19 P — Ground reference for logic and I/O pins.

20 P — Positive supply for logic and I/O pins.

Buffer

Type

ST/CMOS

Description

(3)

Oscillator crystal input/external clock source input.

oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

active low reset to the device. PORTA is a bi-directional I/O port.

open drain type.

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.

(1)

(2) (2)

RB0 can also be the external interrupt pin.

Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

input.

output.

SPI and I

C modes.

data I/O (I

C mode).

DS39016A-page 4

Preliminary

1998 Microchip Technology Inc.



PIC16C72 Series

2.0 MEMORY ORGANIZATION

There are two memory blocks in PIC16C72 Series devices. These are the program memory and the data memory. Each block has its own bus, so that access to both blocks can occur during the same oscillator cycle.

The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.

Additional information on device memory may be found in the PICmicro™ Mid-Range Reference Manual, DS33023.

2.1 Pr

PIC16C72 Series devices have a 13-bit program counter capable of addressing a 2K x 14 program memory space. The address range for this program memory is 0000h - 07FFh. Accessing a location above the physically implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is at 0004h.

ogram Memory Organization

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK

PC<12:0>

CALL, RETURN RETFIE, RETLW

Space

User Memory

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

0000h

0004h 0005h

07FFh 0800h

1FFFh

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 5

PIC16C72 Series



2.2 Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.

RP1* RP0 (STATUS<6:5>)

= 00 → Bank0 = 01 → Bank1 = 10 → Bank2 (not implemented) = 11 → Bank3 (not implemented)

Maintain this bit clear to ensure upward compatibility with future products.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Abo v e the Special Function Registers are General Purpose Registers, implemented as static RAM.

All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access (ex; the STATUS register is in Bank 0 and Bank 1).

2.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly or indi-

rectly through the File Select Register FSR (Section 2.5).

FIGURE 2-2: REGISTER FILE MAP

File

Address

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

20h

(1)

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

ADRES

ADCON0

General Purpose Register

(1)

INDF

OPTION

PCL

STATUS

FSR TRISA TRISB TRISC

PCLATH INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

ADCON1

General Purpose Register

File

Address

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

A0h

BFh C0h

DS39016A-page 6

Preliminary

7Fh

Bank 0 Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

1998 Microchip Technology Inc.

FFh



PIC16C72 Series

2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

T ABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

(1)

00h

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register

(1)

02h

PCL Program Counter's (PC) Least Signiﬁcant Byte

(1)

03h

STATUS

(1)

04h

FSR Indirect data memory address pointer 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read 07h PORTC PORTC Data Latch when written: PORTC pins when read 08h 09h — Unimplemented — —

(1,2)

0Ah

(1)

0Bh 0Ch PIR1 0Dh 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register (LSB) 16h CCPR1H Capture/Compare/PWM Register (MSB) 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h-1Dh 1Eh ADRES A/D Result Register 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

— Unimplemented — —

PCLATH

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented — —

(4)

IRP

— — PORTA Data Latch when written: PORTA pins when read

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

RP1

(4)

RP0 T

O PD Z DC C 0001 1xxx 000q quuu

Value on:

xxxx xxxx uuuu uuuu 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

--0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.

POR, BOR

Value on all other resets

(3)

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 7

PIC16C72 Series

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_REG RBPU

(1)

82h

PCL Program Counter's (PC) Least Signiﬁcant Byte

(1)

83h

STATUS

(1)

84h

FSR Indirect data memory address pointer 85h TRISA 86h TRISB PORTB Data Direction Register 87h TRISC PORTC Data Direction Register 88h 89h — Unimplemented — —

(1,2)

8Ah

(1)

8Bh 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

— Unimplemented — —

PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(4)

IRP

— — PORTA Data Direction Register

(5)

RP1

CKE

(4)

RP0 T

(5)

D/A P S R/W UA BF 0000 0000 0000 0000

O PD Z DC C 0001 1xxx 000q quuu

Value on:

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

--11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.

POR, BOR

Value on all

other resets

(3)



DS39016A-page 8

Preliminary

1998 Microchip Technology Inc.

PIC16C72 Series

2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-3, contains

the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This lea v es the STATUS register as 000u u1uu (where u = unchanged).

O and PD bits are not

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register . For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: These devices do not use bits IRP and

RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borro

and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain

this bit clear.

bit 4: T

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borro

bit 0: C: Carry/borro

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borro second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

 1998 Microchip Technology Inc. Preliminary DS39016A-page 9

PIC16C72 Series

2.2.2.2 OPTION_REG REGISTER The OPTION_REG register is a readable and writable

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer.

able register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB .

FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS39016A-page 10 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

2.2.2.3 INTCON REGISTER The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the TMR0 register overﬂow, RB Port change and Exter nal RB0/INT pin interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

 1998 Microchip Technology Inc. Preliminary DS39016A-page 11

PIC16C72 Series

2.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the

peripheral interrupts.

FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt

0 = Disables the TMR1 overﬂow interrupt

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS39016A-page 12 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

2.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bits for the

Peripheral interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software)

0 = TMR1 register did not overﬂow

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

 1998 Microchip Technology Inc. Preliminary DS39016A-page 13

PIC16C72 Series

2.2.2.6 PCON REGISTER The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset (POR) to an external MCLR Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition.

Reset or WDT Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked on subsequent resets to see if BOR clear, indicating a brown-out has occurred. The BOR not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

status bit is a don't care and is

FIGURE 2-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR BOR R = Readable bit

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

bit 0: BOR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS39016A-page 14 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

2.3 PCL and PCLATH

The program counter (PC) speciﬁes the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.

Figure 2-9 shows the four situations for the loading of the PC. Example 1 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH<4:3> → PCH). Example 3 shows ho w the PC is loaded during a CALL instruction (PCLATH<4:3> → PCH), with the PC loaded (PUSHed) onto the Top of Stack. Finally, example 4 shows how the PC is loaded during one of the return instructions where the PC is loaded (POPed) from the Top of Stack.

FIGURE 2-9: LOADING OF PC IN DIFFERENT SITUATIONS

Situation 1 - Instruction with PCL as destination

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

ALU result

Situation 2 - GOTO Instruction

PCH PCL

12 11 10 0

8 7

PCLATH<4:3>

PCLATH

Opcode <10:0>

STACK (13-bits x 8)

Top of STACK

STACK (13-bits x 8)

Top of STACK

Situation 3 - CALL Instruction

PCH PCL

12 11 10 0

8 7

PCLATH<4:3>

PCLATH

Opcode <10:0>

Situation 4 - RETURN, RETFIE, or RETLW Instruction

PCH PCL

12 11 10 0

8 7

PCLATH

Opcode <10:0>

STACK (13-bits x 8)

Top of STACK

STACK (13-bits x 8)

Top of STACK

Note: PCLATH is not updated with the contents of PCH.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 15

PIC16C72 Series

2.3.1 STACK The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return address from this branch in program execution.

Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modiﬁed when the stack is PUSHed or POPed.

After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on). An example of the overwriting of the stack is shown in Figure 2-10.

FIGURE 2-10: STACK MODIFICATION

STACK

Push1 Push9 Push2 Push10 Push3 Push4

Push5 Push6 Push7 Push8

Top of STACK

2.4 Program Memory Paging

The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack).

Note: PIC16C72 Series devices ignore paging

bit PCLATH<4>. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.

DS39016A-page 16 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 2-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

FIGURE 2-11: DIRECT/INDIRECT ADDRESSING

RP1:RP0 6

(2)

bank select location select

from opcode

00 01 10 11

00h

80h

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ; to RAM NEXT clrf INDF ;clear INDF register incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;NO, clear next CONTINUE : ;YES, continue

An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (ST ATUS<7>), as shown in Figure 2-11. However, IRP is not used in the PIC16C72 Series.

Indirect AddressingDirect Addressing

(2)

bank select

location select

100h

IRP FSR register

180h

not used

Data Memory(1)

7Fh

FFh

(3) (3)

17Fh

1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Note 1: For register ﬁle map detail see Figure 2-2.

2: Maintain RP1 and IRP as clear for upward compatibility with future products. 3: Not implemented.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 17

PIC16C72 Series

NOTES:

DS39016A-page 18 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

3.1 PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional por t. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs and analog V selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

Note: On a Power-on Reset, these pins are con-

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ; CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'.

REF input. The operation of each pin is

ﬁgured as analog inputs and read as '0'.

FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

Data bus

WR Port

WR TRIS

RD PORT

To A/D Converter

Note 1: I/O pins have protection diodes to VDD and

VSS.

Data Latch

TRIS Latch

RD TRIS

Analog input mode

Q D

VDD

I/O pin

TTL input buffer

FIGURE 3-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger input buffer

Q D

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to V

 1998 Microchip Technology Inc. Preliminary DS39016A-page 19

SS only.

PIC16C72 Series

TABLE 3-1 PORTA FUNCTIONS

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2 bit2 TTL Input/output or analog input RA3/AN3/V RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

RA5/SS Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

REF bit3 TTL Input/output or analog input or VREF

Output is open drain type

/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input

Value on:

POR,

BOR

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Value on all

other resets

DS39016A-page 20 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin.

EXAMPLE 3-1: INITIALIZING PORTB

BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION<7>). The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disab led on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

TTL Input Buffer

DD and VSS.

weak

pull-up

RD Port

I/O pin

(2)

RBPU

Data bus

WR Port

WR TRIS

RB0/INT

Note 1: I/O pins have diode protection to V

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

Data Latch

TRIS Latch

RD TRIS

RD Port

Schmitt Trigger Buffer

bit (OPTION<7>).

Q D

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 3-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Latch

TTL Input Buffer

weak pull-up

I/O pin

Buffer

RD Port

(1)

(2)

RBPU

Data bus

WR Port

(1)

WR TRIS

Set RBIF

From other RB7:RB4 pins

RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

Data Latch

TRIS Latch

RD TRIS

RD Port

Q D

bit (OPTION<7>).

 1998 Microchip Technology Inc. Preliminary DS39016A-page 21

PIC16C72 Series

TABLE 3-3 PORTB FUNCTIONS

Name Bit# Buffer Function

(1)

RB0/INT bit0 TTL/ST

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

RB6 bit6 TTL/ST

RB7 bit7 TTL/ST

Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

Input/output pin or external interrupt input. Internal software programmable weak pull-up.

weak pull-up.

(2)

Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock.

(2)

Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data.

Value on:

POR, BOR

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Value on all other resets

DS39016A-page 22 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

3.3 PORTC and the TRISC Register

PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin.

PORTC is multiplex ed with se ver al peripheral functions (T ab le 3-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in deﬁning TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

EXAMPLE 3-1: INITIALIZING PORTC

BCF STATUS, RP0 ; Select Bank 0 CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs

FIGURE 3-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT OVERRIDE)

PORT/PERIPHERAL Select Peripheral Data Out

Data bus

WR PORT

WR TRIS

Peripheral

(3)

Peripheral input

Note 1: I/O pins have diode protection to VDD and VSS.

Data Latch

TRIS Latch

RD TRIS

RD PORT

2: Port/Peripheral select signal selects between port

data and peripheral output.

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

(2)

Schmitt Trigger

VSS

I/O pin

QD Q

Q D

(1)

 1998 Microchip Technology Inc. Preliminary DS39016A-page 23

PIC16C72 Series

TABLE 3-5 PORTC FUNCTIONS

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1

RC3/SCK/SCL bit3 ST

RC4/SDI/SDA bit4 ST RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output

RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input

TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged.

bit0

ST Input/output port pin or Timer1 oscillator output/Timer1 clock input

output RC3 can also be the synchronous serial clock for both SPI and I

modes.

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

Value on:

POR, BOR

C mode).

Value on all

other resets

DS39016A-page 24 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

4.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• Internal or external clock select

• Edge select for external clock

• 8-bit software programmable prescaler

• Interrupt on overﬂow from FFh to 00h Figure 4-1 is a simpliﬁed block diagram of the Timer0

module. Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

4.1 Timer0 Operation

Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is wr itten, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in below.

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T incrementing of Timer0 after synchronization.

OSC). Also, there is a delay in the actual

Additional information on external clock requirements is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

4.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually e xclusiv ely shared betw een the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable.

Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When assigned

to WDT , a CLRWDT instruction will clear the prescaler along with the WDT.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

FIGURE 4-1: TIMER0 BLOCK DIAGRAM

PSout

Data bus

TMR0

Set interrupt ﬂag bit T0IF

on overﬂow

T0CS

Programmable

Prescaler

PS2, PS1, PS0

PSA

PSout

Sync with

Internal

clocks

(2 cycle delay)

RA4/T0CKI pin

FOSC/4

T0SE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).

 1998 Microchip Technology Inc. Preliminary DS39016A-page 25

PIC16C72 Series

4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

Note: To avoid an unintended device RESET, a

speciﬁc instruction sequence (shown in the PICmicro™ Mid-Range MCU Reference Manual, DS3023) must be executed when changing the prescaler assignment from

4.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interr upt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.

Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (=Fosc/4)

RA4/T0CKI

Watchdog

Timer

T0SE

U X

T0CS

M U

PSA

8-bit Prescaler

8 - to - 1MUX

PSA

SYNC

Cycles

PS2:PS0

Data Bus

TMR0 reg

Set ﬂag bit T0IF

on Overﬂow

M U X

WDT

Time-out

PSA

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh,

10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

DS39016A-page 26 Preliminary  1998 Microchip Technology Inc.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Value on:

POR, BOR

Value on all

other resets

PIC16C72 Series

5.0 TIMER1 MODULE

The Timer1 module timer/counter has the following features:

• 16-bit timer/counter

(Two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (Both registers)

• Internal or external clock select

• Interrupt on overﬂow from FFFFh to 0000h

• Reset from CCP module trigger Timer1 has a control register, shown in Figure 5-1.

Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).

Figure 5-2 is a simpliﬁed block diagram of the Timer1 module.

Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

5.1 Timer1 Operation

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction

cycle. In counter mode, it increments on every rising edge of the external clock input.

When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.

Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 7.0).

FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain

bit 2: T1SYNC

: Timer1 External Clock Input Synchronization Control bit

R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (F

bit 0: TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

 1998 Microchip Technology Inc. Preliminary DS39016A-page 27

OSC/4)

PIC16C72 Series

FIGURE 5-2: TIMER1 BLOCK DIAGRAM

Set ﬂag bit TMR1IF on Overﬂow

RC0/T1OSO/T1CKI

RC1/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

TMR1H

T1OSC

TMR1

TMR1L

T1OSCEN Enable

Oscillator

(1)

FOSC/4

Internal

Clock

TMR1ON

on/off

TMR1CS

T1SYNC

Prescaler

1, 2, 4, 8

T1CKPS1:T1CKPS0

Synchronized

clock input

Synchronize

det

SLEEP input

DS39016A-page 28 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

5.2 Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (ampliﬁer output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.

TABLE 5-1 CAPACITOR SELECTION

FOR THE TIMER1 OSCILLATOR

5.3 Timer1 Interrupt

The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overﬂow which is latched in interrupt ﬂag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

5.4 Resetting Timer1 using a CCP Trigger Output

If the CCP module is conﬁgured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled).

Note: The special event triggers from the CCP1

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up

Timer1 must be conﬁgured for either timer or synchronized counter mode to take advantage of this f eature. If Timer1 is running in asynchronous counter mode, this reset operation may not work.

In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.

In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 8Ch PIE1 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: These bits are unimplemented, read as '0'.

(1)

ADIF

(1)

ADIE

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE

Value on:

POR, BOR

0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--00 0000 --uu uuuu

Value on all other

resets

 1998 Microchip Technology Inc. Preliminary DS39016A-page 29

PIC16C72 Series

NOTES:

DS39016A-page 30 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

6.0 TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (Both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to generate clock shift

Timer2 has a control register, shown in Figure 6-2. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption.

Figure 6-1 is a simpliﬁed block diagram of the Timer2 module.

Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

6.1 Timer2 Operation

Timer2 can be used as the PWM time-base for PWM mode of the CCP module.

The TMR2 register is readable and writable, and is cleared on any device reset.

The input clock (F 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in ﬂag bit TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

OSC/4) has a prescale option of 1:1,

reset,

6.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.

6.3 Output of TMR2

The output of TMR2 (before the postscaler) is f ed to the Synchronous Serial Port module which optionally uses it to generate shift clock.

FIGURE 6-1: TIMER2 BLOCK DIAGRAM

Sets ﬂag bit TMR2IF

Note 1: TMR2 register output can be software selected

TMR2

(1)

output

Reset

TMR2 reg

Postscaler

1:1 1:16

by the SSP Module as a baud clock.

Comparator

PR2 reg

Prescaler

1:1, 1:4, 1:16

OSC/4

 1998 Microchip Technology Inc. Preliminary DS39016A-page 31

PIC16C72 Series

FIGURE 6-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale 0001 = 1:2 Postscale

•

• 1111 = 1:16 Postscale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE 0Ch PIR1 8Ch PIE1 11h TMR2 Timer2 module’s register 12h T2CON 92h PR2 Timer2 Period Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

2: These bits are unimplemented, read as '0'.

(1)

ADIF

(1)

ADIE

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

T0IE INTE RBIE T0IF INTF RBIF

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

Value on:

POR,

BOR

0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

-000 0000 -000 0000 1111 1111 1111 1111

Value on all other

resets

DS39016A-page 32 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

7.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes.

Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.

Additional information on the CCP module is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

T ABLE 7-1 CCP MODE - TIMER

RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Signiﬁcant bits

Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D

conversion (if A/D module is enabled))

11xx = PWM mode

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

Timer1 Timer1 Timer2

 1998 Microchip Technology Inc. Preliminary DS39016A-page 33

PIC16C72 Series

7.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an e vent occurs on pin RC2/CCP1. An event is deﬁned as:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the interrupt request ﬂag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost.

7.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be conﬁg-

ured as an input by setting the TRISC<2> bit.

Note: If the RC2/CCP1 is conﬁgured as an out-

put, a write to the port can cause a capture condition.

FIGURE 7-2: CAPTURE MODE

OPERATION BLOCK DIAGRAM

Set ﬂag bit CCP1IF

(PIR1<2>)

CCP1CON<3:0>

CCPR1H CCPR1L

Capture Enable

TMR1H TMR1L

RC2/CCP1 Pin

Prescaler ÷ 1, 4, 16

and

edge detect

Q’s

7.1.4 CCP PRESCALER There are four prescaler settings, speciﬁed by bits

CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter.

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the ﬁrst capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 7-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; mode value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value

7.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work.

7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the ﬂag bit CCP1IF following any such change in operating mode.

DS39016A-page 34 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

7.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:

• driven High

• driven Low

• remains Unchanged

The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt ﬂag bit CCP1IF is set.

FIGURE 7-3: COMPARE MODE

OPERATION BLOCK DIAGRAM

7.2.1 CCP PIN CONFIGURATION The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the default low level. This is not the data latch.

7.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

7.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1

Special event trigger will: reset Timer1, but not set interrupt ﬂag bit TMR1IF (PIR1<0>), and set bit GO/DONE which starts an A/D conversion

RC2/CCP1 Pin

TRISC<2>

Output Enable

(ADCON0<2>)

Special Event Trigger

Q S

Output

Logic

CCP1CON<3:0> Mode Select

Set ﬂag bit CCP1IF (PIR1<2>)

CCPR1H CCPR1L

match

TMR1H TMR1L

Comparator

pin is not affected. Only a CCP interrupt is generated (if enabled).

7.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated

which may be used to initiate an action. The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmab le period register for Timer1.

The special trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled).

Note: The special event trigger from the CCP1

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

TABLE 7-2 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 8Ch PIE1 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits/registers are unimplemented, read as '0'.

(1)

ADIF

(1)

ADIE

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on:

POR, BOR

Value on

all other

resets

 1998 Microchip Technology Inc. Preliminary DS39016A-page 35

PIC16C72 Series

7.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the POR TC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.

Figure 7-4 shows a simpliﬁed block diagram of the CCP module in PWM mode.

For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3.

FIGURE 7-4: SIMPLIFIED PWM BLOCK

DIAGRAM

Clear Timer, CCP1 pin and latch D.C.

CCP1CON<5:4>

RC2/CCP1

TRISC<2>

Duty cycle registers

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

(Note 1)

A PWM output (Figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

FIGURE 7-5: PWM OUTPUT

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

7.3.1 PWM PERIOD The PWM period is speciﬁed by writing to the PR2 reg-

ister. The PWM period can be calculated using the following formula:

PWM period = [(PR2) + 1] ¥ 4 ¥ T

OSC ¥

(TMR2 prescale value)

PWM frequency is deﬁned as 1 / [PWM period]. When TMR2 is equal to PR2, the following three ev ents

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into CCPR1H

Note: The Timer2 postscaler (see Section 6.0) is

not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.

7.3.2 PWM DUTY CYCLE

The PWM duty cycle is speciﬁed by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) ¥ Tosc ¥ (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle . This double buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM frequency:

OSC

PWM

)

bits

log(

log(2)

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be cleared.

DS39016A-page 36 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

For an example PWM period and duty cycle calculation, see the PICmicro™ Mid-Range MCU Reference Manual (DS33023).

7.3.3 SET-UP FOR PWM OPERATION

3. Make the CCP1 pin an output by clearing the TRISC<2> bit.

4. Set the TMR2 prescale value and enab le Timer2 by writing to T2CON.

5. Conﬁgure the CCP1 module for PWM operation.

The following steps should be taken when conﬁguring the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

T ABLE 7-3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5

TABLE 7-4 REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE 0Ch PIR1 8Ch PIE1

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s period register 1111 1111 1111 1111 12h T2CON

(1)

ADIF

(1)

ADIE

— TOUTPS3TOUTPS2TOUTPS1TOUTPS0TMR2ONT2CKPS1T2CKPS0-000 0000 -000 0000

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on:

POR,

BOR

Value on

all other

resets

15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.

Note 1: These bits/registers are unimplemented, read as '0'.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 37

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

PIC16C72 Series

NOTES:

DS39016A-page 38 Preliminary  1998 Microchip Technology Inc.

8.0 SYNCHRONOUS SERIAL

PORT (SSP) MODULE

8.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

The SSP module in I PIC16C72 series devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C72 and the PIC16CR72 device.

The register deﬁnitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C72 and the PIC16CR72 device. The default reset values of both the SPI modules is the same regardless of the device:

8.2 SPI Mode for PIC16C72..................................40

8.3 SPI Mode for PIC16CR72 ............................... 43

8.4 SSP I

For an I Range MCU Reference Manual (DS33023). Also, refer to Application Note AN578,

the I

C Operation .......................................... 47

C Overview, refer to the PICmicro™ Mid-

C Multi-Master Environment.”

C mode works the same in all

“Use of the SSP Module in

PIC16C72 Series

 1998 Microchip Technology Inc. Preliminary DS39016A-page 39

PIC16C72 Series

8.2 SPI Mode for PIC16C72

This section contains register deﬁnitions and operational characteristics of the SPI module on the PIC16C72 device only.

Additional information on SPI operation may be found in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16C72)

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — D/A P S R/W UA BF R = Readable bit

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

bit 3: S: Start bit (I

1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

bit 2: R/W

This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or A 1 = Read 0 = Write

bit 1: UA: Update Address (10-bit I

1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0: BF: Buffer Full Status bit

Receiv 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)

: Read/Write bit information (I2C mode only)

CK bit.

C mode only)

e (SPI and I2C modes)

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

DS39016A-page 40 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16C72)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Detect bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overﬂow, the data in SSPSR register is lost. Overﬂow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master operation, the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overﬂow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

C mode

In I 1 = Enables the serial port and conﬁgures the SDA and SCL pins as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins In both modes, when enabled, these pins must be properly conﬁgured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.

C mode

In I SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master operation, clock = Fosc/4 0001 = SPI master operation, clock = Fosc/16 0010 = SPI master operation, clock = Fosc/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS 0101 = SPI slave mode, clock = SCK pin. SS

0110 = I 0111 = I 1011 = I 1110 = I 1111 = I

C slave mode, 7-bit address

C slave mode, 10-bit address

C firmware controlled master operation (slave idle)

C slave mode, 7-bit address with start and stop bit interrupts enabled

C slave mode, 10-bit address with start and stop bit interrupts enabled

pin control enabled. pin control disabled. SS can be used as I/O pin.

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

 1998 Microchip Technology Inc. Preliminary DS39016A-page 41

PIC16C72 Series

8.2.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16C72

A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3.

• SCK (Slave mode) must have TRISC<3> set

• SS

must have TRISA<5> set (if implemented)

FIGURE 8-3: SSP BLOCK DIAGRAM

(SPI MODE)

The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

Read Write

Internal

data bus

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

SSPBUF reg

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS

When initializing the SPI, several options need to be speciﬁed. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>). These control bits allow the following to be speciﬁed:

• Master Operation (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Output/Input data on the Rising/

Falling edge of SCK)

• Clock Rate (master operation only)

• Slave Select Mode (Slave mode only)

To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is:

• SDI must have TRISC<4> set

) RA5/SS/AN4

pins as serial port

RC4/SDI/SDA

RC5/SDO

RA5/SS

/AN4

RC3/SCK/ SCL

bit0

Control

Enable

Edge

Select

SSPM3:SSPM0

Edge

Select

TRISC<3>

SSPSR reg

Clock Select

shift

clock

TMR2 output

Prescaler

4, 16, 64

• SDO must have TRISC<5> cleared

• SCK (master operation) must have TRISC<3>

cleared

TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 8Ch PIE1

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSP-

STAT

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are unimplemented, read as '0'.

(1)

ADIF

(1)

ADIE

— — D/A P S R/W UA BF --00 0000 --00 0000

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on:

POR,

BOR

Value on all other

resets

DS39016A-page 42 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

8.3 SPI Mode for PIC16CR72

This section contains register deﬁnitions and operational characteristics of the SPI module on the PIC16CR72 device only.

Additional information on SPI operation may be found in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

FIGURE 8-4: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16CR72)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

bit7 bit0

bit 7: SMP: SPI data input sample phase

SPI

Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Sla

ve Mode

SMP must be cleared when SPI is used in slave mode

bit 6: CKE: SPI Clock Edge Select

CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK

bit 5: D/A

bit 4: P: Stop bit (I

bit 3: S: Start bit (I

bit 2: R/W

bit 1: UA: Update Address (10-bit I

bit 0: BF: Buffer Full Status bit

: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or A 1 = Read 0 = Write

1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

e (SPI and I2C modes)

Receiv 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

P S R/W UA BF R = Readable bit

C mode only. This bit is cleared when the SSP module is disabled, or when the Star t bit is

C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is

CK bit.

C mode only)

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

 1998 Microchip Technology Inc. Preliminary DS39016A-page 43

PIC16C72 Series

FIGURE 8-5: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16CR72)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Indicator bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overﬂow, the data in SSPSR is lost. Overﬂow can only occur in slave mode. The user must read the SSPBUF , even if only transmitting data, to avoid setting overﬂow. In master operation, the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

C mode

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level

In I

C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master operation, clock = F 0001 = SPI master operation, clock = F 0010 = SPI master operation, clock = F

OSC/4 OSC/16 OSC/64

0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS 0101 = SPI slave mode, clock = SCK pin. SS

0110 = I

C slave mode, 7-bit address

0111 = I

C slave mode, 10-bit address

1011 = I

C firmware controlled master operation (slave idle)

1110 = I

C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I

C slave mode, 10-bit address with start and stop bit interrupts enabled

pin control enabled. pin control disabled. SS can be used as I/O pin

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

DS39016A-page 44 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

8.3.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16CR72

A block diagram of the SSP Module in SPI Mode is shown in Figure 8-6.

The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS

) RA5/SS/AN4

When initializing the SPI, several options need to be speciﬁed. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be speciﬁed:

• Master Operation (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock Edge (Output data on rising/falling edge of

SCK)

• Clock Rate (master operation only)

• Slave Select Mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (master operation) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

• SS

must have TRISA<5> set

Note: When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS to V

DD.

pin is set

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS

pin control must be

enabled.

FIGURE 8-6: SSP BLOCK DIAGRAM

(SPI MODE)(PIC16CR72)

Internal

data bus

Read Write

SSPBUF reg

RC4/SDI/SDA

RC5/SDO

S/AN4

RA5/S

RC3/SCK/ SCL

bit0

Control

Enable

Edge

Select

SSPM3:SSPM0

Edge

Select

TRISC<3>

SSPSR reg

Clock Select

shift

clock

TMR2 output

Prescaler

4, 16, 64

 1998 Microchip Technology Inc. Preliminary DS39016A-page 45

PIC16C72 Series

TABLE 8-2 REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16CR72)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 8Ch PIE1

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Always maintain these bits clear.

(1)

ADIF

(1)

ADIE

(1) (1) (1) (1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on:

POR,

BOR

Value on all other

resets

DS39016A-page 46 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

8.4 SSP I2C Operation

The SSP module in I2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ﬁrmware implementations of the master functions. The SSP module implements the standard mode speciﬁcations as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must conﬁgure these pins as inputs or outputs through the TRISC<4:3> bits.

The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>).

FIGURE 8-7: SSP BLOCK DIAGRAM

(I2C MODE)

Internal

data bus

Read Write

shift

clock

SSPBUF reg

SSPSR reg

MSb

Match detect

SSPADD reg

Start and

Stop bit detect

LSb

(SSPSTAT reg)

Addr Match

Set, Reset S, P bits

RC3/SCK/SCL

RC4/

SDI/ SDA

The SSP module has ﬁve registers for I2C operation. These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces-

sible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I

C Slave mode (7-bit address)

• I

C Slave mode (10-bit address)

• I

C Slave mode (7-bit address), with start and

stop bit interrupts enabled

• I

C Slave mode (10-bit address), with start and

stop bit interrupts enabled

• I

C Firmware controlled master operation, slave

C modes to be selected:

C opera-

is idle

Selection of any I

C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

Additional information on SSP I

C operation may be found in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

8.4.1 SLAVE MODE In slave mode, the SCL and SDA pins must be conﬁg-

ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (A

CK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.

There are certain conditions that will cause the SSP module not to give this A

CK pulse. These are if either

(or both): a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The ov erﬂow bit SSPO V (SSPCON<6>) w as set

before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 8-3 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overﬂow condition. Flag bit BF is cleared by reading the SSPB UF register while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low for proper operation. The high and low times of the

C speciﬁcation as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 47

PIC16C72 Series

8.4.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register. b) The buffer full bit, BF is set. c) An A d) SSP interrupt ﬂag bit, SSPIF (PIR1<3>) is set

In 10-bit address mode, two address bytes need to be received by the slave. The ﬁve Most Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. Bit R/W so the slave device will receive the second address byte. For a 10-bit address the ﬁrst byte would equal

CK pulse is generated.

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse.

(SSPSTAT<2>) must specify a write

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 f or slav e-transmitter:

1. Receive ﬁrst (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line).

3. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

4. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set).

5. Update the SSP ADD register with the ﬁrst (high) byte of Address, if match releases SCL line, this will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (bits SSPIF and BF are set).

9. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

TABLE 8-3 DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

BF SSPOV

0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes

SSPSR

→ SSPBUF

Generate A

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

DS39016A-page 48 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

8.4.1.2 RECEPTION When the R/W

address match occurs, the R/W

bit of the address byte is clear and an

bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.

When the address byte overﬂow condition exists, then no acknowledge (A dition is deﬁned as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.

FIGURE 8-8: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Receiving Address

A7 A6 A5 A4

1 234

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

R/W=0

A3 A2 A1SDA

Receiving Data D5

D6D7

1 2

Cleared in software

SSPBUF register is read

Bit SSPOV is set because the SSPBUF register is still full.

D3D4

5 6

8 9

D6D7

1 2 3

CK) pulse is given. An o verﬂo w con-

Receiving Data

D3D4

ACK is not sent.

Bus Master terminates transfer

 1998 Microchip Technology Inc. Preliminary DS39016A-page 49

PIC16C72 Series

8.4.1.3 TRANSMISSION When the R/W

and an address match occurs, the R/W

bit of the incoming address byte is set

bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The A

CK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices ma y be holding off the master b y stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SD A signal is valid during the SCL high time (Figure 8-9).

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse.

As a slave-transmitter, the A receiver is latched on the rising edge of the ninth SCL input pulse. If the SD A line was high (not A data transfer is complete. When the A the slave, the slav e logic is reset (resets SSPSTA T register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (A the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 8-9: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>) BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

Data in sampled

SCL held low while CPU

responds to SSPIF

cleared in software

SSPBUF is written in software

Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set)

CK pulse from the master-

CK), then the

CK is latched by

CK),

CKTransmitting DataR/W = 1Receiving Address

From SSP interrupt service routine

DS39016A-page 50 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

8.4.2 MASTER OPERATION Master operation is supported in ﬁrmware using inter-

rupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of

the I

C bus may be taken when the P bit is set, or the

bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manip-

ulated in ﬁrmware by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit.

The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received Master operation can be done with either the slave

mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt.

For more information on master operation, see

- Software Implementation of I

C Bus Master

AN554

8.4.3 MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on

the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and ST AR T (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high le vel is e xpected and a low le v el is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer When the slave logic is enabled, the slave continues to

receive. If arbitr ation was lost during the address transfer stage, communication to the device may be in progress. If addressed an A

CK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.

For more information on master operation, see

- Use of the SSP Module in the of I Environment

TABLE 8-4 REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh, 8Bh, 10Bh,18Bh

0Ch 8Ch 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 94h SSPSTAT SMP 87h TRISC

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Note 1: These bits are unimplemented, read as '0'.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

PIR1 PIE1

Shaded cells are not used by SSP module in SPI mode.

2: The SMP and CKE bits are implemented on the PIC16CR72 only. On the PIC16C72, these two bits are unimplemented,

read as '0'.

(1)

ADIF

(1)

ADIE

(2)

CKE

PORTC Data Direction register

(1) (1)

(2)

D/A P S R/W UA BF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on

POR, BOR

0000 000x 0000 000u

xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

1111 1111 1111 1111

AN578

C Multi-Master

Value on

all other

resets

 1998 Microchip Technology Inc. Preliminary DS39016A-page 51

PIC16C72 Series

NOTES:

DS39016A-page 52 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has ﬁve inputs for the PIC16C72/R72.

The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’ s positive supply v oltage (V or the voltage level on the RA3/AN3/V

The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

REF pin.

DD)

Additional information on the A/D module is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.

The A/D module has three registers. These registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted.

The ADCON0 register, shown in Figure 9-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 9-2, conﬁgures the functions of the port pins. The port pins can be conﬁgured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.

FIGURE 9-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an internal RC oscillator)

bit 5-3: CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4)

bit 2: GO/DONE

If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

: A/D Conversion Status bit

— ADON R =Readable bit

W =Writable bit U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

 1998 Microchip Technology Inc. Preliminary DS39016A-page 53

PIC16C72 Series

FIGURE 9-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

bit7 bit0

bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Conﬁguration Control bits

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF

000 A A A A A VDD 001 A A A A VREF RA3 010 A A A A A V 011 A A A A VREF RA3 100 A A D D A V 101 A A D D VREF RA3 11x D D D D D GND

A = Analog input D = Digital I/O

W =Writable bit U =Unimplemented

- n = Value at POR reset

bit, read as ‘0’

DS39016A-page 54 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit ADIF is set. The block diagram of the A/D module is shown in Figure 9-3.

The value that is in the ADRES register is not modiﬁed for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.

After the A/D module has been conﬁgured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 9.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference / and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

FIGURE 9-3: A/D BLOCK DIAGRAM

VAIN

(Input voltage)

A/D

Converter

VREF

(Reference

voltage)

PCFG2:PCFG0

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is deﬁned as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

CHS2:CHS0

100

011

010

001

000 or 010 or 100

001 or 011 or 101

000

RA5/AN4

RA3/AN3/V

RA2/AN2

RA1/AN1

RA0/AN0

REF

 1998 Microchip Technology Inc. Preliminary DS39016A-page 55

PIC16C72 Series

9.1 A/D Acquisition Requirements

For the A/D converter to meet its speciﬁed accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-4. The source impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the capacitor C impedance varies over the device voltage (V

HOLD. The sampling switch (RSS)

DD). The

source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum

recommended impedance for analog sources is 10 kΩ. After the analog input channel is selected

(changed) this acquisition must be done before the conversion can be started.

FIGURE 9-4: ANALOG INPUT MODEL

VDD

Legend CPIN

VT I leakage

R SS C

ANx

CPIN 5 pF

= input capacitance = threshold voltage

= leakage current at the pin due to

various junctions

= interconnect resistance

= sampling switch = sample/hold capacitance (from DAC)

HOLD

VT = 0.6V

T = 0.6V

To calculate the minimum acquisition time, T

ACQ, see

the PICmicro™ Mid-Range MCU Reference Manual, DS33023. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its speciﬁed accuracy.

Sampling Switch

IC ≤ 1k

I leakage ± 500 nA

CHOLD = DAC capacitance = 51.2 pF

6V 5V

4V 3V 2V

5 6 7 8 9 10 11

Sampling Switch

( kΩ )

DS39016A-page 56 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

9.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The A/D conversion requires 9.5T The source of the A/D conversion clock is software selectable. The four possible options for T

OSC

• 2T

• 8TOSC

• 32TOSC

• Internal RC oscillator

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of 1.6 µs. Table 9-1 shows the resultant T

the device operating frequencies and the A/D clock source selected.

AD per 8-bit conversion.

AD are:

AD times derived from

9.3 Configuring Analog Port Pins

The ADCON1, TRISA, and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

Note 1: When reading the por t register, all pins

conﬁgured as analog input channels will read as cleared (a low level). Pins conﬁgured as digital inputs, will convert an analog input. Analog levels on a digitally conﬁgured input will not affect the conversion accuracy.

OH or VOL) will be

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices speciﬁcation.

TABLE 9-1 TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD) Device Frequency

Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz

OSC 00

2T 8TOSC 01

100 ns 400 ns

(2) (2)

32TOSC 10 1.6 µs 6.4 µs RC

(5)

2 - 6 µs

(1,4)

Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical T

2: These values violate the minimum required T

AD time of 4 µs.

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

(2)

400 ns

1.6 µs 6.4 µs

25.6 µs

(1,4)

2 - 6 µs

1.6 µs 6 µs 24 µs

(3)

(1,4)

96 µs

2 - 6 µs

(3) (3)

(1)

 1998 Microchip Technology Inc. Preliminary DS39016A-page 57

PIC16C72 Series

9.4 A/D Conversions

GO/DONE

bit will be set, starting the A/D conversion,

and the Timer1 counter will be reset to zero. Timer1 is

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

9.5 Use of the CCP Trigger

An A/D conversion can be started by the “special e v ent trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the

reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE

bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter.

TABLE 9-2 REGISTERS/BITS ASSOCIATED WITH A/D

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh 0Ch 8Ch 1Eh 1Fh 9Fh 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 85h TRISA — — PORTA Data Direction Register

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PIR1 PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 ADRES A/D Result Register xxxx xxxx uuuu uuuu ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

Value on:

POR, BOR

--0x 0000 --0u 0000

--11 1111 --11 1111

Value on all

other Resets

DS39016A-page 58 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

10.0 SPECIAL FEATURES OF THE CPU

The PIC16C72 series has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-Circuit Serial Programming™

The PIC16CXXX family has a Watchdog Timer which can be shut off only through conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is sta-

ble. The other is the Power-up Timer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Sev er al oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

Additional information on special features is availab le in the PICmicro™ Mid-Range MCU Family Reference Manual, DS33023.

10.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/conﬁguration memory space (2000h 3FFFh), which can be accessed only during programming.

FIGURE 10-1: CONFIGURATION WORD FOR PIC16C72/R72

CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit13 bit0

bit 13-8 CP1:CP0: Code Protection bits 5-4: 11 = Code protection off

10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected

bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit

1 = BOR enabled 0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWR

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 59

(2)

(1)

TE.

PIC16C72 Series

10.2 Oscillator Conﬁgurations

10.2.1 OSCILLATOR TYPES The PIC16CXXX family can be operated in four differ-

ent oscillator modes. The user can program two conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

10.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP or HS modes a cr ystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 10-2). The PIC16CXXX family oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 10-3).

FIGURE 10-2: CRYSTAL/CERAMIC

RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

(1)

XTAL

(2)

OSC1

OSC2

(3)

internal logic

SLEEP

PIC16CXXX

Note1: See Table 10-1 and Table 10-2 for recom-

mended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen.

FIGURE 10-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

Clock from ext. system

Open

OSC1

PIC16CXXX

OSC2

TABLE 10-1 CERAMIC RESONATORS

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

These values are for design guidance only. See notes at bottom of page.

68 - 100 pF 15 - 68 pF 15 - 68 pF

10 - 68 pF 10 - 22 pF

68 - 100 pF 15 - 68 pF 15 - 68 pF

10 - 68 pF 10 - 22 pF

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

TABLE 10-2 CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

Osc Type

LP 32 kHz 33 pF 33 pF

XT 200 kHz 47-68 pF 47-68 pF

HS 4 MHz 15 pF 15 pF

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EPSON CA-301 20.000M-C ± 30 PPM

Crystal

Freq

200 kHz 15 pF 15 pF

1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design guidance only. See notes at bottom of page.

Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 10-1).

2: Higher capacitance increases the stability

of oscillator but also increases the start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

4: Rs may be required in HS mode as well as

XT mode to avoid overdriving crystals with low drive level speciﬁcation.

Cap. Range C1Cap. Range

Crystals Used

DS39016A-page 60 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

10.2.3 RC OSCILLATOR For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low C

EXT values. The user also needs to take into account

variation due to tolerance of external R and C components used. Figure 10-4 shows how the R/C combination is connected to the PIC16CXXX family.

FIGURE 10-4: RC OSCILLATOR MODE

VDD

Rext

Cext

VSS

Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ

Fosc/4

OSC1

OSC2/CLKOUT

Cext > 20pF

Internal

clock

PIC16CXXX

10.3 Reset

The PIC16CXXX family differentiates between various kinds of reset:

• Power-on Reset (POR)

• MCLR

reset during normal operation

• MCLR

reset during SLEEP

• WDT Reset (normal operation)

• Brown-out Reset (BOR) Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR WDT Reset, on MCLR

reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 10-5.

The PIC16C72/CR72 have a MCLR MCLR

reset path. The ﬁlter will detect and ignore small

noise ﬁlter in the

pulses. It should be noted that a WDT Reset

MCLR

pin low.

does not drive

and

 1998 Microchip Technology Inc. Preliminary DS39016A-page 61

PIC16C72 Series

FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

WDT

Module

DD rise

detect

VDD

Brown-out

Reset

OST/PWRT

OSC1

(1)

On-chip RC OSC

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

SLEEP

WDT

Time-out

Reset

Power-on Reset

BODEN

OST

10-bit Ripple counter

PWRT

10-bit Ripple counter

Enable PWRT

Enable OST

Chip_Reset

DS39016A-page 62 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

10.4 Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR directly (or through a resistor) to V

DD. This will eliminate

external RC components usually needed to create a Power-on Reset. A maximum rise time for V

DD is spec-

iﬁed. See Electrical Speciﬁcations for details. For a slow rise time, see Figure 10-6.

When the device starts normal operation (exits the reset condition), device operating parameters (voltage , frequency , temper ature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions.

FIGURE 10-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

MCLR

Note 1: External Power-on Reset circuit is

required only if V slow. The diode D helps discharge the capacitor quickly when V

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C in the event of MCLR/ down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

PIC16CXXX

DD power-up slope is too

DD powers down.

VPP pin break-

10.5 Power-up Timer (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT’s time delay allows V

DD to rise to an acceptable

level. A conﬁguration bit is provided to enable/disable the PWRT.

The power-up time delay will vary from chip to chip due to V

DD, temperature, and process variation. See DC

parameters for details.

10.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is ov er. This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

10.7 Brown-Out Reset (BOR)

A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if V

4.0V for less than parameter #35. The chip will remain in Brown-out Reset until V Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If V BV go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled.

DD falls below 4.0V (3.8V - 4.2V range) for

DD falls below

DD rises above BVDD. The

DD drops below

DD while the Power-up Timer is running, the chip will

DD rises above BVDD,

 1998 Microchip Technology Inc. Preliminary DS39016A-page 63

PIC16C72 Series

10.8 Time-out Sequence

On power-up the time-out sequence is as follows: First PWRT time-out is invok ed after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 10-7, Figure 10-8, Figure 10-9 and Figure 10-10 depict timeout sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR (Figure 10-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX family device operating in parallel.

Table 10-5 shows the reset conditions for some special function registers, while Table 10-6 shows the reset conditions for all the registers.

high will begin execution immediately

10.9 Power Control/Status Register

The Power Control/Status Register, PCON has up to two bits, depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR

cleared, indicating a BOR occurred. The BOR bit is a "Don’t Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Conﬁguration Word).

Bit1 is POR on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

TABLE 10-3 TIME-OUT IN VARIOUS SITUATIONS

Oscillator Conﬁgura-

tion

XT, HS, LP 72 ms +

RC 72 ms — 72 ms —

PWR

1024T

Power-up

TE = 0 PWRTE = 1

1024TOSC 72 ms + 1024TOSC 1024TOSC

OSC

TABLE 10-4 STATUS BITS AND THEIR SIGNIFICANCE

POR

BOR TO PD

0 x 1 1 Power-on Reset 0 x 0 x Illegal, T 0 x x 0 Illegal, PD is set on POR 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR 1 1 1 0 MCLR

O is set on POR

Reset during normal operation Reset during SLEEP or interrupt wake-up from SLEEP

TABLE 10-5 RESET CONDITION FOR SPECIAL REGISTERS

(PCON)

. Bit BOR is

(Power-on Reset Status bit). It is cleared

Brown-out

Wake-up from

SLEEP

Condition

Power-on Reset 000h 0001 1xxx ---- --0x MCLR

Reset during normal operation 000h 000u uuuu ---- --uu Reset during SLEEP 000h 0001 0uuu ---- --uu

MCLR WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1 Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

DS39016A-page 64 Preliminary  1998 Microchip Technology Inc.

Program

Counter

(1)

STATUS Register

uuu1 0uuu ---- --uu

PCON

PIC16C72 Series

TABLE 10-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset

W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1 STATUS 0001 1xxx 000q quuu FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA --0x 0000 --0u 0000 --uu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu PIR1 -0-- 0000 -0-- 0000 -u-- uuuu TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 0000 0000 0000 0000 uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON --00 0000 --00 0000 --uu uuuu ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION 1111 1111 1111 1111 uuuu uuuu TRISA --11 1111 --11 1111 --uu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu TRISC 1111 1111 1111 1111 uuuu uuuu PIE1 -0-- 0000 -0-- 0000 -u-- uuuu PCON ---- --0u ---- --uu ---- --uu PR2 1111 1111 1111 1111 1111 1111 SSPADD 0000 0000 0000 0000 uuuu uuuu SSPSTAT --00 0000 --00 0000 --uu uuuu ADCON1 ---- -000 ---- -000 ---- -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 10-5 for reset value for speciﬁc condition.

MCLR Resets

WDT Reset

(3)

Wake-up via WDT or Inter-

rupt

uuuq quuu

(2)

(3)

(1) (1)

 1998 Microchip Technology Inc. Preliminary DS39016A-page 65

PIC16C72 Series

FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TOST

FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

T TIME-OUT

PWR

OST TIME-OUT

INTERNAL RESET

FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

T TIME-OUT

PWR

NOT TIED TO VDD): CASE 1

TOST

NOT TIED TO VDD): CASE 2

TOST

OST TIME-OUT

INTERNAL RESET

DS39016A-page 66 Preliminary  1998 Microchip Technology Inc.

FIGURE 10-10: SLOW RISE TIME (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

T TIME-OUT

PWR

OST TIME-OUT

INTERNAL RESET

TPWRT

PIC16C72 Series

TOST

 1998 Microchip Technology Inc. Preliminary DS39016A-page 67

PIC16C72 Series

10.10 Interrupts

The PIC16C72/CR72 has 8 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits.

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GIE bit.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enab led, and an interrupt’s ﬂag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overﬂow interrupt ﬂags are contained in the INTCON register.

The peripheral interrupt ﬂags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interr upt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit

10.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, ﬂag bit INTF (INTCON<1>) is set. This interr upt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.13 for details on SLEEP mode.

10.10.2 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0)

10.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets ﬂag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)

FIGURE 10-11: INTERRUPT LOGIC

T0IF T0IE

ADIF ADIE

SSPIF SSPIE

CCP1IF CCP1IE

TMR1IF

TMR1IE TMR2IF TMR2IE

DS39016A-page 68 Preliminary  1998 Microchip Technology Inc.

INTF INTE

RBIF RBIE

PEIE GIE

Wake-up (If in SLEEP mode)

Interrupt to CPU Clear GIE bit

PIC16C72 Series

10.11 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software.

Example 10-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be deﬁned in each bank and must be deﬁned at the same offset from the bank base address (i.e., if W_TEMP is deﬁned at 0x20 in bank 0, it must also be deﬁned at 0xA0 in bank

1).

The example: a) Stores the W register.

b) Stores the STATUS register in bank 0. c) Executes the ISR code. d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to W_TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :Interrupt Service Routine (ISR) - user defined : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

 1998 Microchip Technology Inc. Preliminary DS39016A-page 69

PIC16C72 Series

10.12 Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the de vice is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The T

O bit in the ST ATUS register

will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing

conﬁguration bit WDTE (Section 10.1).

FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source (Figure 4-2)

WDT Timer

WDT

Enable Bit

U X

PSA

WDT time-out period values may be found in the Electrical Speciﬁcations section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register.

Note: The CLRWDT and SLEEP instructions clear

the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.

Postscaler

8 - to - 1 MUX

PS2:PS0

To TMR0 (Figure 4-2)

Note: PSA and PS2:PS0 are bits in the OPTION register.

MUX

WDT

Time-out

PSA

FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits 81h,181h OPTION

(1)

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

BODEN

(1)

CP1 CP0

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 10-1 for operation of these bits.

DS39016A-page 70 Preliminary  1998 Microchip Technology Inc.

PWRTE

(1)

WDTE FOSC1 FOSC0

PIC16C72 Series

10.13 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD T

O (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O por ts maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).

For lowest current consumption in this mode, place all I/O pins at either V cuitry is drawing current from the I/O pin, power-down the A/D, disable exter nal clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by ﬂoating inputs. The T0CKI input should also be at V current consumption. The contribution from on-chip pull-ups on PORTB should be considered.

The MCLR

10.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR

2. Watchdog Timer Wake-up (if WDT was

3. Interrupt from INT pin, RB port change, or some

External MCLR other events are considered a continuation of program execution and cause a "wake-up". The T in the STATUS register can be used to determine the cause of device reset. The PD power-up, is cleared when SLEEP is inv oked. The T is cleared if a WDT time-out occurred (and caused wake-up).

The following peripheral interrupts can wake the de vice from SLEEP:

1. TMR1 interrupt. Timer1 must be operating as

2. SSP (Start/Stop) bit detect interrupt.

3. SSP transmit or receive in slave mode (SPI/I

4. CCP capture mode interrupt.

5. A/D conversion (when A/D clock source is RC).

6. Special event trigger (Timer1 in asynchronous

pin must be at a logic high level (VIHMC).

enabled).

Peripheral Interrupts.

an asynchronous counter.

mode using an external clock).

bit (STATUS<3>) is cleared, the

DD, or VSS, ensure no external cir-

DD or VSS for lowest

pin.

Reset will cause a device reset. All

O and PD bits

bit, which is set on

O bit

C).

Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instr uction after the SLEEP instr uction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

10.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit and interrupt ﬂag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the T be set and PD

• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the T be cleared.

Even if the ﬂag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD

bit. If the PD bit is set, the SLEEP instruction was

executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

bits will not be cleared.

O bit will be set and the PD bit will

O bit will not

 1998 Microchip Technology Inc. Preliminary DS39016A-page 71

PIC16C72 Series

FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

UCTION FLOW

INSTR

Instruction fetched

Instruction executed

Note 1: XT, HS or LP oscillator mode assumed.

2: T 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

OST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

Inst(PC + 1)

SLEEP

Processor in

SLEEP

OST(2)

PC+2

Inst(PC + 2)

Inst(PC + 1)

Interrupt Latency

(Note 2)

PC + 2 0004h 0005h

Inst(0004h)

Dummy cycle

Inst(0005h)

Inst(0004h)

10.14 Pr

ogram Veriﬁcation/Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

Note: Microchip does not recommend code pro-

tecting windowed devices.

10.15 ID Locations

Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least signiﬁcant bits of the ID location are used.

For ROM devices, these values are submitted along with the ROM code.

10.16 In-Circuit Serial Programming™

PIC16CXXX family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, DS30277.

DS39016A-page 72 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

11.0 INSTRUCTION SET SUMMARY

Each PIC16CXXX family instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX family instruction set summary in Table 11-2 lists byte- oriented, bit-oriented, and literal and control opera- tions. Table 11-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 11-1 OPCODE FIELD

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

d Destination select; d = 0: store result in W,

PC Program Counter TO PD Power-down bit

The instruction set is highly orthogonal and is grouped into three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

DESCRIPTIONS

Microchip software tools.

d = 1: store result in ﬁle register f.

Default is d = 1

Time-out bit

Table 11-2 lists the instructions recognized by the MPASM assembler.

Figure 11-1 shows the general formats that the instructions can have.

Note: To maintain upward compatibility with

future PIC16CXXX products, do not use the OPTION and TRIS instructions.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

13 8 7 6 0

OPCODE d f (FILE #)

d = 0 for destination W d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations

General

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

CALL and GOTO instructions only

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

A description of each instruction is available in the PICmicro™ Mid-Range MCU Family Reference Manual, DS33023.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 73

PIC16C72 Series

TABLE 11-2 PIC16CXXX INSTRUCTION SET

Mnemonic,

Operands

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BCF BSF BTFSC BTFSS

ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

f, d

Add W and f

f, d

AND W with f

Clear f

Clear W

f, d

Complement f

f, d

Decrement f

f, d

Decrement f, Skip if 0

f, d

Increment f

f, d

Increment f, Skip if 0

f, d

Inclusive OR W with f

f, d

Move f

Move W to f

No Operation

f, d

Rotate Left f through Carry

f, d

Rotate Right f through Carry

f, d

Subtract W from f

f, d

Swap nibbles in f

f, d

Exclusive OR W with f

f, b

Bit Clear f

f, b

Bit Set f

f, b

Bit Test f, Skip if Clear

f, b

Bit Test f, Skip if Set

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Description Cycles 14-Bit Opcode Status

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

0111

1(2)

BIT-ORIENTED FILE REGISTER OPERATIONS

1 (2)

LITERAL AND CONTROL OPERATIONS

0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

00bb 01bb 10bb 11bb

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

bfff bfff bfff bfff

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

Affected

C,DC,Z

Z Z Z Z Z

Z Z

C C

C,DC,Z

O,PD

TO,PD

C,DC,Z

Notes

1,2,3

1,2 1,2

1,2

1,2 1,2

1,2 1,2 1,2 1,2 1,2

1,2 1,2

3 3

DS39016A-page 74 Preliminary  1998 Microchip Technology Inc.

12.0 DEVELOPMENT SUPPORT

12.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• PICMASTER In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE

• PICSTART Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System (

fuzzy

A description of each development tool is available in the Midrange Reference Manual, DS33023.

12.2 PICDEM-2 Low-Cost PIC16CXX

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART -Plus , and easily test ﬁrmware . The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I tion to an LCD module and a keypad.



/PICMASTER CE Real-Time



II Universal Programmer



Plus Entry-Level Prototype

TECH−MP)

Demonstration Board

C bus and separate headers for connec-

PIC16C72 Series

 1998 Microchip Technology Inc. Preliminary DS39016A-page 75

PIC16C72 Series

NOTES:

DS39016A-page 76 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

13.0 ELECTRICAL CHARACTERISTICS - PIC16C72 SERIES

Absolute Maximum Ratings †

Parameter PIC16C72 PIC16CR72

Ambient temperature under bias -55 to +125˚C -55 to +125˚C Storage temperature -65˚C to +150˚C -65˚C to +150˚C Voltage on an y pin with respect to V Voltage on V Voltage on MCLR

DD with respect to VSS -0.3 to +7.5V TBD

with respect to VSS (Note 1) -0.3 to +14V TBD Voltage on RA4 with respect to Vss -0.3 to +14V TBD Total power dissipation (Note 2) 1.0W 1.0W Maximum current out of V Maximum current into V Input clamp current, I

SS pin 300 mA 300 mA

DD pin 250 mA 250 mA

IK (VI < 0 or VI > VDD) ± 20 mA ± 20 mA

Output clamp current, IOK (V Maximum output current sunk by any I/O pin 25 mA 25 mA Maximum output current sourced by any I/O pin 25 mA 25 mA Maximum current sunk by PORTA and PORTB (combined) 200 mA 200 mA Maximum current sourced by PORTA and PORTB (combined) 200 mA 200 mA Maximum current sunk by PORTC 200 mA 200 mA Maximum current sourced by PORTC 200 mA 200 mA

1. Voltage spikes below V

a series resistor of 50-100Ω should be used when applying a “low” le v el to the MCLR pin directly to V

SS.

2. Power dissipation is calculated as follows: Pdis = V

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

SS (except VDD, MCLR, and RA4) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V)

O < 0 or VO > VDD) ± 20 mA ± 20 mA

SS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,

pin rather than pulling this

DD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).

 1998 Microchip Technology Inc. Preliminary DS39016A-page 77

PIC16C72 Series

TABLE 13-1 CROSS REFERENCE OF DEVICE SPECS (PIC16C72) FOR OSCILLATOR

CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC PIC16C72-04 PIC16C72-10 PIC16C72-20 PIC16LC72-04 JW Devices

DD: 4.0V to 6.0V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.0V to 6.0V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V

IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V

DD: 52.5 µA typ. at

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations.

32 kHz, 4.0V

PD: 0.9 µA typ. at 4.0V

I Freq: 200 kHz max.

Not recommended for use

in LP mode

Not recommended for use

in LP mode

It is recommended that the user select the device type that ensures the speciﬁcations required.

DD: 2.5V to 6.0V

DD: 3.8 mA max. at 3.0V

PD: 5.0 µA max. at 3V

I Freq: 4 MHz max.

DD: 2.5V to 6.0V

DD: 3.8 mA max. at 3.0V

PD: 5.0 µA max. at 3V

I Freq: 4 MHz max.

Not recommended for use

in HS mode

DD: 2.5V to 6.0V

DD: 48 µA max. at

32 kHz, 3.0V

PD: 5.0 µA max. at 3.0V

I Freq: 200 kHz max.

DD: 4.0V to 6.0V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.0V to 6.0V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.5V to 5.5V

DD: 2.5V to 6.0V

DD: 48 µA max. at

32 kHz, 3.0V

PD: 5.0 µA max. at 3.0V

I Freq: 200 kHz max.

TABLE 13-2 CROSS REFERENCE OF DEVICE SPECS (PIC16CR72) FOR OSCILLATOR

CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC PIC16CR72-04 PIC16CR72-10 PIC16CR72-20 PIC16LCR72-04 JW Devices

DD: 4.0V to 5.5V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.0V to 5.5V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

I Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

VDD: 4.5V to 5.5V

DD: 2.7 mA typ. at 5.5V

PD: 1.5 µA typ. at 4V

Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V

IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 5.5V

DD: 52.5 µA typ. at

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations.

32 kHz, 4.0V

PD: 0.9 µA typ. at 4.0V

I Freq: 200 kHz max.

Not recommended for use

in LP mode

Not recommended for use

in LP mode

It is recommended that the user select the device type that ensures the speciﬁcations required.

DD: 2.5V to 5.5V

DD: 3.8 mA max. at 3.0V

PD: 5.0 µA max. at 3V

I Freq: 4 MHz max.

DD: 2.5V to 5.5V

DD: 3.8 mA max. at 3.0V

PD: 5.0 µA max. at 3V

I Freq: 4 MHz max.

Not recommended for use

in HS mode

DD: 2.5V to 5.5V

DD: 48 µA max. at

32 kHz, 3.0V

PD: 5.0 µA max. at 3.0V

I Freq: 200 kHz max.

DD: 4.0V to 5.5V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.0V to 5.5V

DD: 5 mA max. at 5.5V

PD: 16 µA max. at 4V

I Freq: 4 MHz max.

DD: 4.5V to 5.5V

DD: 2.5V to 5.5V

DD: 48 µA max. at

32 kHz, 3.0V

PD: 5.0 µA max. at 3.0V

I Freq: 200 kHz max.

DS39016A-page 78 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

13.1 DC Characteristics: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param

No.

D001 D001A

D002* RAM Data Retention

D003 VDD start voltage to

D004* VDD rise rate to ensure

D005 Brown-out Reset Volt-

D010 Supply Current

D013 - 10 20 - 10 20 mA HS osc

D015 Brown-out Reset

D020 Power-down Current

D021 - 1.5 16 - 1.5 16 µA VDD = 4.0V, WDT dis-

D021A - 1.5 19 - 1.5 19 µA VDD = 4.0V, WDT dis-

D021B - 2.5 19 - 2.5 19 µA VDD = 4.0V, WDT dis-

D023 Brown-out Reset

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These par ameters are f or design guidance only and are not

Note 1: This is the limit to which VDD can be lowered without losing RAM data. Note 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and

Note 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with

Note 4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

Note 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the speciﬁcation. This value is from characterization and

Note 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

Characteristic Sym

Supply Voltage VDD 4.0

Voltage (Note 1)

ensure internal Poweron Reset Signal

internal Power-on Reset Signal

age

(Note 2,5)

Current (Note 6)

(Note 3,5)

Current (Note 6)

tested.

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

formula Ir = VDD/2Rext (mA) with Rext in kOhm.

is for design guidance only. This is not tested.

base IDD or IPD measurement.

Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,

Min Typ† Max Min Typ† Max

4.5--

VDR - 1.5 - - 1.5 - V

VPOR - VSS - - VSS - V See section on Power-

SVDD 0.05 - - 0.05 - - V/ms See section on Power-

Bvdd 3.7 4.0 4.3 3.7 4.0 4.3 V BODEN bit in conﬁgura-

3.7 4.0 4.4 3.7 4.0 4.4 V Extended Only

DD - 2.7 5.0 - 2.7 5.0 mA XT, RC osc

∆Ibor - 350 425 - 350 425 µA BOR enabled,

IPD - 10.5 42 - 10.5 42 µA VDD = 4.0V, WDT

∆Ibor - 350 425 - 350 425 µA BOR enabled VDD =

-40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial

PIC16C72 PIC16CR72

6.0

4.0

5.5

4.5--

Units Conditions

5.5

5.5VV

DD and VSS.

XT, RC and LP osc HS osc

on Reset for details

tion word enabled

FOSC = 4 MHz, VDD = 5.5V (Note 4)

FOSC = 20 MHz, VDD = 5.5V

VDD = 5.0V

enabled, -40°C to +85°C

abled, -0°C to +70°C

abled, -40°C to +85°C

abled, -40°C to +125°C

5.0V

 1998 Microchip Technology Inc. Preliminary DS39016A-page 79

PIC16C72 Series

13.2 DC Characteristics: PIC16LC72/LCR72-04 (Commercial, Industrial)

DC CHARACTERISTICS

Param

No.

D001 Supply Voltage V D002* RAM Data Retention

D003 VDD start voltage to

D004* VDD rise rate to ensure

D005 Brown-out Reset Volt-

D010 Supply Current

D010A - 22.5 48 - 22.5 48 µA LP osc conﬁguration

D015* Brown-out Reset

D020 Power-down Current

D021 - 0.9 5 - 0.9 5 µA VDD = 3.0V, WDT dis-

D021A - 0.9 5 - 0.9 5 µA VDD = 3.0V, WDT dis-

D023* Brown-out Reset

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are f or design guidance only and are not

Note 3: The power-down current in SLEEP mode does not depend on the oscillator type. Po wer-down current is measured with

Note 4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

Note 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the speciﬁcation. This value is from characterization and

Note 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

Characteristic Sym

Voltage (Note 1)

ensure internal Poweron Reset signal

internal Power-on Reset signal

age

(Note 2,5)

Current (Note 6)

(Note 3,5)

Current (Note 6)

tested.

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.

The test conditions for all I OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

formula Ir = VDD/2Rext (mA) with Rext in kOhm.

is for design guidance only. This is not tested.

base IDD or IPD measurement.

Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and

PIC16C72 PIC16CR72

Min Typ† Max Min Typ† Max

DD 2.5 - 6.0 2.5 - 5.5 V LP, XT, RC (DC - 4 MHz)

VDR - 1.5 - - 1.5 - V

VPOR - VSS - - VSS - V See section on Power-

SVDD 0.05 - - 0.05 - - V/ms See section on Power-

Bvdd 3.7 4.0 4.3 3.7 4.0 4.3 V BODEN bit in conﬁgura-

IDD - 2.0 3.8 - 2.0 3.8 mA XT, RC osc conﬁguration

∆Ibor - 350 425 - 350 425 µA BOR enabled VDD =

IPD - 7.5 30 - 7.5 30 µA VDD = 3.0V, WDT

∆Ibor - 350 425 - 350 425 µA BOR enabled VDD =

DD measurements in active operation mode are:

0˚C ≤ TA ≤ +70˚C for commercial

Units Conditions

on Reset for details

tion word enabled

FOSC = 4 MHz, VDD =

3.0V (Note 4)

FOSC = 32 kHz, VDD =

3.0V, WDT disabled

5.0V

enabled, -40°C to +85°C

abled, 0°C to +70°C

abled, -40°C to +85°C

5.0V

DS39016A-page 80 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

13.3 DC Characteristics: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 13.1 and

Param

No.

Input Low Voltage

I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A Vss - 0.8V V 4.5 ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) V

Input High Voltage

I/O ports VIH D040 with TTL buffer 2.0 - VDD V 4.5 ≤ VDD ≤ 5.5V D040A 0.25VDD +

D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - Vdd V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 †400 µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-

D061 MCLR, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

Output Low Voltage

D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V,

D083 OSC2/CLKOUT (RC osc conﬁg) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,

D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V,

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be

driven with external clock in RC mode.

Note 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed levels repre-

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

Note 3: Negative current is deﬁned as current sourced by the pin.

Characteristic Sym Min Typ† Max Units Conditions

Section 13.2.

SS - 0.3VDD V Note1

0.8V

-40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial

- VDD V For entire VDD range

impedance

osc conﬁguration

-40°C to +85°C

-40°C to +125°C

-40°C to +85°C

-40°C to +125°C

 1998 Microchip Technology Inc. Preliminary DS39016A-page 81

PIC16C72 Series

Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ T

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 13.1 and

Param

No.

D090 I/O ports (Note 3) V

D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

D092 OSC2/CLKOUT (RC osc conﬁg) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

D150* Open-Drain High Voltage Vod - - 14 V RA4 pin, PIC16C72/LC72

D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when

D101 D102

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be

Note 2: The leakage current on the MCLR

Note 3: Negative current is deﬁned as current sourced by the pin.

Output High Voltage

Capacitive Loading Specs on Output Pins

All I/O pins and OSC2 (in RC mode) SCL, SDA in I2C mode

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

driven with external clock in RC mode.

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

Characteristic Sym Min Typ† Max Units Conditions

Section 13.2.

OH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

- - TBD V RA4 pin, PIC16CR72/LCR72

CIO Cb

/VPP pin is strongly dependent on the applied voltage level. The speciﬁed levels repre-

-40˚C ≤ TA ≤ +85˚C for industrial and

A ≤ +125˚C for extended,

0˚C ≤ TA ≤ +70˚C for commercial

-40°C to +85°C

-40°C to +125°C

-40°C to +85°C

-40°C to +125°C

external clock is used to drive OSC1.

400pFpF

DS39016A-page 82 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

13.4 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C speciﬁcations only)

2. TppS 4. Ts (I2C speciﬁcations only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

C only

I AA output access High High BUF Bus free Low Low TCC:ST (I2C speciﬁcations only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition

FIGURE 13-1: LOAD CONDITIONS

Load condition 1

VDD/2

Pin Pin

RL = 464Ω

L = 50 pF for all pins except OSC2

15 pF for OSC2 output

 1998 Microchip Technology Inc. Preliminary DS39016A-page 83

Load condition 2

VSS

PIC16C72 Series

13.5 Timing Diagrams and Speciﬁcations

FIGURE 13-2: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

OSC1

CLKOUT

TABLE 13-3 EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

1 Tosc External CLKIN Period

2 T 3 TosL,

4 TosR,

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are based on

Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequency

(Note 1)

Oscillator Frequency (Note 1)

(Note 1)

Oscillator Period (Note 1)

CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

External Clock in (OSC1) High or

TosH

Low Time

External Clock in (OSC1) Rise or

TosF

Fall Time

tested.

characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode

0.1 — 4 MHz XT osc mode 45—

— 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10)

50 — — ns HS osc mode (-20)

5 — — µs LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 10050—

—

5 — — µs LP osc mode

100 — — ns XT oscillator

2.5 — — µs LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator

200

250 250nsns

MHz

HS osc mode

kHz

LP osc mode

HS osc mode (-10) HS osc mode (-20)

DS39016A-page 84 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-3: CLKOUT AND I/O TIMING

PIC16C72 Series

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

old value

Note: Refer to Figure 13-1 for load conditions.

20, 21

Q2 Q3

new value

TABLE 13-4 CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

10* 11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5T 15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1↑ (Q2 cycle) to

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C72/CR72 — 10 40 ns

21* TioF Port output fall time PIC16C72/CR72 — 10 40 ns

22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

Sym Characteristic Min Typ† Max Units Conditions

TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1

CY + 20 ns Note 1

Port input invalid (I/O in hold time)

only and are not tested.

PIC16C72/CR72 100 — — ns PIC16LC72/LCR72 200 — — ns

PIC16LC72/LCR72 — — 80 ns

 1998 Microchip Technology Inc. Preliminary DS39016A-page 85

PIC16C72 Series

FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Note: Refer to Figure 13-1 for load conditions.

FIGURE 13-5: BROWN-OUT RESET TIMING

VDD

BVDD

TABLE 13-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

31* Twdt Watchdog Timer Time-out Period

32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period

33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C

34 TIOZ I/O Hi-impedance from MCLR Low

35 TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ BVDD (D005)

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

DS39016A-page 86 Preliminary  1998 Microchip Technology Inc.

Sym Characteristic Min Typ† Max Units Conditions

TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40˚C to +125˚C

(No Prescaler)

7 18 33 ms V

— — 2.1 µs

or Watchdog Timer Reset

tested.

DD = 5V, -40˚C to +125˚C

PIC16C72 Series

FIGURE 13-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

RC0/T1OSO/T1CKI

TMR0 or TMR1

Note: Refer to Figure 13-1 for load conditions.

TABLE 13-6 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

40*

41*

Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

42*

Tt0P T0CKI Period No Prescaler TCY + 40 — — ns

45*

Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

46*

Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

47*

Tt1P T1CKI input

Ft1 Timer1 oscillator input frequency range

48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

period

(oscillator enabled by setting bit T1OSCEN)

Synchronous, Prescaler = 2,4,8 Asynchronous PIC16C7X/CR72 30 — — ns

Synchronous PIC16C7X/CR72 Greater of:

Asynchronous PIC16C7X/CR72 60 — — ns

With Prescaler 10 — — ns

With Prescaler Greater of:

20 or TCY + 40

PIC16C7X/CR72 15 — — ns PIC16LC7X/LCR72 25 — — ns

PIC16LC7X/LCR72 50 — — ns

PIC16C7X/CR72 15 — — ns PIC16LC7X/LCR72 25 — — ns

PIC16LC7X/LCR72 50 — — ns

30 OR TCY + 40

PIC16LC7X/LCR72 Greater of:

50 OR TCY + 40

PIC16LC7X/LCR72 100 — — ns

DC — 200 kHz

parameter 42

— — ns N = prescale value

(2, 4, ..., 256)

parameter 47

— — ns N = prescale value

(1, 2, 4, 8)

N = prescale value (1, 2, 4, 8)

 1998 Microchip Technology Inc. Preliminary DS39016A-page 87

PIC16C72 Series

FIGURE 13-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1)

RC2/CCP1

(Capture Mode)

50 51

(Compare or PWM Mode)

RC2/CCP1

53 54

Note: Refer to Figure 13-1 for load conditions.

TABLE 13-7 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

50* TccL CCP1 input low time No Prescaler 0.5TCY + 20 — — ns

With Prescaler PIC16C72/CR72 10 — — ns

PIC16LC72/LCR72 20 — — ns

51* TccH CCP1 input high time No Prescaler 0.5T

With Prescaler PIC16C72/CR72 10 — — ns

PIC16LC72/LCR72 20 — — ns

52* TccP CCP1 input period 3TCY + 40N— — ns N = prescale

53* TccR CCP1 output rise time PIC16C72/CR72 — 10 25 ns

PIC16LC72/LCR72 — 25 45 ns

54* TccF CCP1 output fall time PIC16C72/CR72 — 10 25 ns

PIC16LC72/LCR72 — 25 45 ns

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

CY + 20 — — ns

value (1,4 or 16)

DS39016A-page 88 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-8: SPI MASTER OPERATION TIMING (CKE = 0)

SCK (CKP = 0)

SCK (CKP = 1)

71 72

PIC16C72 Series

SDO

SDI

Refer to Figure 13-1 for load conditions.

MSB LSB

MSB IN

BIT6 - - - - - -1

75, 76

BIT6 - - - -1

FIGURE 13-9: SPI MASTER OPERATION TIMING (CKE = 1)

SCK (CKP = 0)

SCK (CKP = 1)

SDO

71 72

MSB

BIT6 - - - - - -1

LSB IN

LSB

75, 76

SDI

Refer to Figure 13-1 for load conditions.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 89

MSB IN

BIT6 - - - -1

LSB IN

PIC16C72 Series

FIGURE 13-10: SPI SLAVE MODE TIMING (CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

Refer to Figure 13-1 for load conditions.

71 72

MSB LSB

MSB IN BIT6 - - - -1 LSB IN

BIT6 - - - - - -1

75, 76

FIGURE 13-11: SPI SLAVE MODE TIMING (CKE = 1)

SCK

(CKP = 0)

71 72

SCK

(CKP = 1)

SDO

SDI

DS39016A-page 90 Preliminary  1998 Microchip Technology Inc.

MSB BIT6 - - - - - -1 LSB

75, 76

MSB IN BIT6 - - - -1 LSB IN

Refer to Figure 13-1 for load conditions.

PIC16C72 Series

TABLE 13-8 SPI SLAVE MODE REQUIREMENTS (CKE=0) - PIC16C72

Param

No.

71 72 73

75 76 77 78 79 80

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

TABLE 13-9 SPI MODE REQUIREMENTS - PIC16CR72

Parameter

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

Sym Characteristic Min Typ† Max Units Conditions

TssL2scH, TssL2scL

TscH SCK input high time (slave mode) TCY + 20 — — ns TscL SCK input low time (slave mode) TCY + 20 — — ns TdiV2scH,

TdiV2scL TscH2diL,

TscL2diL TdoR SDO data output rise time — 10 25 ns

TdoF SDO data output fall time — 10 25 ns TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns TscR SCK output rise time (master mode) — 10 25 ns TscF SCK output fall time (master mode) — 10 25 ns TscH2doV,

TscL2doV

tested.

No.

70* TssL2scH,

71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH,

74* TscH2diL,

75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV,

81* TdoV2scH,

82* TssL2doV SDO data output valid after SS↓

83* TscH2ssH,

tested.

SS↓ to SCK↓ or SCK↑ input TCY — — ns

Setup time of SDI data input to SCK edge 50 — — ns

Hold time of SDI data input to SCK edge 50 — — ns

SDO data output valid after SCK edge — — 50 ns

Sym Characteristic Min Typ† Max Units Conditions

↓ to SCK↓ or SCK↑ input TCY — — ns

TssL2scL

TdiV2scL

TscL2diL

TscL2doV

TdoV2scL

TscL2ssH

Setup time of SDI data input to SCK edge

Hold time of SDI data input to SCK edge

SDO data output valid after SCK edge

SDO data output setup to SCK edge

edge SS ↑ after SCK edge 1.5TCY + 40 — — ns

100 — — ns

— — 50 ns

TCY — — ns

— — 50 ns

 1998 Microchip Technology Inc. Preliminary DS39016A-page 91

PIC16C72 Series

FIGURE 13-12: I2C BUS START/STOP BITS TIMING

SCL

SDA

Note: Refer to Figure 13-1 for load conditions

TABLE 13-10 I

Parameter

No.

91 THD:STA START condition 100 kHz mode 4000 — — ns After this period the ﬁrst clock

92 TSU:STO STOP condition 100 kHz mode 4700 — — ns

93 THD:STO STOP condition 100 kHz mode 4000 — — ns

C BUS START/STOP BITS REQUIREMENTS

Sym Characteristic Min Typ Max Units Conditions

TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for repeated ST ART

START

Condition

Setup time 400 kHz mode 600 — —

Hold time 400 kHz mode 600 — —

Setup time 400 kHz mode 600 — —

Hold time 400 kHz mode 600 — —

condition

pulse is generated

STOP

Condition

DS39016A-page 92 Preliminary  1998 Microchip Technology Inc.

PIC16C72 Series

FIGURE 13-13: I2C BUS DATA TIMING

103

SCL

SDA In

SDA Out

Note: Refer to Figure 13-1 for load conditions

TABLE 13-11 I

Parameter

No.

THIGH Clock high time 100 kHz mode 4.0 — µs Device must operate at a mini-

100

101 TLOW Clock low time 100 kHz mode 4.7 — µs Device must operate at a mini-

102 TR SDA and SCL rise

103 TF SDA and SCL fall time 100 kHz mode — 300 ns

90 TSU:STA START condition

91 THD:STA START condition hold

106 THD:DAT Data input hold time 100 kHz mode 0 — ns

107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2

92 TSU:STO STOP condition setup

109 TAA Output valid from

110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free

Cb Bus capacitive loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undeﬁned region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

Note 2: A fast-mode (400 kHz) I

tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus speciﬁcation) before the SCL line is released.

91 92

109

C BUS DATA REQUIREMENTS

Sym Characteristic Min Max Units Conditions

time

setup time

time

clock

C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement

100

101

106

400 kHz mode 0.6 — µs Device must operate at a mini-

SSP Module 1.5T

400 kHz mode 1.3 — µs Device must operate at a mini-

SSP Module 1.5TCY — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is speciﬁed to be from

400 kHz mode 20 + 0.1Cb 300 ns Cb is speciﬁed to be from

100 kHz mode 4.7 — µs Only relevant for repeated 400 kHz mode 0.6 — µs 100 kHz mode 4.0 — µs After this period the ﬁrst clock 400 kHz mode 0.6 — µs

400 kHz mode 0 0.9 µs

400 kHz mode 100 — ns 100 kHz mode 4.7 — µs 400 kHz mode 0.6 — µs 100 kHz mode — 3500 ns Note 1 400 kHz mode — — ns

400 kHz mode 1.3 — µs

107

109

CY —

102

110

mum of 1.5 MHz

mum of 10 MHz

mum of 1.5 MHz

mum of 10 MHz

10 to 400 pF

START condition

pulse is generated

before a new transmission can start

 1998 Microchip Technology Inc. Preliminary DS39016A-page 93

PIC16C72 Series

TABLE 13-12 A/D CONVERTER CHARACTERISTICS:

PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial)

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

A01 NR Resolution — — 8 bits bit VREF = VDD = 5.12V,

A02 EABS Total Absolute error — — < ± 1 LSb VREF = VDD = 5.12V,

A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,

A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,

A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,

A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,

A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of

A40 IAD A/D conversion

A50 IREF VREF input current (Note 2) 10

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

Note 1: When A/D is off, it will not consume any current other than minor leakage current.

Note 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

analog voltage source

current (VDD)

tested.

The power-down current spec includes any such leakage from the A/D module.

PIC16C72/CR72 — 180 — µA Average current conPIC16LC72/LCR72 — 90 — µA

— — 10.0 kΩ

—

100010µAµADuring VAIN acquisition.

SS ≤ VAIN ≤ VREF

VSS ≤ VAIN ≤ VREF

sumption when A/D is on. (Note 1)

Based on differential of VHOLD to VAIN to charge CHOLD, see Section 9.1.

During A/D Conversion cycle

DS39016A-page 94 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-14: A/D CONVERSION TIMING

PIC16C72 Series

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

134

132

(1)

OSC/2)

7 6 5 4 3 2 1 0

OLD_DATA

131

130

SAMPLING STOPPED

1 TCY

NEW_DATA

DONE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

TABLE 13-13 A/D CONVERSION REQUIREMENTS

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

TAD A/D clock period PIC16C72/LCR72 1.6 — — µs TOSC based, VREF ≥ 2.5V

130

131 TCNV Conversion time

(not including S/H time) (Note 1)

132 TACQ Acquisition time Note 25*20

134 Tgo Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected

135 Tswc Switching from convert → sample time 1.5 § — — T

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

§ This speciﬁcation ensured by design.

Note 1: ADRES register may be read on the following TCY cycle. Note 2: See Section 9.1 for min conditions.

PIC16LC72/LCR72 2.0 — — µs TOSC based, VREF full range PIC16C72/LCR72 2.0 4.0 6.0 µs A/D RC Mode PIC16LC72/LCR72 2.5 6.0 9.0 µs A/D RC Mode

— 9.5 — TAD

——µs

—

µs The minimum time is the ampliﬁer

settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD).

as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

 1998 Microchip Technology Inc. Preliminary DS39016A-page 95

PIC16C72 Series

NOTES:

DS39016A-page 96 Preliminary  1998 Microchip Technology Inc.

PIC16C72 PIC16C72 Series

14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES - PIC16C72

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables, the data presented are outside speciﬁed operating range (i.e., outside speciﬁed V

range). This is for information only and devices are guaranteed to operate properly only within the speciﬁed range. The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C, while 'max' or 'min' represents (mean + 3σ) and (mean - 3σ) respectively, where σ is standard deviation.

FIGURE 14-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)

IPD (nA)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FIGURE 14-2: MAXIMUM I

10.000

1.000

0.100

IPD (µA)

0.010

0.001

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

PD vs. VDD (WDT DISABLED, RC MODE)

VDD (Volts)

85°C 70°C

25°C

0°C

-40°C

 1998 Microchip Technology Inc. Preliminary DS39016A-page 97

PIC16C72 Series PIC16C72

FIGURE 14-3: TYPICAL IPD vs. VDD @ 25°C

(WDT ENABLED, RC MODE)

IPD (µA)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FIGURE 14-4: MAXIMUM I

PD vs. VDD (WDT

ENABLED, RC MODE)

IPD (µA)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

-40°C

0°C

70°C

85°C

FIGURE 14-5: TYPICAL RC OSCILLATOR

FREQUENCY vs. V

6.0

5.5

5.0

4.5

4.0

3.5

3.0

Fosc (MHz)

2.5

2.0

1.5

1.0

0.5

0.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Shaded area is beyond recommended range.

Cext = 22 pF, T = 25°C

DD (Volts)

R = 5k

R = 10k

R = 100k

FIGURE 14-6: TYPICAL RC OSCILLATOR

FREQUENCY vs. V

2.4

2.2

2.0

1.8

1.6

1.4

1.2

Fosc (MHz)

1.0

0.8

0.6

0.4

0.2

0.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Cext = 100 pF, T = 25°C

DD (Volts)

R = 3.3k

R = 5k

R = 10k

R = 100k

FIGURE 14-7: TYPICAL RC OSCILLATOR

FREQUENCY vs. V

1000

900 800 700 600 500

Fosc (kHz)

400 300 200 100

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Data based on matrix samples. See ﬁrst page of this section for details.

DS39016A-page 98 Preliminary  1998 Microchip Technology Inc.

Cext = 300 pF, T = 25°C

DD (Volts)

R = 3.3k

R = 5k

R = 10k

R = 100k

PIC16C72 PIC16C72 Series

FIGURE 14-8: TYPICAL IPD vs. VDD BROWN-

OUT DETECT ENABLED (RC MODE)

1400 1200 1000

DD (Volts)

PD vs. VDD

Device NOT in

Brown-out Reset

800

IPD (µA)

600

Device in

400

Brown-out

Reset

200

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

The shaded region represents the built-in hysteresis of the brown-out reset circuitry.

FIGURE 14-9: MAXIMUM I

BROWN-OUT DETECT ENABLED (85°C TO -40°C, RC MODE)

1600 1400 1200 1000

800

IPD (µA)

Device in

600

Brown-out

400

Reset

200

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

The shaded region represents the built-in hysteresis of the brown-out reset circuitry.

4.3

DD (Volts)

Device NOT in

Brown-out Reset

FIGURE 14-10: TYPICAL I

PD vs. TIMER1

ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE)

IPD (µA)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FIGURE 14-11: MAXIMUM I

DD (Volts)

PD vs. TIMER1

ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85°C TO -40°C, RC MODE)

45 40 35 30 25 20

IPD (µA)

15 10

5 0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

DD (Volts)

 1998 Microchip Technology Inc. Preliminary DS39016A-page 99

Data based on matrix samples. See ﬁrst page of this section for details.

PIC16C72 Series PIC16C72

FIGURE 14-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C)

2000 1800 1600

1400

1200

1000

IDD (µA)

800

600

400

200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Frequency (MHz)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Shaded area is beyond recommended range

FIGURE 14-13: MAXIMUM I

2000 1800 1600

1400

1200

1000

IDD (µA)

800

600

400

200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

DD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)

Frequency (MHz)

Shaded area is beyond recommended range

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Data based on matrix samples. See ﬁrst page of this section for details.

DS39016A-page 100 Preliminary  1998 Microchip Technology Inc.

MICROCHIP PIC16C72 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual