MICROCHIP PIC16C712, PIC16C716 Technical data

PIC16C712/716

8-Bit CMOS Microcontrollers with A/D Converter

and Capture/Compare/PWM

Devices included in this Data Sheet:

• PIC16C712 • PIC16C716

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program
branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

Device

PIC16C712 1K 128
PIC16C716 2K 128

• Interrupt capability
(up to 7 internal/external interrupt sources)

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Brown-out detection circuitry for
Brown-out Reset (BOR)

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM
technology

• Fully static design

• In-Circuit Serial Programming (ICSP)

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial, Indust rial and Extended temp erature
ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 22.5 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Program

Memory

Data Memory

Pin Diagrams

18-pin PDIP, SOIC, Windowed CERDIP

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

MCLR/VPP

VSS

RB0/INT

RB1/T1OSO/T1CKI

RB2/T1OSI

RB3/CCP1

PIC16C716

PIC16C712

18
17
16
15
14
13
12

11
10

1
2
3
4
5
6
7
8
9

RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4

20-pin SSOP

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

MCLR/VPP

VSS
VSS

RB0/INT

RB1/T1OSO/T1CKI

RB2/T1OSI

RB3/CCP1

1
2
3
4
5
6
7
8
9
10

PIC16C712

PIC16C716

20
19
18
17
16
15
14

13
12
11

RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Capture, Compare, PWM module

• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum reso lution is 10-bit

• 8-bit multi-channel Analo g-to-Digital converter

1999 Microchip Technology Inc.



Preliminary DS41106A-page 1

PIC16C712/716

Key Features

PICmicro

™

Mid-Range Reference Manual

(DS33023)

Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)
Program Memory (14-bit words) 1K 2K
Data Memory (bytes) 128 128
Interrupts 7 7
I/O Ports Ports A,B Ports A,B
Timers 3 3
Capture/Compare/PWM modules 1 1
8-bit Analog-to-Digital Module 4 input channels 4 input channels

PIC16C7XX FAMILY OF DEVICES

PIC16C710 PIC16C71 PIC16C711 PIC16C712 PIC16C715 PIC16C716 PIC16C72A PIC16C73B

Clock

Memory

Peripherals

Features

Maximum Frequency
of Operation (MHz)

EPROM Program
Memory
(x14 words)

Data Memor y (bytes) 36 36 68 128 128 128 128 192
Timer Module(s) TMR0 TMR0 TMR0 TMR0

Capture/Compare/
PWM Module(s)

Serial Port(s)

2

C, USART)

(SPI/I
A/D Converter (8-bit)

Channels
Interrupt Sources 4 4 4 7 4 7 8 11
I/O Pins 13 13 13 13 13 13 22 22
Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5
In-Circuit Serial

Programming
Brown-out Reset Yes — Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP,

20 20 20 20 20 20 20 20

512 1K 1K 1K 2K 2K 2K 4K

——— 1 — 1 1 2

— — — — — — SPI/I

444 4 4 4 55

Yes Yes Yes Yes Yes Yes Yes Yes

SOIC;
20-pin SSOP

18-pin DIP,
SOIC

18-pin DIP,
SOIC;
20-pin SSOP

PIC16C712 PIC16C716

TMR1
TMR2

18-pin DIP,
SOIC;
20-pin SSOP

TMR0 TMR0

18-pin DIP,
SOIC;
20-pin SSOP

TMR1
TMR2

18-pin DIP,
SOIC;
20-pin SSOP

TMR0
TMR1
TMR2

28-pin SDIP,
SOIC, SSOP

2

CSPI/I2C,

TMR0
TMR1
TMR2

USART

28-pin SDIP,
SOIC

DS41106A-page 2 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

Table of Contents

1.0 Device Overview............................................................ ...... ..... ...... ..... ...... .................................. ..... ...... ..... ...... ..5

2.0 Memory Organization..........................................................................................................................................9

3.0 I/O Ports ............................................................................................................................................................21

4.0 Timer0 Module...................................................................................................................................................29

5.0 Timer1 Module...................................................................................................................................................31

6.0 Timer2 Module...................................................................................................................................................36

7.0 Capture/Compare/PWM (CCP) Module(s)........................................................................................................39

8.0 Analog-to-Digital Converter (A/D) Module.........................................................................................................45

9.0 Special Features of the CPU.............................................................................................................................51

10.0 Instruction Set Summary...................................................................................................................................67

11.0 Development Support........................................................................................................................................69

12.0 Electrical Characteristics..................................................... ..... ...... ..... ...... .................................. ..... ...... ..... ......75

13.0 DC and AC Characteristics Graphs and Tables................................................................................................91

14.0 Packaging Information.......................................................................................................................................93

Revision History ...........................................................................................................................................................99

Conversion Consideration s ...................................................... ...... ................................. ...... .. ... ...... ...... ..... .................99

Migration from Base-line to Mid-Range Devices ..........................................................................................................99

Index...........................................................................................................................................................................101

On-Line Support..........................................................................................................................................................105

Reader Response.......................................................................................................................................................106

PIC16C712/716 Product Identification System...........................................................................................................107

To Our Valued Customers

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1999 Microchip Technology Inc.



Preliminary DS41106A-page 3

PIC16C712/716

NOTES:

DS41106A-page 4 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

1.0 DEVICE OVERVIEW

This document contains device-specific information.

Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen­tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple­mentary document to this data she et, and is h ighly rec-

FIGURE 1-1: PIC16C712/716 BLOCK DIAGRAM

13

Program Counter

8 Level Stack

Direct Addr

8

(13-bit)

RAM Addr

7

Program

Bus

EPROM

1K X 14

or

2K x 14

Program
Memory

14

Instruction reg

ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.

There are two devices (PIC16C712, PIC16C716) cov­ered by this datasheet.

Figure 1- 1 is the block diagram for both devices. T he
pinouts are listed in Table 1-1.

Data Bus

RAM

128 x 8

File

Registers

(1)

Addr MUX

FSR reg

STATUS reg

8

9

Indirect

8

Addr

PORTA

PORTB

RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI

RB0/INT
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1
RB4
RB5
RB6
RB7

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VDD, VSS

MCLR

OSC1/CLKIN

OSC2/CLKOUT

Instruction

Decode &

Control

Timing

Generation

Timer0 Timer1 Timer2

CCP1

Note 1: Higher order bits are from the STATUS register.

3

8

A/D

MUX

ALU

W reg

1999 Microchip Technology Inc.



Preliminary DS41106A-page 5

PIC16C712/716

TABLE 1-1 PIC16C712/716 PINOUT DESCRIPTION

Pin PIC16C712/716 Pin Buffer

Name DIP, SOIC SSOP Type Type Description

MCLR/VPP

MCLR
VPP

OSC1/CLKIN

OSC1

CLKIN

44

I

P

16 18

I

I

ST Master clear (reset) input. This pin is an

active low reset to the device.
Programming voltage input

ST

CMOS

Oscillator crystal input or external clock
source input. ST buffer when configured in
RC mode. CMOS otherwi se.
External clock source input.

OSC2/CLKOUT

OSC2

CLKOUT

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2

RA2
AN2

RA3/AN3/V

RA4/T0CKI

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

REF

RA3
AN3
VREF

RA4
T0CKI

ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resistor is required if this pin is used as an output
NPU = N-channel pull-up PU = Weak internal pull-up
No-P diode = No P-diode to V
I = input O = output
P = Power L = LCD Driver

15 17

17 19

18 20

11

22

33

DD AN = Analog input or output

O

O

I/O

I/O

I/O

I/O

I/O

—

—

TTL

I

I

I

I
I

I

Analog

TTL

Analog

TTL

Analog

TTL
Analog
Analog

ST/OD

ST

Oscillator crystal output. Connects to
crystal or resonator in crystal oscillator
mode.
In RC mode, OSC2 pin outputs CLKOUT
which has 1/4 the frequenc y of OSC1, and
denotes the instruction cycle rate.

PORTA is a bi-directional I/O port.

Digital I/O
Analog input 0

Digital I/O
Analog input 1

Digital I/O
Analog input 2

Digital I/O
Analog input 3
A/D Reference Voltage input.

Digital I/O. Open drain when configured
as output.
Timer0 external clock input

DS41106A-page 6 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

TABLE 1-1 PIC16C712/716 PINOUT DESCRIPTION (Cont.’d)

Pin PIC16C712/716 Pin Buffer

Name DIP, SOIC SSOP Type Type Description

PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs .

RB0/INT

RB0
INT

RB1/T1OSO/T1CKI

RB1
T1OSO

T1CKI

RB2/T1OSI

RB2
T1OSI

RB3/CCP1

RB3
CCP1

RB4 10 12 I/O TTL Digital I/O

RB5 11 12 I/O TTL Digital I/O

RB6 12 13 I/O

RB7 13 14 I/O

SS 5 5, 6 P — Ground reference for logic and I/O pins.

V

DD 14 15, 16 P — Positive supply for logic and I/O pins.

V
Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resistor is required if this pin is used as an output
NPU = N-channel pull-up PU = Weak internal pull-up
No-P diode = No P-diode to V
I = input O = output
P = Power L = LCD Driver

67

78

89

910

DD AN = Analog input or output

I/O

I/O

O

I/O

I/O
I/O

I/O

TTL

I

I

I

I

ST

TTL

—

ST

TTL

—

TTL

ST

TTL

ST

TTL

ST

Digital I/O
External Interrupt

Digital I/O
Timer1 oscillator output. Connects to
crystal in oscillator mode.
Timer1 external clock input.

Digital I/O
Timer1 oscillator input. Connects to
crystal in oscillator mode.

Digital I/O
Capture1 input, Compa re1 output, PWM1
output.

Interrupt on change pin.

Interrupt on change pin.
Digital I/O

Interrupt on change pin.
ICSP programming clock.

Digital I/O
Interrupt on change pin.
ICSP programming data.

1999 Microchip Technology Inc.



Preliminary DS41106A-page 7

PIC16C712/716

NOTES:

DS41106A-page 8 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these
PICmicro
gram Memor y and Data Memor y) has its own bus so
that concurrent access can occur.

Additional inf ormation on de vice m emory may be f ound
in the PICmicro Mid-Range Reference Manual,
(DS33023).

2.1 Program Memory Organization

The PIC16C712/716 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. PIC16C712 has 1K x 14 words of program
memory and PIC16C716 has 2K x 14 words of progr am
memory. Accessing a location above the physically
implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is
at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

®

microcontr oller devices. Each blo ck (Pro-

AND STACK OF THE
PIC16C712

PC<12:0>

CALL, RETURN
RETFIE, RETLW

13

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK OF PIC16C716

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Space

User Memory

On-chip Program

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

Memory

13

0000h

0004h
0005h

07FFh
0800h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

Space

User Memory

On-chip Program

Memory

0000h

0004h
0005h

03FFh
0400h

1FFFh

1FFFh

1999 Microchip Technology Inc.



Preliminary DS41106A-page 9

PIC16C712/716

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.

(1)

RP1

= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)

Note 1: Maintain this bit clear to ensure upward compati-

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers . Abo v e the Sp ecial Functi on Regi s­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special

function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indi-

rectly through the File Select Register FSR
(Section 2.5).

RP0 (STATUS<6:5>)

bility with future products.

FIGURE 2-3: REGISTER FILE MAP

File

Address

00h INDF
01h TMR0
02h PCL PCL 82h
03h STATU S S TATUS 83h
04h FSR FSR 84h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
07h DATACCP TRISCCP 87h
08h

09h
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Dh
0Eh TMR1L PCON 8Eh

0Fh TRM1H
10h T1CON
11h TRM2
12h T2CON PR2 92h
13h
14h
15h CCPR1L
16h CCPR1H
17h CCP1CON
18h

19h
1Ah
1Bh
1Ch
1Dh
1Eh ADRES

1Fh ADCON0 ADCON1 9Fh

20h

(1)

General

Purpose

Registers

96 Bytes

(1)

INDF

OPTION_REG

General

Purpose

Registers

32 Bytes

80h
81h

88h
89h

8Dh

8Fh
90h
91h

93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh

A0h

BFh
C0h

File

Address

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations,

read as ’0’.

Note 1: Not a physical register.

DS41106A-page 10 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.2.2 SPECIAL FUNCTION REGISTERS

The special fu nction re gisters can b e classifi ed into two
sets; core (CPU) and periphe ral. Those registers asso-

The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.

ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h INDF
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h PCL
03h STATUS
04h FSR
05h PORTA
06h PORTB
07h DATACCP —
08h-09h — Unimplemented — —
0Ah PCLATH
0Bh INTCON
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding register for th e Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON
13h-14h
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
18h-1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,

Shaded locations are unimplemented, read as ’0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include: external reset through MCLR
4: The IRP and RP1 bits are reserved. Always maintain these bits clear .
5: On any device reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

(1)

(5,6)

(5,6)

(1,2)

(1)

(4)

IRP

Indirect data memory address pointer xxxx xxxx uuuu uuuu

— ——

PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

(7)

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

—ADIF— — — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

— — T1CKPS1 T 1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

RP1

—

(4)

RP0 TO PD ZDCCrr01 1xxx rr0q quuu

(7)

PORTA Data Latch when written: PORTA pins when read --xx xxxx --xu uuuu

(7)

(7)

—

(7)

—

(7)

—

DCCP

(7)

—

—ADON0000 00-0 0000 00-0

DT1CK

xxxx xxxx xxxx xuxu

and the Watchdog Timer Reset.

Value on all

other resets

(4)

1999 Microchip Technology Inc.



Preliminary DS41106A-page 11

PIC16C712/716

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h INDF

81h

82h PCL
83h STATUS
84h FSR
85h TRISA

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISCCP —
88h-89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh-91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h-9Eh — Unimplemented — —
9Fh ADCON1

OPTION_
REG

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

RBPU

(1)

Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

(1)

IRP

(1)

Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

(1)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(4)

— ——

(7)

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

—ADIE— — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000

— — — — — —PORBOR ---- --qq ---- --uu

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

RP1

—

(4)

RP0 TO PD ZDCCrr01 1xxx rr0q quuu

(7)

PORTA Data Direction Register --x1 1111 --x1 1111

(7)

(7)

—

(7)

—

(7)

—

TCCP

(7)

—

TT1CK

Value on:

POR,

BOR

xxxx x1x1 xxxx x1x1

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,

Shaded locations are unimplemented, read as ’0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include: external reset through MCLR

and the Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved. Always maintain these bits clear .
5: On any device reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.

Value on all

other resets

(4)

DS41106A-page 12 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 2-4, contains

the arithmetic status of th e ALU , the RE SET status an d
the bank select bits for data memory.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. The se bi ts ar e set or c leared accordi ng to the
device logic. Fur th er more, the TO
writable. Therefore, the result of an instruction with the
STATUS re gister as desti nation may be different t han
intended.

For example, CLRF STATUS will clear th e up p er -t h ree
bits and set the Z bi t. T his lea v e s the STATUS register
as 000u u1uu (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC b its from the STATUS register. F or
other instructions, not affecting any status bits, see the
"Instruction Set Summary."

Note 1: These devices do not use bits IRP and

RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub­traction. See the SUBLW and SUBWF
instructions for examples.

FIGURE 2-4: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect add ressing)

1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear
0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes
Note: RP1 = not implemented, maintain clear

bit 4: TO

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow

bit 0: C: Carry/borrow

: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borro w the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.

the polarity is reversed. A subtract io n is execut ed by adding the two’s complement of the

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

1999 Microchip Technology Inc.



Preliminary DS41106A-page 13

PIC16C712/716

2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable

register , which contai ns various c ontrol bits to c onfigure
the TMR0 prescaler/WDT postscaler (single assign­able regist er kno wn also as the prescale r), the Ext ernal
INT Interrupt, TMR0 and the w eak pull-up s on PORTB.

FIGURE 2-5: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

bit 6: INTEDG: Interrupt Edge Select bit

bit 5: T0CS: TMR0 Clock Source Select bit

bit 4: T0SE: TMR0 Source Edge Select bit

bit 3: PSA: Prescaler Assignment bit

bit 2-0: PS2:PS0: Prescaler Rate Select bits

INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enab led b y ind iv idu al port latch va lue s

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Note: To achieve a 1:1 prescaler as signmen t for

the TMR0 register, assign the prescaler to
the Watchdog Timer.

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS41106A-page 14 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.2.2.3 INTCON REGISTER
The INTCON Regi ster i s a rea dab le a nd w ritabl e regi s-

ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.

Note: Interrupt flag bits get set when an interrupt

condition occurs , re ga rdless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

FIGURE 2-6: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4: IINTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

1999 Microchip Technology Inc.



Preliminary DS41106A-page 15

PIC16C712/716

2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the

peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE — — — CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7: Unimplemented: Read as ‘0’
bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt
bit 5-3: Unimplemented: Read as ‘0’
bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS41106A-page 16 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.2.2.5 PIR1 REGI STER
This register contains the individual flag bits for the

peripheral interrupts.

Note: Interrupt flag bits get set when an interrupt

condition occurs , re ga rdless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

FIGURE 2-8: PIR1 REGISTER (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF — — — CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7: Unimplemen ted: Read as ‘0’
bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete
bit 5-3: Unimplemented: Read as ‘0’
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 re gister capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

1999 Microchip Technology Inc.



Preliminary DS41106A-page 17

PIC16C712/716

2.2.2.6 PCON REGISTER
The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset
(POR) to an external MCLR
These devices contain an additional bit to differentiate
a Brown-out Reset condition from a Power-on Reset
condition.

Reset or WDT Reset.

Note: If the BODEN configuration bit is set, BOR

is ’1’ on Power-on Reset. If the BODEN
configuration bit is clear, BOR
on Power-on Reset.

The BOR status bit is a "don't care" and is
not necessarily predictab le if the brow n-out
circuit is disabled (the BOD EN configura­tion bit is clear). BOR
the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.

FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — —PORBOR R = Readable bit

bit7 bit0

bit 7-2: Unimplemented: Read as ’0’
bit 1: POR

bit 0: BOR

: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

is unknown

must then be set by

read as ‘0’

DS41106A-page 18 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

2.3 PCL and PCLATH

The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg­ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not dir ect ly read able or writable. All updates
to the PCH register go through the PCLATH register.

2.3.1 STACK The stack a llows a co mbination o f up to 8 pr ogram ca lls

and interrupts to occur. The stack contains the return
address from this branch in program execution.

Midrange devices have an 8 level deep x 1 3-bit wide
hardware stack. T he stack space is not part of either
program or data space and the stack pointer is not
readable or writab le. The PC is PUSHed onto the stac k
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.

After the stac k has been PUSHe d eight t imes, th e ninth
push overw rites th e value that was stored from the first
push. The tenth push overwrites the second pus h (an d
so on).

2.4 Program Memory Paging

The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bit is pro­grammed so th at th e des ire d pr ogram memory page is
addressed. If a return from a CALL instruction (or inter­rupt) is executed, the entire 1 3-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).

1999 Microchip Technology Inc.



Preliminary DS41106A-page 19

PIC16C712/716

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical r e gis ter. Address­ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a

pointer

). This is indirect ad dressi ng .

EXAMPLE 2-1: INDIRECT ADDRESSING

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the v alue of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).

FIGURE 2-10: DIRECT/INDIRECT ADDRESSING

RP1:RP0 6

(2)

from opcode

0

A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM

USING INDIRECT
ADDRESSING

movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue

An effective 9-bit addres s is o btai ne d by concatenatin g
the 8-bit FSR register an d the IRP b it (STATUS<7>), as
shown in Figure 2-10. However, IRP is not used in the
PIC16C712/716.

Indirect AddressingDirect Addressing

IRP FSR register

7

(2)

0

bank select location select

00 01 10 11

00h

80h

Data
Memory(1)

7Fh

FFh

Bank 0 Bank 1 Bank 2 Bank 3

Note 1: For register file map detail see Figure 2-3.

2: Maintain clear for upward compatibility with future products.
3: Not implemented.

100h

(3) (3)

17Fh

180h

1FFh

bank select

location select

DS41106A-page 20 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

Additional information on I/O ports ma y b e found in the

PICmicro™ Mid-Range Reference Manual,
(DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 5-bit wide bi-directional port. The corre­sponding data direction register is TRISA. Setting a
TRISA bit (=1) will m ake the correspondi ng PORTA pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corre sponding POR TA pin an output, (i .e., put
the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, the val ue is mod ifi ed, and then written to the port
data latch.

Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers .

PORTA pins, RA3:0, are m ultiplex ed with ana log inputs
and analog V

REF input. The operation of each pin is

selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).

Note: On a Power-on Reset, these pins are con-

figured as analog inputs and read as '0'.

The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bi ts in the TRISA registe r are
maintained set when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xEF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<4> as outputs
BCF STATUS, RP0 ; Return to Bank 0

FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0

DATA
BUS

WR
PORT

WR
TRIS

CK

Data Latch

CK

TRIS Latch

RD PORT

QD

Q

QD

Q

RD TRIS

QD

EN

VDD

P

N

SS

V

Analog
input
mode

VSS

VDD

I/O pin

TTL
Input
Buffer

1998 Microchip Technology Inc.



To A/D Conver ter

Preliminary DS41106A-page 21

PIC16C712/716

FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN

DA TA
BUS

WR
PORT

WR
TRIS

RD PORT

TMR0 Clock Input

QD

Q

CK

Data Latch

QD

Q

CK

TRIS Latch

RD TRIS

N

V

QD

EN

EN

TABLE 3-1 PORTA FUNCTIONS

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2 bit2 TTL Input/output or analog input
RA3/AN3/V

RA4/T0CKI bit4 ST
Legend: TTL = TTL input, ST = Schmitt Trigger input

REF bit3 TTL Input/output or analog input or VREF

Input/output or external clock input for Timer0
Output is open drain type

SS

VSS

Schmitt
Trigger
Input
Buffer

I/O Pin

TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR,
BOR

05h PORTA

85h TRISA
9Fh ADCON1

— — —
— — —
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

(1)

RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu

(1)

PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by

PORTA.

Note 1: Reserved bits; Do Not Use.

DS41106A-page 22 Preliminary 

1998 Microchip Technology Inc.

Value on all

other resets

PIC16C712/716

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corre­sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the correspon ding POR TB pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, (i.e.,
put the contents of the output latch on the selected pin).

EXAMPLE 3-1: INITIALIZING PORTB

BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs

FIGURE 3-3: BLOCK DIAGRAM OF RB0 PIN

(1)

RBPU

DATA BUS

WR PORT

WR TRIS

Data Latch

QD

CK

TRIS Latch

QD

CK

Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-u ps. This is per­formed by clea ring bi t RBPU

(OPTION_REG<7>). The
weak pull-u p is auto matical ly tur ned off when the p or t
pin is configured as an output. The pull-ups are dis­abled on a Power-on Reset.

V

DD

VDD

weak

P

pull-up

I/O
pin

TTL
Input
Buffer

VSS

RB0/INT

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

1999 Microchip Technology Inc.



RD TRIS

RD PORT

Schmitt Trigger
Buffer

QD

EN

RD PORT

Preliminary DS41106A-page 23

PIC16C712/716

PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (T able 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
periphe rals override the TRIS bit to make a pin an out­put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify­write instructions (BSF, BCF, XORWF) with TRISB as
destination shou ld be a voi ded. The us er should refe r to
the corresponding peripheral section for the correct
TRIS bit settings.

Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to oc cur (i.e . any RB7:RB4 pin con­figured as an output is excluded from the interrupt on
change comparison). The input pins, RB7:RB4, are

PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter­rupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The
user, i n the interrupt service routine , can clea r the inter­rupt in the following manner:

a) Any read or write of PORTB will end the mis-

match condition.

b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.

The interrupt on change feature is recommended for
wake-up on key depression operation and opera tions
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.

compared with th e o ld value latche d o n the la st read of

FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN

(1)

RBPU
T1OSCEN
T1CS

DATA BUS

RD
DATACCP

WR
DATACCP

WR
TRISCCP

WR
PORTB

WR TRISB
T1OSCEN
TMR1CS

DATACCP<0>

QD
Q

CK

TRISCCP<0>

QD
Q

CK

PORTB<1>

QD
Q

CK

TRISB<1>

QD
Q

CK

1
0

1
0

V

DD

P

weak
pull-up

VDD

RB1/T1OSO/T1CKI

VSS

1

TTL Buffer

RD PORTB

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

DS41106A-page 24 Preliminary 

0

T1CLKIN

ST
Buffer

1999 Microchip Technology Inc.

FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN

(1)

RBPU
T1OSCEN

DATA B US

WR PORTB

PORTB<2>

QD

Q

CK

V

P

DD

weak
pull-up

PIC16C712/716

VDD

RB1/T1OSO/T1CKI

TRISB<2>

QD

WR TRISB

T1OSCEN

RD PORTB

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

CK

Q

TTL Buffer

FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN

(1)

RBPU

CCPON

CCPON

CK

CK

1
0

CCPOUT

1

QD
Q

QD
Q

0

1
0

QD
Q

QD

Q

1
0

DATA BUS
RD

DATACCP

WR
DATACCP

WR
TRISCCP

CCP
Output
Mode

WR
PORTB

WR
TRISB

DATACCP<2>

TRISCCP<2>

PORTB<3>

CK

TRISB<3>

CK

VSS

V

DD

P

CCPIN

weak
pull-up

VDD

RB3/CCP1

VSS

CCPON

RD PORTB

1999 Microchip Technology Inc.



1

0

TTL Buffer

Note 1: To enable weak pull-ups, set the appropr iate TRIS b it(s)

and clear the RBPU bit (OPTION_REG<7>).

Preliminary DS41106A-page 25

PIC16C712/716

FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS

(1)

RBPU

DATA BUS

WR PORT

WR TRIS

Data Latch

QD

CK

TRIS Latch

QD

CK

TTL
Buffer

V

P

DD

weak
pull-up

ST

Buffer

VDD

I/O
pin

VSS

RD TRIS

Set RBIF

From other
RB7:RB4 pins

RB7:RB6 in serial programming mode

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

RD PORT

Latch

QD

EN

QD

EN

Q1

RD PORT

Q3

TABLE 3-3 PORTB FUNCTIONS

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

RB1/T1OS0/

bit1

TTL/ST

T1CKI

RB2/T1OSI bit2

RB3/CCP1 bit3

TTL/ST

TTL/ST

RB4 bit4 TTL Input/output pin (with interrupt on chang e). Internal so ftware prog ra mmab le

RB5 bit5 TTL Input/output pin (with interrupt on chang e). Internal so ftware prog ra mmab le

RB6 bit6 TTL/ST

RB7 bit7 TTL/ST

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

(1)

Input/output pin or external interrupt input. Internal software
programmable weak pull-up.

(1)

Input/output pin or Timer 1 os cilla tor outpu t, or Tim er 1 cl oc k inp ut. Inte rnal
software programmable weak pull-up. See Timer1 section for detailed
operation.

(1)

Input/output pin or T imer 1 os cilla tor in put. Internal s oftw are prog ram mab le
weak pull-up. See Timer1 section for detailed operation.

(1)

Input/output pin or Captu re 1 input , or Com pare 1 outp ut, or PWM1 output.
Internal software programmable weak pull-up. See CCP1 section for
detailed operation.

weak pull-up .

weak pull-up .

(2)

Input/output pin (with in terrupt on ch ange). In ternal softw are prog ramm ab le
weak pull-up. Serial programming clock.

(2)

Input/output pin (with in terrupt on ch ange). In ternal softw are prog ramm ab le
weak pull-up. Serial programming data.

DS41106A-page 26 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h OPTION_REG RBPU

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Value on:

POR,

BOR

Value on all

other resets

1999 Microchip Technology Inc.



Preliminary DS41106A-page 27

PIC16C712/716

NOTES:

DS41106A-page 28 Preliminary 

1999 Microchip Technology Inc.

PIC16C712/716

4.0 TIMER0 MODUL E

The Timer0 module ti mer/count er has the f ollo wing f ea­tures:

• 8-bit timer/counter

• Readable and writable

• Internal or external clock select

• Edge select for external clock

• 8-bit software programmable prescaler

• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0

module.
Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,
(DS33023).

4.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In timer mode, the Timer0 mod­ule will increment every instruction cycle (without pres­caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.

Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0 SE sel ec ts the ris­ing edge. Restrictions on the external clock input are
discussed be low.

When an ex ternal clock i nput is used f or Timer0 , it must
meet certain requirements. The requirements ensure
the external c lock can be synchron ized w ith the int ernal
phase clock (T
incrementing of Timer0 after synchronization.

OSC). Also, there is a delay in the actual

Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manual, (DS33023).

4.2 Prescaler

An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
avail able, w hich is mutually exclus ively sha red between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.

The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler a ssignment an d prescale ratio .
Clearing bit PSA will assign the prescale r to the Time r0

module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.

Setting bit PSA will assign the prescaler to the Watch­dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.

When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g . CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.

FIGURE 4-1: TIMER0 BLOCK DIAGRAM

FOSC/4

RA4/T0CKI
pin

T0SE

(1)

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).

1999 Microchip Technology Inc.



0

1

T0CS

Programmable

PS2, PS1, PS0

(1)

Prescaler

(2)

3

(1)

Preliminary DS41106A-page 29

PSA

1

0

PSout

(1)

Sync with

Internal

clocks

(2 cycle delay)

Data Bus

8

TMR0

PSout

Set interrupt

flag bit T0IF

on overflow

PIC16C712/716

4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the fly” during program
ex ec utio n.

Note: To avoid an unintended d evice RESET, a

specific instruction sequence (shown in
the PICmicro™ Mid-Range Reference
Manual, DS33023) must be executed
when changing the prescaler a ssignment

4.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg­ister overflows from FFh to 00 h. This overflow sets bit
T0IF (INTC ON<2>). The inter rupt can be mas ked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in softwa re b y the T imer0 mo dule interrupt s er­vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.

from Timer0 to the WDT. This sequence
must be followed even if the WDT is dis­abled.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (=Fos c/ 4)

RA4/T0CKI

pin

T0SE

0

1

T0CS

M
U

X

1

M
U

0

X

PSA

SYNC

2

Cycles

Data Bus

8

TMR0 reg

Set flag bit T0IF

on Overflow

0

M

U

1

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

X

PSA

8-bit Prescaler

8

8 - to - 1MUX

0

M U X

WDT

Time-out

PS2:PS0

1

PSA

TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE
81h OPTION_REG
85h TRISA

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— — —

(1)

Bit 4 PORTA Data Direction Register --11 1111 --11 1111

Value on:

POR,

BOR

Note 1: Reserved bit; Do Not Use.

Value on all

other resets

DS41106A-page 30 Preliminary 

1999 Microchip Technology Inc.