MICROCHIP PIC16C6X Technical data

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•

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

查询PIC16C61供应商

PIC16C6X

8-Bit CMOS Microcontrollers

Devices included in this data sheet:

• PIC16C61 • PIC16C64A

• PIC16C62 • PIC16CR64

• PIC16C62A • PIC16C65

• PIC16CR62 • PIC16C65A

• PIC16C63 • PIC16CR65

• PIC16CR63 • PIC16C66

• PIC16C64 • PIC16C67

PIC16C6X Microcontroller Core Features:

• High performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program
branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM/ROM
technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• Commercial, Industrial, and Extended
temperature ranges

• Low-power consumption:

< 2 mA @ 5V, 4 MHz
15 µ A typical @ 3V, 32 kHz
< 1 µ A typical standby current

PIC16C6X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via
external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Capture/Compare/PWM (CCP) module(s)

• Capture is 16-bit, max resolution is 12.5 ns,
Compare is 16-bit, max resolution is 200 ns,
PWM max resolution is 10-bit.

• Synchronous Serial Port (SSP) with SPI

• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with
external RD

, WR and CS controls

• Brown-out detection circuitry for
Brown-out Reset (BOR)



and I

2



C

PIC16C6X Features 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Program Memory
(EPROM) x 14

(ROM) x 14 — — — 2K — 4K — — 2K — — 4K — —
Data Memory (Bytes) x 8 36 128 128 128 192 192 128 128 128 192 192 192 368 368
I/O Pins 13 22 22 22 22 22 33 33 33 33 33 33 22 33
Parallel Slave Port ———— — —YesYesYesYes Yes Yes — Yes
Capture/Compare/PWM

Module(s)
Timer Modules 1333 3 3 333 33333
Serial Communication

In-Circuit Serial
Programming

Brown-out Reset — — Yes Yes Yes Yes — Yes Yes — Yes Yes Yes Yes
Interrupt Sources 377710 10 888 11 11 11 10 11
Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25

1997 Microchip Technology Inc. DS30234D-page 1

1K 2K 2K — 4K — 2K 2K — 4K 4K — 8K 8K

—1112211122222

SPI/

— SPI/

2

C

I

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Ye s

SPI/

2

2

I

C

I

C

2

SPI/I

USART

C,

2

SPI/I

USART

SPI/

C,

SPI/

2

C

I

SPI/

2

2

I

C

I

C

SPI/I

USART

2

C,

2

SPI/I

USART

C,

2

SPI/I

USART

C,

2

SPI/I

USART

C,

2

SPI/I

USART

C,



PIC16C6X

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

RA2
RA3

RA4/T0CKI

MCLR/VPP

VSS

RB0/INT

RB1
RB2
RB3

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4

PIC16C61

SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V

DD

VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA

SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSI/T1CKI

RC1/T1OSO

RC2/CCP1

RC3/SCK/SCL

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA

PIC16C62

SDIP, SOIC, Windowed CERDIP (300 mil)

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7
RB6

RB5
RB4
RB3
RB2
RB1
RB0/INT
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS
RE0/RD

RE1/WR

RE2/CS

VDD
VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSI/T1CKI

RC1/T1OSO

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

PIC16C62A
PIC16CR62

40

1

39

2

38

3

37

4

36

5

35

6

34

7

33

8

32

9

31

10

30

11

29

12

28

13

27

14

26

15

25

16

24

17

23

18

22

19

21

20

PIC16C64

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V

DD

VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

PDIP , Windowed CERDIP

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS
RE0/RD

RE1/WR

RE2/CS

VDD

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI
RC2/CCP1

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC16C64A
PIC16CR64

PIC16C63
PIC16CR63
PIC16C66

40

RB7

39

RB6

38

RB5

37

RB4

36

RB3

35

RB2

34

RB1

33

RB0/INT

32

V

31
30
29
28
27
26
25
24
23
22
21

DD

VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

MCLR/VPP

RA0
RA1
RA2
RA3

RA4/T0CKI

RA5/SS
RE0/RD

RE1/WR

RE2/CS

VDD
VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

RB7

39

RB6

38

RB5

37

RB4

36

RB3

35

RB2

34

RB1

33

RB0/INT

32

V
31
30
29
28
27
26
25
24
23
22
21

DD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

PIC16C65
PIC16C65A
PIC16CR65
PIC16C67

DS30234D-page 2

1997 Microchip Technology Inc.

Pin Diagrams (Cont.’d)



PIC16C6X

MQFP

RC4/SDI/SDA

RC6

RC5/SDO

RD3/PSP3

4443424140393837363534

RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V
VDD

RB0/INT

RB1
RB2
RB3

SS

1
2
3
4
5
6

PIC16C64

7
8
9
10
11

RB4

NC

NC

RB5

RB6

MQFP,
TQFP (PIC16C64A only)

RC4/SDI/SDA

RC6

RC5/SDO

RD3/PSP3

RD2/PSP2

RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V

VDD

RB0/INT

RB1

RB2

RB3

SS

1
2
3
4
5
6

PIC16C64A

7
8

PIC16CR64

9
10
11

RD2/PSP2

RD1/PSP1

RD0/PSP0

RA0

MCLR

RB7

/VPP

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

NC

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSO

33
32
31
30
29
28
27
26
25
24
23

2221201918171615141312

RA3

RA2

RA1

NC

RC2/CCP1

RC1/T1OSI

3435363738394041424344

33
32
31
30
29
28
27
26
25
24
23

2221201918171615141312

NC
RC0/T1OSI/T1CKI

OSC2/CLKOUT
OSC1/CLKIN

SS

V

VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI

NC
RC0/T1OSO/T1CKI

OSC2/CLKOUT
OSC1/CLKIN

SS

V
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI

PLCC

RA4/T0CKI

RA5/SS
RE0/RD
RE1/WR

RE2/CS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSI/T1CKI

PLCC

RA4/T0CKI

RA5/SS
RE0/RD

RE1/WR

RE2/CS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

VDD

VSS

RA3

65432

7
8
9
10

VDD
VSS

NC

NC

11
12
13
14
15
16
17

RC1/T1OSO

RA3

65432

7
8
9
10
11
12

PIC16C64A

13

PIC16CR64

14
15
16
17

NC

RA2

RA1

RA0

MCLR/VPP

1

PIC16C64

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

NC

RA2

RA1

RA0

MCLR/VPP

RB7

1

4443424140

RB7

RB6

RB5

RB4

4443424140

2827262524232221201918

NC

RC6

RC5/SDO

RC4/SDI/SDA

RB6

RB5

RB4

NC

2827262524232221201918

NC

39
38
37
36
35
34
33
32
31
30
29

39
38
37
36
35
34
33
32
31
30
29

RB3
RB2
RB1
RB0/INT

DD

V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7

RB3
RB2
RB1
RB0/INT

DD

V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7

MCLR

RB7

RB6

RB5

RB4

NC

NC

/VPP

MQFP,
TQFP (Not on PIC16C65)

RC4/SDI/SDA

RC6/TX/CK

RC5/SDO

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

4443424140393837363534

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V
VDD

RB0/INT

RB1
RB2
RB3

SS

1
2
3
4

PIC16C65

5

PIC16C65A

6
7

PIC16CR65

8
9

PIC16C67

10
11

RB5

RB4

NC

NC

RB6

RB7

MCLR/VPP

RA3

RA2

RA1

RA0

NC

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

2221201918171615141312

RA3

RA2

RA1

RA0

NC

RC6

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

PLCC

RA3

65432

RA4/T0CKI

33
32
31
30
29
28
27
26
25
24
23

NC
RC0/T1OSO/T1CKI

OSC2/CLKOUT
OSC1/CLKIN

SS

V
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI

RA5/SS
RE0/RD

RE1/WR

RE2/CS

VDD
VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

NC

7
8
9
10
11
12
13
14
15
16
17

RC1/T1OSI

/CCP2

NC

RA2

RA1

RA0

MCLR/VPP

RB7

RB6

1

4443424140

PIC16C65

PIC16C65A
PIC16CR65

PIC16C67

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RB5

RB4

2827262524232221201918

NC

RC6/TX/CK

RC5/SDO

NC

39
38
37
36
35
34
33
32
31
30
29

RB3
RB2
RB1
RB0/INT

DD

V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT

1997 Microchip Technology Inc. DS30234D-page 3



PIC16C6X

Table Of Contents

1.0 General Description....................................................................................................................................................................... 5

2.0 PIC16C6X Device Varieties........................................................................................................................................................... 7

3.0 Architectural Overview................................................................................................................................................................... 9

4.0 Memory Organization................................................................................................................................................................... 19

5.0 I/O Ports....................................................................................................................................................................................... 51

6.0 Overview of Timer Modules......................................................................................................................................................... 63

7.0 Timer0 Module............................................................................................................................................................................. 65

8.0 Timer1 Module............................................................................................................................................................................. 71

9.0 Timer2 Module............................................................................................................................................................................. 75

10.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 77

11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 83

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module ....................................................................... 105

13.0 Special Features of the CPU ..................................................................................................................................................... 123

14.0 Instruction Set Summary............................................................................................................................................................ 143

15.0 Development Support ................................................................................................................................................................ 159

16.0 Electrical Characteristics for PIC16C61..................................................................................................................................... 163

17.0 DC and AC Characteristics Graphs and Tables for PIC16C61.................................................................................................. 173

18.0 Electrical Characteristics for PIC16C62/64................................................................................................................................ 183

19.0 Electrical Characteristics for PIC16C62A/R62/64A/R64............................................................................................................ 199

20.0 Electrical Characteristics for PIC16C65..................................................................................................................................... 215

21.0 Electrical Characteristics for PIC16C63/65A ............................................................................................................................. 231

22.0 Electrical Characteristics for PIC16CR63/R65........................................................................................................................... 247

23.0 Electrical Characteristics for PIC16C66/67................................................................................................................................ 263

24.0 DC and AC Characteristics Graphs and Tables for:
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64,

PIC16C65A, PIC16C66, PIC16C67........................................................................................................................................... 281

25.0 Packaging Information ............................................................................................................................................................... 291

Appendix A: Modifications.............................................................................................................................................................. 307

Appendix B: Compatibility .............................................................................................................................................................. 307

Appendix C: What’s New................................................................................................................................................................ 308

Appendix D: What’s Changed ........................................................................................................................................................ 308

Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 309

Pin Compatibility ................................................................................................................................................................................ 315

Index .................................................................................................................................................................................................. 317

List of Equation and Examples........................................................................................................................................................... 326

List of Figures..................................................................................................................................................................................... 326

List of Tables...................................................................................................................................................................................... 330

Reader Response.............................................................................................................................................................................. 334

PIC16C6X Product Identification System........................................................................................................................................... 335

For register and module descriptions in this data sheet, device legends show which de vices apply to those sections . For
example, the legend below shows that some features of only the PIC16C62A, PIC16CR62, PIC16C63, PIC16C64A,
PIC16CR64, and PIC16C65A are described in this section.

Applicable Devices

62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

61

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS30234D-page 4

1997 Microchip Technology Inc.



PIC16C6X

1.0 GENERAL DESCRIPTION

The PIC16CXX is a family of
mance, CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller f am­ily has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available . Additionally, a large register set gives
some of the architectural innovations used to achie v e a
very high performance.

PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.

The PIC16C61 device has 36 bytes of RAM and 13 I/O
pins. In addition a timer/counter is available.

The PIC16C62/62A/R62 devices have 128 bytes of
RAM and 22 I/O pins. In addition, several peripheral
features are available, including: three timer/counters,
one Capture/Compare/PWM module and one serial
port. The Synchronous Serial Por t can be configured
as either a 3-wire Serial Peripheral Interface (SPI  ) or
the two-wire Inter-Integrated Circuit (I

The PIC16C63/R63 devices have 192 bytes of RAM,
while the PIC16C66 has 368 bytes. All three devices
have 22 I/O pins. In addition, several peripheral fea­tures are available, including: three timer/counters, two
Capture/Compare/PWM modules and two serial ports.
The Synchronous Serial Port can be configured as
either a 3-wire Serial Peripheral Interface (SPI) or the
two-wire Inter-Integrated Circuit (I
sal Synchronous Asynchronous Receiver Transmitter
(USART) is also know as a Serial Communications
Interface or SCI.

The PIC16C64/64A/R64 devices have 128 bytes of
RAM and 33 I/O pins. In addition, several peripheral
features are available, including: three timer/counters,
one Capture/Compare/PWM module and one serial
port. The Synchronous Serial Por t can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I
Parallel Slave Port is also provided.

The PIC16C65/65A/R65 devices have 192 bytes of
RAM, while the PIC16C67 has 368 bytes. All four
devices hav e 33 I/O pins. In addition, se ver al peripheral
features are available, including: three timer/counters,
two Capture/Compare/PWM modules and two serial
ports. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I
versal Synchronous Asynchronous Receiver Transmit-

low-cost, high-perfor-

2

C) bus.

2

C) bus. The Univer-

2

C) bus. An 8-bit

2

C) bus. The Uni-

ter (USART) is also known as a Serial Communications
Interface or SCI. An 8-bit P arallel Sla ve Port is also pro­vided.

The PIC16C6X device family has special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power con­sumption. There are f our oscillator options , of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers a power saving
mode. The user can wake the chip from SLEEP
through several external and internal interrupts, and
resets.

A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock­up.

A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective
One-Time-Programmable (OTP) version is suitable for
production in any volume.

The PIC16C6X family fits perfectly in applications rang­ing from high-speed automotive and appliance control
to low-power remote sensors, keyboards and telecom
processors. The EPROM technology makes customi­zation of application programs (transmitter codes,
motor speeds, receiver frequencies, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applica­tions with space limitations. Low-cost, low-power, high
performance, ease-of-use, and I/O flexibility make the
PIC16C6X very versatile ev en in areas where no micro­controller use has been considered before (e.g. timer
functions, serial communication, capture and compare,
PWM functions, and co-processor applications).

1.1 F

Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to
PIC16CXX family of devices (Appendix B).

1.2 De

PIC16C6X devices are supported by the complete line
of Microchip Development tools.

Please refer to Section 15.0 for more details about
Microchip’s development tools.

amily and Upward Compatibility

velopment Support

1997 Microchip Technology Inc. DS30234D-page 5

PIC16C6X

TABLE 1-1: PIC16C6X FAMILY OF DEVICES



Clock

Memory

Peripherals

Features

PIC16C61

Maximum Frequency
of Operation (MHz)

EPROM Program Memory
(x14 words)

ROM Program Memory
(x14 words)

Data Memory (bytes) 36 128 128 192 192
Timer Module(s) TMR0 TMR0,

Capture/Compare/
PWM Module(s)

Serial Port(s)

2

(SPI/I

C, USART)
Parallel Slave Port — — — — —
Interrupt Sources 3 7 7 10 10
I/O Pins 13 22 22 22 22
Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes Yes
Brown-out Reset — Yes Yes Yes Yes
Packages 18-pin DIP, SO 28-pin SDIP,

20 20 20 20 20

1K 2K — 4K —

— — 2K — 4K

—1122

— SPI/I

PIC16C62A PIC16CR62 PIC16C63 PIC16CR63

TMR1,
TMR2

2

C SPI/I

SOIC, SSOP

TMR0,
TMR1,
TMR2

2

C SPI/I

28-pin SDIP,
SOIC, SSOP

TMR0,
TMR1,
TMR2

2

C,

USART

28-pin SDIP,
SOIC

TMR0,
TMR1,
TMR2

SPI/I
USART

28-pin SDIP,
SOIC

2

C

PIC16C64A

Clock

Memory

Peripherals

Features

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.

Maximum Frequency
of Operation (MHz)

EPROM Program Memory
(x14 words)

ROM Program Memory (x14
words)

Data Memory (bytes) 128 128 192 192 368 368
Timer Module(s) TMR0,

Capture/Compare/PWM Mod­ule(s)

Serial Port(s) (SPI/I

Parallel Slave Port Yes Yes Yes Yes — Yes
Interrupt Sources 8 8 11 11 10 11
I/O Pins 33 33 33 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes Yes Yes
Packages 40-pin DIP;

2

C, USART) SPI/I2C SPI/I2C SPI/I2C,

20 20 20 20 20 20

2K — 4K — 8K 8K

—2K— 4K——

TMR1,
TMR2

1 1 2 222

44-pin PLCC,
MQFP, TQFP

PIC16CR64 PIC16C65A PIC16CR65 PIC16C66 PIC16C67

TMR0,
TMR1,
TMR2

40-pin DIP;
44-pin PLCC,
MQFP, TQFP

TMR0,
TMR1,
TMR2

USART

40-pin DIP;
44-pin PLCC,
MQFP, TQFP

TMR0,
TMR1,
TMR2

SPI/I2C,
USART

40-pin DIP;
44-pin
PLCC,
MQFP,
TQFP

TMR0,
TMR1,
TMR2

SPI/I2C,
USART

28-pin SDIP,
SOIC

TMR0,
TMR1,
TMR2

SPI/I2C,
USART

40-pin DIP;
44-pin
PLCC,
MQFP,
TQFP

DS30234D-page 6

1997 Microchip Technology Inc.

PIC16C6X

2.0 PIC16C6X DEVICE VARIETIES

A variety of frequency ranges and packaging options
are available . Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C6X Product Identifi­cation System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.

For the PIC16C6X family of devices, there are four
device “types” as indicated in the device number:

1. C, as in PIC16C64. These devices have
EPROM type memory and operate over the
standard voltage range.

2. LC, as in PIC16LC64. These devices have
EPROM type memory and operate over an
extended voltage range.

3. CR, as in PIC16CR64. These devices have
ROM program memory and operate over the
standard voltage range.

4. LCR, as in PIC16LCR64. These devices have
ROM program memory and operate over an
extended voltage range.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.

Microchip's PICSTART
programmers both support programming of the
PIC16C6X.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.

The OTP devices, packaged in plastic packages, per­mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.



Plus and PRO MATE II

2.3 Quick-Turnaround-Production (QTP)
Devices

Microchip offers a QTP Programming Service for fac­tory production orders. This ser vice is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi­lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc­tion shipments are available. Please contact your local
Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround
Production (SQTPSM) Devices

Microchip offers a unique programming service where
a few user-defined locations in each device are pro­grammed with different serial numbers. The serial num­bers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.

ROM devices do not allow serialization information in
the program memory space. The user may have this
information programmed in the data memory space.

For information on submitting ROM code, please con­tact your regional sales office.

2.5 Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.

For information on submitting ROM code, please con­tact your regional sales office.

 1997 Microchip Technology Inc. DS30234D-page 7

PIC16C6X

NOTES:

DS30234D-page 8  1997 Microchip Technology Inc.

PIC16C6X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be
attributed to a number of architectural features com­monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memo­ries using separate buses. This improves bandwidth
over traditional von Neumann architecture where pro­gram and data may be fetched from the same memory
using the same bus. Separ ating program and data b us­ses further allows instructions to be sized differently
than 8-bit wide data words. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two­stage pipeline overlaps fetch and execution of instruc­tions (Example 3-1). Consequently, all instructions exe­cute in a single cycle (200 ns @ 20 MHz) except for
program branches.

The PIC16C61 addresses 1K x 14 of program memory.
The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 of
program memory, and the PIC16C63/R63/65/65A/R65
devices address 4K x 14 of program memory. The
PIC16C66/67 address 8K x 14 program memory. All
program memory is internal.

The PIC16CXX can directly or indirectly address its
register files or data memory. All special function reg­isters including the program counter are mapped in
the data memory. The PIC16CXX has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
“special optimal situations” makes programming with
the PIC16CXX simple yet efficient, thus significantly
reducing the learning curve.

The PIC16CXX device contains an 8-bit ALU and work­ing register (W). The ALU is a general pur pose arith­metic unit. It perf orms arithmetic and Boolean functions
between data in the working register and any register
file.

The ALU is 8-bits wide and capable of addition, sub­traction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple­ment in nature. In two-operand instructions, typically
one operand is the working register (W register), the
other operand is a file register or an immediate con­stant. In single operand instructions, the operand is
either the W register or a file register.

The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.

Depending upon the instruction executed, the ALU ma y
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. Bits C and DC
operate as a borro
tively, in subtraction. See the SUBLW and SUBWF
instructions for examples.

w and digit borrow out bit, respec-

 1997 Microchip Technology Inc. DS30234D-page 9

PIC16C6X

FIGURE 3-1: PIC16C61 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

EPROM

Program

Memory
1K x 14

14

Instruction reg

Instruction

Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

MCLR

(13-bit)

Timer

Reset

Timer

VDD, VSS

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

36 x 8

(1)

Addr MUX

FSR reg

STATUS reg

ALU

W reg

Timer0

9

8

MUX

8

Indirect

Addr

PORTA

RA0
RA1
RA2
RA3

RA4/T0CKI

PORTB

RB0/INT

RB7:RB1

Note 1: Higher order bits are from the STATUS register.

DS30234D-page 10  1997 Microchip Technology Inc.

FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM

PIC16C6X

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

EPROM/

ROM

Program

Memory

2K x 14

14

Instruction reg

Instruction
Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Start-up Timer

Watchdog

Brown-out

MCLR

(13-bit)

Power-up

Timer

Oscillator

Power-on

Reset

Timer

(3)

Reset

VDD, VSS

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

128 x 8

(1)

9

Addr MUX

8

FSR reg

STATUS reg

MUX

ALU

W reg

Parallel Slave

Port

8

Indirect

Addr

PORTA

PORTB

PORTC

PORTD

PORTE

RA0
RA1
RA2

RA3
RA4/T0CKI
RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1

RC3/SCK/SCL
RC4/SDI/SDA

RC5/SDO
RC6
RC7

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

RE0/RD

(4)

(4)

Timer1 Timer2 CCP1

Timer0

Synchronous

Serial Port

Note 1: Higher order bits are from the STATUS register.

2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62.
3: Brown-out Reset is not available on the PIC16C62/64.
4: Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64.

RE1/WR

RE2/CS

(Note 2)

 1997 Microchip Technology Inc. DS30234D-page 11

PIC16C6X

FIGURE 3-3: PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN
OSC2/CLKOUT

EPROM

Program

Memory

4K x 14

14

Instruction reg

Instruction
Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

MCLR

(13-bit)

Timer

Reset

Timer

Reset

(3)

VDD, VSS

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

192 x 8

(1)

9

Addr MUX

8

FSR reg

STATUS reg

MUX

ALU

W reg

Parallel Slave

Port

8

Indirect

Addr

PORTA

PORTB

PORTC

PORTD

PORTE

RA0
RA1
RA2
RA3
RA4/T0CKI

RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1

RC3/SCK/SCL
RC4/SDI/SDA

RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

RE0/RD

Timer0 Timer1 Timer2

USART

Synchronous

Serial Port

CCP2CCP1

Note 1: Higher order bits are from the STATUS register.

2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C63/R63.
3: Brown-out Reset is not available on the PIC16C65.

RE1/WR

RE2/CS

(Note 2)

DS30234D-page 12  1997 Microchip Technology Inc.

FIGURE 3-4: PIC16C66/67 BLOCK DIAGRAM

PIC16C6X

Program

Bus

OSC1/CLKIN
OSC2/CLKOUT

EPROM

Program

Memory
8K x 14

14

Instruction reg

Instruction
Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Power-up

Start-up Timer

Power-on

Watchdog

Brown-out

MCLR

(13-bit)

Timer

Oscillator

Reset

Timer

Reset

VDD, VSS

RAM Addr

7

3

8

Data Bus

RAM

File

Registers

368 x 8

(1)

9

Addr MUX

8

FSR reg

STATUS reg

MUX

ALU

W reg

Parallel Slave

Port

8

Indirect

Addr

PORTA

PORTB

PORTC

PORTD

PORTE

RA0
RA1
RA2
RA3
RA4/T0CKI

RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1

RC3/SCK/SCL
RC4/SDI/SDA

RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

RE0/RD

Timer0 Timer1 Timer2

USART

Synchronous

Serial Port

Note 1: Higher order bits are from the STATUS register.

2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66.

RE1/WR

RE2/CS

(Note 2)

CCP2CCP1

 1997 Microchip Technology Inc. DS30234D-page 13

PIC16C6X

TABLE 3-1: PIC16C61 PINOUT DESCRIPTION

Pin Name

OSC1/CLKIN 16 16 I
OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal

MCLR

/VPP

RA0 17 17 I/O TTL
RA1 18 18 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST RA4 can also be the clock input to the Timer0 timer/counter.

RB0/INT 6 6 I/O TTL/ST
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST
RB7 13 13 I/O TTL/ST
VSS 5 5 P — Ground reference for logic and I/O pins.
VDD 14 14 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

2: This buffer is a Schmitt Trigger input when configured as the external interrupt.
3: This buffer is a Schmitt Trigger input when used in serial programming mode.

DIP

Pin#

— = Not used TTL = TTL input ST = Schmitt Trigger input

SOIC

4 4 I/P ST Master clear reset input or programming voltage input. This pin is an

Pin#

Pin Type

Buffer

Type

ST/CMOS

Description

(1)

Oscillator crystal input/external clock source input.

oscillator mode. In RC mode, the pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.

active low reset to the device.
PORTA is a bi-directional I/O port.

Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro­grammed for internal weak pull-up on all inputs.

(2)

(3)
(3)

RB0 can also be the external interrupt pin.

Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.

DS30234D-page 14  1997 Microchip Technology Inc.

TABLE 3-2: PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION

PIC16C6X

Pin Name Pin# Pin Type

OSC1/CLKIN 9 I

Buffer

Type

ST/CMOS

Description

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crys-

tal oscillator mode. In RC mode, the pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.

M

CLR/VPP

1 I/P ST Master clear reset input or programming voltage input. This pin is

an active low reset to the device.

PORTA is a bi-directional I/O port.
RA0 2 I/O TTL
RA1 3 I/O TTL
RA2 4 I/O TTL
RA3 5 I/O TTL
RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 timer/counter.

Output is open drain type.

RA5/SS 7 I/O TTL RA5 can also be the slave select for the synchronous serial

port.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs.
RB0/INT 21 I/O TTL/ST

(4)

RB0 can also be the external interrupt pin.
RB1 22 I/O TTL
RB2 23 I/O TTL
RB3 24 I/O TTL
RB4 25 I/O TTL Interrupt on change pin.
RB5 26 I/O TTL Interrupt on change pin.
RB6 27 I/O TTL/ST
RB7 28 I/O TTL/ST

(5)
(5)

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

.

(1)

or Timer1

(1)

or Capture2

RC0/T1OSO

RC1/T1OSI

(1)

(1)

/T1CKI

/CCP2

11 I/O ST RC0 can also be the Timer1 oscillator output

clock input.

(2)

12 I/O ST RC1 can also be the Timer1 oscillator input

input/Compare2 output/PWM2 output

(2)

RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output.
RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous ser ial clock input/output

for both SPI and I

2

C modes.

RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).
RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).

RC6/TX/CK

RC7/RX/DT

(2)

(2)

17 I/O ST RC6 can also be the USART Asynchronous Transmit

Synchronous Clock

18 I/O ST RC7 can also be the USART Asynchronous Receive

Synchronous Data

(2)

.

(2)

.

(2)

or

(2)

or

VSS 8,19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C62.

2: The USART and CCP2 are not available on the PIC16C62/62A/R62.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: This buffer is a Schmitt Trigger input when configured as the external interrupt.
5: This buffer is a Schmitt Trigger input when used in serial programming mode.

 1997 Microchip Technology Inc. DS30234D-page 15

PIC16C6X

TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION

DIP

Pin Name

Pin#

PLCC

Pin#

OSC1/CLKIN 13 14 30 I

TQFP

MQFP

Pin#

Pin

Type

Buffer

Type

ST/CMOS

Description

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the pin outputs CLK­OUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.

MCLR

/VPP

1 2 18 I/P ST Master clear reset input or programming voltage input. This

pin is an active low reset to the device.

PORTA is a bi-directional I/O port.
RA0 2 3 19 I/O TTL
RA1 3 4 20 I/O TTL
RA2 4 5 21 I/O TTL
RA3 5 6 22 I/O TTL
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0

timer/counter. Output is open drain type.

RA5/SS 7 8 24 I/O TTL RA5 can also be the slave select for the synchronous

serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST

(4)

RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST
RB7 40 44 17 I/O TTL/ST

(5)
(5)

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO

(1)

/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output

(1)

Timer1 clock input.
RC1/T1OSI

(1)

/CCP2

(2)

16 18 35 I/O ST RC1 can also be the Timer1 oscillator input

Capture2 input/Compare2 output/PWM2 output

(1)

or

(2)

.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output.
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/out-

put for both SPI and I

2

C modes.

RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK

RC7/RX/DT

(2)

(2)

25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit

or Synchronous Clock

26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive

or Synchronous Data

(2)

.

(2)

.

(2)

(2)

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C64.

2: CCP2 and the USART are not available on the PIC16C64/64A/R64.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: This buffer is a Schmitt Trigger input when configured as the external interrupt.
5: This buffer is a Schmitt Trigger input when used in serial programming mode.
6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slav e

Port mode (for interfacing to a microprocessor bus).

or

DS30234D-page 16  1997 Microchip Technology Inc.

PIC16C6X

TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d)

TQFP

MQFP

Pin#

Pin

Type

Buffer

Type

Description

Pin Name

DIP

Pin#

PLCC

Pin#

PORTD can be a bi-directional I/O port or parallel slave port

for interfacing to a microprocessor bus.

RD0/PSP0 19 21 38 I/O ST/TTL
RD1/PSP1 20 22 39 I/O ST/TTL
RD2/PSP2 21 23 40 I/O ST/TTL
RD3/PSP3 22 24 41 I/O ST/TTL
RD4/PSP4 27 30 2 I/O ST/TTL
RD5/PSP5 28 31 3 I/O ST/TTL
RD6/PSP6 29 32 4 I/O ST/TTL
RD7/PSP7 30 33 5 I/O ST/TTL

(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)

PORTE is a bi-directional I/O port.

RE0/RD 8 9 25 I/O ST/TTL
RE1/WR 9 10 26 I/O ST/TTL
RE2/CS 10 11 27 I/O ST/TTL

(6)
(6)
(6)

RE0 can also be read control for the parallel slav e port.
RE1 can also be write control for the parallel slave port.

RE2 can also be select control for the parallel slav e port.
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,

28,40

12,13,

33,34

— — These pins are not internally connected. These pins should

be left unconnected.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C64.

2: CCP2 and the USART are not available on the PIC16C64/64A/R64.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: This buffer is a Schmitt Trigger input when configured as the external interrupt.
5: This buffer is a Schmitt Trigger input when used in serial programming mode.
6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slav e

Port mode (for interfacing to a microprocessor bus).

 1997 Microchip Technology Inc. DS30234D-page 17

PIC16C6X

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the pro­gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instr uc­tion is decoded and executed during the following Q1
through Q4. The clock and instruction execution flow is
shown in Figure 3-5.

FIGURE 3-5: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1
Q2
Q3

Q4

(Program counter)

OSC2/CLKOUT

PC

(RC mode)

Q1

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1)

Q1

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cycle , the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Q1

Execute INST (PC+1)

Internal
Phase
Clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS30234D-page 18  1997 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16C6X

4.0 MEMORY ORGANIZATION

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

4.1 Program Memory Organization

The PIC16C6X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:

Device

PIC16C61 1K x 14 0000h-03FFh
PIC16C62 2K x 14 0000h-07FFh
PIC16C62A 2K x 14 0000h-07FFh
PIC16CR62 2K x 14 0000h-07FFh
PIC16C63 4K x 14 0000h-0FFFh
PIC16CR63 4K x 14 0000h-0FFFh
PIC16C64 2K x 14 0000h-07FFh
PIC16C64A 2K x 14 0000h-07FFh
PIC16CR64 2K x 14 0000h-07FFh
PIC16C65 4K x 14 0000h-0FFFh
PIC16C65A 4K x 14 0000h-0FFFh
PIC16CR65 4K x 14 0000h-0FFFh
PIC16C66 8K x 14 0000h-1FFFh
PIC16C67 8K x 14 0000h-1FFFh

For those devices with less than 8K program memory,
accessing a location above the physically implemented
address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is
at 0004h.

FIGURE 4-1: PIC16C61 PROGRAM

CALL, RETURN
RETFIE, RETLW

Space

User Memory

Program

Memory

Address Range

MEMORY MAP AND STACK

PC<12:0>

Stack Level 1

Stack Level 8

Reset Vector

Peripheral Interrupt Vector

On-chip Program

Memory

13

•

•

•

0000h

0004h

0005h

03FFh
0400h

FIGURE 4-2: PIC16C62/62A/R62/64/64A/

R64 PROGRAM MEMORY
MAP AND STACK

CALL, RETURN
RETFIE, RETLW

Peripheral Interrupt Vector

Space

User Memory

PC<12:0>

Stack Level 1

Stack Level 8

Reset Vector

On-chip Program

Memory

13

•

•

•

0000h

0004h
0005h

07FFh
0800h

1FFFh

FIGURE 4-3: PIC16C63/R63/65/65A/R65

PROGRAM MEMORY MAP
AND STACK

CALL, RETURN
RETFIE, RETLW

Peripheral Interrupt Vector

Space

User Memory

PC<12:0>

Stack Level 1

•

•

•

Stack Level 8

Reset Vector

On-chip Program
Memory (Page 0)

On-chip Program
Memory (Page 1)

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

1FFFh

1FFFh

 1997 Microchip Technology Inc. DS30234D-page 19

PIC16C6X

FIGURE 4-4: PIC16C66/67 PROGRAM

MEMORY MAP AND STACK

CALL, RETURN
RETFIE, RETLW

Peripheral Interrupt Vector

Space

User Memory

PC<12:0>

Stack Level 1

•

•

•

Stack Level 8
Reset Vector

On-chip Program
Memory (Page 0)

On-chip Program
Memory (Page 1)

On-chip Program
Memory (Page 2)

On-chip Program
Memory (Page 3)

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

17FFh
1800h

1FFFh

4.2 Data Memory Organization

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.

RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.

For the PIC16C61, general purpose register locations
8Ch-AFh of Bank 1 are not physically implemented.
These locations are mapped into 0Ch-2Fh of Bank 0.

FIGURE 4-5: PIC16C61 REGISTER FILE

MAP

File Address

(1)

00h
01h

02h
03h
04h
05h
06h
07h
08h
09h
0Ah

0Bh
0Ch

2Fh
30h

7Fh

Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.

INDF

TMR0 OPTION

PCL

STATUS

FSR
PORTA
PORTB

PCLATH

INTCON

General
Purpose
Register

Bank 0

2: These locations are unimplemented in

Bank 1. Any access to these locations will
access the corresponding Bank 0 register.

INDF

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

Mapped

in Bank 0

Bank 1

File Address

(1)

(2)

80h
81h
82h
83h
84h
85h
86h
87h

88h
89h
8Ah
8Bh

8Ch

AFh
B0h

FFh

4.2.1 GENERAL PURPOSE REGISTERS
These registers are accessed either directly or indi-

rectly through the File Select Register (FSR)
(Section 4.5).

DS30234D-page 20  1997 Microchip Technology Inc.

PIC16C6X

FIGURE 4-6: PIC16C62/62A/R62/64/64A/

R64 REGISTER FILE MAP

(1)

(2)

(2)

File Address

80h
81h
82h
83h
84h
85h
86h
87h

88h
89h

8Ah
8Bh

8Ch
8Dh
8Eh
8Fh

90h
91h

92h
93h

94h
95h
96h
97h

98h

File Address

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h

0Ah
0Bh
0Ch

0Dh
0Eh

0Fh
10h

11h

12h
13h

14h
15h
16h
17h

18h

(1)

INDF

INDF

TMR0 OPTION

PCL

STATUS

FSR

PORTA

PORTB

PCL

STATUS

FSR
TRISA
TRISB

PORTC TRISC

(2)

PORTD
PORTE

PCLATH
INTCON

(2)

TRISD

TRISE
PCLATH
INTCON

PIR1 PIE1

TMR1L PCON
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

PR2

SSPADD

SSPSTAT

CCPR1L

CCPR1H

CCP1CON

FIGURE 4-7: PIC16C63/R63/65/65A/R65

REGISTER FILE MAP

(1)

(2)
(2)

File Address

80h
81h
82h
83h
84h
85h
86h
87h

88h
89h

8Ah
8Bh

8Ch

8Dh

8Eh

8Fh
90h

91h

92h
93h

94h
95h
96h
97h

98h
99h

9Ah

File Address

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h

0Ah
0Bh

0Ch
0Dh

0Eh
0Fh

10h
11h

12h
13h

14h
15h
16h
17h

18h
19h

1Ah

(1)

INDF

INDF

TMR0 OPTION

PCL

STATUS

FSR
PORTA
PORTB

PCL

STATUS

FSR
TRISA
TRISB

PORTC TRISC

(2)

PORTD
PORTE

PCLATH
INTCON

(2)

TRISD

TRISE
PCLATH
INTCON

PIR1 PIE1

PIR2 PIE2
TMR1L PCON
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

PR2

SSPADD

SSPSTAT

CCPR1L

CCPR1H
CCP1CON

RCSTA
TXREG

TXSTA
SPBRG

RCREG

9Bh
9Ch
9Dh

9Eh

9Fh
A0h

FFh

1Fh
20h

9Fh
A0h

General

Purpose

General
Purpose
Register

7Fh

Bank 0

Register

BFh

C0h

FFh

Bank 1

Unimplemented data memory location; read as '0'.

Note 1: Not a physical register.

2: PORTD and PORTE are not available on

the PIC16C62/62A/R62.

1Bh
1Ch
1Dh

CCPR2L
CCPR2H

CCP2CON

1Eh

1Fh

20h

7Fh

General
Purpose
Register

Bank 0

General
Purpose
Register

Bank 1

Unimplemented data memory location; read as '0'.

Note 1: Not a physical register

2: PORTD and PORTE are not available on

the PIC16C63/R63.

 1997 Microchip Technology Inc. DS30234D-page 21

PIC16C6X

FIGURE 4-8: PIC16C66/67 DATA MEMORY MAP

PCL

FSR

PIE1
PIE2

PR2

(*)

80h
81h
82h
83h
84h
85h
86h
87h

(1)

88h

(1)

89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

Indirect addr.

TMR0

PCL

STATUS

FSR
PORTA
PORTB

PORTC
PORTD

PORTE
PCLATH
INTCON

PIR1
PIR2

TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG
RCREG

CCPR2L

CCPR2H

CCP2CON

(*)

00h
01h

Indirect addr.

OPTION

02h
03h

STATUS

04h
05h
06h
07h

(1)

08h

(1)

09h
0Ah
0Bh

TRISA
TRISB
TRISC
TRISD

TRISE

PCLATH
INTCON

0Ch
0Dh
0Eh

PCON

0Fh
10h
11h
12h
13h
14h

SSPADD

SSPSTAT

15h
16h
17h
18h
19h

TXSTA

SPBRG

1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

Indirect addr.

TMR0

PCL

STATUS

FSR

PORTB

PCLATH
INTCON

General
Purpose
Register

16 Bytes

File

Address

PCL

FSR

(*)

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh

1A0h

(*)

100h
101h

Indirect addr.

OPTION
102h
103h

STATUS
104h

105h
106h

TRISB
107h
108h
109h
10Ah
10Bh

PCLATH
INTCON

10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h

General
Purpose
Register

16 Bytes

11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h

General
Purpose
Register

96 Bytes

7Fh

Bank 0

Unimplemented data memory locations, read as '0'.

* Not a physical register.
These registers are not implemented on the PIC16C66.

General
Purpose
Register

General
Purpose
Register

General
Purpose
Register

80 Bytes 80 Bytes 80 Bytes

accesses

70h-7Fh

in Bank 0

Bank 1

EFh
F0h

FFh

accesses

70h-7Fh

in Bank 0

Bank 2

16Fh
170h

17Fh

accesses

70h-7Fh

in Bank 0

Bank 3

1EFh
1F0h

1FFh

Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This ma y require

relocation of data memory usage in the user application code if upgrading to the PIC16C66/67.

DS30234D-page 22  1997 Microchip Technology Inc.

PIC16C6X

4.2.2 SPECIAL FUNCTION REGISTERS:

The special function registers can be classified into two
sets (core and peripheral). The registers associated

The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.

with the “core” functions are described in this section
and those related to the operation of the peripheral fea­tures are described in the section of that peripheral fea­ture.

TABLE 4-1: SPECIAL FUNCTION REGISTERS FOR THE PIC16C61

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h — Unimplemented
08h
09h
0Ah
0Bh

Bank 1

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111

87h – Unimplemented
88h
89h
8Ah
8Bh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(4)

IRP

— — — PORTA Data Latch when written: PORTA pins when read ---x xxxx ---u uuuu

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

— —

—

Unimplemented

—

Unimplemented

(1,2)

PCLATH — — —

(1)

INTCON GIE — T0IE INTE RBIE T0IF INTF RBIF 0-00 000x 0-00 000u

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(4)

IRP

— — — PORTA Data Direction Register ---1 1111 ---1 1111

RP1

(4)

Write Buffer for the upper 5 bits of the Program Counter

RP0 TO PD ZDCC0001 1xxx 000q quuu

— —
— —

---0 0000 ---0 0000

— —

– Unimplemented

Unimplemented

–

(1,2)

PCLATH — — —

(1)

INTCON GIE — T0IE INTE RBIE T0IF INTF RBIF 0-00 000x 0-00 000u

Write Buffer for the upper 5 bits of the Program Counter

— —
— —

---0 0000 ---0 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.

Shaded locations are unimplemented and read as ‘0’

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-

tents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.

Value on

all other
resets

(3)

 1997 Microchip Technology Inc. DS30234D-page 23

PIC16C6X

TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —

0Ah
0Bh

0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h-1Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented

(5)

IRP

— — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu

(6) (6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000

RP1

(5)

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

— —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C62, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

Value on

all other

resets

(3)

DS30234D-page 24  1997 Microchip Technology Inc.

PIC16C6X

TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —

8Ah
8Bh

8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h-9Fh — Unimplemented — —

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(5)

IRP

— — PORTA Data Direction Register --11 1111 --11 1111

(6) (6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000

— — — — — — POR

Synchronous Serial Port (I

RP1

(5)

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

BOR

2

C mode) Address Register

Value on:

POR,

BOR

---0 0000 ---0 0000

(4)

---- --qq ---- --uu

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3: Other (non power-up) resets include external reset through MCLR

and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C62, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 25

PIC16C6X

TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —

0Ah
0Bh
0Ch PIR1
0Dh PIR2

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA
19h TXREG
1Ah RCREG
1Bh CCPR2L
1Ch
1Dh
1Eh-1Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

CCPR2H
CCP2CON

— Unimplemented

(4)

IRP

— — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu

(5) (5)

— — — —– — — — CCP2IF ---- ---0 ---- ---0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

SPEN RX9 SREN CREN
USART Transmit Data Register 0000 0000 0000 0000
USART Receive Data Register 0000 0000 0000 0000
Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu

— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

RCIF TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

— FERR OERR RX9D 0000 -00x 0000 -00x

---0 0000 ---0 0000

— —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.
5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 26

PIC16C6X

TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —

8Ah
8Bh
8Ch PIE1
8Dh PIE2

8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —

98h
99h

9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh — Unimplemented — —

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(2)

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

(2)

SPBRG Baud Rate Generator Register 0000 0000 0000 0000

(4)

IRP

— — PORTA Data Direction Register --11 1111 --11 1111

(5) (5)

— — — — — — — CCP2IE ---- ---0 ---- ---0
— — — — — — POR BOR ---- --qq ---- --uu

Synchronous Serial Port (I

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

RCIE TXIE

2

C mode) Address Register

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Value on:

POR,

BOR

---0 0000 ---0 0000

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.
5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 27

PIC16C6X

TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h

09h
0Ah
0Bh

0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

PORTD
PORTE

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented

(5)

IRP

— — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu

PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

PSPIF

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

(5)

RP1

(6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

— —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C64, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

Value on

all other
resets

(3)

DS30234D-page 28  1997 Microchip Technology Inc.

PIC16C6X

TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h TRISD
89h TRISE
8Ah
8Bh
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —

90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h-9Fh — Unimplemented — —

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(5)

IRP

— — PORTA Data Direction Register --11 1111 --11 1111

PORTD Data Direction Register 1111 1111 1111 1111

IBF OBF IBOV PSPMODE

PSPIE

— — — — — — POR

Synchronous Serial Port (I

(5)

RP1

(6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000

RP0 TO PD ZDCC0001 1xxx 000q quuu

— PORTE Data Direction Bits 0000 -111 0000 -111

Write Buffer for the upper 5 bits of the Program Counter

BOR

2

C mode) Address Register

Value on:

POR,

BOR

---0 0000 ---0 0000

(4)

---- --qq ---- --uu

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C64, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 29

PIC16C6X

TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h

09h
0Ah
0Bh

0Ch PIR1
0Dh PIR2

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA
19h TXREG
1Ah RCREG
1Bh CCPR2L
1Ch
1Dh
1Eh-1Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

PORTD
PORTE

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

CCPR2H
CCP2CON

— Unimplemented

(5)

IRP

— — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu

PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

PSPIF

— — — —– — — — CCP2IF ---- ---0 ---- ---0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

SPEN RX9 SREN CREN
USART Transmit Data Register 0000 0000 0000 0000
USART Receive Data Register 0000 0000 0000 0000
Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu

— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

RP1

(6)

(5)

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

RCIF TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

— FERR OERR RX9D 0000 -00x 0000 -00x

---0 0000 ---0 0000

— —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

Value on

all other
resets

(3)

DS30234D-page 30  1997 Microchip Technology Inc.

PIC16C6X

TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h TRISD
89h TRISE
8Ah
8Bh
8Ch PIE1
8Dh PIE2

8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —

98h TXSTA
99h SPBRG

9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh — Unimplemented — —

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(5)

IRP

— — PORTA Data Direction Register --11 1111 --11 1111

PORTD Data Direction Register 1111 1111 1111 1111

IBF OBF IBOV PSPMODE

PSPIE

— — — — — — — CCP2IE ---- ---0 ---- ---0
— — — — — — POR

Synchronous Serial Port (I

CSRC TX9 TXEN SYNC

Baud Rate Generator Register 0000 0000 0000 0000

RP1

(6)

(5)

RP0 TO PD ZDCC0001 1xxx 000q quuu

— PORTE Data Direction Bits 0000 -111 0000 -111

Write Buffer for the upper 5 bits of the Program Counter

RCIE TXIE

2

C mode) Address Register

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

BOR

— BRGH TRMT TX9D 0000 -010 0000 -010

Value on:

POR,

BOR

---0 0000 ---0 0000

(4)

---- --qq ---- --uu

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 31

PIC16C6X

TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Bank 0

(1)

00h
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h
03h
04h

05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h
09h
0Ah
0Bh
0Ch PIR1
0Dh PIR2

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA
19h TXREG
1Ah RCREG
1Bh CCPR2L
1Ch
1Dh
1Eh-1Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

— — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu

(5)

PORTD

(5)

PORTE

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

CCPR2H
CCP2CON

PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

Write Buffer for the upper 5 bits of the Program Counter

(6)

PSPIF

— — — —– — — — CCP2IF ---- ---0 ---- ---0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

SPEN RX9 SREN CREN
USART Transmit Data Register 0000 0000 0000 0000
USART Receive Data Register 0000 0000 0000 0000
Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu
Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu

— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

— Unimplemented

(4)

RCIF TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

— FERR OERR RX9D 0000 -00x 0000 -00x

---0 0000 ---0 0000

— —

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

Value on

all other
resets

(3)

DS30234D-page 32  1997 Microchip Technology Inc.

PIC16C6X

TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

(1)

80h
81h OPTION RBPU

82h
83h
84h

85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h
89h
8Ah
8Bh
8Ch PIE1
8Dh PIE2

8Eh PCON
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —

98h TXSTA
99h SPBRG

9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh — Unimplemented — —

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(5)

TRISD

(5)

TRISE

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

IRP RP1

— — PORTA Data Direction Register --11 1111 --11 1111

PORTD Data Direction Register 1111 1111 1111 1111

IBF OBF IBOV PSPMODE

(6)

PSPIE

— — — — — — — CCP2IE ---- ---0 ---- ---0
— — — — — — POR

Synchronous Serial Port (I

CSRC TX9 TXEN SYNC

Baud Rate Generator Register 0000 0000 0000 0000

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

— PORTE Data Direction Bits 0000 -111 0000 -111

Write Buffer for the upper 5 bits of the Program Counter

RCIE TXIE

2

C mode) Address Register

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

BOR

— BRGH TRMT TX9D 0000 -010 0000 -010

Value on:

POR,

BOR

---0 0000 ---0 0000

---- --qq ---- --uu

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

Value on
all other

(3)

resets

 1997 Microchip Technology Inc. DS30234D-page 33

PIC16C6X

TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

(1)

100h
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

102h
103h
104h

105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —

10Ah
10Bh

10Ch­10Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented — —

IRP RP1

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

Value on:

POR,

BOR

---0 0000 ---0 0000

Bank 3

(1)

180h
181h OPTION RBPU

182h
183h
184h

185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —

18Ah
18Bh

18Ch­19Fh

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

(1)

STATUS

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

(1,2)

PCLATH — — —

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

— Unimplemented — —

IRP RP1

RP0 TO PD ZDCC0001 1xxx 000q quuu

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

Value on

all other
resets

(3)

DS30234D-page 34  1997 Microchip Technology Inc.

PIC16C6X

4.2.2.1 STATUS REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The ST ATUS register, sho wn in Figure 4-9, contains the
arithmetic status of the ALU, the RESET status and the
bank select bits for data memory.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T

O and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STA TUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these
bits clear to ensure upward compatibility
with future products.

Note 2: The C and DC bits operate as a borro

and digit borrow bit, respectively, in sub­traction. See the SUBLW and SUBWF
instructions for examples.

intended.
For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).

FIGURE 4-9: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

bit7 bit0

bit 7: IRP: RegIster Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (f or ADDWF, ADDLW,SUBLW, and SUBWF instructions) (For borrow the polarity is rev ersed).

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result
Note: a subtraction is executed by adding the two’s complement of the second operand.

w bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions)( For borrow the polarity is reversed).

For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

W = Writable bit

- n = Value at POR reset
x = unknown

w

 1997 Microchip Technology Inc. DS30234D-page 35

PIC16C6X

4.2.2.2 OPTION REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The OPTION register is a readable and writable regis­ter which contains various control bits to configure the
TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.

FIGURE 4-10: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Note: To achieve a 1:1 prescaler assignment for

TMR0 register, assign the prescaler to the
Watchdog Timer .

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS30234D-page 36  1997 Microchip Technology Inc.

PIC16C6X

4.2.2.3 INTCON REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The INTCON Register is a readable and writable regis-

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).

ter which contains the various enable and flag bits for
the TMR0 register overflow , RB port change and exter­nal RB0/INT pin interrupts.

FIGURE 4-11: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

bit7 bit0

bit 7: GIE:

bit 6: PEIE:

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

bit 4: INTE: RB0/INT External Interrupt Enable bit

bit 3: RBIE: RB Port Change Interrupt Enable bit

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

bit 1: INTF: RB0/INT External Interrupt Flag bit

bit 0: RBIF: RB Port Change Interrupt Flag bit

(1)

Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

(2)

Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

1 = TMR0 register overflowed (must be cleared in software)
0 = TMR0 register did not overflow

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear the interrupt)
0 = None of the RB7:RB4 pins have changed state

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset
x = unknown

read as ‘0’

Note 1: For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally

be re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 13.5 for a detailed
description.

2: The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'.

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

 1997 Microchip Technology Inc. DS30234D-page 37

PIC16C6X

4.2.2.4 PIE1 REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

This register contains the individual enable bits for the
peripheral interrupts.

FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch)

RW-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7-6: Reserved: Always maintain these bits clear.
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS30234D-page 38  1997 Microchip Technology Inc.

FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7-6: Reserved: Always maintain these bits clear.
bit 5: RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4: TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

PIC16C6X

read as ‘0’

FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch)

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE

bit7 bit0

bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

bit 6: Reserved: Always maintain this bit clear.
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

bit 2: CCP1IE: CCP1 Interrupt Enable bit

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

— — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

 1997 Microchip Technology Inc. DS30234D-page 39

PIC16C6X

FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt
bit 6: Reserved: Always maintain this bit clear.
bit 5: RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS30234D-page 40  1997 Microchip Technology Inc.

PIC16C6X

4.2.2.5 PIR1 REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

This register contains the individual flag bits for the
peripheral interrupts.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

FIGURE 4-16: PIR1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 0Ch)

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7-6: Reserved: Always maintain these bits clear.
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive

bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)
0 = No TMR1 register overflow occurred

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

 1997 Microchip Technology Inc. DS30234D-page 41

PIC16C6X

FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7-6: Reserved: Always maintain these bits clear.
bit 5: RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

DS30234D-page 42  1997 Microchip Technology Inc.

FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch)

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF — — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place
bit 6: Reserved: Always maintain this bit clear.
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register occurred

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

PIC16C6X

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

 1997 Microchip Technology Inc. DS30234D-page 43

PIC16C6X

FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place
bit 6: Reserved: Always maintain this bit clear.
bit 5: RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

DS30234D-page 44  1997 Microchip Technology Inc.

4.2.2.6 PIE2 REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

This register contains the CCP2 interrupt enable bit.

FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IE R = Readable bit

bit7 bit0

bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

PIC16C6X

read as ‘0’

 1997 Microchip Technology Inc. DS30234D-page 45

PIC16C6X

4.2.2.7 PIR2 REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

This register contains the CCP2 interrupt flag bit.

.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF R = Readable bit

bit7 bit0

bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.

DS30234D-page 46  1997 Microchip Technology Inc.

PIC16C6X

4.2.2.8 PCON REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The Power Control register (PCON) contains a flag bit
to allow differentiation between a P o wer-on Reset to an
external MCLR

reset or WDT reset. Those devices with
brown-out detection circuitry contain an additional bit to
differentiate a Brown-out Reset condition from a

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked
on subsequent resets to see if BOR
clear, indicating a brown-out has occurred.
The BOR

status bit is a “don't care” and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).

Power-on Reset condition.

FIGURE 4-22: PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR — R = Readable bit

bit7 bit0

bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: Reserved

This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general
purpose read/write bit is not recommended, since this may affect upward compatibility with future products.

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset
q = value depends on conditions

is

read as ‘0’

FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67

(ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR BOR R = Readable bit

bit7 bit0

bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: B

OR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset
q = value depends on conditions

 1997 Microchip Technology Inc. DS30234D-page 47

PIC16C6X

4.3 PCL and PCLATH

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLA TH register . On an y reset, the upper bits of the PC
will be cleared. Figure 4-24 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).

FIGURE 4-24: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PC

PCLATH<4:0>

5

PCLATH

PCH PCL

12 11 10 0

PC

2

87

PCLATH<4:3>

PCLATH

8

11

uction with

Instr
PCL as
destination

ALU

GOTO, CALL

Opcode <10:0>

Note 1: There are no status bits to indicate stack

overflows or stack underflow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt
address

4.4 Program Memory Paging

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X devices are capable of addressing a contin­uous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper two
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe­cuted, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).

Note: PIC16C6X devices with 4K or less of pro-

gram memory ignore paging bit
PCLATH<4>. The use of PCLATH<4> as a
general purpose read/write bit is not rec­ommended since this may affect upward
compatibility with future products.

4.3.1 COMPUTED GOTO
A computed GOT O is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the tab le location crosses a PCL
memory boundary (each 256 word block). Refer to the
application note

“Implementing a Table Read”

(AN556).

4.3.2 STACK
The PIC16CXX family has an 8 deep x 13-bit wide

hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLA TH is not aff ected by a PUSH or a POP oper ation.

The stack operates as a circular buff er . This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).

DS30234D-page 48  1997 Microchip Technology Inc.

PIC16C6X

Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
service routine (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
BCF PCLATH,4 ;Only on >4K devices
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
:
ORG 0x900
SUB1_P1: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
;in page 0 (000h-7FFh)

4.5 Indirect Addressing, INDF and FSR
Registers

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The INDF register is not a physical register. Address­ing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg­ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg­ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will produce 00h. Wr iting to the INDF regis­ter indirectly results in a no-operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS<7>), as shown in Figure 4-25.

A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue

FIGURE 4-25: DIRECT/INDIRECT ADDRESSING

Direct Addressing

RP1:RP0 6 0

bank select bank select

location select

from opcode

00 01 10 11

00h

80h

100h

180h

Data
Memory

7Fh

Bank 0

For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.

FFh

Bank 1

17Fh

Bank 2

1FFh

IRP 7 FSR 0

Bank 3

Indirect Addressing

location select

 1997 Microchip Technology Inc. DS30234D-page 49

PIC16C6X

NOTES:

DS30234D-page 50  1997 Microchip Technology Inc.

PIC16C6X

5.0 I/O PORTS

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Some pins for these I/O ports are multiplexed with an
alternate function(s) for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

All devices have a 6-bit wide PORTA, except for the
PIC16C61 which has a 5-bit wide PORTA.

Pin RA4/T0CKI is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input lev­els and full CMOS output drivers. All pins have data
direction bits (TRIS registers) which can configure
these pins as output or input.

Setting a bit in the TRISA register puts the correspond­ing output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.

Reading PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There­fore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.

Pin RA4 is multiplexed with Timer0 module clock input
to become the RA4/T0CKI pin.

FIGURE 5-1: BLOCK DIAGRAM OF THE

RA3:RA0 PINS AND THE RA5
PIN

Data
bus

WR
Port

Data Latch

WR
TRIS

TRIS Latch

RD PORT

Note 1: I/O pins have protection diodes to VDD and

VSS.

2: The PIC16C61 does not have an RA5 pin.

CK

CK

QD

Q

QD

Q

RD TRIS

VDD

P

N

VSS

TTL
input
buffer

QD

EN

I/O pin

(1)

EXAMPLE 5-1: INITIALIZING PORTA

BCF STATUS, RP0 ;
BCF STATUS, RP1 ; PIC16C66/67 only
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.

FIGURE 5-2: BLOCK DIAGRAM OF THE

RA4/T0CKI PIN

Data
bus

WR
PORT

WR
TRIS

RD PORT

TMR0 clock input

Note 1: I/O pin has protection diodes to V

QD

Q

CK

Data Latch

QD

Q

CK

TRIS Latch

RD TRIS

N

V

SS

Schmitt
T rigger
input
buffer

QD

EN

EN

I/O pin

SS only.

(1)

 1997 Microchip Technology Inc. DS30234D-page 51

PIC16C6X

TABLE 5-1: PORTA FUNCTIONS

Name Bit# Buffer Type Function

RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0.

Output is open drain type.

RA5/SS

(1)

Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C61 does not have PORTA<5> or TRISA<5>, read as ‘0’.

TABLE 5-2: REGISTERS/BITS ASSOCIATED WITH PORTA

bit5 TTL Input/output or slave select input for synchronous serial port.

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h PORTA — — RA5
85h TRISA — —

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5> and TRISA<5> are not implemented on the PIC16C61, read as '0'.

(1)

RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

PORTA Data Direction Register

(1)

POR,

BOR

--11 1111 --11 1111

Value on all

other resets

DS30234D-page 52  1997 Microchip Technology Inc.

PIC16C6X

5.2 PORTB and TRISB Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PORTB is an 8-bit wide bi-directional port. The corre­sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance mode. Clearing a bit in the
TRISB register puts the contents of the output latch on
the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit R
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are also
disabled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).

BPU (OPTION<7>). The

This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter­rupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with soft­ware configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, Application Note,

Wake-up on Key Stroke” (AN552)

“Implementing

.

Note: For PIC16C61/62/64/65, if a change on the

I/O pin should occur when a read operation
is being executed (start of the Q2 cycle),
then interrupt flag bit RBIF may not get set.

The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.

FIGURE 5-3: BLOCK DIAGRAM OF THE

RB7:RB4 PINS FOR
PIC16C61/62/64/65

DD

TTL
Input
Buffer

V

P

weak
pull-up

I/O
pin

ST
Buffer

(1)

RBPU

Data bus

WR Port

WR TRIS

(2)

Data Latch

QD

CK

TRIS Latch

QD

CK

RD TRIS

Set RBIF

From other
RB7:RB4 pins

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPB

 1997 Microchip Technology Inc. DS30234D-page 53

RD Port

U bit (OPTION<7>).

Latch

QD

EN

QD

EN

RD Port

PIC16C6X

FIGURE 5-4: BLOCK DIAGRAM OF THE

RB7:RB4 PINS FOR
PIC16C62A/63/R63/64A/65A/
R65/66/67

DD

EN

EN

TTL
Input
Buffer

V

P

weak
pull-up

I/O
pin

ST
Buffer

Q1

RD Port

(2)

RBPU

Data bus

WR Port

WR TRIS

Set RBIF

From other
RB7:RB4 pins

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPB

Data Latch

QD

CK

TRIS Latch

QD

CK

RD TRIS

RD Port

U bit (OPTION<7>).

Latch

QD

QD

Q3

FIGURE 5-5: BLOCK DIAGRAM OF THE

RB3:RB0 PINS

DD

TTL
Input
Buffer

EN

V

weak

P

pull-up

RD Port

I/O
pin

(1)

(2)

RBPU

Data bus

WR Port

(1)

WR TRIS

RB0/INT

Note 1: I/O pins have diode protection to V

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPB

Data Latch

QD

CK

TRIS Latch

QD

CK

RD TRIS

RD Port

Schmitt T rigger
Buffer

U bit (OPTION<7>).

QD

DD and VSS.

TABLE 5-3: PORTB FUNCTIONS

Name Bit# Buffer Type Function

(1)

RB0/INT bit0

TTL/ST

Input/output pin or external interrupt input. Internal software programmable

weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.
RB6 bit6

TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmab le

weak pull-up. Serial programming clock.
RB7 bit7

TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmab le

weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR,

BOR

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuuu
86h, 186h TRISB

PORTB Data Direction Register

1111 1111 1111 1111

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

Value on all

other resets

DS30234D-page 54  1997 Microchip Technology Inc.

PIC16C6X

5.3 PORTC and TRISC Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PORTC is an 8-bit wide bi-directional port. Each pin is
individually configurable as an input or output through
the TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.

When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out­put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify­write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.

EXAMPLE 5-3: INITIALIZING PORTC

BCF STATUS, RP0 ;
BCF STATUS, RP1 ; PIC16C66/67 only
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs

FIGURE 5-6: PORTC BLOCK DIAGRAM

PORT/PERIPHERAL Select
Peripheral Data Out

Data bus

WR
PORT

WR
TRIS

Peripheral

(3)

OE

Peripheral input

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port

3: Peripheral OE (output enable) is only activated if

CK

Data Latch

CK

TRIS Latch

RD TRIS

RD
PORT

data and peripheral output.

peripheral select is active.

(2)

0

QD

1

Q

QD
Q

QD

EN

VDD

P

I/O
pin

N

VSS

Schmitt
T rigger

(1)

TABLE 5-5: PORTC FUNCTIONS FOR PIC16C62/64

Name Bit# Buffer Type Function

RC0/T1OSI/T1CKI bit0 ST Input/output port pin or Timer1 oscillator input or Timer1 clock input
RC1/T1OSO bit1 ST Input/output port pin or Timer1 oscillator output
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output
RC3/SCK/SCL bit3 ST

RC3 can also be the synchronous serial clock for both SPI and I

RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I
RC5/SDO

RC6
RC7

bit5 ST
bit6 ST Input/output port pin
bit7 ST Input/output port pin

Input/output port pin or synchronous serial port data output

Legend: ST = Schmitt Trigger input

2

2

C mode).

C modes.

 1997 Microchip Technology Inc. DS30234D-page 55

PIC16C6X

TABLE 5-6: PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input
RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM1 output
RC3/SCK/SCL bit3 ST

RC3 can also be the synchronous serial clock for both SPI and I

RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I
RC5/SDO

RC6
RC7

bit5 ST
bit6 ST Input/output port pin
bit7 ST Input/output port pin

Input/output port pin or synchronous serial port data output

Legend: ST = Schmitt Trigger input

TABLE 5-7: PORTC FUNCTIONS FOR PIC16C63/R63/65/65A/R65/66/67

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2

RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output
RC3/SCK/SCL bit3 ST
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I

RC5/SDO
RC6/TX/CK

RC7/RX/DT

bit5 ST
bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Syn-

bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Syn-

Legend: ST = Schmitt Trigger input

output/PWM2 output

RC3 can also be the synchronous serial clock for both SPI and I

Input/output port pin or synchronous serial port data output

chronous Clock

chronous Data

2

2

C mode).

2

2

C mode).

C modes.

C modes.

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.

POR,

BOR

Value on all

other resets

DS30234D-page 56  1997 Microchip Technology Inc.

PIC16C6X

5.4 PORTD and TRISD Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PORTD is an 8-bit port with Schmitt Trigger input buff­ers. Each pin is individually configurable as input or out­put.

PORTD can be configured as an 8-bit wide micropro­cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode , the input b uff ers
are TTL.

FIGURE 5-7: PORTD BLOCK DIAGRAM

(IN I/O PORT MODE)

Data
bus

WR
PORT

Data Latch

WR
TRIS

TRIS Latch

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

CK

CK

RD TRIS

QD

I/O pin

QD

Schmitt
T rigger
input
buffer

QD

EN

EN

(1)

TABLE 5-9: PORTD FUNCTIONS

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL
RD1/PSP1 bit1 ST/TTL
RD2/PSP2 bit2 ST/TTL
RD3/PSP3 bit3 ST/TTL
RD4/PSP4 bit4 ST/TTL
RD5/PSP5 bit5 ST/TTL
RD6/PSP6 bit6 ST/TTL
RD7/PSP7 bit7 ST/TTL

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port mode.

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTD.

PORTE Data Direction Bits

POR,

BOR

0000 -111 0000 -111

Value on all
other resets

 1997 Microchip Technology Inc. DS30234D-page 57

PIC16C6X

5.5 PORTE and TRISE Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PORTE has three pins, RE2/CS, RE1/WR, and
RE0/RD

which are individually configurable as inputs
or outputs. These pins have Schmitt Trigger input buff­ers.

I/O PORTE becomes control inputs for the micropro­cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which controls
the parallel slave port operation and also controls the
direction of the PORTE pins.

FIGURE 5-9: TRISE REGISTER (ADDRESS 89h)

FIGURE 5-8: PORTE BLOCK DIAGRAM

(IN I/O PORT MODE)

Data
bus

WR
PORT

WR
TRIS

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

QD

CK

Data Latch

QD

CK

TRIS Latch

RD TRIS

Schmitt
T rigger
input
buffer

QD

EN

EN

I/O pin

(1)

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit

bit7 bit0

bit 7 : IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received

bit 6: OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word
0 = The output buffer has been read

bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred

bit 4: PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode
0 = General purpose I/O mode

bit 3: Unimplemented: Read as '0'

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

PORTE Data Direction Bits

bit 2: Bit2: Direction Control bit for pin RE2/CS

1 = Input
0 = Output

bit 1: Bit1: Direction Control bit for pin RE1/WR

1 = Input
0 = Output

bit 0: Bit0: Direction Control bit for pin RE0/RD

1 = Input
0 = Output

DS30234D-page 58  1997 Microchip Technology Inc.

PIC16C6X

TABLE 5-11: PORTE FUNCTIONS

Name Bit# Buffer Type Function

RE0/RD

RE1/WR

RE2/CS

bit0 ST/TTL

bit1 ST/TTL

bit2 ST/TTL

Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port (PSP) mode.

TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

(1)

Input/output port pin or Read control input in parallel slave port mode.

RD
1 = Not a read operation
0 = Read operation. The system reads the PORTD register (if

chip selected)

(1)

Input/output port pin or Write control input in parallel slave port mode.

WR
1 = Not a write operation
0 = Write operation. The system writes to the POR TD register (if

chip selected)

(1)

Input/output port pin or Chip select control input in parallel slave port
mode.

CS
1 = Device is not selected
0 = Device is selected

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells not used by PORTE.

PORTE Data Direction Bits

POR,

BOR

0000 -111 0000 -111

Value on all

other resets

 1997 Microchip Technology Inc. DS30234D-page 59

PIC16C6X

5.6 I/O Programming Considerations

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

5.6.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, ex ecute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs . However , if
bit0 is switched into output mode later on, the content
of the data latch may now be unknown.

Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF , etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.

Example 5-4 shows the effect of two sequential
read-modify-write instructions on an I/O port.

EXAMPLE 5-4: READ-MODIFY-WRITE

INSTRUCTIONS ON AN
I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
; PORT latch PORT pins
; ---------- --------­ BCF PORTB, 7 ; 01pp pppp 11pp pppp
BCF PORTB, 6 ; 10pp pppp 11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp pppp 11pp pppp
BCF TRISB, 6 ; 10pp pppp 10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).

A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.

5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-10). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen­dent) before the next instruction which causes that file
to be read into the CPU is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.

FIGURE 5-10: SUCCESSIVE I/O OPERATION

Q3

PC + 3

NOP

NOP

Q4

Note:
This example shows a write to PORTB

followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies,
a write followed by a read ma y be prob­lematic.

NOP

Q3

Q4

Q1 Q2

Q4

Q1 Q2

PC

Instruction

fetched

RB7:RB0

Instruction

executed

DS30234D-page 60  1997 Microchip Technology Inc.

MOVWF PORTB

Q3

PC PC + 1 PC + 2

write to
PORTB

Q1 Q2

MOVF PORTB,W

MOVWF PORTB

write to
PORTB

Q3

Q4

Q1 Q2

TPD

MOVF PORTB,W

Port pin
sampled here

PIC16C6X

5.7 Parallel Slave Port

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PORTD operates as an 8-bit wide parallel slave por t
(microprocessor port) when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through
R

D control input (RE0/RD) and WR control input pin

(RE1/WR
It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).

There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data flow.

A write to the PSP occurs when both the CS
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full status flag bit IBF (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-12). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The input Buffer Overflow status flag bit
IBOV (TRISE<5>) is set if a second write to the P arallel
Slave P ort is attempted when the previous b yte has not
been read out of the buffer.

A read from the PSP occurs when both the CS
lines are first detected low. The Output Buffer Full sta­tus flag bit OBF (TRISE<6>) is cleared immediately
(Figure 5-13) indicating that the PORTD latch is waiting
to be read by the external bus. When either the CS
RD
bit PSPIF is set on the Q4 clock cycle, following the
next Q2 cycle, indicating that the read is complete.
OBF remains low until data is written to PORTD by the
user firmware.

When not in Parallel Slav e P ort mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previ­ously set, it must be cleared in firmware.

An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).

).

to be the RD input, RE1/WR

and WR

and RD

or

pin becomes high (level triggered), the interrupt flag

FIGURE 5-11: PORTD AND PORTE AS A

PARALLEL SLAVE PORT

Data bus

WR
PORT

RD
PORT

One bit of PORTD

Set interrupt flag
PSPIF (PIR1<7>)

Note: I/O pin has protection diodes to VDD and VSS.

QD

CK

QD

EN

EN

TTL

Read

Chip Select

Write

TTL

TTL

TTL

RDx
pin

RD

CS

WR

 1997 Microchip Technology Inc. DS30234D-page 61

PIC16C6X

FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1 Q2 Q3 Q4

CS

WR
RD

PORTD<7:0>

IBF

OBF

PSPIF

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS

Q1 Q2 Q3 Q4

CS

WR
RD

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 5-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —
0Ch PIR1 PSPIF
8Ch PIE1 PSPIE
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.

Note 1: These bits are reserved, always maintain these bits clear.

2: These bits are implemented on the PIC16C65/65A/R65/67 only.

(1)
(1)

RCIF

RCIE

(2)
(2)

TXIF
TXIE

(2)

SSPIF CCP1IF TMR2IF TRM1IF 0000 0000 0000 0000

(2)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PORTE Data Direction Bits

POR,
BOR

0000 -111 0000 -111

Value on all
other resets

DS30234D-page 62  1997 Microchip Technology Inc.

PIC16C6X

6.0 OVERVIEW OF TIMER
MODULES

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

All PIC16C6X devices hav e three timer modules except
for the PIC16C61, which has one timer module. Each
module can generate an interrupt to indicate that an
event has occurred (i.e., timer overflow). Each of these
modules are detailed in the following sections. The
timer modules are:

• Timer0 module (Section 7.0)

• Timer1 module (Section 8.0)

• Timer2 module (Section 9.0)

6.1 Timer0 Overview

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The Timer0 module is a simple 8-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock. When the clock
source is an external clock, the Timer0 module can be
selected to increment on either the rising or falling
edge.

The Timer0 module also has a programmable pres­caler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler, and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. TMR0
can increment at the following rates: 1:1 when the pres­caler is assigned to Watchdog Timer, 1:2, 1:4, 1:8,
1:16, 1:32, 1:64, 1:128, and 1:256.

Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre­quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.

6.2 Timer1 Overview

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an external
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (external clock source), the counter can either
operate synchronized to the device or asynchronously
to the device. Asynchronous operation allo ws Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power sav­ings of SLEEP mode.

TImer1 also has a prescaler option which allows TMR1
to increment at the following rates: 1:1, 1:2, 1:4, and
1:8. TMR1 can be used in conjunction with the Capture/
Compare/PWM module. When used with a CCP mod­ule, Timer1 is the time-base for 16-bit capture or 16-bit
compare and must be synchronized to the device.

6.3 Timer2 Overview

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Timer2 is an 8-bit timer with a programmable prescaler
and a programmable postscaler, as well as an 8-bit
Period Register (PR2). Timer2 can be used with the
CCP module (in PWM mode) as well as the Baud Rate
Generator for the Synchronous Serial Port (SSP). The
prescaler option allows Timer2 to increment at the fol­lowing rates: 1:1, 1:4, and 1:16.

The postscaler allows TMR2 register to match the
period register (PR2) a programmable number of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).

6.4 CCP Overview

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The CCP module(s) can operate in one of three modes:
16-bit capture, 16-bit compare, or up to 10-bit Pulse
Width Modulation (PWM).

Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or sixteenth rising edge of the
CCPx pin.

Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs, an interrupt can be generated and the
output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control
bits CCPxM3:CCPxM0.

PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 reg­ister = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an out­put) will be forced high.

 1997 Microchip Technology Inc. DS30234D-page 63

PIC16C6X

NOTES:

DS30234D-page 64  1997 Microchip Technology Inc.

PIC16C6X

7.0 TIMER0 MODULE

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Read and write capability

- Interrupt on overflow from FFh to 00h

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0
module.

Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS. In this
mode, Timer0 will increment either on ever y rising or
falling edge of pin RA4/T0CKI. The incrementing edge
is determined by the source edge select bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are dis­cussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres­caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.

7.1 TMR0 Interrupt

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The TMR0 interrupt is generated when the register
(TMR0) overflows from FFh to 00h. This overflow sets
interrupt flag bit T0IF (INTCON<2>). The interrupt can
be masked by clearing enable bit T0IE (INTCON<5>).
Flag bit T0IF must be cleared in softw are by the TImer0
interrupt service routine before re-enabling this inter­rupt. The TMR0 interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
Figure 7-4 displays the Timer0 interrupt timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

RA4/T0CKI
pin

Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).

FOSC/4

T0SE

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed diagram).

0

1

T0CS

Programmable

Prescaler

3

PS2, PS1, PS0

1

0

PSA

PSout

Sync with

Internal

clocks

(2 cycle delay)

FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

PC
(Program
Counter)

Instruction

Fetch

TMR0

Instruction
Executed

Q1 Q2 Q3 Q4

PC-1

T0

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0
executed

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

PSout

Data bus

TMR0 reg

Read TMR0
reads NT0 + 1

8

Set bit T0IF
on overflow

Read TMR0
reads NT0 + 2

 1997 Microchip Technology Inc. DS30234D-page 65

PIC16C6X

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC
(Program
Counter)

Instruction

Fetch

TMR0

Instruction
Execute

Q1 Q2 Q3 Q4

PC-1

T0 NT0+1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0+1

Write TMR0
executed

FIGURE 7-4: TMR0 INTERRUPT TIMING

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit
(INTCON<2>)

GIE bit
(INTCON<7>)

UCTION

INSTR

LOW

F

FEh

1

FFh 00h 01h 02h

1

Read TMR0
reads NT0

NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0 + 1

T0

Instruction
fetched

Instruction
executed

PC

PC

Inst (PC)

Inst (PC-1)

PC +1 PC +1 0004h 0005h

Inst (PC+1)

Inst (PC)

Note 1: Interrupt flag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

DS30234D-page 66  1997 Microchip Technology Inc.

PIC16C6X

7.2 Using Timer0 with External Clock

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

When an external clock input is used for Timer0, it m ust
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom­plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.

OSC). Also, there is a delay in the actual

When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres­caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There­fore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini­mum pulse width requirement of 10 ns. Ref er to param­eters 40, 41 and 42 in the electrical specification of the
desired device.

7.2.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod­ule is actually incremented. Figure 7-5 shows the dela y
from the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or
Prescaler output

External Clock/Prescaler
Output after sampling

Increment Timer0 (Q4)

(2)

(1)

(3)

Small pulse
misses sampling

Timer0

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.

T0 T0 + 1 T0 + 2

 1997 Microchip Technology Inc. DS30234D-page 67

PIC16C6X

7.3 Prescaler

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (Figure 7-6). For simplicity,
this counter is being referred to as “prescaler” through­out this data sheet. Note that the prescaler may be
used by either the Timer0 module or the Watchdog
Timer, but not both. Thus, a prescaler assignment for
the Timer0 module means that there is no prescaler f or
the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0,bitx) will clear the pres­caler count. When assigned to the Watchdog Timer, a
CLRWDT instruction will clear the Watchdog Timer and
the prescaler count. The prescaler is not readable or
writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (=Fosc/4)

RA4/T0CKI

pin

T0SE

0

1

T0CS

M
U

X

1

M
U

0

X

PSA

SYNC

2

Cycles

Data Bus

8

TMR0 reg

Set flag bit T0IF

on Overflow

0

M

U

1

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

X

PSA

8-bit Prescaler

8 - to - 1MUX

0

8

M U X

WDT

Time-out

PS2:PS0

1

PSA

DS30234D-page 68  1997 Microchip Technology Inc.

7.3.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the fly” during program
execution.

Note: To avoid an unintended device RESET, the

following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.

EXAMPLE 7-1: CHANGING PRESCALER (TIMER0→WDT)

PIC16C6X

Lines 2 and 3 do NOT have to
be included if the final desired
prescale value is other than 1:1.
If 1:1 is final desired value, then
a temporary prescale value is
set in lines 2 and 3 and the final
prescale value will be set in lines
10 and 11.

1) BSF STATUS, RP0 ;Bank 1

2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of

3) MOVWF OPTION_REG ;other than 1:1

4) BCF STATUS, RP0 ;Bank 0

5) CLRF TMR0 ;Clear TMR0 and prescaler

6) BSF STATUS, RP1 ;Bank 1

7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value

8) MOVWF OPTION_REG ;

9) CLRWDT ;Clears WDT and prescaler

10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT

11) MOVWF OPTION_REG ;

12) BCF STATUS, RP0 ;Bank 0

To change prescaler from the WDT to the Timer0 mod­ule, use the sequence shown in Example 7-2.

EXAMPLE 7-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT ;Clear WDT and prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and clock source
MOVWF OPTION_REG ;
BCF STATUS, RP0 ;Bank 0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h, 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,

10Bh,18Bh
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — —
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

Note 1: TRISA<5> and bit PEIE are not implemented on the PIC16C61, read as '0'.

 1997 Microchip Technology Inc. DS30234D-page 69

INTCON GIE PEIE

(1)

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

PORTA Data Direction Register

(1)

POR,

BOR

--11 1111 --11 1111

Value on all

other resets

PIC16C6X

NOTES:

DS30234D-page 70  1997 Microchip Technology Inc.

PIC16C6X

8.0 TIMER1 MODULE

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Timer1 is a 16-bit timer/counter consisting of two 8-bit
registers (TMR1H and TMR1L) which are readable and
writable. Register TMR1 (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear­ing the TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

• As a timer

• As a counter
The operating mode is determined by clock select bit,

TMR1CS (T1CON<1>) (Figure 8-2).
In timer mode, Timer1 increments every instruction

cycle. In counter mode, it increments on every rising
edge of the external clock input.

Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).

Timer1 also has an internal “reset input”. This reset can
be generated by CCP1 or CCP2 (Capture/Compare/
PWM) module. See Section 10.0 for details. Figure 8-1
shows the Timer1 control register.

For the PIC16C62A/R62/63/R63/64A/R64/65A/R65/
R66/67, when the Timer1 oscillator is enabled
(T1OSCEN is set), the RC1 and RC0 pins become
inputs. That is, the TRISC<1:0> value is ignored.

For the PIC16C62/64/65, when the Timer1 oscillator is
enabled (T1OSCEN is set), RC1 pin becomes an input,
however the RC0 pin will have to be configured as an
input by setting the TRISC<0> bit.

The Timer1 module also has a software prog rammable
prescaler.

FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit

bit7 bit0

bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input

TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1OSI (on the rising edge) (See pinouts for pin with T1OSI function)
0 = Internal clock (Fosc/4)

bit 0: TMR1ON: Timer1 On bit

1 = Enables Timer1
0 = Stops Timer1

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

 1997 Microchip Technology Inc. DS30234D-page 71

PIC16C6X

8.1 Timer1 Operation in Timer Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Timer mode is selected by clearing bit TMR1CS
(T1CON<1>). In this mode, the input clock to the timer
is Fosc/4. The synchronize control bit T1

SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.

8.2 Timer1 Operation in Synchronized

Counter Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on T1OSI when enable bit T1OSCEN is set
or pin with T1CKI when bit T1OSCEN is cleared.

Note: The T1OSI function is multiplexed to differ-

ent pins, depending on the device. See the
pinout descriptions to see which pin has
the T1OSI function.

If T1SYNC
synchronized with internal phase clocks. The synchro­nization is done after the prescaler stage. The pres­caler stage is an asynchronous ripple counter.

In this configuration, during SLEEP mode, Timer1 will
not increment even if an e xternal clock is present, since
the synchronization circuit is shut off. The prescaler,
however, will continue to increment.

is cleared, then the external clock input is

8.2.1 EXTERNAL CLOCK INPUT TIMING FOR
SYNCHRONIZED COUNTER MODE

When an external clock input is used for Timer1 in syn­chronized counter mode, it must meet certain require­ments. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after syn­chronization.

When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom­plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to appropriate
electrical specification section, parameters 45, 46, and

47.

When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple­counter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple counter must be taken
into account. Therefore, it is necessary for T1CKI to
have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that the y do
not violate the minimum pulse width requirements of
10 ns). Refer to applicable electrical specification sec­tion, parameters 40, 42, 45, 46, and 47.

FIGURE 8-2: TIMER1 BLOCK DIAGRAM

TMR1IF
Overflow
Interrupt
flag bit

(2)

T1OSO

(2)

T1OSI

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

2: See pinouts for pins with T1OSO and T1OSI functions.
3: For the PIC16C62/64/65, the Schmitt Trigger is not implemented in external clock mode.

TMR1H

T1OSC

TMR1

TMR1L

T1OSCEN
Enable

Oscillator

(1)

(3)

Fosc/4
Internal

Clock

TMR1ON

on/off

1

0

TMR1CS

0

1

T1SYNC

Prescaler

1, 2, 4, 8

2

T1CKPS1:T1CKPS0

Synchronized

clock input

Synchronize

det

SLEEP input

DS30234D-page 72  1997 Microchip Technology Inc.

PIC16C6X

8.3 Timer1 Operation in Asynchronous
Counter Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and gener­ate an interrupt on overflow which will wak e the proces­sor. However, special precautions in software are
needed to read-from or write-to the Timer1 register
pair, TMR1L and TMR1H (Section 8.3.2).

In asynchronous counter mode, Timer1 cannot be used
as a time-base for capture or compare operations.

8.3.1 EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK

If control bit T1SYNC
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements,
as specified in timing parameters (45 - 47).

8.3.2 READING AND WRITING TMR1 IN
ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L, while the timer is r unning
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.

For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten­tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre­dictable value in the timer register.

Reading the 16-bit value requires some care.
Example 8-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.

is set, the timer will increment

EXAMPLE 8-1: READING A 16-BIT

FREE-RUNNING TIMER

; All Interrupts are disabled

MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
MOVF TMR1H, W ;Read high byte
SUBWF TMPH, W ;Sub 1st read

;with 2nd read
BTFSC STATUS,Z ;is result = 0
GOTO CONTINUE ;Good 16-bit read

; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.

MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;

; Re-enable Interrupt (if required)
CONTINUE ;Continue with

: ;your code

8.4 Timer1 Oscillator

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

A crystal oscillator circuit is built in-between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla­tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 8-1 shows the capacitor
selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.
The user must allow a software time delay to ensure
proper oscillator start-up.

TABLE 8-1: CAPACITOR SELECTION

FOR THE TIMER1
OSCILLATOR

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up
time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the
resonator/crystal manufacturer for appropri­ate values of external components.

 1997 Microchip Technology Inc. DS30234D-page 73

PIC16C6X

8.5 Resetting Timer1 using a CCP Trigger
Output

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

CCP2 is implemented on the PIC16C63/R63/65/65A/
R65/66/67 only.

If CCP1 or CCP2 module is configured in Compare
mode to generate a “special event trigger”
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer1.

Note: The “special event trigger” from the

CCP1and CCP2 modules will not set inter­rupt flag bit TMR1IF(PIR1<0>).

Timer1 must be configured for either timer or synchro­nized counter mode to take advantage of this feature.
If the Timer1 is running in asynchronous counter mode,
this reset operation may not work.

In the event that a write to Timer1 coincides with a spe­cial event trigger from CCP1 or CCP2, the write will
take precedence.

In this mode of operation, the CCPRxH:CCPRxL regis­ters pair effectively becomes the period register for the
Timer1 module.

8.6 Resetting of TMR1 Register Pair
(TMR1H:TMR1L)

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The TMR1H and TMR1L registers are not reset to 00h
on a POR or any other reset except by the CCP1 or
CCP2 special event trigger.

The T1CON register is reset to 00h on a Power-on
Reset or a Brown-out Reset, which shuts off the timer
and leaves a 1:1 prescaler. In all other resets, the reg­ister is unaffected.

8.7 Timer1 Prescaler

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.

TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh
10Bh,18Bh

0Ch PIR1 PSPIF
8Ch PIE1 PSPIE
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

(2) (3)
(2) (3)

2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.

RCIF
RCIE

(1)
(1)

TXIF

TXIE

(1)

SSPIF CCP1IF TMR2IF TMR1IF

(1)

SSPIE CCP1IE TMR2IE TMR1IE

POR,

BOR

0000 000x 0000 000u

0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu

--00 0000 --uu uuuu

Value on
all other

resets

DS30234D-page 74  1997 Microchip Technology Inc.

PIC16C6X

9.0 TIMER2 MODULE

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Timer2 is an 8-bit timer with a prescaler and a
postscaler. It is especially suitable as PWM time-base
for PWM mode of CCP module(s). TMR2 is a readable
and writable register, and is cleared on any device
reset.

The input clock (F
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).

The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register . The PR2 register is ini­tialized to FFh upon reset.

The match output of the TMR2 register goes through a
4-bit postscaler (which gives a 1:1 to 1:16 scaling,
inclusive) to generate a TMR2 interrupt (latched in flag
bit TMR2IF (PIR1<1>)).

The Timer2 module can be shut off by clearing control
bit TMR2ON (T2CON<2>) to minimize power con­sumption.

Figure 9-2 shows the Timer2 control register . T2CON is
cleared upon reset which initializes Timer2 as shut off
with the prescaler and postscaler at a 1:1 value.

OSC/4) has a prescale option of 1:1,

9.1 Timer2 Prescaler and Postscaler

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The prescaler and postscaler counters are cleared
when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (POR, BOR, M

CLR Reset, or

WDT Reset).

TMR2 is not cleared when T2CON is written.

9.2 Output of TMR2

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The output of TMR2 (bef ore the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.

FIGURE 9-1: TIMER2 BLOCK DIAGRAM

Sets
TMR2

interrupt
flag bit,

TMR2IF

Postscaler

1:1 to 1:16

4

TMR2

output

Reset

(1)

EQ

TMR2 reg

Comparator

PR2 reg

Prescaler

1:1, 1:4, 1:16

2

Fosc/4

Note 1: TMR2 register output can be software selected by

the SSP Module as a baud clock.

FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

bit7 bit0

bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 postscale
0001 = 1:2 postscale

•

•

1111 = 1:16 postscale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on
0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = 1:1 prescale
01 = 1:4 prescale
1x = 1:16 prescale

W = Writable bit
U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

 1997 Microchip Technology Inc. DS30234D-page 75

PIC16C6X

TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh
10Bh,18Bh

0Ch PIR1 PSPIF
8Ch PIE1 PSPIE
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — T OUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer2.

Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(2) (3)
(2) (3)

2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.

RCIF
RCIE

(1)
(1)

TXIF
TXIE

(1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

(1)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

POR,

BOR

Value on
all other

resets

DS30234D-page 76  1997 Microchip Technology Inc.

PIC16C6X

10.0 CAPTURE/COMPARE/PWM
(CCP) MODULE(s)

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP2

Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave duty cycle register. Both the CCP1 and
CCP2 modules are identical in operation, with the
exception of the operation of the special event tr igger.
Table 10-1 and Table 10-2 show the resources and
interactions of the CCP modules(s). In the following
sections, the operation of a CCP module is described
with respect to CCP1. CCP2 operates the same as
CCP1, except where noted.

CCP1 module:

Capture/Compare/PWM Register1 (CCPR1) is com­prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.

TABLE 10-2: INTERACTION OF TWO CCP MODULES

CCP2 module:

Capture/Compare/PWM Register2 (CCPR2) is com­prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.

For use of the CCP modules, refer to the

Control Handbook,

“Using the CCP Modules” (AN594).

Embedded

TABLE 10-1: CCP MODE - TIMER

RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1
Timer1
Timer2

CCPx Mode CCPy Mode Interaction

Capture Capture Same TMR1 time-base.
Capture Compare The compare should be configured for the special event trigger, which clears TMR1.
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM Capture None
PWM Compare None

 1997 Microchip Technology Inc. DS30234D-page 77

PIC16C6X

FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit

bit7 bit0

bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits

Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (bit CCPxIF is set)
1001 = Compare mode, clear output on match (bit CCPxIF is set)
1010 = Compare mode, generate software interrupt on match (bit CCPxIF is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1)
11xx = PWM mode

W =Writable bit
U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

10.1 Capture Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an ev ent occurs
on pin RC2/CCP1 (Figure 10-2). An event is defined as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter­rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs bef ore
the value in register CCPR1 is read, the old captured
value will be lost.

10.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-

ured as an input by setting the TRISC<2> bit.

Note: If the RC2/CCP1 pin is configured as an

output, a write to PORTC can cause a cap­ture condition.

FIGURE 10-2: CAPTURE MODE

OPERATION BLOCK
DIAGRAM

Set CCP1IF

Prescaler

÷ 1, 4, 16

RC2/CCP1
pin

and

edge detect

CCP1CON<3:0>

Q’s

10.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work consistently.

10.1.3 SOFTWARE INTERRUPT
When the Capture event is changed, a false capture

interrupt may be generated. The user should clear
enable bit CCP1IE (PIE1<2>) to avoid false interr upts
and should clear flag bit CCP1IF following any such
change in operating mode.

PIR1<2>

CCPR1H CCPR1L

Capture
Enable

TMR1H TMR1L

DS30234D-page 78  1997 Microchip Technology Inc.

PIC16C6X

10.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.

Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom­mended method for switching between capture pres­calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load the W reg with

; the new prescaler
; mode value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with

; this value

10.2 Compare Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time interrupt flag bit CCP1IF is set.

10.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.

10.2.1 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.

10.2.2 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the

CCP1 pin is not affected. Only a CCP interrupt is gen­erated (if enabled).

10.2.3 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated

which may be used to initiate an action.
The special event trigger output of CCP1 and CCP2

resets the TMR1 register pair. This allows the
CCPR1H:CCPR1L and CCPR2H:CCPR2L registers to
effectively be 16-bit programmable period register(s)
for Timer1.

For compatibility issues, the special event trigger out­put of CCP1 (P
P

IC16C7X devices) also starts an A/D conversion.

IC16C72) and CCP2 (all other

Note: The “special event trigger” from the

CCP1and CCP2 modules will not set inter­rupt flag bit TMR1IF (PIR1<0>).

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK
DIAGRAM

Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).

Special Event Trigger

Set CCP1IF
PIR1<2>

CCPR1H CCPR1L

QS

Output

RC2/CCP1

TRISC<2>

Output Enable

 1997 Microchip Technology Inc. DS30234D-page 79

Logic

R

CCP1CON<3:0>

Mode Select

match

Comparator

TMR1H TMR1L

PIC16C6X

10.3 PWM Mode

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the POR TC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.

Figure 10-4 shows a simplified block diagram of the
CCP module in PWM mode.

For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 10.3.3.

FIGURE 10-4: SIMPLIFIED PWM BLOCK

DIAGRAM

Duty cycle registers

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

(Note 1)

Clear Timer,
CCP1 pin and
latch D.C .

A PWM output (Figure 10-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).

CCP1CON<5:4>

R

S

Q

RC2/CCP1

TRISC2

FIGURE 10-5: PWM OUTPUT

Period

Duty Cycle

10.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the fol­lowing formula:

PWM period = [(PR2) + 1] • 4 • T

OSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the f ollowing three e v ents

occur on the next increment cycle:

• TMR2 is cleared

• The PWM duty cycle is latched from CCPR1L into
CCPR1H

• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)

Note: The Timer2 postscaler (see Section 9.1) is

not used in the determination of the PWM
frequency . The postscaler could be used to
have a servo update rate at a different fre­quency than the PWM output.

10.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 con­catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM
frequency:

OSC

F
F

PWM

)

bits

log(

=

log(2)

TMR2 = PR2

TMR2 = Duty Cycle

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be
forced to the low level.

TMR2 = PR2

DS30234D-page 80  1997 Microchip Technology Inc.

PIC16C6X

EXAMPLE 10-2: PWM PERIOD AND DUTY

CYCLE CALCULATION

Desired PWM frequency is 78.125 kHz,
Fosc = 20 MHz
TMR2 prescale = 1

1/78.125 kHz = [(PR2) + 1] • 4 • 1/20 MHz • 1

12.8 µs = [(PR2) + 1] • 4 • 50 ns • 1
PR2 = 63

Find the maximum resolution of the duty cycle that can
be used with a 78.125 kHz frequency and 20 MHz
oscillator:

1/78.125 kHz = 2

12.8 µs= 2
256 = 2

PWM RESOLUTION
PWM RESOLUTION
PWM RESOLUTION

log(256) = (PWM Resolution) • log(2)

8.0 = PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained

• 1/20 MHz • 1

• 50 ns • 1

In order to achieve higher resolution, the PWM fre­quency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.

Table 10-3 lists example PWM frequencies and resolu­tions for Fosc = 20 MHz. The TMR2 prescaler and PR2
values are also shown.

10.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 regis­ter.

2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.

5. Configure the CCP1 module for PWM operation.

from a 78.125 kHz frequency and a 20 MHz oscillator,
i.e., 0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value
greater than 255 will result in a 100% duty cycle.

TABLE 10-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1111
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5

TABLE 10-4: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE

Value on:

Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh
10Bh,18Bh

0Ch PIR1 PSPIF
0Dh
8Ch PIE1 PSPIE
8Dh
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
1Ch
1Dh
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in these modes.

Note 1: These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

(2) (3)

(4)

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

(4)

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

(4)

CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu

(4)

CCPR2H Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu

(4)

CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear.
4: These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67.

(2) (3)

RCIF

RCIE

(1)

(1)

TXIF

TXIE

(1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

(1)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

POR,

BOR

0000 000x 0000 000u

Value on

all other

Resets

 1997 Microchip Technology Inc. DS30234D-page 81

PIC16C6X

TABLE 10-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Value on:

POR,

BOR

Value on

all other

Resets

10Bh,18Bh
0Ch PIR1 PSPIF

(4)

0Dh

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch PIE1 PSPIE

(4)

8Dh

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

(2) (3)

(2) (3)

RCIF

RCIE

(1)

(1)

TXIF

TXIE

(1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

(1)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

87h TRISC PORTC Data Direction register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s Period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L
16h CCPR1H

Capture/Compare/PWM1 (LSB)
Capture/Compare/PWM1 (MSB)

xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
1Ch
1Dh

(4)

CCPR2L

(4)

CCPR2H

(4)

CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Capture/Compare/PWM2 (LSB)
Capture/Compare/PWM2 (MSB)

xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in this mode.
Note 1: These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.

2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear.
4: These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67.

DS30234D-page 82  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.0 SYNCHRONOUS SERIAL
PORT (SSP) MODULE

11.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral
or microcontroller devices. These peripheral devices
may be Serial EEPROMs, shift registers, display dr iv­ers, A/D converters, etc. The SSP module can operate
in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

The SSP module in I
PIC16C6X devices that hav e an SSP module. However
the SSP Module in SPI mode has differences between
the PIC16C66/67 and the other PIC16C6X devices.

The register definitions and operational description of
SPI mode has been split into two sections because of
the differences between the PIC16C66/67 and the
other PIC16C6X devices. The default reset values of
both the SPI modules is the same regardless of the
device:

11.2 SPI Mode for PIC16C62/62A/R62/63/R63/64/

64A/R64/65/65A/R65 .......................................84

11.3 SPI Mode for PIC16C66/67..............................89

11.4 I2C™ Overview................................................95

11.5 SSP I2C Operation...........................................99

2

C)

2

C mode works the same in all

PIC16C6X

Refer to Application Note AN578,

ule in the I

2

C Multi-Master Environment.”

“Use of the SSP Mod-

 1997 Microchip Technology Inc. DS30234D-page 83

Applicable Devices

PIC16C6X

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.2 SPI Mode for PIC16C62/62A/R62/63/
R63/64/64A/R64/65/65A/R65

This section contains register definitions and opera­tional characteristics of the SPI module for the
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63,
PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64,
PIC16C65, PIC16C65A, PIC16CR65.

FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — D/A P S R/W UA BF R = Readable bit

bit7 bit0

bit 7-6: Unimplemented: Read as '0'
bit 5: D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last

bit 3: S: Start bit (I

1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last

bit 2: R/W

bit 1: UA: Update Address (10-bit I

bit 0: BF: Buffer Full Status bit

: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or A
1 = Read
0 = Write

1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

Receiv
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty

T

ransmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty

2

C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)

2

C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)

CK bit.

2

C mode only)

e (SPI and I2C modes)

W =Writable bit
U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

DS30234D-page 84  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision

bit 6: SSPOV: Receive Overflow Detect bit

In SPI mode
1 = A new byte is received while the SSPB UF register is still holding the previous data. In case of ov erflow ,
the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSP­BUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set
since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow

2

In I

C mode
1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins

2

C mode

In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode
1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.
0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.

2

C mode

In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = Fosc/4
0001 = SPI master mode, clock = Fosc/16
0010 = SPI master mode, clock = Fosc/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. S
0101 = SPI slave mode, clock = SCK pin. S
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I

2

C slave mode, 7-bit address

2

C slave mode, 10-bit address

2

C firmware controlled Master Mode (slave idle)

2

C slave mode, 7-bit address with start and stop bit interrupts enabled

2

C slave mode, 10-bit address with start and stop bit interrupts enabled

S pin control enabled.
S pin control disabled. SS can be used as I/O pin.

W =Writable bit
U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

 1997 Microchip Technology Inc. DS30234D-page 85

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.2.1 OPERATION OF SSP MODULE IN SPI
MODE

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The SPI mode allows 8-bits of data to be synchro­nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally a fourth pin may be used when in a slave
mode of operation:

• Slave Select (SS

)

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Output/Input data on the Rising/

Falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that b yte is mo v ed to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and flag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is expecting to receive v alid data, the SSPB UF register
should be read before the next byte of data to transfer
is written to the SSPBUF register. The Buffer Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has com­pleted. The SSPBUF register must be read and/or writ­ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col­lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register for data transmis­sion. The shaded instruction is only required if the
received data is meaningful.

EXAMPLE 11-1: LOADING THE SSPBUF

(SSPSR) REGISTER

BSF STATUS, RP0 ;Specify Bank 1

LOOP BTFSS SSPSTAT, BF ;Has data been

;received
;(transmit

;complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;W reg = contents

;of SSPBUF
MOVWF RXDATA ;Save in user RAM
MOVF TXDATA, W ;W reg = contents

; of TXDATA
MOVWF SSPBUF ;New data to xmit

The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Addi­tionally, the SSP status register (SSPSTAT) indicates
the various status conditions.

FIGURE 11-3: SSP BLOCK DIAGRAM

(SPI MODE)

Internal

data bus

Read Write

SSPBUF reg

SSPSR reg

2

shift

clock

TMR2 output

Prescaler

4, 16, 64

2

T

CY

RC4/SDI/SDA

RC5/SDO

RA5/SS

RC3/SCK/
SCL

bit0

Control

SS

Enable

Edge

Select

SSPM3:SSPM0

Edge

Select

TRISC<3>

Clock Select

4

DS30234D-page 86  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This config­ures the SDI, SDO, SCK, and SS

pins as serial port
pins. For the pins to behave as the serial port function,
they must hav e their data direction bits (in the TRIS reg­ister) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRISA<5> set (if implemented)

Any serial port function that is not desired may be over­ridden by programming the corresponding data direc­tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS

could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.

Figure 11-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro­grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

The master can initiate the data transfer at any time
because it controls the SCK. The master deter mines
when the slave (Processor 2) is to broadcast data by
the software protocol.

In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.

In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched interrupt flag bit SSPIF (PIR1<3>) is
set.

The clock polarity is selected by appropriately program­ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-5 and Figure 11-6 where the MSB is trans­mitted first. In master mode , the SPI clock r ate (bit rate)
is user programmable to be one of the following:

• Fosc/4 (or T

• Fosc/16 (or 4 • T

• Fosc/64 (or 16 • T

CY)

CY)

CY)

• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)

of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data
and wake the device from sleep.

FIGURE 11-4: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SDO

Serial Input Buffer

(SSPBUF register)

Shift Register

(SSPSR)

MSb

PROCESSOR 1

 1997 Microchip Technology Inc. DS30234D-page 87

LSb

SDI

SCK

Serial Clock

SPI Slave SSPM3:SSPM0 = 010xb

SDI

Serial Input Buffer
(SSPBUF register)

SDO

SCK

Shift Register

(SSPSR)

MSb

PROCESSOR 2

LSb

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set the for synchro­nous slave mode to be enabled. When the SS

pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS

pin goes high,
the SDO pin is no longer driven, even if in the mid­dle of a transmitted byte, and becomes a floating
output. If the SS

pin is taken low without resetting

SPI mode, the transmission will continue from the

point at which it was taken high. Exter nal pull-up/
pull-down resistors may be desirab le, depending on the
application.

To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.

FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL

SCK
(CKP = 0)

SCK
(CKP = 1)

SDO

SDI

SSPIF

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL

SS

SCK
(CKP = 0)

SCK
(CKP = 1)

SDO

SDI

SSPIF

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh INTCON GIE PEIE
0Ch PIR1 PSPIF
8Ch PIE1 PSPIE
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h

87h
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI

Note 1: These bits are associated with the USART which is implemented on the PIC16C63/R63/65/65A/R65 only.

TRISA — —
TRISC PORTC Data Direction Register

mode.

2: PSPIF and PSPIE are reserved on the PIC16C62/62A/R62/63/R63, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.

(2) (3)

(2) (3)

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

(1)

RCIF

(1)

RCIE

PORTA Data Direction Register

TXIF

TXIE

(1)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

(1)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

POR,

BOR

--11 1111 --11 1111
1111 1111 1111 1111

Value on

all other

Resets

DS30234D-page 88  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

11.3 SPI Mode for PIC16C66/67

This section contains register definitions and opera­tional characterisitics of the SPI module on the
PIC16C66 and PIC16C67 only.

FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C66/67)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

bit7 bit0

bit 7: SMP: SPI data input sample phase

SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Sla

ve Mode

SMP must be cleared when SPI is used in slave mode

bit 6: CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13)

CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK

bit 5: D/A

bit 4: P: Stop bit (I

bit 3: S: Start bit (I

bit 2: R/W

bit 1: UA: Update Address (10-bit I

bit 0: BF: Buffer Full Status bit

: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address

2

detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last

2

detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last

: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or A
1 = Read
0 = Write

1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

e (SPI and I2C modes)

Receiv
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty

T

ransmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty

P S R/W UA BF R = Readable bit

W =Writable bit
U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is

C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is

CK bit.

2

C mode only)

 1997 Microchip Technology Inc. DS30234D-page 89

Applicable Devices

PIC16C6X

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C66/67)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision

bit 6: SSPOV: Receive Overflow Indicator bit

In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over­flow , the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF,
even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since
each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow

2

In I

C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins

2

C mode

In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level

2

In I

C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = F
0001 = SPI master mode, clock = F
0010 = SPI master mode, clock = F

OSC/4
OSC/16
OSC/64

0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS
0101 = SPI slave mode, clock = SCK pin. SS
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I

2

C slave mode, 7-bit address

2

C slave mode, 10-bit address

2

C firmware controlled master mode (slave idle)

2

C slave mode, 7-bit address with start and stop bit interrupts enabled

2

C slave mode, 10-bit address with start and stop bit interrupts enabled

pin control enabled.
pin control disabled. SS can be used as I/O pin

W =Writable bit
U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

DS30234D-page 90  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

11.3.1 SSP MODULE IN SPI MODE FOR
PIC16C66/67

The SPI mode allows 8-bits of data to be synchro­nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave
mode of operation:

• Slave Select (SS

) RA5/SS

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol­lowing to be specified:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8-bits of data
have been received, that b yte is mo v ed to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>)
are set. This double buffering of the received data
(SSPBUF) allows the next b yte to start reception before
reading the data that was just received. An y write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit WCOL
(SSPCON<7>) will be set. User softw are must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed success­fully. When the application software is expecting to
receive valid data, the SSPBUF should be read before
the next byte of data to transfer is written to the
SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
bit BF is cleared. This data may be irrelevant if the SPI
is only a transmitter. Generally the SSP Interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or writ­ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col­lision does not occur. Example 11-2 shows the loading
of the SSPBUF (SSPSR) for data transmission. The
shaded instruction is only required if the received data
is meaningful.

EXAMPLE 11-2: LOADING THE SSPBUF

(SSPSR) REGISTER
(PIC16C66/67)

BCF STATUS, RP1 ;Specify Bank 1
BSF STATUS, RP0 ;
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(transmit
;complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;W reg = contents
; of SSPBUF
MOVWF RXDATA ;Save in user RAM

MOVF TXDATA, W ;W reg = contents
; of TXDATA
MOVWF SSPBUF ;New data to xmit

The block diagram of the SSP module, when in SPI
mode (Figure 11-9), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the var ious
status conditions.

FIGURE 11-9: SSP BLOCK DIAGRAM

(SPI MODE)(PIC16C66/67)

Internal

data bus

Read Write

SSPBUF reg

SSPSR reg

2

shift

clock

TMR2 output

Prescaler

4, 16, 64

2

T

CY

RC4/SDI/SDA

RC5/SDO

S

RA5/S

RC3/SCK/
SCL

bit0

Control

SS

Enable

Edge

Select

SSPM3:SSPM0

Edge

Select

TRISC<3>

Clock Select

4

 1997 Microchip Technology Inc. DS30234D-page 91

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg­ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS

pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro­priately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRISA<5> set

Any serial port function that is not desired may be over­ridden by programming the corresponding data direc­tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS

could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.

Figure 11-10 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro­grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application firmware. This leads to three scenarios for
data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

The master can initiate the data transfer at any time
because it controls the SCK. The master deter mines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.

In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.

In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.

The clock polarity is selected by appropriately program­ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-11, Figure 11-12, and Figure 11-13 where
the MSB is transmitted first. In master mode, the SPI
clock rate (bit rate) is user programmable to be one of
the following:

•F

OSC/4 (or TCY)

•F

OSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)

of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data
and wake the device from sleep.

• Master sends dummy data — Slave sends data

FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C66/67)

SPI Master SSPM3:SSPM0 = 00xxb

SDO

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

PROCESSOR 1

DS30234D-page 92  1997 Microchip Technology Inc.

LSb

SDI

SCK

Serial Clock

SPI Slave SSPM3:SSPM0 = 010xb

SDI

Serial Input Buffer

(SSPBUF)

SDO

SCK

Shift Register

(SSPSR)

MSb

PROCESSOR 2

LSb

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the synchro­nous slave mode to be enabled. When the SS

pin is
low , transmission and reception are enabled and the
SDO pin is driven. When the SS

pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output. If
the S

S pin is taken low without resetting SPI mode,
the transmission will continue from the point at
which it was taken high. Exter nal pull-up/ pull-down
resistors may be desirable, depending on the applica­tion.

Note: When the SPI is in Slav e Mode with SS pin

control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS
to V

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS
enabled.

To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.

FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C66/67)

SCK (CKP = 0,

CKE = 0)

SCK (CKP = 0,

CKE = 1)

SCK (CKP = 1,

CKE = 0)

SCK (CKP = 1,

CKE = 1)

pin is set

DD.

pin control must be

SDO

SDI (SMP = 0)

SDI (SMP = 1)

SSPIF

bit7 bit6 bit5

bit7

bit7 bit0

bit4

bit3

bit2

FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C66/67)

SS (optional)

SCK (CKP = 0)
SCK (CKP = 1)

SDO

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5

bit7 bit0

bit4

bit3

bit2

bit1 bit0

bit0

bit1 bit0

 1997 Microchip Technology Inc. DS30234D-page 93

Applicable Devices

PIC16C6X

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C66/67)

SS
(not optional)

SCK (CKP = 0)
SCK (CKP = 1)

SDO

SDI (SMP = 0)

SSPIF

bit7

bit7 bit0

bit6 bit5

bit4

bit3

bit2

bit1 bit0

TABLE 11-2: REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C66/67)

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh,8Bh,
10Bh,18Bh

0Ch
8Ch
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA
87h TRISC
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear.

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

PIR1 PSPIF
PIE1 PSPIE

Shaded cells are not used by SSP module in SPI mode.

2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.

(1) (2)
(1) (2)

— — PORTA Data Direction register --11 1111 --11 1111

PORTC Data Direction register

RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Power-on

Reset

1111 1111 1111 1111

Value on all

other resets

DS30234D-page 94  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

11.4 I2C™ Overview

This section provides an overview of the Inter-Inte­grated Circuit (I
the operation of the SSP module in I

2

C bus is a two-wire serial interface de veloped by

The I
the Philips
standard mode, was for data transfers of up to 100
Kbps. The enhanced specification (fast mode) is also
supported. This device will communicate with both
standard and fast mode devices if attached to the same
bus. The clock will determine the data rate.

2

The I

C interface employs a comprehensiv e protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard­ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXX software. Table 11-3 defines some of the

2

I

C bus terminology. For additional information on the

2

I

C interface specification, refer to the Philips docu-

ment “

The I2C bus and how to use it.”

which can be obtained from the Philips Corporation.
In the I

address. When a master wishes to initiate a data trans­fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans­fer . That is they can be thought of as operating in either
of these two relations:

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver

2

C) bus, with Section 11.5 discussing

®

Corporation. The original specification, or

2

C mode.

#939839340011,

2

C interface protocol each device has an

In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)

lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no de vice is pulling the line do wn. The num­ber of devices that may be attached to the I

2

C bus is
limited only by the maximum bus loading specification
of 400 pF.

11.4.1 INITIATING AND TERMINATING DATA

TRANSFER

During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The STAR T condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure 11-14 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans­fer. Due to the definition of the START and STOP con­ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.

FIGURE 11-14: START AND STOP

CONDITIONS

SDA

S

SCL

Start

Condition

Change

of Data

Allowed

Change

of Data

Allowed

P

Stop

Condition

TABLE 11-3: I2C BUS TERMINOLOGY

Term Description

Transmitter The device that sends the data to the bus.
Receiver The device that receives the data from the bus.
Master The device which initiates the transfer, generates the clock and terminates the transfer.
Slave The device addressed by a master.
Multi-master More than one master device in a system. These masters can attempt to control the bus at the

same time without corrupting the message.

Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that

the transfer data does not get corrupted.

Synchronization Procedure where the clock signals of two or more devices are synchronized.

 1997 Microchip Technology Inc. DS30234D-page 95

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.4.2 ADDRESSING I2C DEVICES
There are two address formats. The simplest is the

7-bit address format with a R/W
more complex is the 10-bit address with a R/W

bit (Figure 11-15). The

bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.

FIGURE 11-15: 7-BIT ADDRESS FORMAT

MSb LSb

ACK

S

slave address

S

Start Condition

R/W

Read/Write pulse

Acknowledge

ACK

2

FIGURE 11-16: I

S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

S

- Start Condition

R/W

- Read/Write Pulse

ACK

- Acknowledge

C 10-BIT ADDRESS FORMAT

11.4.3 TRANSFER ACKNOWLEDGE
All data must be transmitted per byte, with no limit to the

number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl­edge bit (A

CK) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).

R/W

Sent by

Slave

sent by slave
= 0 for write

FIGURE 11-17: SLAVE-RECEIVER

ACKNOWLEDGE

Data

Output by

Transmitter

Data

Output by

Receiver

SCL from

Master

S

Start

Condition

If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.

If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slav e to mov e the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech­nique can also be implemented at the bit level,
Figure 11-18. The sla ve will inherently stretch the cloc k,
when it is a transmitter, b ut will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.

1

not acknowledge

acknowledge

2

8

9

Clock Pulse for

Acknowledgment

FIGURE 11-18: DATA TRANSFER WAIT STATE

SDA

MSB acknowledgment

SCL

S

Start

Condition

DS30234D-page 96  1997 Microchip Technology Inc.

12 789 123 • 89

Address R/W

signal from receiver

byte complete
interrupt with receiver

clock line held low while
interrupts are serviced

ACK Wait

State

Data ACK

acknowledgment
signal from receiver

P

Stop

Condition

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

Figure 11-19 and Figure 11-20 show Master-transmit­ter and Master-receiver data transfer sequences.

When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con­dition (Sr) must be generated. This condition is identi­cal to the start condition (SDA goes high-to-low while

FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE

For 7-bit address:

S

Slave AddressR/W A Data A Data A/A P

'0' (write) data transferred

A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.

From master to slave

From slave to master

(n bytes - acknowledge)

A = acknowledge (SDA low)

= not acknowledge (SDA high)

A
S = Start Condition
P = Stop Condition

FIGURE 11-20: MASTER-RECEIVER SEQUENCE

For 7-bit address:

Slave AddressR/W

S

'1' (read) data transferred

A master reads a slave immediately after the first byte.

From master to slave

From slave to master

A Data A Data A P

(n bytes - acknowledge)

A = acknowledge (SDA low)

= not acknowledge (SDA high)

A
S = Start Condition
P = Stop Condition

SCL is high), but occurs after a data transfer acknowl­edge pulse (not the bus-free state). This allows a mas­ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.

For 10-bit address:

Slave Address

S R/W

First 7 bits

(write)

Data A Data P

A master transmitter addresses a slave receiver
with a 10-bit address.

For 10-bit address:

Slave Address

S R/W

First 7 bits

(write)

Slave Address

Sr R/W A3 AData A PData

First 7 bits

A master transmitter addresses a slave receiver
with a 10-bit address.

A1Slave Address

Second byte

A/A

A1Slave Address

Second byte

(read)

A2

A2

FIGURE 11-21: COMBINED FORMAT

(read or write)

(n bytes + acknowledge)

S

Slave AddressR/W A Data A/A Sr P

(read) Sr = repeated

Transfer direction of data and acknowledgment bits depends on R/W

Combined format:

Slave Address

Sr R/W A

First 7 bits

(write)

Combined format - A master addresses a slave with a 10-bit address, then transmits

From master to slave

From slave to master

 1997 Microchip Technology Inc. DS30234D-page 97

data to this slave and reads data from this slave.

Start Condition

Slave Address

Second byte

A = acknowledge (SDA low)
A

= not acknowledge (SDA high)
S = Start Condition
P = Stop Condition

Slave Address R/W

(write) Direction of transfer

Data Sr Slave Address

A Data A/A

may change at this point

bits.

First 7 bits

(read)

A Data A A PA A Data A/A Data

R/W

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.4.4 MULTI-MASTER

2

The I

C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbi­tration and synchronization occur.

11.4.4.1 ARBITRATION
Arbitration takes place on the SDA line, while the SCL

line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 11-22), and turns off its data output stage. A
master which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.

FIGURE 11-22: MULTI-MASTER

ARBITRATION
(TWO MASTERS)

transmitter 1 loses arbitration

DATA 1 SDA

DATA 1

DATA 2

SDA

SCL

11.2.4.2 Clock Synchronization
Clock synchronization occurs after the devices have

started arbitration. This is performed using a wired­AND connection to the SCL line. A high to low transition
on the SCL line causes the concerned devices to start
counting off their low period. Once a device clock has
gone low, it will hold the SCL line low until its SCL high
state is reached. The low to high transition of this clock
may not change the state of the SCL line, if another
device clock is still within its low period. The SCL line is
held low by the device with the longest low period.
Devices with shorter low periods enter a high wait­state, until the SCL line comes high. When the SCL line
comes high, all devices start counting off their high
periods. The first device to complete its high period will
pull the SCL line low. The SCL line high time is deter­mined by the device with the shortest high period,
Figure 11-23.

FIGURE 11-23: CLOCK SYNCHRONIZATION

start counting

HIGH period

CLK

1

CLK

2

state

counter

reset

wait

Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning mas­ter-transmitter may be addressing it.

Arbitration is not allowed between:

• A repeated START condition

• A STOP condition and a data bit

• A repeated START condition and a STOP condi-

tion

Care needs to be taken to ensure that these conditions
do not occur.

SCL

DS30234D-page 98  1997 Microchip Technology Inc.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PIC16C6X

11.5 SSP I2C Operation

The SSP module in I2C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifica­tions as well as 7-bit and 10-bit addressing. Two pins
are used for data transfer. These are the RC3/SCK/
SCL pin, which is the clock (SCL), and the RC4/SDI/
SDA pin, which is the data (SDA). The user must con­figure these pins as inputs or outputs through the
TRISC<4:3> bits. The SSP module functions are
enabled by setting SSP Enable bit SSPEN (SSP­CON<5>).

FIGURE 11-24: SSP BLOCK DIAGRAM

(I2C MODE)

Internal

data bus

Read Write

shift

MSb

SSPBUF reg

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

LSb

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

clock

RC4/

SDI/
SDA

The SSP module has five registers for I2C operation.
These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces­sible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C opera­tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I

2

C Slave mode (7-bit address)

•I

2

•I

C Slave mode (10-bit address)

2

•I

C Slave mode (7-bit address), with start and

2

C modes to be selected:

stop bit interrupts enabled

2

•I

C Slave mode (10-bit address), with start and

stop bit interrupts enabled

2

•I

C Firmware controlled Master Mode, slave is

idle

2

Selection of any I

C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro­vided these pins are programmed to inputs by setting
the appropriate TRISC bits.

The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of 10­bit address, and if this will be a read or write data trans­fer. The SSPSTAT register is read only.

The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver . This allows reception of the next b yte to begin
before reading the last byte of receiv ed data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.

The SSPADD register holds the slave address. In 10-bit
mode, the user first needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).

 1997 Microchip Technology Inc. DS30234D-page 99

PIC16C6X

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

11.5.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).

When an address is matched or the data transfer after
an address match is received, the hardware automati­cally will generate the acknowledge (A
then load the SSPBUF register with the received value
currently in the SSPSR register.

There are certain conditions that will cause the SSP
module not to give this A
(or both):

a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overflow bit SSPO V (SSPCON<6>) w as set

before the transfer was received.

In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 11-4 shows what happens when a data transfer
byte is received, given the status of bits BF and SSPO V.
The shaded cells show the condition where user soft­ware did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPBUF register while
bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the

2

I

C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param­eter #101.

11.5.1.1 ADDRESSING
Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condi­tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The

CK pulse. These are if either

CK) pulse, and

address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register.
b) The buffer full bit, BF is set.
c) An A
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

In 10-bit address mode, two address bytes need to be
received by the slav e (Figure 11-16). The fiv e Most Sig­nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W
specify a write so the slave device will receive the sec­ond address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follo ws, with steps 7- 9 for sla ve­transmitter:

1. Receive first (high) byte of Address (bits SSPIF,

2. Update the SSPADD register with second (low)

3. Read the SSPBUF register (clears bit BF) and

4. Receive second (low) byte of Address (bits

5. Update the SSPADD register with the first (high)

6. Read the SSPBUF register (clears bit BF) and

7. Receive repeated START condition.

8. Receive first (high) byte of Address (bits SSPIF

9. Read the SSPBUF register (clears bit BF) and

CK pulse is generated.

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse.

(SSPSTAT<2>) must

BF, and bit UA (SSPSTAT<1>) are set).

byte of Address (clears bit UA and releases the

SCL line).

clear flag bit SSPIF.

SSPIF, BF, and UA are set).

byte of Address, if match releases SCL line, this

will clear bit UA.

clear flag bit SSPIF.

and BF are set).

clear flag bit SSPIF.

TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

BF SSPOV

00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes

DS30234D-page 100  1997 Microchip Technology Inc.

SSPSR

→ SSPBUF

Generate A

CK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)