MICROCHIP PIC16C64X, PIC16C66X Technical data
查询PIC16C641-04/JW供应商
PIC16C64X & PIC16C66X
8-Bit EPROM Microcontrollers with Analog Comparators
Devices included in this data sheet:
• PIC16C641
• PIC16C642
• PIC16C661
• PIC16C662
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Device Program
Memory x14
Data
Memory x8
PIC16C641 2K 128
PIC16C642
4K 176
PIC16C661 2K 128
PIC16C662
4K 176
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• Up to 33 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(V
) module
REF
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/V
OSC1/CLKIN
OSC2/CLKOUT
REF
RA3/AN3
RA4/T0CKI
RA5
V
RC0
RC1
RC2
RC3
SS
1
2
3
PIC16C64X
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7
RC6
RC5
RC4
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/V
OSC1/CLKIN
OSC2/CLKOUT
REF
RA3/AN3
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
RC0
RC1
RC2
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
• Four user programmable ID locations
• Program Memory Parity Error checking circuitry
with Parity Error Reset (PER)
• CMOS Technology:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range: 3.0V to 6.0V
• Commercial, Industrial and Automotive
temperature ranges
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µ A typical @ 3.0V, 32 kHz
- < 1.0 µ A typical standby current @ 3.0V
40
39
38
37
36
PIC16C66X
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 1
PIC16C64X & PIC16C66X
Pin Diagrams (Cont.’d)
TQFP
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
37
36 3435
38
PIC16C66X
1819 20 212212 131415
1617
RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3
44 434241 40 39
1
2
3
4
5
SS
6
7
8
9
10
11
RC2
RC1
NC
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
OSC2/CLKOUT
OSC1/CLKIN
SS
V
VDD
RE2/CS
RE1/WR
RE0/RD
RA5
RA4/T0CKI
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
NC
NC
NC
RB7
RB6
RB5
RB4
RA3/AN3
RA2/AN2/VREF
RA1/AN1
654321
7
8
9
10
11
12
PIC16C66X
13
14
15
16
17
181920212223242526
RD0/PSP0
RC3
RC2
RC1
RA1/AN1
RA0/AN0
MCLR
/VPP
PLCC
/VPP
RA0/AN0
MCLR
NC
RB7
44
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RA3/AN3
RA2/AN2/V
REF
RB6
RB5
RB4
NC
40414243
39
38
37
36
35
34
33
32
31
30
29
2728
NC
RC6
RC5
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
DS30559A-page 2
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Table of Contents
1.0 General Description..........................................................................................................................................5
2.0 PIC16C64X & PIC16C66X Device Varieties ....................................................................................................7
3.0 Architectural Overview...................................................................................................................................... 9
4.0 Memory Organization .....................................................................................................................................17
5.0 I/O Ports..........................................................................................................................................................29
6.0 Timer0 Module................................................................................................................................................ 41
7.0 Comparator Module........................................................................................................................................47
8.0 Voltage Reference Module.............................................................................................................................53
9.0 Special Features of the CPU..........................................................................................................................55
10.0 Instruction Set Summary ................................................................................................................................73
11.0 Development Support.....................................................................................................................................87
12.0 Electrical Specifications..................................................................................................................................91
13.0 Device Characterization Information.............................................................................................................103
14.0 Packaging Information..................................................................................................................................105
Appendix A: Enhancements......................................................................................................................................115
Appendix B: Compatibility.........................................................................................................................................115
Appendix C: What’s New ..........................................................................................................................................116
Appendix D: What’s Changed...................................................................................................................................116
Appendix E: PIC16/17 Microcontrollers .....................................................................................................................117
Pin Compatibility .........................................................................................................................................................125
Index ...........................................................................................................................................................................127
List of Examples.......................................................................................................................................................... 129
List of Figures..............................................................................................................................................................129
List of Tables...............................................................................................................................................................130
On-Line Support..........................................................................................................................................................131
Reader Response.......................................................................................................................................................132
PIC16C64X & PIC16C66X Product Identification System..........................................................................................135
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 3
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 4
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
1.0 GENERAL DESCRIPTION
PIC16C64X & PIC16C66X devices are 28-pin and
40-pin EPROM-based members of the versatile
PIC16CXXX family of low-cost, high-performance,
CMOS, fully-static, 8-bit microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXXX family has
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single-cycle, except for program branches (which require
two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in its class.
The PIC16C641 has 128 bytes of RAM and the
PIC16C642 has 176 bytes of RAM. Both devices have
22 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, they have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers, threshold detectors, white goods
controllers, etc.).
The PIC16C661 has 128 bytes of RAM and the
PIC16C662 has 176 bytes of RAM. Both devices have
33 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. They also have an 8-bit Parallel
Slave Port. In addition, the devices have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers, threshold detectors, white goods
controllers, etc.).
PIC16CXXX devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and resets.
A highly reliable Watchdog Timer (WDT) with its own
on-chip RC oscillator provides protection against software lock-up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
The PIC16CXXX series fit perfectly in applications
ranging from battery chargers to low-power remote
sensors. The EPROM technology makes
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low-cost, low-power,
high-performance, ease of use, and I/O flexibility make
the PIC16C64X & PIC16C66X very versatile.
1.1 F
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to the
PIC16C64X & PIC16C66X (Appendix B).
1.2 De
PIC16C64X & PIC16C66X devices are supported by
the complete line of Microchip Development tools,
including:
• MPLAB Integrated Development Environment
including MPLAB-Simulator.
• MPASM Universal Assembler and MPLAB-C Universal C compiler.
• PRO MATE II and PICSTART Plus device programmers.
• PICMASTER In-circuit Emulator System
•
fuzzy
• DriveWay Visual Programming Tool
Please refer to Section 11.0 for more details about
these and other Microchip development tools.
amily and Upward Compatibility
velopment Support
TECH-MP Fuzzy Logic Development Tools
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 5
PIC16C64X & PIC16C66X
TABLE 1-1: PIC16C64X & PIC16C66X DEVICE FEATURES
Packages
Clock Memory Peripherals Features
Brown-out Reset
Voltage Range (Volts)
I/O Pins
Interrupt Sources
Parallel Slave Port
Internal Reference Voltage
Comparator(s)
Timer Module(s)
Program Memory
Data Memory (bytes)
EPROM
Maximum Frequency of Operation (MHz)
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
20 2K 128 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP
20 4K 176 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP
20 2K 128 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes
DS30559A-page 6
PIC16C641
PIC16C642
Preliminary
PIC16C661
PIC16C662 20 4K 176 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog T imer, selectable code protect, and high I/O current
capability.
All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
2.0 PIC16C64X & PIC16C66X
DEVICE V ARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in the Product Identification System page at the end of this data sheet. When placing
orders, please use that page of the data sheet to specify the correct part number.
2.1 UV Erasab
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
programmers both support programming of the
PIC16C64X & PIC16C66X.
2.2 One-Time-Pr
Devices
The availability of OTP devices is especially useful for
customers who need flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
le Devices
Plus and PRO MATE
ogrammable (OTP)
2.3 Quic
k-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the
OTP devices but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4 Serializ
Production (SQTP
II
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
ed Quick-Turnaround-
SM
vices
) De
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 7
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 8
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C64X &
PIC16C66X devices can be attributed to a number of
architectural features commonly found in RISC microprocessors. To begin with, the PIC16C64X &
PIC16C66X use a Harvard architecture in which program and data are accessed from separate memories
using separate buses. This improves bandwidth over
traditional von Neumann architecture where program
and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than an 8-bit wide data
word. Instruction opcodes are 14-bits wide making it
possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single cycle (200 ns @
20 MHz) except for program branches, which require
two cycles.
The PIC16C641 and PIC16C661 both address 2K x 14
on-chip program memory while the PIC16C642 and
PIC16C662 address 4K x 14. All program memory is
internal.
PIC16C64X & PIC16C66X devices can directly or indirectly address their register files or data memory. All
special function registers including the program
counter are mapped in the data memory. These
devices have an orthogonal (symmetrical) instruction
set that makes it possible to carry out any operation on
any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’
make programming with the PIC16C64X & PIC16C66X
simple yet efficient. In addition, the learning curve is
reduced significantly.
PIC16C64X & PIC16C66X devices contain an 8-bit
ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and
any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift, and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Bo
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
rrow and Digit Borrow out bit,
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 9
PIC16C64X & PIC16C66X
FIGURE 3-1: PIC16C641/642 BLOCK DIAGRAM
PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
Parity Error
MCLR
(13-bit)
Timer
Reset
Timer
Reset
Reset
VDD, VSS
RAM Bank
Select
7
Data Bus
RAM
File
Registers
Addr MUX
STATUS reg
3
ALU
W reg
9
8
FSR reg
MUX
8
Indirect
Addr
Voltage
Reference
Comparator
-
+
-
+
Timer0
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
DS30559A-page 10
Preliminary
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 3-2: PIC16C661/662 BLOCK DIAGRAM
PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
13
Program Counter
8 Level Stack
Direct Addr
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
Parity Error
MCLR
(13-bit)
Timer
Reset
Timer
Reset
Reset
VDD, VSS
RAM Bank
Select
7
RE0/RD
Data Bus
RAM
File
Registers
Addr MUX
STATUS reg
3
ALU
W reg
9
8
FSR reg
MUX
Parallel
Slave
Port
PORTE
8
Indirect
Addr
Voltage
Reference
Comparator
+
+
Timer0
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
1996 Microchip Technology Inc.
RE1/WR
RE2/CS
Preliminary
PORTD
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
DS30559A-page 11
PIC16C64X & PIC16C66X
TABLE 3-1: PIC16C641/642 PINOUT DESCRIPTION
Name Pin #
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN 9 I ST/CMOS Oscillator crystal input or external clock source input.
OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR
/V
PP
1 I/P ST Master clear (reset) input or programming voltage input. This pin is
an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 I/O ST Analog comparator input.
RA1/AN1 3 I/O ST Analog comparator input.
RA2/AN2/V
REF
4 I/O ST Analog comparator input or V
REF
output.
RA3/AN3 5 I/O ST Analog comparator input or comparator output.
RA4/T0CKI 6 I/O ST Can be selected to be the clock input to the Timer0 timer/counter
or a comparator output. Output is open drain type.
RA5 7 I/O ST
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/INT 21 I/O
TTL/ST
(1)
RB0 can also be selected as an external interrupt pin.
RB1 22 I/O TTL
RB2 23 I/O TTL
RB3 24 I/O TTL
RB4 25 I/O TTL Interrupt on change pin.
RB5 26 I/O TTL Interrupt on change pin.
RB6 27 I/O
RB7 28 I/O
TTL/ST
TTL/ST
(2)
(2)
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0 11 I/O ST
RC1 12 I/O ST
RC2 13 I/O ST
RC3 14 I/O ST
RC4 15 I/O ST
RC5 16 I/O ST
RC6 17 I/O ST
RC7 18 I/O ST
V
SS
V
DD
8,19 P — Ground reference for logic and I/O pins.
20 P — Positive supply for logic and I/O pins.
Legend: O = output I/O = input/output P = power
I = input — = not used ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS30559A-page 12
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 3-2: PIC16C661/662 PINOUT DESCRIPTION
Name
OSC1/CLKIN 13 30 14 I ST/CMOS Oscillator crystal input or external clock source
OSC2/CLKOUT 14 31 15 O — Oscillator crystal output. Connects to crystal or reso-
MCLR
/V
PP
RA0/AN0 2 19 3 I/O ST Analog comparator input.
RA1/AN1 3 20 4 I/O ST Analog comparator input.
RA2/AN2/V
RA3/AN3 5 22 6 I/O ST Analog comparator input or comparator output.
RA4/T0CKI 6 23 7 I/O ST Can be selected to be the clock input to the
RA5 7 24 8 I/O ST
RB0/INT 33 8 36 I/O
RB1 34 9 37 I/O TTL
RB2 35 10 38 I/O TTL
RB3 36 11 39 I/O TTL
RB4 37 14 41 I/O TTL Interrupt on change pin.
RB5 38 15 42 I/O TTL Interrupt on change pin.
RB6 39 16 43 I/O
RB7 40 17 44 I/O
RC0 15 32 16 I/O ST
RC1 16 35 18 I/O ST
RC2 17 36 19 I/O ST
RC3 18 37 20 I/O ST
RC4 23 42 25 I/O ST
RC5 24 43 26 I/O ST
RC6 25 44 27 I/O ST
RC7 26 1 29 I/O ST
Legend: O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
DIP
Pin #
REF
QFP
Pin #
1 18 2 I/P ST Master clear (reset) input or programming voltage
4 21 5 I/O ST Analog comparator input or V
I = input — = not used ST = Schmitt Trigger input
TTL = TTL input
PLCC
Pin #
I/O/P
Type
Buffer
Type
TTL/ST
TTL/ST
TTL/ST
Description
input.
nator in crystal oscillator mode. In RC mode, OSC2
pin outputs CLKOUT which has 1/4 the frequency of
OSC1, and denotes the instruction cycle rate.
input. This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
output.
REF
Timer0 timer/counter or a comparator output.
Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
(1)
(2)
(2)
RB0 can also be selected as an external
interrupt pin.
Interrupt on change pin. Serial programming
clock.
Interrupt on change pin. Serial programming
data.
PORTC is a bi-directional I/O port.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 13
PIC16C64X & PIC16C66X
Name
DIP
Pin #
QFP
Pin #
PLCC
Pin #
I/O/P
Type
Buffer
Type
Description
PORTD can be a bi-directional I/O port or parallel
slave port for interfacing to a microprocessor bus.
RD0/PSP0 19 38 21 I/O ST/TTL
RD1/PSP1 20 39 22 I/O ST/TTL
RD2/PSP2 21 40 23 I/O ST/TTL
RD3/PSP3 22 41 24 I/O ST/TTL
RD4/PSP4 27 2 30 I/O ST/TTL
RD5/PSP5 28 3 31 I/O ST/TTL
RD6/PSP6 29 4 32 I/O ST/TTL
RD7/PSP7 30 5 33 I/O ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PORTE is a bi-directional I/O port.
RE0/RD
RE1/WR
RE2/CS
V
SS
V
DD
8 25 9 I/O ST/TTL
9 26 10 I/O ST/TTL
10 27 11 I/O ST/TTL
12,31 6,29 13,34 P — Ground reference for logic and I/O pins.
11,32 7,28 12,35 P — Positive supply for logic and I/O pins.
NC — 12,13,
33,34
1,17
28,40
— — Not Connected.
(3)
(3)
(3)
RE0/RD
read control for parallel slave port.
RE1/WR write control for parallel slave port.
RE2/CS
select control for parallel slave port.
Legend: O = output I/O = input/output P = power
I = input — = not used ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
DS30559A-page 14
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.1 Cloc
king Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3.
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q1
3.2 Instruction Flo
w/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO )
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Execute INST (PC) Fetch INST (PC+2)
Q2 Q3 Q4
Q1
Execute INST (PC+1)
Internal
phase
clock
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1996 Microchip Technology Inc.
Fetch 1 Execute 1
Fetch 2 Execute 2
Preliminary
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
DS30559A-page 15
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 16
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.0 MEMORY ORGANIZATION
4.1 Pr
The PIC16C64X & PIC16C66X have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16C641 and PIC16C661
only the first 2K x 14 (0000h - 07FFh) is physically
implemented. For the PIC16C642 and PIC16C662 only
the first 4K x 14 (0000h - 0FFh) is physically implemented. Accessing a location above the 2K or 4K
boundary will cause a wrap-around. The reset vector is
at 0000h and the interrupt vector is at 0004h (Figure 41 and Figure 4-2). See Section 4.4 for Program Memory paging.
FIGURE 4-1: PIC16C641/661 PROGRAM
CALL, RETURN
RETFIE, RETLW
ogram Memory Organization
MEMORY MAP AND STACK
PC<12:0>
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
FIGURE 4-2: PIC16C642/662 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
Page0
User Memory Space
On-chip Program
Memory
Page1
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
Interrupt Vector
User Memory Space
On-chip Program
Memory
TEST
Configuration Word
TEST
0004h
0005h
07FFh
0800h
1FFFh
2000h
2007h
3FFFh
TEST
Configuration Word
TEST
1FFFh
2000h
2007h
3FFFh
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 17
PIC16C64X & PIC16C66X
4.2 D
The data memory (Figure 4-4) is partitioned into two
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when
bit RP0 (STATUS<5>) is cleared. Bank 1 is selected
when the RP0 bit is set. The Special Function Registers are located in the first 32 locations of each Bank.
Register locations A0h-EFh (Bank 1) are general purpose registers implemented as static RAM. Some special function registers are mapped in Bank 1.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 176 x 8 for the
PIC16C642/662, and 128 x8 for the PIC16C641/661.
Each is accessed either directly, or indirectly through
the File Select Register FSR (Section 4.5).
ata Memory Organization
FIGURE 4-3: PIC16C641/661 DATA
MEMORY MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
CMCON
General
Purpose
Register
(1)
(2)
(2)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PCON
VRCON
General
Purpose
Register
(1)
(2)
(2)
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
DS30559A-page 18
Preliminary
Mapped
7Fh
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Not implemented on the PIC16C641.
Bank 0 Bank 1
in Page 0
1996 Microchip Technology Inc.
EFh
F0h
FFh
PIC16C64X & PIC16C66X
FIGURE 4-4: PIC16C642/662 DATA
MEMORY MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC TRISC
PORTD
PORTE
(2)
(2)
PCLATH
INTCON
PIR1
CMCON
(1)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISD
TRISE
PCLATH
INTCON
PIE1
PCON
VRCON
(2)
(2)
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
4.2.2 SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral Modules for controlling the desired
operation of the device (T able 4-1). These registers are
static RAM.
The special function registers can be classified into two
sets (core and peripheral). The special function registers associated with the “core” functions are described
in this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
General
Purpose
Register
in Bank 0
7Fh
Note 1: Not a physical register.
1996 Microchip Technology Inc.
Bank 0 Bank 1
Unimplemented data memory loca-
tions, read as '0'.
2: Not implemented on the PIC16C642.
General
Purpose
Register
Mapped
EFh
F0h
FFh
Preliminary
DS30559A-page 19
PIC16C64X & PIC16C66X
TABLE 4-1: SPECIAL FUNCTION REGISTERS
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register
02h PCL Program Counter's (PC) Least Significant Byte
03h STATUS IRP
04h FSR Indirect data memory address pointer
05h PORTA
06h PORTB PORTB Data Latch when written: PORTB pins when read
06h PORTC PORTC Data Latch when written: PORTC pins when read
06h PORTD
06h PORTE
0Ah PCLATH
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
0Ch PIR1 PSPIF
0Dh-1Eh
1Fh CMCON C2OUT C1OUT
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION RBPU
82h PCL Program Counter's (PC) Least Significant Byte
83h STATUS IRP
84h FSR Indirect data memory address pointer
85h TRISA
86h TRISB PORTB Data Direction Register
86h TRISC PORTC Data Direction Register
86h TRISD
86h TRISE
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
8Ch PIE1 PSPIE
8Dh
8Eh PCON MPEEN
8Fh-9Eh
9Fh VRCON VREN VROE VRR
Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR
2: The IRP and RP1 bits are reserved, always maintain these bits clear.
3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.
4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
(3)
(3)
Unimplemented
(3)
(3)
Unimplemented
Unimplemented
(2)
— — PORTA Data Latch when written: PORTA pins when read
PORTD Data Latch when written: PORTD pins when read
—
— — — Write buffer for upper 5 bits of program counter
(4)
(2)
— — PORTA Data Direction Register
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
— — — Write buffer for upper 5 bits of program counter
(4)
(2)
RP1
— — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
CMIF
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
RP1
CMIE
— — — — PER POR BOR
RP0 T
— — — — — — 00-- ---- 00-- ----
— — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
(2)
RP0 TO PD ZDCC
— — — — — — 00-- ---- 00-- ----
Reset and Watchdog Timer Reset during normal operation.
O PD ZDCC
— TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
— VR3 VR2 VR1 VR0 000- 0000 000- 0000
POR,
BOR,
PER
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx 0000 --xu 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
---0 0000 ---0 0000
—
u--- -qqq u--- -uuu
—
Value on
all other
resets
—
—
—
(1)
DS30559A-page 20
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
11
10
01
00
4.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 4-5, contains
the arithmetic status of the ALU, the RESET status, and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
O and PD bits are not
It is recommended, therefore, that only BCF, BSF,
SWAPF, and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary.”
Note 1: The IRP and RP1 bits (ST A TUS<7:6>) are
reserved on the PIC16C64X &
PIC16C66X and should be maintained
clear. Use of these bits as general purpose R/W bits is NOT recommended,
since this may affect upward compatibility
with future products.
Note 2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
FIGURE 4-5: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.
bit 6-5: RP1:RP0 : Register Bank Select bits (used for direct addressing)
= Bank 3 (180h - 1FFh)
= Bank 2 (100h - 17Fh)
= Bank 1 (80h - FFh)
= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit
clear.
bit 4: T
bit 3: PD
bit 2: Z: Zero bit
bit 1: DC: Digit carry/borrow
bit 0: C: Carry/borrow
O
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF , ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF , ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
the polarity is reversed. A subtraction is executed by adding the two’s complement of the
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 21
PIC16C64X & PIC16C66X
4.2.2.2 OPTION REGISTER
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-6: OPTION REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit7 bit0
bit 7: RBPU
bit 6: INTEDG: Interrupt Edge Select bit
bit 5: T0CS: TMR0 Clock Source Select bit
bit 4: T0SE: TMR0 Source Edge Select bit
bit 3: PSA: Prescaler Assignment bit
bit 2-0: PS2:PS0: Prescaler Rate Select bits
INTEDG T0CS T0SE PSA PS2 PS1 PS0 R= Readable bit
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT.
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
DS30559A-page 22 Preliminary 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.3 INTCON REGISTER
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all non-peripheral interrupt sources.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-7: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R= Readable bit
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt)
0 = None of the RB7:RB4 pins have changed state
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
1996 Microchip Technology Inc. Preliminary DS30559A-page 23
PIC16C64X & PIC16C66X
4.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-8: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
(1)
PSPIE
bit7 bit0
bit 7: PSPIE
bit 6: CMIE: Comparator Interrupt Enable bit
bit 5-0: Unimplemented: Read as '0'
CMIE — — — — — — R= Readable bit
(1)
: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.
DS30559A-page 24 Preliminary 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
comparator and Parallel Slave Port interrupts.
Note: Interrupt flag bits get set when an interrupt
FIGURE 4-9: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
(1)
PSPIF
bit7 bit0
bit 7: PSPIF
bit 6: CMIF: Comparator Interrupt Flag bit
bit 5-0: Unimplemented: Read as '0'
CMIF — — — — — — R= Readable bit
(1)
: Parallel Slave Port Interrupt Flag bit
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.
1996 Microchip Technology Inc. Preliminary DS30559A-page 25
PIC16C64X & PIC16C66X
4.2.2.6 PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset (POR), an external MCLR
reset, WDT reset, Brown-out Reset (BOR), and Parity
Error Reset (PER). The PCON register also contains a
status bit, MPEEN, which reflects the value of the
MPEEN bit in Configuration Word. See Table 9-4 for
status of these bits on various resets.
Note: BOR is unknown on Power-on Reset. It
FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)
R-U U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-u
MPEEN
bit7 bit0
bit 7: MPEEN: Memory Parity Error Circuitry Status bit
bit 6-3: Unimplemented: Read as '0'
bit 2: PER
bit 1: POR
bit 0: BOR
— — — —PER POR BOR R= Readable bit
Reflects the value of Configuration Word bit, MPEEN
: Memory Parity Error Reset Status bit
1 = No error occurred
0 = Program memory fetch parity error occurred
(must be set in software after a Parity Error Reset occurs)
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
must then be set by the user and checked
on subsequent resets to see if BOR
cleared, indicating a brown-out has
occurred. The BOR
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
programming the BODEN bit in the
Configuration word).
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
status bit is a “don't
is
DS30559A-page 26 Preliminary 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is readable and
writable. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-11 shows the two
situations for the loading of the PC. The upper example
in the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-11: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note
“Implementing a Table Read”
(AN556).
8
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
4.3.2 STACK
PIC16C64X & PIC16C66X devices have an 8 level
deep x 13-bit wide hardware stack (Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
4.4 Program Memory Paging
PIC16C642 and PIC16C662 devices have 4K of program memory, but the CALL and GOTO instructions only
have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow CALL and GOTO instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program memory page. This paging bit comes from the PCLATH<3>
bit (Figure 4-11). When doing a CALL or GOTO instruction, the user must ensure that this page select bit
(PCLATH<3>) is programmed so that the desired program memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire
13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the
return instructions (which POPs the address from the
stack).
Note: The PIC16C64X & PIC16C66X ignore the
PCLATH<4> bit, which is used for program
memory pages 2 and 3 (1000h - 1FFFh).
The use of PCLATH<4> as a general purpose read/write bit is not recommended
since this may affect upward compatibility
with future products.
1996 Microchip Technology Inc. Preliminary DS30559A-page 27
PIC16C64X & PIC16C66X
4.5 Indirect Addressing, INDF, and FSR
Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-12. However, bit IRP is not used in
the PIC16C64X & PIC16C66X.
FIGURE 4-12: DIRECT/INDIRECT ADDRESSING
(1)
RP1 RP0 6
bank select location select
from opcode
00h
0
00 01 10 11
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no goto next
;yes continue
CONTINUE:
Indirect AddressingDirect Addressing
(1)
IRP
bank select
00h
7
FSR register
location select
0
Data
not used
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
For memory map detail see Figure 4-3 and Figure 4-4.
Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.
7Fh
DS30559A-page 28 Preliminary 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.0 I/O PORTS
The PIC16C641 and PIC16C642 have three ports,
PORTA, PORTB, and PORTC. PIC16C661 and
PIC16C662 devices have five ports, PORTA through
PORTE. Some pins for these I/O ports are multiplexed
with alternate functions for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
5.1 POR
PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Pin RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control) register. When selected as
comparator inputs, these pins will read as '0's.
TA and TRISA Registers
FIGURE 5-1: BLOCK DIAGRAM OF
RA1:RA0 PINS
Data
bus
WR
Port
Data Latch
WR
TRIS
TRIS Latch
RD PORT
To Comparator
Note: I/O pins have protection diodes to VDD and VSS.
Note: On reset, the TRISA register is set to all
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the V
a very hi-impedance output. The user must set the
TRISA<2> bit and use hi-impedance loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
QD
VDD
CK
Q
QD
CK
Q
Analog
Input Mode
Schmitt Trigger
RD TRIS
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
P
N
VSS
Input Buffer
DQ
EN
I/O Pin
pin is
REF
1996 Microchip Technology Inc.
EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA ;Initialize PORTA by
;clearing output latches
MOVLW 0x07 ;Turn comparators off,
MOVWF CMCON ;enable pins for I/O
BSF STATUS, RP0 ;Select bank1
MOVLW 0x1F ;Value to initialize
;data direction
MOVWF TRISA ;Set RA<4:0> as inputs
;TRISA<7:5> are clear
Preliminary
DS30559A-page 29
PIC16C64X & PIC16C66X
FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN
Data
bus
WR
Port
Data Latch
WR
TRIS
TRIS Latch
CK
CK
RD TRIS
QD
Q
QD
Q
Analog
Input Mode
Schmitt Trigger
Input Buffer
EN
VDD
P
N
VSS
DQ
RA2 Pin
RD PORT
To Comparator
VROE
VREF
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN
Data
bus
WR
Port
WR
TRIS
CK
Data Latch
CK
TRIS Latch
RD TRIS
QD
Comparator Output
Q
QD
Q
Comparator Mode = 110
Analog
Input Mode
Schmitt Trigger
Input Buffer
VDD
P
N
VSS
RA3 Pin
RD PORT
To Comparator
DS30559A-page 30
Preliminary
DQ
EN
1996 Microchip Technology Inc.
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