MICROCHIP PIC16C63A, PIC16C65B, PIC16C73B, PIC16C74B User Manual
PIC16C63A/65B/73B/74B
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
• PIC16C63A • PIC16C73B
• PIC16C65B • PIC16C74B
PIC16CXX Microcontroller Core Feature s:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4 K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power-saving SLEEP mode
• Selectable oscillator options
• Low power, high speed CMOS EPROM
technology
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Automotive
temperature ranges
• Low power consumption:
- < 5 mA @ 5V, 4 MHz
-23 µA typical @ 3V, 32 kHz
-< 1.2 µA typical standby current
Devices
I/O
Pins
PIC16C63A 22 - No 10
PIC16C65B 33 - Yes 11
PIC16C73B 22 5 No 11
PIC16C74B 33 8 Yes 12
A/D
Chan.
PSP Interrupts
PIC16C7X Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM mo dul es
- Capture is 16-bit, max. resolution is 200 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit multichannel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI
2
TM
C
and I
TM
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide with
external RD
, WR and CS controls
• Brown-out detection circuitr y for Brow n -out Reset
(BOR)
Pin Diagram:
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
RE1/WR
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF
RA4/T0CKI
/AN4
RA5/SS
RE0/RD
/AN5
/AN6
RE2/CS
/AN7
V
VSS
OSC1/CLKIN
RC2/CCP1
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
DD
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
PIC16C65B
PIC16C74B
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
DD
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
2000 Microchip Technology Inc. DS30605C-page 1
PIC16C63A/65B/73B/74B
SDIP, SOIC, Windowed CERDIP
PLCC
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3/AN3/VREF
RA2/AN2
65432
7
8
9
10
PIC16C65B
11
12
PIC16C74B
13
14
15
16
17
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF
RA4/T0CKI
RA5/SS/AN4
V
RC2/CCP1
/VPP
NC
RA1/AN1
RA0/AN0
MCLR
RB7
RB6
RB5
RB4
NC
1
4443424140
39
38
37
36
35
34
33
32
31
30
29
2827262524232221201918
SS
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
RB3
RB2
RB1
RB0/INT
DD
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
PIC16C63A
PIC16C73B
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MQFP
TQFP
V
VDD
RB0/INT
RB1
RB2
RB3
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
SS
DD
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
4443424140393837363534
1
2
3
4
5
PIC16C65B
6
7
PIC16C74B
8
9
10
11
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
33
32
31
30
29
28
27
26
25
24
23
2221201918171615141312
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
NC
NC
RB5
RB4
RB6
RB7
/VPP
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
RA3/AN3/VREF
RC2/CCP1
RC3/SCK/SCL
RD1/PSP1
RD0/PSP0
RD3/PSP3
RD2/PSP2
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
RC1/T1OSI/CCP2
Key Features
PICmicro™ Mid-Range MCU Family
PIC16C63A PIC16C65B PIC16C73B PIC16C74B
Reference Manual (DS33023)
Program Memory (EPROM) x 14 4 K 4 K 4 K 4 K
Data Memory (Bytes) x 8 192 192 192 192
Pins 28 40 28 40
Parallel Slave Port — Yes — Yes
Capture/Compare/PWM Modules 2 2 2 2
Timer Modules 3 3 3 3
A/D Channels —— 58
2
Serial Communication SPI/I
C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART
In-Circuit Serial Programming Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes
Interrupt Sources 10 11 11 12
Packages 28-pin SDIP, SOIC,
SSOP,
Windowed CERDIP
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed CERDIP
28-pin SDIP, SOIC,
SSOP,
Windowed CERDIP
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed CERDIP
DS30605C-page 2 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Table of Contents
1.0 General Description............................................................................ ....... .... .. .... .. .... ...................................................................5
2.0 PIC16C63A/65B/7 3 B/74B Device Varieties................................................................................................................................. 7
3.0 Architectural Overview................................................................................................................................................................. 9
4.0 Memory Organization.................................................................................................................................................................15
5.0 I/O Ports................ ..................................... ...................................... ..........................................................................................29
6.0 Timer0 Module ........................................................................................................................................................................... 39
7.0 Timer1 Module ........................................................................................................................................................................... 43
8.0 Timer2 Module ........................................................................................................................................................................... 47
9.0 Capture/Compare/PWM Modules ............................................................... .... .... .. .... ....... .... .... .. ................................................ 49
10.0 Synchronous Serial Port (SSP) Module .....................................................................................................................................55
11.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )................................................................ 65
12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79
13.0 Special Features of the CPU...................................................................................................................................................... 85
14.0 Instruction Set Summary............................................................................................................................................................ 99
15.0 Development Support............................................................................................................................................................... 107
16.0 Electrical Characteristics.......................................................................................................................................................... 113
17.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................139
18.0 Packaging Information. ............................................................... ...................................... ........................................................ 153
Appendix A: Revision History ........................................................................................................................................................ 165
Appendix B: Device Differences...................................................................................... ....... .... ....................................................165
Appendix C: Device Migrations - PIC16C63/65A/73A/74A → PIC16C63A/65B/73B/74B .............................................................166
Appendix D: Migration from Baseline to Mid-Range Devices......................................................................................................... 168
On-Line Support................................................................................................................................................................................. 175
Reader Response.............................................................................................................................................................................. 176
Product Identification System............................................................................................................................................................ 177
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2000 Microchip Technology Inc. DS30605C-page 3
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 4 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
1.0 GENERAL DESCRIPTION
The PIC16C63A/65B/73B/74B devices are low cost,
high performance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX mid-range family.
®
All PICmicro
RISC architecture. The PIC16CXX microcontroller
family has enhanced core features, eight-level deep
stack and multiple internal and external interrupt
sources. The separate instruction and data buses of
the Harvard architecture allow a 14- bit w ide ins truc tio n
word with the separate 8-bit wide data. The two stage
instruction pipeline allows all instructions to execute in
a single cycle, except for program branches, which
require two cycles. A total of 35 instructions (reduced
instruction set) are available. Additionally, a large register set gives some of the architectural innovations
used to achieve a very high performance.
The PIC16C63A/73B devices have 22 I/O pins. The
PIC16C65B/74B devices have 33 I/O pins. Each
device has 192 bytes of RAM. In addition, several
peripheral features ar e available, includi ng: three timer/
counters, two Capture/Compare/PWM modules, and
two serial ports. The Synchronous Serial Port (SSP)
can be configured as either a 3-wire Serial Peripheral
Interface (SPI) or the two-wire Inter-Integrated Circuit
2
C) bus. The Universal Synchronous Asynchronous
(I
Receiver Transmitter (USART) is also known as the
Serial Communications Interface or SCI. Also, a 5channel high speed 8-bit A/D is provided on the
PIC16C73B, while the PIC16C74B offers 8 channels.
The 8-bit resolution is ideally suited for applications
requiring low cost analog interface, e.g., thermostat
control, pressure sensing, etc.
The PIC16C63A/65B/73B/74B devices have special
features to reduce ex ternal com ponent s, th us redu cing
cost, enhancing system reliability and reducing power
consumption. Th ere are four osci llator options, of which
the single pin RC oscillator prov ides a low cost s olution,
the LP oscillator minimizes power consumption, XT is
a standard crystal, and the HS is for high speed crystals. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake-up the chip
from SLEEP through several external and internal
interrupts and RESETS.
microcontrollers employ an advanced
A highly reliable Watchdog Timer (WDT), with its own
on-chip RC oscillator, provides protection against software lockup, and also provides one way of waking the
device from SLEEP.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost effective One-TimeProgrammable (OTP) versi on is suit a ble for pro duction
in any volume.
The PIC16C63A/65B/73B/74B devices fit nicely in
many applications ranging from security and remote
sensors to appliance control and automotive. The
EPROM technology makes customization of application programs (transmitter codes, motor speeds,
receiver frequencies, etc.) extremely fast and convenient. The small foo tprint p acka ges ma ke this microcontroller series perfect for all applications with space
limitations. Low cost, low power, high performance,
ease of use and I/O flexibility make the PIC16C63A/
65B/73B/74B devices very versatile, even in areas
where no microcontroller use has been considered
before (e.g., timer functions, serial communication,
capture and compar e, PWM functions and copro cessor
applications).
1.1 Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendi x A f or
a detailed list of enhancements. Code written for the
PIC16C5X can be easily po rted to th e PIC 16 CXX fam ily of devices (Appendix B).
1.2 Development Support
PICmicro® devices are supported by the complete line
of Microchip Develo pme nt tool s.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
2000 Microchip Technology Inc. DS30605C-page 5
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 6 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.0 PIC16C63A/65B/73B/74B DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depen ding on applicati on and production
requirements, t he proper devic e option can be s elected
using the information in the PIC16C63A/65B/73B/74B
Product Identification Sys tem sectio n at the end of this
data sheet. When placing orders, please use that page
of the data sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1. C, as in PIC16C74. These devices have
EPROM type memory and operate over the
standard voltage range.
2. LC, as in PIC16LC74. These devices have
EPROM type memory and operate over an
extended voltage range.
2.1 UV Erasable Devices
The UV erasable vers ion, offered i n windowed CERDIP
packages, is optimal for prototype development and
pilot programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
programmers both support programming of the
PIC16C63A/65B/73B/74B.
Plus and PRO MATEII
2.3 Quick-Turnaround-Production (QTP) Devices
Microchip o ffers a QTP Progr amming Servic e for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The device s are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are ava il abl e. Plea se co ntact your local
Microchip Technology sales office for more details.
2.4 Serialized Quick-Turnaround
Production (SQTP
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with dif ferent ser ial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
SM
) Devices
2.2 One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devic es, packaged in plas tic packag es, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
2000 Microchip Technology Inc. DS30605C-page 7
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 8 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture, in which
program and data are fetched from the same memory
using the same bus. Separating program and data
buses furthe r all ow s inst r uct i on s to be si ze d diffe ren t ly
than the 8-bit wide data word. Instruction opcodes are
14-bits wide, making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions (Example 3-1). Consequently, most
instructions execute in a single cycle (200 ns @
20 MHz) except for program branches.
All devices covered by this data sheet contain
4K x 14-bit program memory and 192 x 8-bit data
memory.
The PIC16CXX can directly, or indirectly, address its
register files or dat a memory. All Special Funct ion Registers, including the program counter, are mapped in
the data memory. The PIC16CXX has an orthogonal
(symmetrica l) instruct ion set that m akes it possib le to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16CXX simple yet effic ient. In addi tion, the learnin g
curve is reduced significantly.
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit workin g register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the ST ATUS register. The C and DC bits
operate as a borrow
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
bit and a digit borrow out bit,
2000 Microchip Technology Inc. DS30605C-page 9
PIC16C63A/65B/73B/74B
FIGURE 3-1: PIC16C63A/65B/73B/74B BLOCK DIAGRAM
13
Program Counter
EPROM
Program
Memory
Program
OSC1/CLKIN
OSC2/CLKOUT
Timer0 Timer1 Timer2
Bus
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
Direct Addr
8
MCLR
8 Level Stack
(13-bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD, VSS
RAM Addr
7
Data Bus
RAM
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
Parallel Slave Port
9
Indirect
8
Addr
FSR reg
STATUS reg
MUX
(3)
(2)
A/D
8
PORTA
PORTB
PORTC
PORTD
PORTE
(2)
RA0/AN0
(2)
RA1/AN1
(2)
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
(3)
(3)
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD
RE1/WR/AN6
RE2/CS/AN7
/AN4
/AN5
(2)
(2)
(2,3)
(2,3)
(2,3)
CCP1 CCP2
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: A/D is not available on the PIC16C63A/65B.
3: PSP and Ports D and E are not available on PIC16C63A/73B.
DS30605C-page 10 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION
Pin Name
DIP
Pin#
OSC1/CLKIN 9 9 I ST/CMOS
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
/VPP 1 1 I/P ST Master clear (RESET) input or programming voltage input.
MCLR
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
(4)
(4)
(4)
(4)
REF
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
RA5/SS/AN4
(4)
RB0/INT 21 21 I/O TTL/ST
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6 27 27 I/O TTL/ST
RB7 28 28 I/O TTL/ST
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
RC1/T1OSI/CCP2 12 12 I/O S T RC1 can also be the Timer1 oscillator input or Capture2
RC2/CCP1 13 13 I/O S T RC2 can also be the Capture1 input/Compare1
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O S T RC6 can also be the USART Asynchronous Transmit
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive
SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
DD 20 20 P — Positive supply for logic and I/O pins.
V
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: A/D module is not available in the PIC16C63A.
SOIC
Pin#
I/O/P
Type
Buffer
Type
Description
(3)
Oscillator crystal input/external clock source input.
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
2 2 I/O TTL RA0 can also be analog input 0
3 3 I/O TTL RA1 can also be analog input 1
4 4 I/O TTL RA2 can also be analog input 2
5 5 I/O TTL RA3 can also be analog input 3 or analog reference
voltage
(4)
.
(4)
.
(4)
.
(4)
.
Output is open drain type.
7 7 I/O TTL RA5 can also be analog input 4
(4)
or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Serial programming clock.
Interrupt-on-change pin. Serial programming data.
PORTC is a bi-directional I/O port.
clock input.
input/Compare2 output/PWM2 output.
output/PWM1 output.
2
2
C mode).
C modes.
for both SPI and I
data I/O (I
or Synchronous Clock.
or Synchronous Data.
2000 Microchip Technology Inc. DS30605C-page 11
PIC16C63A/65B/73B/74B
TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION
DIP
Pin Name
Pin#
PLCC
Pin#
OSC1/CLKIN 13 14 30 I ST/CMOS
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input.
MCLR
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
(5)
(5)
(5)
(5)
REF
2 3 19 I/O TTL RA0 can also be analog input 0
3 4 20 I/O TTL RA1 can also be analog input 1
4 5 21 I/O TTL RA2 can also be analog input 2
5 6 22 I/O TTL RA3 can also be analog input 3 or analog reference
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
/AN4
(5)
7 8 24 I/O TTL RA5 can also be analog input 4
RA5/SS
RB0/INT 33 36 8 I/O TTL/ST
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt-on-change pin.
RB5 38 42 15 I/O TTL Interrupt-on-change pin.
RB6 39 43 16 I/O TTL/ST
RB7 40 44 17 I/O TTL/ST
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
TQFP
MQFP
Pin#
I/O/P
Type
Buffer
Type
Description
(4)
Oscillator crystal input/external clock source input.
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
(5)
.
(5)
.
(5)
.
(5)
voltage
.
counter. Output is open drain type.
(5)
or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Serial programming clock.
Interrupt-on-change pin. Serial programming data.
DS30605C-page 12 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
Pin#
PLCC
Pin#
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
RD0/PSP0 19 21 38 I/O ST/TTL
RD1/PSP1 20 22 39 I/O ST/TTL
RD2/PSP2 21 23 40 I/O ST/TTL
RD3/PSP3 22 24 41 I/O ST/TTL
RD4/PSP4 27 30 2 I/O ST/TTL
RD5/PSP5 28 31 3 I/O ST/TTL
RD6/PSP6 29 32 4 I/O ST/TTL
RD7/PSP7 30 33 5 I/O ST/TTL
(5)
/AN5
RE0/RD
(5)
RE1/WR
RE2/CS
V
V
/AN6
(5)
/AN7
SS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
8925I/OST/TTL
91026I/OST/TTL
10 11 27 I/O ST/TTL
NC — 1,17,28,4012,13,
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
TQFP
MQFP
Pin#
33,34
I/O/P
Type
Buffer
Type
Description
PORTC is a bi-directional I/O port.
Timer1 clock input.
input/Compare2 output/PWM2 output.
PWM1 output.
output for both SPI and I
data I/O (I
2
C mode).
2
C modes.
(SPI mode).
Synchronous Clock.
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0 can also be read control for the parallel slave port,
or analog input 5
RE1 can also be write control for the parallel slave port,
or analog input 6
RE2 can also be select control for the parallel slave
port, or analog input 7
(5)
.
(5)
.
(5)
.
— These pins are not internally connected. These pins should
be left unconnected.
2000 Microchip Technology Inc. DS30605C-page 13
PIC16C63A/65B/73B/74B
3.1 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q1
Execute INST (PC) Fetch INST (PC+2)
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruc tio n fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are req uired to c omplete the ins truction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cy cle, the fetched instruction i s latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Q2 Q3 Q4
Q1
Execute INST (PC+1)
Internal
phase
clock
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruc tion is
“flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS30605C-page 14 2000 Microchip Technology Inc.
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16C63A/65B/73B/74B
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1: PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 8
13
4.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks con t ai n SFR s. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
Note: Maintain the IRP and RP1 bits clear in
these devices.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be acces sed either directly, or indirectly, through the File Select Register (FSR)
(Section 4.5).
RESET Vector
Interrupt Vector
On-chip Program
Space
User Memory
Memory (Page 0)
On-chip Program
Memory (Page 1)
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
2000 Microchip Technology Inc. DS30605C-page 15
PIC16C63A/65B/73B/74B
FIGURE 4-2: REGISTER FILE MAP 4.2.2 SPECIAL FUNCTION REGISTERS
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
(2)
(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
(3)
ADCON0
OPTION_REG
(3)
(1)
INDF
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
20h A0h
(2)
(2)
(3)
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associated with the “core” fun ction s are des cribe d in this section, and those related to the operation o f the peripheral
features are described in the section of that peripheral
feature.
General
Purpose
Register
7Fh
General
Purpose
Register
FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
DS30605C-page 16 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h PCL
03h STATUS
04h FSR
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h PORTD
09h PORTE
0Ah PCLATH
0Bh INTCON
0Ch PIR1 PSPIF
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data register 0000 0000 0000 0000
1Ah RCREG USART Receive Data register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES
1Fh ADCON0
(4)
(4)
(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
(5)
(5)
(1,4)
(4)
(6)
(6)
(2)
IRP
Indirect data memory address pointer xxxx xxxx uuuu uuuu
PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
— — — W rite Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(5)
A/D Result register xxxx xxxx uuuu uuuu
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
RP1
ADIF
(2)
RP0 TO PD ZDCC0001 1xxx 000q quuu
(6)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
Value on:
POR, BOR
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RES ETS include external RESET through MCLR
and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
Value on
all other
RESETS
(3)
2000 Microchip Technology Inc. DS30605C-page 17
PIC16C63A/65B/73B/74B
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
80h INDF
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL
83h STATUS
84h FSR
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction register 1111 1111 1111 1111
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
88h TRISD
89h TRISE
8Ah PCLATH
8Bh INTCON
8Ch PIE1 PSPIE
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Pe riod register
93h SSPADD Synchronous Serial Port (I2C mode) Address register 0000 0000 0000 0000
94h SSPSTAT — — D/A PSR/WUA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG Baud Rate Generator register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1
(4)
(4)
(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
(4)
(5)
(5)
(1,4)
(4)
(6)
(2)
IRP
Indirect data memory address pointer xxxx xxxx uuuu uuuu
PORTD Data Direction register 1111 1111 1111 1111
IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
(5)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
RP1
ADIE
(2)
RP0 TO PD ZDCC0001 1xxx 000q quuu
(6)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
— BRGH TRMT TX9D 0000 -010 0000 -010
Value on:
POR, BOR
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
Value on
all other
RESETS
(3)
DS30605C-page 18 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.1 STATUS Register
The STATUS register, shown in Register 4-1, contains
the arithmetic st atus of th e ALU, the RE SET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other r egister. If the STATUS register is the destination for an instruction that affects the Z,
DC or C bits, then the write to thes e three bits is disabled.
These bits are set or cleared according to the device
logic. Furt her mo r e, th e TO
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. Thi s leaves th e STATUS register
as 000u u1uu (where u = unchanged).
and PD bits are not writable.
It is recommended that only BCF, BSF, SWAPF and
MOVWF instructions be used to alter the STATUS register. The se in structions do not affec t the Z, C or DC bits
in the STATUS register . For other i nstruction s whic h do
not affect status bits, see the "Instruction Set Summary."
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>), maintain these bits
clear to ensure upward comp atib il ity w i th
future products.
2: The C and DC bits operate a s borrow
digit borrow
tion. See the SUBLW and SUBWF instructions for examples.
REGISTER 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
(1)
IRP
bit 7 bit 0
bit 7 IRP
bit 6-5 RP1
bit 4 TO
bit 3 PD: Power-down bit
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
bit 0 C
(1)
: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
(1)
:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
(2)
: Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result oc curred
RP1
(1)
RP0 TO PD Z DC C
and
bits, respectively, in subtrac-
(2)
Note 1: Maintain the IRP and RP1 bits clear.
2: For borrow
adding the two’s complement of the s econd operand. For rotate (RRF,RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. DS30605C-page 19
and digit borrow, the polarity is reversed. A subtraction is executed by
PIC16C63A/65B/73B/74B
4.2.2.2 OPTION Register
The OPTION_REG register is a readable and writable
register , which cont ains various contr ol bits to conf igure
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the watchdog timer.
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit 7 bit 0
bit 7 RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
INTEDG T0CS T0SE PSA PS2 PS1 PS0
: PORTB Pull-up Enable bit
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30605C-page 20 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.3 INTCON Register
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
Note: Interrupt flag bits are se t w he n an in terru pt
condition occurs, re gardless of the sta te of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt
REGISTER 4-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE:
bit 6 PEIE: Peripheral Interrupt Enable bit
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
bit 4 INTE: RB0/INT External Interrupt Enable bit
bit 3 RBIE: RB Port Change Interrupt Enable bit
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
bit 1 INTF: RB0/INT External Interrupt Flag bit
bit 0 RBIF: RB Port Change Interrupt Flag bit
Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
1 = At least one of the RB7:RB4 pins changed state
0 = None of the RB7:RB4 pins have changed state
(1)
.
Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF
flag bit can be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. DS30605C-page 21
PIC16C63A/65B/73B/74B
4.2.2.4 PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE
bit 7 bit 0
bit 7 PSPIE
bit 6 ADIE
bit 5 RCIE: USART Receive Interrupt Enable bit
bit 4 TXIE: USART Transmit Interrupt Enable bit
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
bit 2 CCP1IE: CCP1 Interrupt Enable bit
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
(1)
: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
(2)
: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
ADIE
(2)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
enable any peripheral interrupt.
Note 1: PIC 16C63A/73B devices do not have a pa rallel slave port imp lemented; always
maintain this bit clear.
2: PI C16C63A/65B devices do not have an A/D implemented; always maintain this bit
clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30605C-page 22 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.5 PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
Note: Interrupt flag bits are se t w he n an in terru pt
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIF
bit 7 bit 0
bit 7 PSPIF
bit 6 ADIF
bit 5 RCIF: USART Receive Interrupt Flag bit
bit 4 TXIF: USART Transmit Interrupt Flag bit
bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
(1)
: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
(2)
: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
1 = The USART receive buffer is full (clear by reading RCREG)
0 = The USART receive buffer is empty
1 = The USART transmit buffer is empty (clear by writing to TXREG)
0 = The USART transmit buffer is full
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
ADIF
(2)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
condition occurs, re gardless of the sta te of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt
.
Note 1: PIC16C63A/73B devices do n ot have a p aral lel slav e port imple mente d. This b it loc a-
tion is reserved on these devices.
2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is
reserved on these devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. DS30605C-page 23
PIC16C63A/65B/73B/74B
4.2.2.6 PIE2 Register
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
4.2.2.7 PIR2 Register
This register contains the CCP2 interrupt flag bit.
Note: Interrupt flag bit s ar e se t whe n an in terru pt
REGISTER 4-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
condition occurs, re gardless of the sta te of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt
.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30605C-page 24 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR
Reset.
Note: BOR is unknown on P OR. It must be set by
REGISTER 4-8: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR
bit 0 BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
the user and checked on subsequent
RESETS to see if BOR
a brown-out has occurre d. The BOR
bit is a “don't care” and is not predi ctable if
the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).
is clear, indicati ng
status
2000 Microchip Technology Inc. DS30605C-page 25
PIC16C63A/65B/73B/74B
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wid e. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLA TH reg is ter. On any RESET, the up per bi t s of the
PC will be cleared. Fig ure4-3 shows the two situations
for the loading of the PC. The up per ex ample in th e figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower exam pl e i n th e fi gure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 4-3: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
4.3.1 COMPUTED GOTO
A computed GOTO is accomplish ed by adding an offs et
to the progr am counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Im plementing a Table Read" (AN556).
4.3.2 STACK
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware s tack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writabl e. The PC i s PUSHed onto th e stac k
when a CALL instruction is executed, or an interrupt
causes a branch. The st ac k is POPed in the ev en t of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack opera tes as a circular buf fer . This means that
after the st ack h as be en PUSHed ei ght ti mes, th e nin th
push overwrites the v alue tha t was stored fro m the first
push. The tenth pus h ov erwri t es the se co nd p us h (an d
so on).
8
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an interrupt address.
4.4 Program Memory Paging
PIC16CXX devices are capable o f addressing a continuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When executing a CALL or GOTO ins truc tio n, t he upper
2 bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruct ion, the user must
ensure that the page select bits are programmed, so
that the desired prog ram memory pa ge is addre ssed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped from the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instruction s (which POPs the
address from the stack).
Note 1: The contents of PCLATH are unchanged
after a return or RETFIE instruction is
executed. The user must set up PCLATH
for any subsequent CALL’s or GOTO’s
2: PCLATH<4> is not used in these
PICmicro
PCLATH<4> as a general purpose r ead/
write bit is not recommended, since this
may affect upward compatibility with
future products.
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory . Thi s example as sumes
that PCLATH is saved and restored by the Interrupt
Service Routine
EXAMPLE 4-1: CALL OF A SUBROUTINE
ORG 0x500
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
®
devices. The use of
(if interrupts are used).
IN PAGE 1 FROM PAGE 0
;in page 0 (000h-7FFh)
DS30605C-page 26 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.5 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physi cal register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly
accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly result s in a no-operation (altho ug h s t atus bits
may be affected ). An ef fective 9- bit add ress is obt ained
by concatenating the 8 -bit FSR regi ster and the IRP b it
(STATUS<7>), as shown in Figur e 4-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4 -2.
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING
RP1:RP0 6
0
bank select location select
from opcode
0
00 01 10 11
00h
80h
100h
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
NEXT clrf INDF ;clear INDF register
CONTINUE
Note: Maintain the IRP and RP1 bits clear.
180h
movwf FSR ;to RAM
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
: ;yes continue
Indirect AddressingDirect Addressing
IRP FSR register
0
bank select
7
location select
0
Data
not used
Memory
7Fh
FFh
17Fh
1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 4-2.
2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
2000 Microchip Technology Inc. DS30605C-page 27
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 28 2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.0 I /O PORTS
Some pins for th ese I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is a 6-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full C MOS output drivers. All pi ns have
data direction bits (TRIS registers), which can configure these pins as output or input.
Setting a TRISA register bit puts the corresponding output driver in a hi-im pedan ce mo de. Clea ring a b it in th e
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins, whereas writing to i t will wri te to th e po rt latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog V
tion of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control
Register1).
REF input. The opera-
FIGURE 5-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Data
Bus
WR
Port
WR
TRIS
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
CK
Data Latch
CK
TRIS Latch
QD
Q
QD
Q
RD TRIS
VDD
P
N
V
SS
Analog
Input
mode
QD
EN
I/O pin
TTL
Input
Buffer
(1)
Note: On all RESETS, pins with analog function s
are configured a s analog a nd digit al input s.
The TRISA register controls the direction of the RA
pins, even when they are be ing us ed as ana lo g inputs.
The user must ensure the bits in the TRISA regi ster are
maintained set when using them as analog inputs.
EXAMPLE 5-1: INITIALIZING PORTA
(PIC16C73B/74B)
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 5-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
Bus
WR
Port
WR
TRIS
RD Port
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
Q
CK
Data Latch
QD
Q
CK
TRIS Latch
RD TRIS
N
SS
V
Schmitt
Trigger
Input
Buffer
QD
EN
EN
I/O pin
(1)
2000 Microchip Technology Inc. DS30605C-page 29
PIC16C63A/65B/73B/74B
TABLE 5-1: PORTA FUNCTIONS
Name Bit# Buffer Function
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
(1)
(1)
(1)
REF
bit0 TTL Digital input/output or analog input.
bit1 TTL Digital input/output or analog input.
bit2 TTL Digital input/output or analog input.
(1)
bit3 TTL Digital input/output or analog input or VREF.
RA4/T0CKI bit4 ST
(1)
RA5/SS
/AN4
bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
Digital input/output or external clock input for Timer0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not
implemented; maintain this register clear.
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0
05h PORTA
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Fh
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
ADCON1
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
— — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
(1)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Val ue on:
POR,
BOR
Val ue on
all other
RESETS
DS30605C-page 30 2000 Microchip Technology Inc.
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