MICROCHIP PIC16C62X Technical data

PIC16C62X

Data Sheet

EPROM-Based 8-Bit

CMOS Microcontrollers

 2003 Microchip Technology Inc. DS30235J

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
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Use of Microchip’s products as critical components in life
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Trademarks

The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.

Accuron, Application Maestro, dsPIC, dsPICDEM,
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS30235J - page ii  2003 Microchip Technology Inc.

PIC16C62X

EPROM-Based 8-Bit CMOS Microcontrollers

Devices included in this data sheet:

Referred to collectively as PIC16C62X.

• PIC16C620 • PIC16C620A

• PIC16C621 • PIC16C621A

• PIC16C622 • PIC16C622A

• PIC16CR620A

High Performance RISC CPU:

• Only 35 instructions to learn

• All single cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

- DC - 40 MHz clock input

- DC - 100 ns instruction cycle

Device

PIC16C620

PIC16C620A

PIC16CR620A

PIC16C621

PIC16C621A

PIC16C622

PIC16C622A

Program

Memory

512 80

512 96

512 96

1K 80

1K 96

2K 128

2K 128

Data

Memory

• Interrupt capability

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

REF) module

(V

- Programmable input multiplexing from device
inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

RA2/AN2/V

RA3/AN3

RA4/T0CKI

MCLR/

RB0/INT

REF

VPP
VSS

RB1
RB2
RB3

•1
2

3
4
5
6
7
8
9

18

PIC16C62X

17
16

15
14
13
12
11
10

RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT

DD

V
RB7
RB6
RB5
RB4

SSOP

RA2/AN2/V

RA3/AN3

RA4/T0CKI

MCLR/

RB0/INT

REF

VPP
VSS
VSS

RB1
RB2
RB3RB3

•1
2

3
4
5
6
7
8
9
10

20
19

PIC16C62X

18
17
16
15
14
13
12
11

RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
V

DD

V

DD

RB7
RB6
RB5
RB4

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

CMOS Technology:

• Low power, high speed CMOS EPROM
technology

• Fully static design

• Wide operating range

- 2.5V to 5.5V

• Commercial, industrial and extended tempera­ture range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

-15 µA typical @ 3.0V, 32 kHz

-< 1.0 µA typical standby current @ 3.0V

 2003 Microchip Technology Inc. DS30235J-page 1

PIC16C62X

Device Differences

Device Voltage Range Oscillator

PIC16C620

PIC16C621

PIC16C622

PIC16C620A

PIC16CR620A

PIC16C621A

PIC16C622A

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

(3)

(3)

(3)

(4)

(2)

(4)

(4)

2: For ROM parts, operation from 2.5V - 3.0V will require the PIC16LCR62X parts.

3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X parts.

4: For OTP parts, operations from 2.7V - 3.0V will require the PIC16LC62XA parts.

2.5 - 6.0 See Note 1 0.9

2.5 - 6.0 See Note 1 0.9

2.5 - 6.0 See Note 1 0.9

2.7 - 5.5 See Note 1 0.7

2.5 - 5.5 See Note 1 0.7

2.7 - 5.5 See Note 1 0.7

2.7 - 5.5 See Note 1 0.7

Process Technology

(Microns)

DS30235J-page 2  2003 Microchip Technology Inc.

PIC16C62X

Table of Contents

1.0 General Description .................................................................................................................................................................. 5

2.0 PIC16C62X Device Varieties.................................................................................................................................................... 7

3.0 Architectural Overview.............................................................................................................................................................. 9

4.0 Memory Organization ............................................................................................................................................................. 13

5.0 I/O Ports.................................................................................................................................................................................. 25

6.0 Timer0 Module........................................................................................................................................................................ 31

7.0 Comparator Module ................................................................................................................................................................ 37

8.0 Voltage Reference Module ..................................................................................................................................................... 43

9.0 Special Features of the CPU .................................................................................................................................................. 45

10.0 Instruction Set Summary ........................................................................................................................................................ 61

11.0 Development Support ............................................................................................................................................................. 75

12.0 Electrical Specifications .......................................................................................................................................................... 81

13.0 Device Characterization Information ..................................................................................................................................... 109

14.0 Packaging Information .......................................................................................................................................................... 113

Appendix A: Enhancements.............................................................................................................................................................. 119

Appendix B: Compatibility ................................................................................................................................................................. 119

Index ............................................................................................................................................................................................... 121

On-Line Support ................................................................................................................................................................................ 123

Systems Information and Upgrade Hot Line ..................................................................................................................................... 123

Reader Response ............................................................................................................................................................................. 124

Product Identification System ........................................................................................................................................................... 125

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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 2003 Microchip Technology Inc. DS30235J-page 3

PIC16C62X

NOTES:

DS30235J-page 4  2003 Microchip Technology Inc.

PIC16C62X

1.0 GENERAL DESCRIPTION

The PIC16C62X devices are 18 and 20-Pin ROM/
EPROM-based members of the versatile PICmicro
family of low cost, high performance, CMOS, fully­static, 8-bit microcontrollers.

All PICmicro microcontrollers employ an advanced
RISC architecture. The PIC16C62X devices have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.

PIC16C62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.

The PIC16C620A, PIC16C621A and PIC16CR620A
have 96 bytes of RAM. The PIC16C622(A) has 128
bytes of RAM. Each device has 13 I/O pins and an 8­bit timer/counter with an 8-bit programmable prescaler.
In addition, the PIC16C62X adds two analog compara­tors with a programmable on-chip voltage reference
module. The comparator module is ideally suited for
applications requiring a low cost analog interface (e.g.,
battery chargers, threshold detectors, white goods
controllers, etc).

PIC16C62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con­sumption. There are four oscillator options, of which the
single pin RC oscillator provides a low cost solution, the
LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (Power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.

A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.

A UV-erasable CERDIP-packaged version is ideal for
code development while the cost effective One-Time­Programmable (OTP) version is suitable for production
in any volume.

Table 1-1 shows the features of the PIC16C62X mid­range microcon troller families.

A simplified block diagram of the PIC16C62X is shown
in Figure 3-1.

The PIC16C62X series fits perfectly in applications
ranging from battery chargers to low power remote
sensors. The EPROM technology makes

customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast

®

and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high
performance, ease of use and I/O flexibility make the
PIC16C62X very versatile.

1.1 Family and Upward Compatibility

Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for the PIC16C5X can be easily ported to
PIC16C62X family of devices (Appendix B). The
PIC16C62X family fills the niche for users wanting to
migrate up from the PIC16C5X family and not needing
various peripheral features of other members of the
PIC16XX mid-range microcontroller family.

1.2 Development Support

The PIC16C62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer. Third Party “C” compilers are
also available.

 2003 Microchip Technology Inc. DS30235J-page 5

PIC16C62X

TABLE 1-1: PIC16C62X FAMILY OF DEVICES

PIC16C620

Clock Maximum Frequency

Memory EPROM Program

Peripherals Timer Module(s) TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0

Features Interrupt Sources 4 4 4 4 4 4 4

of Operation (MHz)

Memory
(x14 words)

Data Memory (bytes) 80 96 96 80 96 128 128

Comparators(s) 2 2 2 2 2 2 2

Internal Reference
Voltage

I/O Pins 13 13 13 13 13 13 13

Voltage Range (Volts) 2.5-6.0 2.7-5.5 2.5-5.5 2.5-6.0 2.7-5.5 2.5-6.0 2.7-5.5

Brown-out Reset Yes Yes Yes Yes Yes Yes Yes

Packages 18-pin DIP,

20 40 20 20 40 20 40

512 512 512 1K 1K 2K 2K

Yes Yes Yes Yes Yes Yes Yes

SOIC;
20-pin SSOP

(3)

PIC16C620A

18-pin DIP,
SOIC;
20-pin SSOP

All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

2: For ROM parts, operation from 2.0V - 2.5V will require the PIC16LCR62XA parts.

3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X part.

4: For OTP parts, operation from 2.7V - 3.0V will require the PIC16LC62XA part.

(1)(4)

PIC16CR620A

18-pin DIP,
SOIC;
20-pin SSOP

(2)

PIC16C621

18-pin DIP,
SOIC;
20-pin SSOP

(3)

PIC16C621A

18-pin DIP,
SOIC;
20-pin SSOP

(1)(4)

PIC16C622

18-pin DIP,
SOIC;
20-pin SSOP

(3)

PIC16C622A

18-pin DIP,
SOIC;
20-pin SSOP

(1)(4)

DS30235J-page 6  2003 Microchip Technology Inc.

PIC16C62X

2.0 PIC16C62X DEVICE VARIETIES

A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the Oscillator modes.

Microchip's PICSTART and PRO MATE
programmers both support programming of the
PIC16C62X.

Note: Microchip does not recommend code

protecting windowed devices.

2.2 One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.

2.3 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP
devices, but with all EPROM locations and configura­tion options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.



2.4 Serialized Quick-Turnaround­Production

Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.

Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.

SM

(SQTPSM) Devices

 2003 Microchip Technology Inc. DS30235J-page 7

PIC16C62X

NOTES:

DS30235J-page 8  2003 Microchip Technology Inc.

PIC16C62X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single
cycle (200 ns @ 20 MHz) except for program branches.

The PIC16C620(A) and PIC16CR620A address
512 x 14 on-chip program memory. The PIC16C621(A)
addresses 1K x 14 program memory. The
PIC16C622(A) addresses 2K x 14 program memory.
All program memory is internal.

The PIC16C62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C62X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C62X simple yet efficient. In addition, the
learning curve is reduced significantly.

The PIC16C62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.

The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.

Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.

and Digit Borrow out bit,

 2003 Microchip Technology Inc. DS30235J-page 9

PIC16C62X

FIGURE 3-1: BLOCK DIAGRAM

Device

PIC16C620

PIC16C620A

PIC16CR620A

PIC16C621

PIC16C621A

PIC16C622

PIC16C622A

Program

Bus

OSC1/CLKIN
OSC2/CLKOUT

Program

Memory

512 x 14
512 x 14
512 x 14

1K x 14
1K x 14
2K x 14
2K x 14

EPROM

Program

Memory

14

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Data Memory

13

Program Counter

8-Level Stack

Direct Addr

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

128 x 8
128 x 8

(13-bit)

Timer

Reset

Timer

Reset

(RAM)

80 x 8
96 x 8
96 x 8
80 x 8
96 x 8

RAM Addr

7

Data Bus

Registers

(1)

Addr MUX

3

RAM

File

FSR reg

STATUS reg

ALU

W reg

9

8

MUX

8

Indirect

Addr

Voltage

Reference

Comparator

­+

­+

TMR0

I/O Ports

RA0/AN0

RA1/AN1

RA2/AN2/VREF

RA3/AN3

RA4/T0CKI

PORTB

VDD, VSS

MCLR

Note 1: Higher order bits are from the STATUS register.

DS30235J-page 10  2003 Microchip Technology Inc.

TABLE 3-1: PIC16C62X PINOUT DESCRIPTION

PIC16C62X

Name

OSC1/CLKIN

OSC2/CLKOUT

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2/VREF

RA3/AN3

RA4/T0CKI

RB0/INT

RB1

RB2

RB3

RB4

RB5

RB6

RB7

VSS

VDD

Legend: O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

DIP/SOIC

Pin #

16 18 I ST/CMOS

15 17 O —

4 4 I/P ST

17 19 I/O ST

18 20 I/O ST

1 1 I/O ST

2 2 I/O ST

3 3 I/O ST

6 7 I/O

7 8 I/O TTL

8 9 I/O TTL

9 10 I/O TTL

10 11 I/O TTL

11 12 I/O TTL

12 13 I/O

13 14 I/O

5 5,6 P —

14 15,16 P —

— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input

SSOP

Pin #

I/O/P Type

Buffer

Type

TTL/ST

TTL/ST

TTL/ST

Oscillator crystal input/external clock source input.

Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode. In RC mode, OSC2 pin out­puts CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.

Master Clear (Reset) input/programming voltage input.
This pin is an Active Low Reset to the device.

PORTA is a bi-directional I/O port.

Analog comparator input

Analog comparator input

Analog comparator input or VREF output

Analog comparator input /output

Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is
open drain type.

PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.

(1)

(2)

(2)

RB0/INT can also be selected as an external
interrupt pin.

Interrupt-on-change pin.

Interrupt-on-change pin.

Interrupt-on-change pin. Serial programming clock.

Interrupt-on-change pin. Serial programming data.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

Description

 2003 Microchip Technology Inc. DS30235J-page 11

PIC16C62X

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

Q1

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1)

Q1

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

Fetch INST (PC+1)

Execute INST (PC)

Q2 Q3 Q4

Q1

Fetch INST (PC+2)

Execute INST (PC+1)

Internal
phase
clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3

Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS30235J-page 12  2003 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

PIC16C62X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 512 x 14 (0000h - 01FFh) for the
PIC16C620(A) and PIC16CR620, 1K x 14 (0000h ­03FFh) for the PIC16C621(A) and 2K x 14 (0000h ­07FFh) for the PIC16C622(A) are physically
implemented. Accessing a location above these
boundaries will cause a wrap-around within the first
512 x 14 space (PIC16C(R)620(A)) or 1K x 14 space
(PIC16C621(A)) or 2K x 14 space (PIC16C622(A)).
The RESET vector is at 0000h and the interrupt vector
is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16C620/PIC16C620A/
PIC16CR620A

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

13

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16C621/PIC16C621A

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

RESET Vector

Interrupt Vector

On-Chip Program

Memory

13

000h

0004
0005

03FFh

0400h

1FFFh

Stack Level 8

RESET Vector

Interrupt Vector

On-Chip Program

Memory

000h

0004
0005

01FFh

0200h

1FFFh

FIGURE 4-3: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16C622/PIC16C622A

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

RESET Vector

Interrupt Vector

On-Chip Program

Memory

13

000h

0004
0005

07FFh

0800h

1FFFh

 2003 Microchip Technology Inc. DS30235J-page 13

PIC16C62X

4.2 Data Memory Organization

The data memory (Figure 4-4, Figure 4-5, Figure 4-6
and Figure 4-7) is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bank 0 is selected when the RP0
bit is cleared. Bank 1 is selected when the RP0 bit
(STATUS <5>) is set. The Special Function Registers
are located in the first 32 locations of each bank.
Register locations 20-7Fh (Bank0) on the
PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and
A0-BFh (Bank1) on the PIC16C622 and PIC16C622A
are General Purpose Registers implemented as static
RAM. Some Special Purpose Registers are mapped in
Bank 1.

Addresses F0h-FFh of bank1 are implemented as
common ram and mapped back to addresses 70h-7Fh
in bank0 on the PIC16C620A/621A/622A/CR620A.

4.2.1 GENERAL PURPOSE REGISTER
FILE

The register file is organized as 80 x 8 in the
PIC16C620/621, 96 x 8 in the PIC16C620A/621A/
CR620A and 128 x 8 in the PIC16C622(A). Each is
accessed either directly or indirectly through the File
Select Register FSR (Section 4.4).

DS30235J-page 14  2003 Microchip Technology Inc.

PIC16C62X

FIGURE 4-4: DATA MEMORY MAP FOR

THE PIC16C620/621

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h

09h
0Ah
0Bh

0Ch
0Dh

0Eh
0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h
1Ah
1Bh

1Ch
1Dh

1Eh
1Fh

20h

6Fh

70h

(1)

INDF

TMR0

PCL

STATUS

FSR
PORTA
PORTB

PCLATH
INTCON

PIR1

CMCON

General
Purpose
Register

(1)

INDF

OPTION

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

VRCON

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

FIGURE 4-5: DATA MEMORY MAP FOR

THE PIC16C622

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h

09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

20h

(1)

INDF

TMR0

PCL

STATUS

FSR
PORTA
PORTB

PCLATH
INTCON

PIR1

CMCON

General
Purpose
Register

(1)

INDF

OPTION

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

VRCON

General
Purpose
Register

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

BFh

C0h

7Fh

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

 2003 Microchip Technology Inc. DS30235J-page 15

Bank 0 Bank 1

FFh

7Fh

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

Bank 0 Bank 1

FFh

PIC16C62X

FIGURE 4-6: DATA MEMORY MAP FOR THE

PIC16C620A/CR620A/621A

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h

09h
0Ah
0Bh
0Ch
0Dh
0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h
1Ah
1Bh
1Ch
1Dh
1Eh

1Fh

20h

(1)

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH
INTCON

PIR1

CMCON

General
Purpose
Register

(1)

INDF

OPTION

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

VRCON

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

FIGURE 4-7: DATA MEMORY MAP FOR

THE PIC16C622A

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h

09h
0Ah
0Bh
0Ch
0Dh
0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h
1Ah
1Bh
1Ch
1Dh
1Eh

1Fh

20h

(1)

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH
INTCON

PIR1

CMCON

General
Purpose
Register

(1)

INDF

OPTION

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

VRCON

General
Purpose
Register

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

BFh

C0h

6Fh

70h

7Fh

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

DS30235J-page 16  2003 Microchip Technology Inc.

General
Purpose
Register

Bank 0 Bank 1

Accesses

70h-7Fh

F0h

FFh

6Fh

70h

7Fh

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

General
Purpose
Register

Bank 0 Bank 1

Accesses

70h-7Fh

F0h

FFh

PIC16C62X

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.

The Special Function Registers can be classified into
two sets (core and peripheral). The Special Function
Registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.

TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C62X

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical

01h TMR0 Timer0 Module’s Register

02h PCL Program Counter's (PC) Least Significant Byte

03h STAT US IRP

04h FSR Indirect data memory address pointer

05h PORTA — — — RA4 RA3 RA2 RA1 RA0

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

07h-09h Unimplemented

0Ah PCLATH — — — Write buffer for upper 5 bits of program counter

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0Ch PIR1 — CMIF — — — — — —

0Dh-1Eh Unimplemented

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

82h PCL Program Counter's (PC) Least Significant Byte

83h STAT US IRP

84h FSR Indirect data memory address pointer

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

87h-89h Unimplemented

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter

8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

8Ch PIE1 — CMIE — — — — — —

8Dh Unimplemented

8Eh PCON — — — — — — POR BOR

8Fh-9Eh Unimplemented

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown,

q = value depends on condition, shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR

normal operation.

2: IRP & RP1 bits are reserved; always maintain these bits clear.

register)

(2)

register)

(2)

RP1

RP1

(2)

RP0 TO PD Z DC C

(2)

RP0 TO PD Z DC C

Reset, Brown-out Reset and Watchdog Timer Reset during

Value on

POR Reset

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---x 0000 ---u 0000

xxxx xxxx uuuu uuuu

— —

---0 0000 ---0 0000

0000 000x 0000 000u

-0-- ---- -0-- ----

— —

00-- 0000 00-- 0000

xxxx xxxx xxxx xxxx

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---1 1111 ---1 1111

1111 1111 1111 1111

— —

---0 0000 ---0 0000

0000 000x 0000 000u

-0-- ---- -0-- ----

— —

---- --0x ---- --uq

— —

000- 0000 000- 0000

Value on all

other

RESETS

(1)

 2003 Microchip Technology Inc. DS30235J-page 17

PIC16C62X

4.2.2.1 STATUS Register

The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bit. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16C62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.

REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved on the PIC16C62X; always maintain this bit clear.

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X; always maintain this bit
clear.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

the polarity is reversed. A subtraction is executed by adding the two’s

DS30235J-page 18  2003 Microchip Technology Inc.

4.2.2.2 OPTION Register

The OPTION register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT
(PSA = 1).

REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

PIC16C62X

bit 7 RBPU

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30235J-page 19

PIC16C62X

4.2.2.3 INTCON Register

The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.

Note: Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).

REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30235J-page 20  2003 Microchip Technology Inc.

4.2.2.4 PIE1 Register

This register contains the individual enable bit for the
comparator interrupt.

REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— CMIE — — — — — —

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt

bit 5-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

4.2.2.5 PIR1 Register

This register contains the individual flag bit for the
comparator interrupt.

PIC16C62X

Note: Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.

REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— CMIF — — — — — —

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed
0 = Comparator input has not changed

bit 5-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30235J-page 21

PIC16C62X

4.2.2.6 PCON Register

The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR
WDT Reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked
on subsequent RESETS to see if BOR
cleared, indicating a brown-out has
occurred. The BOR
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming BODEN bit in the
Configuration word).

STATUS bit is a "don't

REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —PORBOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR

bit 0 BOR

: Power-on Reset STATUS bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset STATUS bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Reset,

is

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS30235J-page 22  2003 Microchip Technology Inc.

PIC16C62X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 4-8 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower
example in the figure shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3> →
PCH).

FIGURE 4-8: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PC

PCLATH<4:0>

5

PCLATH

PCH PCL

12 11 10 0

PC

2

87

PCLATH<4:3>

11

8

Instruction with
PCL as
Destination

ALU result

GOTO,CALL

Opcode <10:0>

4.3.2 STACK

The PIC16C62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.

The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).

Note 1: There are no STATUS bits to indicate

stack overflow or stack underflow
conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.

PCLATH

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note, “Implementing a Table Read"
(AN556).

 2003 Microchip Technology Inc. DS30235J-page 23

PIC16C62X

4.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer
movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer
btfss FSR,7 ;all done?
goto NEXT ;no clear next

CONTINUE:

produce 00h. Writing to the INDF register indirectly
results in a no-operation (although STATUS bits may
be affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-9. However, IRP
is not used in the PIC16C62X.

A simple program to clear RAM location 20h-7Fh using
indirect addressing is shown in Example 4-1.

FIGURE 4-9: DIRECT/INDIRECT ADDRESSING PIC16C62X

RP1 RP0

bank select location select

(1)

6

from opcode

00h

0

00 01 10 11

(1)

IRP

bank select

180h

;yes continue

Indirect AddressingDirect Addressing

7

FSR register

location select

0

Data

not used

Memory

7Fh

1FFh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7).

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

DS30235J-page 24  2003 Microchip Technology Inc.

PIC16C62X

5.0 I/O PORTS

The PIC16C62X have two ports, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output
drivers. All pins have data direction bits (TRIS regis­ters), which can configure these pins as input or output.

A '1' in the TRISA register puts the corresponding out­put driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).

Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.

The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.

Note: On RESET, the TRISA register is set to all

inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.

TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.

The RA2 pin will also function as the output for the
voltage reference. When in this mode, the V

REF pin is a

very high impedance output and must be buffered prior
to any external load. The user must configure
TRISA<2> bit as an input and use high impedance
loads.

In one of the Comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA ;Initialize PORTA by setting

MOVLW 0X07 ;Turn comparators off and

MOVWF CMCON ;enable pins for I/O

BSF STATUS, RP0 ;Select Bank1

MOVLW 0x1F ;Value used to initialize

MOVWF TRISA ;Set RA<4:0> as inputs

;output data latches

;functions

;data direction

;TRISA<7:5> are always

;read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF

RA1:RA0 PINS

Data
Bus

WR
PORTA

WR
TRISA

Data Latch

TRIS Latch

RD PORTA

To Comparator

CK

CK

RD TRISA

QD

Q

QD

Q

VDD

V

Analog

Input Mode

Schmitt Trigger

Input Buffer

EN

VDD

P

N

VSS

SS

DQ

I/O
Pin

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Data
Bus

WR
PORTA

WR
TRISA

RD PORTA

To Comparator

CK

Data Latch

CK

TRIS Latch

RD TRISA

VROE

VREF

QD

Q

QD

Q

Analog

Input Mode

Schmitt Trigger

Input Buffer

EN

VDD

P

N

V

SS

DQ

VSS

VDD

RA2

Pin

 2003 Microchip Technology Inc. DS30235J-page 25

PIC16C62X

FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN

Data
Bus

WR
PORTA

WR
TRISA

CK

Data Latch

CK

TRIS Latch

RD PORTA

To Comparator

QD

Q

QD

Q

RD TRISA

Comparator Output

Comparator Mode = 110

Input Mode

DQ

EN

VDD

P

N

V

Analog

Schmitt Trigger

SS

Input Buffer

VDD

RA3 Pin

VSS

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN

Data
Bus

WR
PORTA

WR
TRISA

CK

Data Latch

CK

TRIS Latch

RD TRISA

RD PORTA

TMR0 Clock Input

QD

Comparator Output

Q

QD

Q

Comparator Mode = 110

DQ

EN

N

V

SS

Schmitt Trigger

Input Buffer

RA4 Pin

VSS

DS30235J-page 26  2003 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

Name Bit #

RA0/AN0

RA1/AN1

RA2/AN2/V

RA3/AN3

RA4/T0CKI

Legend: ST = Schmitt Trigger input

REF

bit0 ST

bit1 ST

bit2 ST

bit3 ST

bit4 ST

Buffer

Type

Function

Input/output or comparator input

Input/output or comparator input

Input/output or comparator input or V

Input/output or comparator input/output

Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.

REF output

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h PORTA

85h TRISA

1Fh CMCON

9Fh VRCON

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown

Note: Shaded bits are not used by PORTA.

— — — RA4 RA3 RA2 RA1 RA0

— — —

C2OUT C1OUT — — CIS CM2 CM1 CM0

VREN VROE

TRISA4TRISA3TRISA2TRISA1TRISA

VRR — VR3 VR2 VR1 VR0

PIC16C62X

Value on

POR

---x 0000 ---u 0000

---1 1111 ---1 1111

0

00-- 0000 00-- 0000

000- 0000 000- 0000

Value on
All Other
RESETS

 2003 Microchip Technology Inc. DS30235J-page 27

PIC16C62X

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a High Impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).

Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (e.g., any RB<7:4> pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).

FIGURE 5-5: BLOCK DIAGRAM OF

RB<7:4> PINS

DD

TTL
Input
Buffer

V

P

weak
pull-up

VCC

VSS

ST
Buffer

I/O
pin

(1)

RBPU

Data Bus

WR PORTB

WR TRISB

Data Latch

QD

Q

CK

TRIS Latch

QD

Q

CK

This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implement­ing Wake-Up on Key Strokes.)

Note: If a change on the I/O pin should occur

when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter­rupt flag may not get set.

The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.

FIGURE 5-6: BLOCK DIAGRAM OF

RB<3:0> PINS

DD

TTL
Input
Buffer

V

P

weak
pull-up

VCC

VSS

I/O
pin

(1)

RBPU

Data Bus

WR PORTB

WR TRISB

Data Latch

CK

D

CK

RD TRISB

QD

Q

Q

Q

QD

RD TRISB

Set RBIF

From other
RB<7:4> pins

RB<7:6> in Serial Programming mode

Note 1: TRISB = 1 enables weak pull-up if RBPU

(OPTION<7>).

RD PORTB

Latch

QD

EN

QD

EN

RD PORTB

= '0'

RD PORTB

RB0/INT

ST
Buffer

Note 1: TRISB = 1 enables weak pull-up if RBPU

(OPTION<7>).

EN

RD PORTB

= '0'

DS30235J-page 28  2003 Microchip Technology Inc.