MICROCHIP PIC16C55X DATA SHEET
PIC16C55X
Data Sheet
EPROM-Based 8-Bit CMOS
Microcontrollers
2002 Microchip Technology Inc. Preliminary DS40143D
Note the following details of the code protection feature on PICmicro® MCUs.
• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, K
EELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS40143D - page ii Preliminary 2002 Microchip Technology Inc.
PIC16C55X
EPROM-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet:
Referred to collectively as PIC16C55X.
• PIC16C554
• PIC16C557
• PIC16C558
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 20 ns instruction cycle
Device
Program
Memory
Data Memory
PIC16C554 512 80
PIC16C557 2 K 128
PIC16C558 2 K 128
• Interrupt capability
• 16-18 special function hardware registers
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Peripheral Features:
• 13-22 I/O pins with individual direction control
- Pull-up resistors on PORTB
• High current sink/source for direct LED drive
• Timer0: 8-bit timer/counter with 8-bit programma-
ble prescaler
Pin Diagram
PDIP, SOIC, Windowed CERDIP
N/C
•1 18
PIC16C554/558
2
3
4
5
6
7
8
9
•1
2
3
4
5
6
7
8
9
10
17
16
15
14
13
12
11
10
20
PIC16C554/558
19
18
17
16
15
14
13
12
11
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
PIC16C557
25
24
23
22
21
20
19
18
17
16
15
RA2
RA3
RA4/T0CKI
/Vpp
MCLR
V
SS
RB0/INT
RB1
RB2
RB3
SSOP
RA2
RA3
RA4/T0CKI
/Vpp
MCLR
SS
V
VSS
RB0/INT
RB1
RB2
RB3
PDIP, SOIC, Windowed CERDIP
RA4/T0CKI
V
DD
VSS
RA5
RA0
RA1
RA2
RA3
RB0/INT
RB1
RB2
RB3
RB4
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
DD
V
RB7
RB6
RB5
RB4
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
DD
V
VDD
RB7
RB6
RB5
RB4
MCLR/
VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
SSOP
VSS
RA4/T0CKI
V
DD
RA5
RA0
RA1
RA2
RA3
RB0/INT
RB1
RB2
RB3
RB4
VSS
2002 Microchip Technology Inc. Preliminary DS40143D-page 1
•1
2
3
PIC16C557
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VPP
MCLR/
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
PIC16C55X
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
Note: For additional information on enhance-
ments, see Appendix A
CMOS Technology:
• Low power, high speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range
- 2.5V to 5.5V
• Commercial, Industrial and Extended temperature
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
-15 µA typical 3.0V, 32 kHz
-< 1.0 µA typical standby current @ 3.0V
Device Differences
Device Voltage Range Oscillator
PIC16C554 2.5 - 5.5 (Note 1)
PIC16C557 2.5 - 5.5 (Note 1)
PIC16C558 2.5 - 5.5 (Note 1)
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40143D-page 2 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 13
5.0 I/O Ports ..................................................................................................................................................................................... 23
6.0 Special Features of the CPU...................................................................................................................................................... 31
7.0 Timer0 Module ........................................................................................................................................................................... 47
8.0 Instruction Set Summary ............................................................................................................................................................ 53
9.0 Development Support................................................................................................................................................................. 67
10.0 Electrical Specifications.............................................................................................................................................................. 73
11.0 Packaging Information................................................................................................................................................................ 87
Appendix A: Enhancements ............................................................................................................................................................. 97
Appendix B: Compatibility ............................................................................................................................................................... 97
Index .................................................................................................................................................................................................... 99
On-Line Support................................................................................................................................................................................. 101
Systems Information and Upgrade Hot Line ...................................................................................................................................... 101
Reader Response .............................................................................................................................................................................. 102
Product Identification System ............................................................................................................................................................ 103
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2002 Microchip Technology Inc. Preliminary DS40143D-page 3
PIC16C55X
NOTES:
DS40143D-page 4 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
1.0 GENERAL DESCRIPTION
The PIC16C55X are 18, 20 and 28-Pin EPROM-based
members of the versatile PIC16CXX family of low cost,
high performance, CMOS, fully-static, 8-bit
microcontrollers.
®
All PICmicro
RISC architecture. The PIC16C55X have enhanced
core features, eight-level deep stack, and multiple
internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate 8bit wide data. The two-stage instruction pipeline allows
all instructions to execute in a single-cycle, except for
program branches (which require two cycles). A total of
35 instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
PIC16C55X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C554 has 80 bytes of RAM. The PIC16C557
and PIC16C558 have 128 bytes of RAM. The
PIC16C554 and PIC16C558 have 13 I/O pins and an 8bit timer/counter with an 8-bit programmable prescaler.
The PIC16C557 has 22 I/O pins and an 8-bit timer/
counter with an 8-bit programmable prescaler.
PIC16C55X devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for high speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
A highly reliable Watchdog Timer, with its own on-chip
RC oscillator, provides protection against software
lock-up.
microcontrollers employ an advanced
A UV-erasable CERDIP packaged version is ideal for
code development while the cost effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16C55X midrange microcontroller families.
A simplified block diagram of the PIC16C55X is shown
in Figure 3-1.
The PIC16C55X series fit perfectly in applications
ranging from motor control to low power remote sensors. The EPROM technology makes customization of
application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The
small footprint packages make this microcontroller
series perfect for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16C55X very versatile.
1.1 Family and Upward Compatibility
Users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of
the PIC16C5X architecture. Please refer to Appendix A
for a detailed list of enhancements. Code written for
PIC16C5X can be easily ported to PIC16C55X family
of devices (Appendix B).
The PIC16C55X family fills the niche for users wanting
to migrate up from the PIC16C5X family and not needing various peripheral features of other members of the
PIC16XX mid-range microcontroller family.
1.2 Development Support
The PIC16C55X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer.
2002 Microchip Technology Inc. Preliminary DS40143D-page 5
PIC16C55X
TABLE 1-1: PIC16C55X FAMILY OF DEVICES
PIC16C554 PIC16C557 PIC16C558
Clock
Memory
Peripherals Timer Module(s) TMR0 TMR0 TMR0
Features
All PICmicro
I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.
Maximum Frequency of Operation
(MHz)
EPROM Program Memory
(x14 words)
Data Memory (bytes) 80 128 128
Interrupt Sources 3 3 3
I/O Pins 13 22 13
Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5
Brown-out Reset — — —
Packages 18-pin DIP, SOIC;
®
Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
20 20 20
512 2K 2K
28-pin DIP, SOIC;
20-pin SSOP
28-pin SSOP
18-pin DIP, SOIC,
SSOP
DS40143D-page 6 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
2.0 PIC16C55X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C55X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1 UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
programmers both support programming of the
PIC16C55X.
2.2 One-Time Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
and PROMATE
2.3 Quick-Turnaround Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium-to-high quantity of units and whose code patterns have stabilized. The devices are identical to the
OTP devices, but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4 Serialized Quick-Turnaround
Production (SQTP
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
SM
) Devices
2002 Microchip Technology Inc. Preliminary DS40143D-page 7
PIC16C55X
NOTES:
DS40143D-page 8 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C55X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C55X uses a Harvard architecture in
which program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently from 8-bit
wide data words. Instruction opcodes are 14-bit wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a singlecycle (200 ns @ 20 MHz) except for program branches.
The table below lists the memory (EPROM and RAM).
Program
Device
PIC16C554 512 80
PIC16C557 2 K 128
PIC16C558 2 K 128
Memory
(EPROM)
Data
Memor
(RAM)
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
and Digit Borrow out bit,
The PIC16C554 addresses 512 x 14 on-chip program
memory. The PIC16C557 and PIC16C558 addresses
2 K x 14 program memory. All program memory is internal.
The PIC16C55X can directly or indirectly address its
register files or data memory. All special function
registers, including the program counter, are mapped
into the data memory. The PIC16C55X has an orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C55X simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16C55X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
2002 Microchip Technology Inc. Preliminary DS40143D-page 9
PIC16C55X
FIGURE 3-1: BLOCK DIAGRAM
Device
Program
Memory
Data
Memory
PIC16C554 512 x 14 80 x 8
PIC16C557 2 K x 14 128 x 8
PIC16C558 2 K x 14 128 x 8
13
Program Counter
8-Level Stack
Direct Addr
8
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
(13-bit)
Timer
Reset
Timer
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
EPROM
Program
Memory
512 x 14
to
2K x 14
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
RAM Addr
7
3
8
Data Bus
RAM
File
Registers
80 x 8 to
128 x 8
(1)
Addr MUX
STATUS reg
ALU
W reg
8
8
FSR
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0
RA1
RA2
RA3
RA4/T0CKI
RB0/INT
RB7:RB1
(2)
RC7:RC0
PP VDD, VSS
V
Note 1: Higher order bits are from STATUS Register.
2: PIC16C557 only.
Timer0
DS40143D-page 10 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
TABLE 3-1: PIC16C55X PINOUT DESCRIPTION
Name
Pin Number
PDIP SOIC SSOP Description
OSC1/CLKIN 16 16 18 I ST/CMOS Oscillator crystal input/external clock source output.
OSC2/CLKOUT 15 15 17 O — Oscillator crystal output. Connects to crystal or resonator
/VPP 4 4 4 I/P ST Master clear (Reset) input/programming voltage input.
MCLR
RA0 17 17 19 I/O ST Bi-directional I/O port
RA1 18 18 20 I/O ST Bi-directional I/O port
RA2 1 1 1 I/O ST Bi-directional I/O port
RA3 2 2 2 I/O ST Bi-directional I/O port
RA4/T0CKI 3 3 3 I/O ST Bi-directional I/O port or external clock input for TMR0.
RB0/INT 6 6 7 I/O TTL/ST
RB1 7 7 8 I/O TTL Bi-directional I/O port can be software programmed for
RB2 8 8 9 I/O TTL Bi-directional I/O port can be software programmed for
RB3 9 9 10 I/O TTL Bi-directional I/O port can be software programmed for
RB4 10 10 11 I/O TTL Bi-directional I/O port can be software programmed for
RB5 11 11 12 I/O TTL Bi-directional I/O port can be software programmed for
RB6 12 12 13 I/O TTL/ST
RB7 13 13 14 I/O TTL/ST
(3)
RC0
(3)
RC1
(3)
RC2
(3)
RC3
(3)
RC4
(3)
RC5
(3)
RC6
(3)
RC7
SS 5 5 5,6 P — Ground reference for logic and I/O pins.
V
DD 14 14 15,16 P — Positive supply for logic and I/O pins.
V
18 18 18 I/O TTL Bi-directional I/O port input buffer.
19 19 19 I/O TTL Bi-directional I/O port input buffer.
20 20 20 I/O TTL Bi-directional I/O port input buffer.
21 21 21 I/O TTL Bi-directional I/O port input buffer.
22 22 22 I/O TTL Bi-directional I/O port input buffer.
23 23 23 I/O TTL Bi-directional I/O port input buffer.
24 24 24 I/O TTL Bi-directional I/O port input buffer.
25 25 25 I/O TTL Bi-directional I/O port input buffer.
Legend: O = Output I/O = Input/output P = Power
— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: PIC16C557 only.
Pin
Typ e
Buffer
Typ e
in Crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
This pin is an active low RESET to the device.
Output is open drain type.
(1)
Bi-directional I/O port can be software programmed for
internal weak pull-up. RB0/INT can also be selected as an
external interrupt pin.
internal weak pull-up.
internal weak pull-up.
internal weak pull-up.
internal weak pull-up. Interrupt-on-change pin.
internal weak pull-up. Interrupt-on-change pin.
(2)
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial programming clock.
(2)
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial programming data.
2002 Microchip Technology Inc. Preliminary DS40143D-page 11
PIC16C55X
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 3-2.
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
Q1
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Q1
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Execute INST (PC) Fetch INST (PC+2)
Q2 Q3 Q4
Q1
Execute INST (PC+1)
Internal
phase
clocks
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40143D-page 12 Preliminary 2002 Microchip Technology Inc.
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16C55X
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C55X has a 13-bit program counter capable
of addressing an 8 K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16C554 and 2K x 14 (0000h - 07FFh) for the
PIC16C557 and PIC16C558 are physically implemented. Accessing a location above these boundaries
will cause a wrap-around within the first 512 x 14
spaces in the PIC16C554, or 2K x 14 space of the
PIC16C558 and PIC16C557. The RESET vector is at
0000h and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C554
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
13
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C557 AND
PIC16C558
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory
13
000h
0004
0005
07FFh
0800h
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory
000h
0004
0005
01FFh
0200h
1FFFh
1FFFh
4.2 Data Memory Organization
The data memory (Figure 4-3 through Figure 4-5) is
partitioned into two banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). Bank 0 is selected when the RP0 bit
(STATUS <5>) is cleared. Bank 1 is selected when the
RP0 bit is set. The Special Function Registers are
located in the first 32 locations of each Bank. Register
locations 20-6Fh (Bank 0) on the PIC16C554 and 207Fh (Bank 0) and A0-BFh (Bank 1) on the PIC16C558
and PIC16C557 are General Purpose Registers implemented as static RAM. Some special purpose registers
are mapped in Bank 1.
4.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 80 x 8 in the
PIC16C554 and 128 x 8 in the PIC16C557 and
PIC16C558. Each can be accessed either directly or
indirectly through the File Select Register, FSR
(Section 4.4).
2002 Microchip Technology Inc. Preliminary DS40143D-page 13
PIC16C55X
FIGURE 4-3: DATA MEMORY MAP FOR
THE PIC16C554
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
6Fh
70h
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
General
Purpose
Register
(1)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PCON
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FIGURE 4-4: DATA MEMORY MAP FOR
THE PIC16C557
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC TRISC
PCLATH
INTCON
General
Purpose
Register
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PCON
General
Purpose
Register
(1)
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
7Fh
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40143D-page 14 Preliminary 2002 Microchip Technology Inc.
Bank 0 Bank 1
FFh
7Fh
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
Bank 0 Bank 1
FFh
PIC16C55X
FIGURE 4-5: DATA MEMORY MAP FOR
THE PIC16C558
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
(1)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
General
Purpose
Register
(1)
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PCON
General
Purpose
Register
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). The special function
registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
7Fh
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2002 Microchip Technology Inc. Preliminary DS40143D-page 15
Bank 0 Bank 1
FFh
PIC16C55X
TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C55X
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a
physical register)
01h TMR0 Timer0 Module’s Register xxxx xxxx 47
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 21
03h STATUS IRP
04h FSR Indirect data memory address pointer xxxx xxxx 21
05h PORTA
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 25
07h PORTC
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
0Bh INTCON GIE
0Ch — Unimplemented — —
0Dh-1Eh — Unimplemented — —
1Fh — Unimplemented — —
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a
81h OPTION RBPU
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 21
83h STATUS
84h FSR Indirect data memory address pointer xxxx xxxx 21
85h TRISA
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 25
87h TRISC
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON GIE
8Ch — Unimplemented — —
8Dh — Unimplemented — —
8Eh PCON
8Fh-9Eh — Unimplemented — —
9Fh — Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.
4: PIC16C557 only.
(4)
(4)
(2)
— — — RA4 RA3 RA2 RA1 RA0 ---x xxxx 23
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 27
— — — Write buffer for upper 5 bits of program counter ---0 0000 21
physical register)
— —RP0TOPD ZDCC0001 1xxx 17
— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 23
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 27
— — — Write buffer for upper 5 bits of program counter ---0 0000 21
— — — — — —POR— ---- --0- 20
(2)
RP1
(3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 19
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 18
(3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 19
RP0 TO PD ZDCC0001 1xxx 17
Reset and Watchdog Timer Reset during normal operation.
Value on
POR Reset
xxxx xxxx 21
xxxx xxxx 21
Detail on
Page:
DS40143D-page 16 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
4.2.2.1 STATUS Register
The STATUS register, shown in Figure 4-2, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions be used to alter the
STATUS register because these instructions do not
affect any status bits. For other instructions, not affecting any status bits, see the “Instruction Set Summary”.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as the destination may be different
2: The C and DC bits operate as a Borrow
than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
REGISTER 4-1: STATUS REGISTER (ADDRESS 03h OR 83h)
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit7 bit0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: For borrow
IRP: Register Bank Select bit (used for Indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C55X, always maintain this bit clear
RP1:RP0: Register Bank Select bits (used for Direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear.
TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
= By execution of the SLEEP instruction
0
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is
reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
are not used by the PIC16C55X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS40143D-page 17
PIC16C55X
4.2.2.2 OPTION Register
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit7 bit0
INTEDG T0CS T0SE PSA PS2 PS1 PS0
Note 1: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
bit 7 RBPU
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS40143D-page 18 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
4.2.2.3 INTCON Register
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE
bit7 bit0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 Reserved: For future use. Always maintain this bit clear.
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
— T0IE INTE RBIE T0IF INTF RBIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS40143D-page 19
PIC16C55X
4.2.2.4 PCON Register
The PCON register contains a flag bit to differentiate
between a Power-on Reset, an external MCLR
or WDT Reset. See Section 6.3 and Section 6.4 for
detailed RESET operation.
REGISTER 4-4: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — —POR—
bit7 bit0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR
bit 0 Unimplemented: Read as '0'
: Power-on Reset status bit
1 = No Power-on Reset occurred
0 = Power-on Reset occurred
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Reset
DS40143D-page 20 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
r
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC<12:8>) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower exam-
ple in Figure 4-6 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-6: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
8
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
4.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2 STACK
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF registe
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
;yes continue
CONTINUE:
2002 Microchip Technology Inc. Preliminary DS40143D-page 21
PIC16C55X
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16C55X
(1)
RP1 RP0 6
from opcode
0
IRP
Indirect AddressingDirect Addressing
(1)
7
FSR register
0
bank select location select
00 01 10 11
00h
not used
Data
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
For memory map detail see Figure 4-3 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
bank select
00h
7Fh
location select
DS40143D-page 22 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
5.0 I/O PORTS
The PIC16C554 and PIC16C558 have two ports,
PORTA and PORTB. The PIC16C557 has three ports,
PORTA, PORTB and PORTC.
5.1 PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open-drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
Note 1: On RESET, the TRISA register is set to all
inputs.
FIGURE 5-2: BLOCK DIAGRAM OF RA4
PIN
Data
bus
WR
PORTA
WR
TRISA
RD PORTA
TMR0 clock input
QD
Q
CK
Data Latch
QD
Q
CK
TRISA Latch
RD TRISA
N
V
SS
Schmitt
Trigger
input
buffer
QD
EN
EN
VSS
I/O pin
(1)
FIGURE 5-1: BLOCK DIAGRAM OF
PORT PINS RA<3:0>
Data
Bus
WR
PORTA
WR
TRISA
RD PORTA
CK
Data Latch
D
CK
TRIS Latch
QD
Q
Q
Q
RD TRISA
QD
Schmitt
Trig ger
input
buffer
EN
VDD
P
N
V
VDD
SS
VSS
I/O pin
2002 Microchip Technology Inc. Preliminary DS40143D-page 23
PIC16C55X
TABLE 5-1: PORTA FUNCTIONS
Name Bit #
RA0 Bit 0 ST Bi-directional I/O port.
RA1 Bit 1 ST Bi-directional I/O port.
RA2 Bit 2 ST Bi-directional I/O port.
RA3 Bit 3 ST Bi-directional I/O port.
RA4/T0CKI Bit 4 ST Bi-directional I/O port or external clock input for TMR0. Output is open
Legend: ST = Schmitt Trigger input
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Buffer
Typ e
Function
drain type.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05h PORTA
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTA.
— — — RA4 RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
Value on
POR
Value on
All Other
RESETS
DS40143D-page 24 Preliminary 2002 Microchip Technology Inc.
PIC16C55X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>). This interrupt can wake the
device from SLEEP. The user, in the interrupt service
routine, can clear the interrupt in the following manner:
• Any read or write of PORTB (this will end the mismatch condition)
• Clear flag bit RBIF
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on mismatch feature, together with
software configurable pull-ups on these four pins,
allows easy interface to a key pad and make it possible
for wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Note 1: If a change on the I/O pin should occur
when the read operation is being executed (start of the Q2 cycle), then the
RBIF interrupt flag may not get set.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-3: BLOCK DIAGRAM OF RB7:RB4 PINS
(1)
RBPU
Latch
Q
VDD
P
N
VSS
D
EN
EN
Data Bus
WR PORTB
WR TRISB
Set RBIF
From other
RB7:RB4 pins
RB7:RB6 in Serial Programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).
Data Latch
QD
CK
TRIS Latch
CK
RD TRISB
RD PORTB
QD
Q
QD
DD
V
P
TTL
Input
Buffer
RD PORTB
weak
pull-up
ST
Buffer
VDD
I/O
pin
VSS
2002 Microchip Technology Inc. Preliminary DS40143D-page 25
PIC16C55X
FIGURE 5-4: BLOCK DIAGRAM OF RB3:RB0 PINS
(1)
Data Bus
WR PORTB
WR TRISB
RBPU
Data Latch
CK
TRIS Latch
CK
QD
QD
Q
VDD
P
N
VSS
TTL
Input
Buffer
V
DD
P
weak
pull-up
ST
Buffer
VDD
I/O
pin
VSS
RD TRISB
RD PORTB
RB0/INT
Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).
ST
Buffer
Latch
Q
D
EN
RD PORTB
TABLE 5-3: PORTB FUNCTIONS
Name Bit # Buffer Type Function
(1)
RB0/INT Bit 0 TTL/ST
RB1 Bit 1 TTL Bi-directional I/O port. Internal software programmable weak pull-up.
RB2 Bit 2 TTL Bi-directional I/O port. Internal software programmable weak pull-up.
RB3 Bit 3 TTL Bi-directional I/O port. Internal software programmable weak pull-up.
RB4 Bit 4 TTL Bi-directional I/O port (with interrupt-on-change). Internal software programmable
RB5 Bit 5 TTL Bi-directional I/O port (with interrupt-on-change). Internal software programmable
RB6 Bit 6 TTL/ST
RB7 Bit 7 TTL/ST
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
Bi-directional I/O port. Internal software programmable weak pull-up.
weak pull-up.
weak pull-up.
(2)
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock pin.
(2)
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data pin.
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB AND TRISB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION RBPU
0BH, 8BH INTCON GIE
Legend: x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTB.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Reserved T0IE INTE BRIE T0IF INTF RBIF 0000 000x 0000 000x
Value o n
POR
DS40143D-page 26 Preliminary 2002 Microchip Technology Inc.
Value on
All Other
RESETS
PIC16C55X
5.3 PORTC and TRISC Registers
(1)
PORTC is a 8-bit wide latch. All pins have data direction bits (TRIS registers) which can configure these
pins as input or output.
A '1' in the TRISC register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISC
register puts the contents of the output latch on the
selected pin(s).
Reading the PORTC register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch
FIGURE 5-5: BLOCK DIAGRAM OF
PORT PINS RC<7:0>
Data
Bus
WR
PORTC
WR
TRISC
RD PORTC
CK
Data Latch
D
CK
TRIS Latch
QD
Q
Q
Q
RD TRISC
QD
EN
VDD
P
N
SS
V
TTL
Input
Buffer
VDD
VSS
I/O pin
TABLE 5-5: PORTC FUNCTIONS
Name Bit # Buffer Type Function
RC0 Bit 0 TTL Bi-directional I/O port.
RC1 Bit 1 TTL Bi-directional I/O port.
RC2 Bit 2 TTL Bi-directional I/O port.
RC3 Bit 3 TTL Bi-directional I/O port.
RC4 Bit 4 TTL Bi-directional I/O port.
RC5 Bit 5 TTL Bi-directional I/O port.
RC6 Bit 6 TTL Bi-directional I/O port.
RC7 Bit 7 TTL Bi-directional I/O port.
Legend: ST = Schmitt Trigger, TTL = TTL input
TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC AND TRISC
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
Note 1: PIC16C557 ONLY.
Value on
POR
Value on
All Other
RESETS
2002 Microchip Technology Inc. Preliminary DS40143D-page 27
PIC16C55X
5.4 I/O Programming Considerations
5.4.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit 0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-1 shows the effect of two sequential readmodify-write instructions (ex., BCF,BSF, etc.) on an
I/O port.
A pin actively outputting a low or high should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
DS40143D-page 28 Preliminary 2002 Microchip Technology Inc.
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