MICROCHIP PIC16F917, PIC16916, PIC16914, PIC16913 DATA SHEET

PIC16F917/916/914/913

Data Sheet

28/40/44-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

© 2005 Microchip Technology Inc. Preliminary DS41250D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR­RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICD EM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS41250D-page ii Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 n s instruction cycle

• Program Memory Read (PMR) capability

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of
8 MHz to 32 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for
power savings

• Power-saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended tempera ture range

• Power-on Reset (PO R)

• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Reset (BOR) with software control
option

• Enhanced Low-Current Watchdog Timer (WDT)
with on-chip oscillator (software selectable
nominal 268 seconds with full prescaler) with
software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

Low-Power Features:

• Standby Current:

- <100 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V , typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• Liquid Crystal Display module:

- Up to 60 pixel drive capability on 28-pin
devices

- Up to 96 pixel drive capability on 40-pin
devices

- Four commons

• Up to 35 I/O pins and 1 input-only pin:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• In-Circuit Serial Programming™ (ICSP™) via two
pins

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(CV

REF) module (% of VDD)

- Comparator inputs and outputs externally

accessible

• A/D Converter:

- 10-bit resolution and up to 8 channels

• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 as Timer1

oscillator if INTOSCIO or LP mode is
selected

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)

• Up to 2 Capture, Compare, PWM modules:

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Synchronous Serial Port (SSP) with I

2

C™

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 1

PIC16F917/916/914/913

Program

Memory

Device

Flash

(words/bytes)

Data Memory

SRAM
(bytes)

EEPROM

(bytes)

I/O

10-bit A/D

(ch)

LCD

(segment

drivers)

CCP

Timers

8/16-

PIC16F913 4K/7K 256 256 24 5 16 1 2/1
PIC16F914 4K/7K 256 256 35 8 24 2 2/1
PIC16F916 8K/14K 352 256 24 5 16 1 2/1
PIC16F917 8K/14K 352 256 35 8 24 2 2/1

Pin Diagrams – PIC16F914/917, 40-Pin

40-pin PDIP

RE3/MCLR/VPP

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/V

RA3/AN3/C1+/V

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKI/T1OSI

RA6/OSC2/CLKO/T1OSO

REF-/COM2

REF+/SEG15

RE0/AN5/SEG21
RE1/AN6/SEG22
RE2/AN7/SEG23

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3

RC3/SEG6

RD0/COM3

/SEG5

V

DD

VSS

RD1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC16F914/917

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
V

DD

VSS
RD7/SEG20
RD6/SEG19
RD5/SEG18
RD4/SEG17
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G
RD3/SEG16
RD2/CCP2

/SDO/SEG11

bit

DS41250D-page 2 Preliminary © 2005 Microchip Technology Inc.

Pin Diagrams – PIC16F913/916, 28-Pin

28-pin PDIP, SOIC, SSOP

PIC16F917/916/914/913

RA3/AN3/C1+/V

28-pin QFN

RE3/MCLR/VPP

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/V

REF+/COM3/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKI/T1OSI

RA6/OSC2/CLKO/T1OSO

REF-/COM2

/SEG5

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3

RC3/SEG6

PIC16F913/916

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
V

DD

VSS
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G

/SDO/SEG11

1
2
3
4
5
6
7

V

SS

8
9

10
11

12
13
14

/VPP

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/V

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS

RA7/OSC1/CLKI/T1OSI

RA6/OSC2/CLKO/T1OSO

REF+/COM3/SEG15

/SEG5

SS

V

RA1/AN1/C2-/SEG7

282627

1
2
3

PIC16F913/916

4
5
6
7

8109

RC0/VLCD1

RA0/AN0/C1-/SEG12

RC1/VLCD2

RE3/MCLR

RB7/ICSPDAT/ICDDAT/SEG13

25

11

RC3/SEG6

RC2/VLCD3

12

RB6/ICSPCLK/ICDCK/SEG14

24

/SDO/SEG11

RC4/T1G

RB5/COM1

23

13

RC5/T1CKI/CCP1/SEG10

RB4/COM0

22

14

RC6/TX/CK/SCK/SCL/SEG9

21
20
19
18
17
16
15

RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0

DD

V
VSS
RC7/RX/DT/SDI/SDA/SEG8

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 3

PIC16F917/916/914/913

Pin Diagrams – PIC16F914/917, 44-Pin

44-pin TQFP

/SDO/SEG11

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G

RD3/SEG16

RD2/CCP2

RD1

RD0/COM3

RC3/SEG6

RC2/VLCD3

RC1/VLCD2

NC

RC7/RX/DT/SDI/SDA/SEG8

RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20

V

RB0/SEG0/INT

VDD

RB1/SEG1
RB2/SEG2
RB3/SEG3

44-pin QFN

4443424140

1
2
3
4

SS

5
6
7
8
9
10
11

121314

NC

RC7/RX/DT/SDI/SDA/SEG8

39

38

PIC16F914/917

16

17

1819202122

15

NC

/VPP

RB4/COM0

RB5/COM1

RE3/MCLR

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20

RB0/INT/SEG0

RB1/SEG1
RB2/SEG2

37

RA0/C1-/AN0/SEG12

V
VDD
VDD

363435

RA1/C2-/AN1/SEG7

SS

33
32
31
30
29
28
27
26
25
24

23

REF-/COM2

REF+/C1+/SEG15

RA2/AN2/C2+/V

RA3/AN3/V

NC
RC0/VLCD1
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI

SS

V
VDD
RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS
RA4/C1OUT/T0CKI/SEG4

/SDO/SEG11

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G

RD3/SEG16

RD2/CCP2

RD1

4443424140

1
2
3
4
5
6
7
8
9
10
11

121314

39

PIC16F914/917

16

17

15

/SEG5

RD0/COM3

RC3/SEG6

RC2/VLCD3

RC1/VLCD2

RC0/VLDC1

363435

37

38

33
32
31
30
29
28
27
26
25
24

23

1819202122

RA6/OSC2/CLK0/T1OSO
RA7/OSC1/CLKI/T1OSI
V

SS

VSS
NC
V

DD

RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS
RA4/C1OUT/T0CKI/SEG4

/SEG5

NC

RB3/SEG3

RB4/COM0

RB5/COM1

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

REF-/COM2

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/V

REF+/SEG15

RA3/AN3/C1+/V

RE3/MCLR/VPP

DS41250D-page 4 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 7

2.0 Memory Organization................................................................................................................................................................. 13

3.0 I/O Ports............................................................................... ..................... .................................................................................31

4.0 Clock Sources............................................................................................................................................................................ 69

5.0 Timer0 Module ........................................................................................................................................................................... 81

6.0 Timer1 Module With Gate Control. ............................................................................................................................................. 85

7.0 Timer2 Module ........................................................................................................................................................................... 90

8.0 Comparator Module.................................................................................................................................................................... 93

9.0 Liquid Crystal Display (LCD) Driver Module............................................................................. .. .............................................. 101

10.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................ 125

11.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT ).............................................................. 127

12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 143

13.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 153

14.0 SSP Module Overview .............................................................................................................................................................159

15.0 Capture/Compare/PWM Modules .................................................................................... .... .... .. .............................................. 177

16.0 Special Features of the CPU.................................................... ..................... ........................................................................... 185

17.0 Instruction Set Summary.......................................................................................................................................................... 205

18.0 Development Support............................................................................................................................................................... 215

19.0 Electrical Specifications............................................................................................................................................................ 221

20.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 247

21.0 Packaging Information. ..................... ..................... ..................... ..................... ......................................................................... 249

Appendix A: Data Sheet Revision History.......................................................................................................................................... 259

Appendix B: Migrating From Other PICmicro® Devices .................................................................................................................... 259

Appendix C: Conversion Considerations ....................................... .... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .................................................. 260

Index .................................................................................................................................................................................................. 261

On-line Support.................................................................................................................................................................................. 269

Systems Information and Upgrade Hot Line...................................................................................................................................... 269

Reader Response..............................................................................................................................................................................270

Product Identification System ............................................................................................................................................................ 271

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© 2005 Microchip Technology Inc. Preliminary DS41250D-page 5

PIC16F917/916/914/913

NOTES:

DS41250D-page 6 Preliminary © 2005 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the PIC16F91X. Addition al informatio n may be found i n
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023), downloaded from the Microchip
web site. The Reference Ma nu al should be consi dered
a complementary document to this data sheet and is
highly recommended reading for a better
understanding of the dev ice arc hitecture and operatio n
of the peripheral modules.

The PIC16F91X devices are covered by this data
sheet. It is available in 28/40/44-pin packages.

PIC16F917/916/914/913

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 7

PIC16F917/916/914/913

5

FIGURE 1-1: PIC16F913/916 BLOCK DIAGRAM

INT

Program Counter

(PRM)

Direct Addr

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSS

Data Bus

RAM

256/352 bytes

Registers

Addr MUX

7

Status Reg

3

ALU

8

W Reg

Program

Bus

OSC1/CLKI

OSC2/CLKO

Internal

Oscillator

Block

Configuration

Flash

4k/8k x 14

Program

Memory

14

Instruction Reg

Instruction

Decode and

Control

Timing

Generation

13

8-Level Stack (13-bit)

Program Memory Read

8

Start-up Timer

VDD

File

RAM Addr

9

8

FSR Reg

MUX

Indirect

Addr

8

PORTA

PORTB

PORTC

PORTE

RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/V
RA3/AN3/C1+/V
RA4/C1OUT/T0CKI/SEG4
RA5/AN4
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI

RB0/INT/SEG0
RB1/SEG1
RB2/SEG2
RB3/SEG3
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RC4/T1G
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC7/RX/DT/SDI/SDA/SEG8

RE3/MCLR

REF-/COM2
REF+/COM3/SEG1

/C2OUT/SS/SEG5

/SDO/SEG11

/VPP

Data EEPROM

Timer0

Comparators

Timer1 Timer2 10-bit A/D

CCP1 SSP

Addressable

USART

256 bytes

BOR

PLVD

LCD

DS41250D-page 8 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

3

FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM

INT

Program Counter

8-Level Stack (13-bit)

(PRM)

Direct Addr

Power-up

Timer

Oscillator

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VSS

Data Bus

256/352 bytes

Registers

Addr MUX

7

3

ALU

8

W Reg

Program

OSC1/CLKI

OSC2/CLKO

Internal

Oscillator

Block

Configuration

4k/8k x 14

Bus

Instruction Reg

Decode and

Flash

Program

Memory

14

Instruction

Control

Timing

Generation

13

Program Memory Read

8

Start-up Timer

VDD

RAM

File

RAM Addr

9

8

FSR Reg

Status Reg

MUX

Indirect

Addr

8

PORTA

PORTB

PORTC

PORTD

RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/V
RA3/AN3/C1+/V
RA4/C1OUT/T0CKI/SEG4
RA5/AN4
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI

RB0/INT/SEG0
RB1/SEG1
RB2/SEG2
RB3/SEG3
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG1

RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RC4/T1G
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC7/RX/DT/SDI/SDA/SEG8

RD0/COM3
RD1
RD2/CCP2
RD3/SEG16
RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20

REF-/COM2
REF+/SEG15

/C2OUT/SS/SEG5

/SDO/SEG11

Timer0

Comparators

Timer1 Timer2 10-bit A/D

CCP1

CCP2 SSP

Addressable

USART

PORTE

BOR

RE0/AN5/SEG21
RE1/AN6/SEG22
RE2/AN7/SEG23
RE3/MCLR

PLVD LCD

/VPP

Data EEPROM

256 bytes

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 9

PIC16F917/916/914/913

TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS

Name Function

RA0/AN0/C1-/SEG12 RA0 TTL CMOS General purpose I/O.

AN0 AN — Analog input Channel 0/C o m parator 1 input – negative.

C1- — AN Comparator 1 negative input.

SEG12 — AN LCD analog ou t put.

RA1/AN1/C2-/SEG7 RA1 TTL CMOS General purpose I/O.

AN1 AN — Analog input Channel 1/C o m parator 2 input – negative.

C2- — AN Comparator 2 negative input.

SEG7 — AN LCD analog output.

RA2/AN2/C2+/V

RA3/AN3/C1+/V
SEG15

RA4/C1OUT/T0CKI/SEG4 RA4 TTL CMOS General purpose I/O.

RA5/AN4/C2OUT/SS

RA6/OSC2/CLKO/T1OSO RA6 T TL CMOS General purpose I/O.

RA7/OSC1/CLKI/T1OSI RA7 TTL CMOS General purpose I/O.

RB0/INT/SEG0 RB0 TTL CMOS General purpose I/O. Individually enabled pull-up.

RB1/SEG1 RB1 TTL CMOS General purpose I/O. Individually enabled pull-up.

Legend: AN = Analog input or output CMOS = CMOS compatible input or ou t put D = Direct

Note 1: COM 3 i s av ai labl e on RA3 for the PIC16F913 /916 and on RD0 for the PIC16F 914/917.

2: Pins available on PIC16F914/917 only.

REF-/COM2 RA2 TTL CMOS General purpose I/O.

AN2 AN — Analog input Channel 2/Comparator 2 input – positive.
C2+ — AN Comparator 2 positive input.

REF- AN — External Voltage Reference – negative.

V

COM2 — AN LCD analog output.

REF+/COM3

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal

(1)

/

RA3 TTL CMOS General purpose I/O.
AN3 AN — Analog input Channel 3/Comparator 1 input – positive.
C1+ — AN Comparator 1 positive input.

REF+ AN — External Voltage Reference – positive.

V

COM3

SEG15 — AN LCD analog ou t put.

C1OUT — CMOS Comparator 1 out p ut .

T0CKI ST — Timer0 clock input.

SEG4 — AN LCD analog output.

/SEG5 RA5 TTL CMOS General purpose I/O.

AN4 AN — Analog input Channel 4.

C2OUT — CMOS Comparator 2 out p ut .

SS

SEG5 — AN LCD analog output.

OSC2 — XTAL Crystal/Resonator.
CLKO — CMOS T

T1OSO — XTAL Timer1 oscillator output.

OSC1 XTAL — Cr ystal/Resonator.

CLKI ST — Clock input.

T1OSI XTAL — Timer1 oscilla to r inpu t.

INT ST — External interrupt pin.

SEG0 — AN LCD analog output.

SEG1 — AN LCD analog output.

Input

(1)

Output

Type

TTL — Slave select input.

Type

— AN LCD analog output.

OSC/4 reference clock.

Description

DS41250D-page 10 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)

Input

Name Function

RB2/SEG2 RB2 TTL CMOS General purpose I/O. Individually enabled pull-up.

SEG2 — AN LCD analog output.

RB3/SEG3 RB3 TTL CMOS General purpose I/O. Individually enabled pull-up.

SEG3 — AN LCD analog output.

RB4/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

COM0 — AN LCD analog output.

RB5/COM1 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

COM1 — AN LCD analog output.

RB6/ICSPCLK/ICDCK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

ICSPCLK ST — ICSP™ clock.

ICDCK ST — ICD clock I/O.
SEG14 — AN LCD analog ou t put.

RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

ICSPDAT ST CMOS ICSP Data I/O.

ICDDAT ST CMOS ICD Data I/O.

SEG13 — AN LCD analog ou t put.

RC0/VLCD1 RC0 ST CMOS General purpose I/O.

VLCD1 AN — LCD analog input.

RC1/VLCD2 RC1 ST CMOS General purpose I/O.

VLCD2 AN — LCD analog input.

RC2/VLCD3 RC2 ST CMOS General purpose I/O.

VLCD3 AN — LCD analog input.

RC3/SEG6 RC3 ST CMOS General purpose I/O.

SEG6 — AN LCD analog output.

RC4/T1G

RC5/T1CKI/CCP1/SEG10 RC5 ST CMOS General purpose I/O.

RC6/TX/CK/SCK/SCL/SEG9 RC6 ST CMOS General purpose I/O.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct

Note 1: COM 3 i s av ai labl e on RA3 for the PIC16F913 /916 and on RD0 for the PIC16F 914/917.

/SDO/SEG11 RC4 ST CMOS General purpose I/O.

T1G ST — Timer1 gate inp ut .

SDO — CMOS Serial data output.

SEG11 — AN LCD analog output.

T1CKI ST — Timer1 clock input.

CCP1 ST CMO S C apture 1 input/Compare 1 output / PW M 1 output.

SEG10 — AN LCD analog ou t put.

TX — CM O S U SART asynchronous seria l transm i t .

CK ST CMOS US ART synchronous se rial cl ock.

SCK ST CMOS SPI™ cl ock.

SCL ST CMOS I

SEG9 — AN LCD analog output.

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal

2: Pins available on PIC16F914/917 only.

Type

Output

Type

Description

change. Individually enabled pull-up.

change. Individually enabled pull-up.

change. Individually enabled pull-up.

change. Individually enabled pull-up.

2

C™ clock.

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 11

PIC16F917/916/914/913

TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)

Name Function

Input

RC7/RX/DT/SDI/SDA/SEG8 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous serial receiv e.
DT ST CM O S USART synchronou s se ri al data.

SDI ST CMOS SPI™ da ta input.

SDA ST CMOS I

SEG8 — AN LCD analog output.

RD0/COM3

(1, 2)

RD0 ST CMOS General purpose I/O.

COM3 — AN LCD analog output.

(2)

RD1
RD2/CCP2

(2)

RD1 ST CMOS General purpose I/O.
RD2 ST CMOS General purpose I/O.

CCP2 ST CMO S C apture 2 input/Compare 2 output / PW M 2 output.

RD3/SEG16

(2)

RD3 ST CMOS General purpose I/O.

SEG16 — AN LCD analog ou t put.

RD4/SEG17

(2)

RD4 ST CMOS General purpose I/O.

SEG17 — AN LCD analog ou t put.

RD5/SEG18

(2)

RD5 ST CMOS General purpose I/O.

SEG18 — AN LCD analog ou t put.

RD6/SEG19

(2)

RD6 ST CMOS General purpose I/O.

SEG19 — AN LCD analog ou t put.

RD7/SEG20

(2)

RD7 ST CMOS General purpose I/O.

SEG20 — AN LCD analog ou t put.

RE0/AN5/SEG21

(2)

RE0 ST CMOS General purpose I/O.
AN5 AN — Analog input Channel 5.

SEG21 — AN LCD analog ou t put.

RE1/AN6/SEG22

(2)

RE1 ST CMOS General purpose I/O.
AN6 AN — Analog input Channel 6.

SEG22 — AN LCD analog ou t put.

RE2/AN7/SEG23

(2)

RE2 ST CMOS General purpose I/O.
AN7 AN — Analog input Channel 7.

SEG23 — AN LCD analog ou t put.

RE3/MCLR

/VPP RE3 ST — Digital input only.

MCLR ST — M aster Clear with internal pull-up.

PP HV — Programming voltage.

V

VDD VDD D — Power supply for microcontroller.

SS VSS D — Ground reference for mi cr ocontroller.

V
Legend: AN = Analog input or output CMOS = CMOS compatible input or ou t put D = Direct

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal

Note 1: COM 3 i s av ai labl e on RA3 for the PIC16F913 /916 and on RD0 for the PIC16F 914/917.

2: Pins available on PIC16F914/917 only.

Type

Output

Type

2

C™ data.

Description

DS41250D-page 12 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F917/916/914/913 has a 13-bit program
counter capable of addressing a 4k x 14 program
memory space for the PIC16F913/914 (0000h-0FFFh)
and an 8k x 14 program memory space for the
PIC16F916/917 (0000h-1FFFh). Accessing a location
above the memory boundaries for the PIC16F913 and
PIC16F914 will cause a wrap around within the first 4k x
14 space. The Reset vector is at 0000h and the interrupt
vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F913/914

pc<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

13

0000h

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F916/917

pc<12:0>

CALL, RETURN
RETFIE, RETLW

On-chip

Program

Memory

Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

Page 0

Page 1

Page 2

Page 3

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

17FFh
1800h

1FFFh

On-chip

Program

Memory

Interrupt Vector

Page 0

Page 1

0004h
0005h

07FFh
0800h

0FFFh
1000h

1FFFh

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 13

PIC16F917/916/914/913

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.

RP0 RP1 (STATUS<6:5>)
= 00: → Bank 0
= 01: → Bank 1
= 10: → Bank 2
= 11: → Bank 3
Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 256x 8 in the
PIC16F913/914 and 352 x 8 in the PIC16F916/917.
Each register is accessed either directly or indirectly
through the File Select Register (FSR) (see Section 2.5
“Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1,

2-2, 2-3 and 2-4). These registers are static RAM.

The special re gisters can be classifi ed into two sets:
core and peripheral. The Special Function Registers
associated with the “c ore” are des cribed in this sect ion.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.

DS41250D-page 14 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS

File File File File
Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 8 3h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h LCDCON 107h 187h

PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh

TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh

T1CON 10h OSCTUNE 90h LCDDATA0 110h

TMR2 11h ANSEL 91h LCDDATA1 111h

T2CON 12h PR2 92h

SSPBUF 13h SSPADD 93h LCDDATA3 113h

SSPCON 14h SSPSTAT 94h LCDDATA4 114h

CCPR1L 15h WPUB 95h

CCPR1H 16h IOCB 96h LCDDATA6 116h

CCP1CON 17h CMCON1 97h LCDDATA7 117h

RCSTA 18h TXSTA 98h

TXREG 19h SPBRG 99h LCDDATA9 119h

RCREG 1Ah

ADRESH 1Eh ADRESL 9Eh
ADCON0 1Fh ADCON1 9Fh

(1)

00h Indirect addr.

08h 88h LCDPS 108h 188h

1Bh 9Bh 11Bh
1Ch CMCON0 9Ch LCDSE0 11Ch
1Dh VRCON 9Dh LCDSE1 11Dh

20h

(1)

80h Indirect addr.

9Ah LCDDATA10 11Ah

A0h

(1)

100h Indirect addr.

EECON2

112h

115h

118h

Purpose

Register

96 Bytes

11Eh
11Fh
120h

General

(2)

(1)

(1)

180h

185h

18Dh
18Eh

190h

General

General
Purpose
Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F913, unimplemented data memory locations, read as ‘0’.

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 15

Purpose
Register

80 Bytes

accesses

70h-7Fh

EFh 16Fh 1EFh
F0h accesses

General
Purpose
Register

80 Bytes

70h-7Fh

170h accesses

70h-7Fh

1F0h

PIC16F917/916/914/913

FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS

File File File File
Address Address Address Address

Indirect addr.

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 8 3h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h LCDCON 107h 187h
PORTD 08h TRISD 88h LCDPS 108h

PORTE 09h TRISE 89h LVDCON 109h 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h

TMR2 11h ANSEL 91h LCDDATA1 111h

T2CON 12h PR2 92h LCDDATA2 112h

SSPBUF 13h SSPADD 93h LCDDATA3 113h

SSPCON 14h SSPSTAT 94h LCDDATA4 114h

CCPR2L 15h WPUB 95h LCDDATA5 115h

CCPR2H 16h IOCB 96h LCDDATA6 116h

CCP2CON 17h CMCON1 97h LCDDATA7 117h

RCSTA 18h TXSTA 98h LCDDATA8 118h
TXREG 19h SPBRG 99h LCDDATA9 119h

RCREG 1Ah

CCPR2L 1Bh 9Bh LCDDATA11 11Bh

CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch

CCPR2CON 1Dh VRCON 9Dh LCDSE1 11Dh

ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh
ADCON0 1Fh ADCON1 9Fh

(1)

00h Indirect addr.

20h

(1)

80h Indirect addr.

9Ah LCDDATA10 11Ah

A0h

(1)

100h Indirect addr.

EECON2

Purpose

Register

96 Bytes

11Fh
120h

General

(2)

(1)

(1)

180h

185h

188h

18Dh
18Eh

190h

General
General
Purpose
Register

96 Bytes

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F914, unimplemented data memory locations, read as ‘0’.

DS41250D-page 16 Preliminary © 2005 Microchip Technology Inc.

Purpose
Register

80 Bytes

accesses

70h-7Fh

EFh 16Fh 1EFh
F0h accesses

General
Purpose
Register

80 Bytes

70h-7Fh

170h accesses

70h-7Fh

1F0h

PIC16F917/916/914/913

TABLE 2-1: PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
08h PORTD
09h PORTE
0Ah PCLATH
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1
0Dh PIR2
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
11h TMR2
12h T2CON
13h SSPBUF Synchron ous Seri al Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP S SPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

(2)

1Bh

(2)

1Ch

(2)

1Dh
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG1 V CFG0 CHS2 CHS1 CHS0 GO/DONE

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

(2)

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

— — — —RE3RE2
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF 0000 -0-0 0000 -0-0

Timer2 Module Register 0000 0000 0000 0000

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

2: PIC16F914/917 only.

Reset and Watchdog Timer Reset dur ing nor mal operation.

PD ZDCC0001 1xxx 000q quuu

(2)

(2)

RE1

TMR1CS TMR1ON 0000 0000 uuuu uuuu

RE0

ADON 0000 0000 0000 0000

Value on

POR/BOR

Reset

(2)

---- xxxx ---- uuuu

Value on

all other

Resets

(1)

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 17

PIC16F917/916/914/913

TABLE 2-2: PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical

81h OPTION_REG RBPU
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h S TATUS IRP RP1 RP0 TO
84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h TRISD
89h TRISE
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE
8Eh PCON
8Fh OSCCON
90h OSCTUNE
91h ANSEL ANS7
92h PR2 Timer2 Peri od Regi ster 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4
97h CMCON1
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
9Dh VRCON VREN
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

(2)

2: PIC 16F 91 4/9 17 only.
3: PIC 16F 91 4/9 17 only, forced ‘0’ on PIC16F91 3/9 16.
4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.0 “Clock

Sources”.

5: Bit is read-only; TRISE = 1 always.

register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

— — — — TRISE3
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

— — —SBOREN— —PORBOR ---1 --qq ---u --uu
— IRCF2 IRCF1 IRCF0 OSTS
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(3)

— — — — — — T1GSS C2SYNC ---- --10 ---- --10

— ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---

(3)

ANS6

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

(3)

ANS5

2

ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

C mode) Address Register 0000 0000 0000 0000

PSR/WUA BF 0000 0000 0000 0000

Reset and Watchdog Timer Reset during normal operation.

(5)

—LVDIE— CCP2IE 0000 -0-0 0000 -0-0

(4)

— — — — 0000 ---- 0000 ----

— BRGH TRMT TX9D 0000 -010 0000 -010

(2)

TRISE2

HTS LTS SCS -110 q000 -110 x000

TRISE1

(2)

TRISE0

Value on

POR/BOR

Reset

xxxx xxxx xxxx xxxx

(2)

---- 1111 ---- 1111

Value on
all other

Resets

(1)

DS41250D-page 18 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

TABLE 2-3: PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h STATUS IRP RP1 RP0 TO
104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h WDTCON
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000
109h LVDCON
10Ah PCLATH
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000

10Ch

EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000

10Dh
10Eh EEDATH
10Fh EEADRH
110h LCDDATA0 SEG7

111h LCDDATA1 SEG15

112h LCDDATA2

113h LCDDATA3 SEG7

114h LCDDATA4 SEG15

115h LCDDATA5

116h LCDDATA6 SEG7

117h LCDDATA7 SEG15

118h LCDDATA8

119h LCDDATA9 SEG7

11Ah LCDDATA10 SEG15

LCDDATA11

11Bh

11Ch LCDSE0
11Dh LCDSE1
11Eh LCDSE2
11Fh — Unimplemented — —

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

(3)
(3)
(2,3)

2: PIC16F914/917 only.
3: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -100 --00 -100
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

— —
— — —

COM0

COM0

(2)

SEG23

COM0

COM1

COM1

(2)

SEG23

COM1

COM2

COM2

(2)

SEG23

COM2

COM3

COM3

(2)

SEG23

COM3

SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu

SEG6

COM0

SEG14

COM0

SEG22

COM0

SEG6

COM1

SEG14

COM1

SEG22

COM1

SEG6

COM2

SEG14

COM2

SEG22

COM2

SEG6

COM3

SEG14

COM3

SEG22

COM3

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

SEG5

COM0

SEG13

COM0

SEG21

COM0

SEG5

COM1

SEG13

COM1

SEG21

COM1

SEG5

COM2

SEG13

COM2

SEG21

COM2

SEG5

COM3

SEG13

COM3

SEG21

COM3

SEG4

COM0

SEG12

COM0

SEG20

COM0

SEG4

COM1

SEG12

COM1

SEG20

COM1

SEG4

COM2

SEG12

COM2

SEG20

COM2

SEG4

COM3

SEG12

COM3

SEG20

COM3

Reset and Watchdog Timer Reset dur ing nor mal operation.

PD ZDCC0001 1xxx 000q quuu

SEG3

COM0

SEG11

COM0

SEG19

COM0

SEG3

COM1

SEG11

COM1

SEG19

COM1

SEG3

COM2

SEG11

COM2

SEG19

COM2

SEG3

COM3

SEG11

COM3

SEG19

COM3

SEG2

COM0

SEG10

COM0

SEG18

COM0

SEG2

COM1

SEG10

COM1

SEG18

COM1

SEG2

COM2

SEG10

COM2

SEG18

COM2

SEG2

COM3

SEG10

COM3

SEG18

COM3

SEG1

COM0

SEG9

COM0

SEG17

COM0

SEG1

COM1

SEG9

COM1

SEG17

COM1

SEG1

COM2

SEG9

COM2

SEG17

COM2

SEG1

COM3

SEG9

COM3

SEG17

COM3

SEG0

COM0

SEG8

COM0

SEG16

COM0

SEG0

COM1

SEG8

COM1

SEG16

COM1

SEG0

COM2

SEG8

COM2

SEG16

COM2

SEG0

COM3

SEG8

COM3

SEG16

COM3

Value on

POR/BOR

Reset

--00 0000 --00 0000

---0 0000 ---0 0000

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Value on

all other

Resets

(1)

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 19

PIC16F917/916/914/913

TABLE 2-4: PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical

181h OPTION_REG RBPU
182h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h STATUS IRP RP1 RP0 TO
184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h

186h TRISB
187h
188h
189h
18Ah PCLATH
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
18Ch EECON1 EEPGD
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR

— Unimplemented — —

— Unimplemented — —
— Unimplemented — —
— Unimplemented — —

register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

— — —

— — —

Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

WRERR WREN WR RD 0--- x000 0--- q000

Reset and Watchdog Timer Reset dur ing nor mal operation.

Value on

POR/BOR

Reset

xxxx xxxx xxxx xxxx

Value on

all other

Resets

(1)

DS41250D-page 20 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

2.2.2.1 Status Register

The Status register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM)
The Status register can be the destination for any

instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. Thi s leav es the Status register as
‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Stat us register , beca use these instru ctions do not af fect
any Status bits. For other instructions not affecting any
Status bits (see Section 17.0 “Instruction Set

Summary”).

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.

REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h OR 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7

bit 6-5

bit 4

bit 3

bit 2

bit 1

bit 0

IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)

RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)

TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow,

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.

the polarity is reversed. A subtraction is executed by adding the two’s

(1)

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 21

PIC16F917/916/914/913

2.2.2.2 Option Register

The Option register is a readable and writable register,
which contains various control bits to configure:

• TMR0/WDT prescaler

• External RB0/INT interrupt

•TMR0

• Weak pull-ups on PORTB

REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU

bit 7 bit 0

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION_REG<3>).
See Section 5.4 “Prescaler”.

bit 7 RBPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RB0/INT/SEG0 pin
0 = Interrupt on falling edge of RB0/INT/SEG0 pin

1 = Transition on RA4/C1OUT/T0CKI/SEG4 pin
0 = Internal instruction cycle clock (CLKO)

1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin
0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

Bit Va lue TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41250D-page 22 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

2.2.2.3 INTCON Register

The INTCON register is a readable and writable
register , which c ontains the various en able and fl ag bit s
for TMR0 register overflow, PORTB change and
external RB0/INT/SEG0 pin interrupts.

Note: Interrupt flag bits are set when an interr upt

condition occurs, regard less of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.

REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh OR

18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 in terrupt

bit 4 INTE: RB0/INT/SEG0 External Interrupt Enable bit

1 = Enables the RB0/INT/SEG0 external interrupt
0 = Disables the RB0/INT/SEF0 external interrupt

bit 3 RBIE: PORTB Change Interrupt Enable bit

1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT/SEG0 External Interrupt Flag bit

1 = The RB0/INT/SEG0 external interrupt occurred (must be cleared in software)
0 = The RB0/INT/SEG0 external interrupt did not occur

bit 0 RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB <5:0> pins changed state (must be cleared in software)
0 = None of the PORTB <7:4> pins have changed state

Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing T0IF bit.

(1)

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 23

PIC16F917/916/914/913

2.2.2.4 PIE1 Regi st er

The PIE1 register contai ns th e in terru pt enable bits, as
shown in Register 2-1.

REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enabled
0 = Disabled

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enabled
0 = Disabled

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41250D-page 24 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

2.2.2.5 PIE2 Regi st er

The PIE2 register contai ns th e in terru pt enable bits, as
shown in Register 2-5.

REGISTER 2-5: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
OSFIE C2IE C1IE LCDIE —LVDIE— CCP2IE

bit 7 bit 0

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 =Disabled

bit 6 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables Comparator 2 interrupt
0 = Disables Comparator 2 interrupt

bit 5 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables Comparator 1 interrupt
0 = Disables Comparator 1 interrupt

bit 4 LCDIE: LCD Module Interrupt Enable bit

1 = LCD interrupt is enabled
0 = LCD interrupt is disabled

bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit

1 = Enables LVD Interrupt
0 = Disables L VD Inte rrup t

bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit (only available in 16F914/917)

1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 25

PIC16F917/916/914/913

2.2.2.6 PIR1 Register

The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.

REGISTER 2-6: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 EEIF: EE Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not started

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = The A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Interrupt Flag bit

1 = A TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = The TMR 1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41250D-page 26 Preliminary © 2005 Microchip Technology Inc.

PIC16F917/916/914/913

2.2.2.7 PIR2 Register

The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.

REGISTER 2-7: PIR2 – PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh)

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 U-0 R/W-0
OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF

bit 7 bit 0

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input ha s changed to INT OSC (must be c leared in s oftware)
0 = System clock operating

bit 6 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed

bit 5 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed

bit 4 LCDIF: LCD Module Interrupt bit

1 = LCD has generated an interrupt
0 = LCD has not generated an int errupt

bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit

1 = LVD has generated an interrupt
0 = LVD has not generated an interrupt

bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit (only available in 16F914/917)

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2005 Microchip Technology Inc. Preliminary DS41250D-page 27

PIC16F917/916/914/913

2.2.2.8 PCON Regist er

The Power Control (PCON) register (See Table 17-2)
contains flag bit s to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR
The PCON register also control s the software enable of

the BOR.
The PCON register bits are shown in Register 2-8.

REGISTER 2-8: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)

bit 7-5 Unimplemented: Read as ‘0’
bit 4 SBOREN: Software BOR Enable bit

bit 3-2 Unimplemented: Read as ‘0’
bit 1 POR

bit 0 BOR

)

Reset

U-0 U-0 U-0 R/W-1 U-0 U-0 R/W-0 R/W-x

— — — SBOREN — —PORBOR

bit 7 bit 0

(1)

1 = BOR enabled
0 = BOR disabled

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01 in the Configuration Word regi ster for this bit to c ontrol the BOR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

.

DS41250D-page 28 Preliminary © 2005 Microchip Technology Inc.