MICROCHIP PIC12F609, PIC12HV609, PIC12F615, PIC12HV615 User Manual

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin C ount Patent: U .S. Patent N o. 5,847,450. Addit ional U.S. and

查询PIC12F609-E/MD供应商

PIC12F609/HV609
PIC12F615/HV615

Data Sheet

8-Pin Flash-Based, 8-Bit

CMOS Microcontrollers

foreign patents and applications m ay be issued or pending.

© 2006 Microchip Technology Inc. Preliminary DS41302A

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MAT E, Pow erSm art , rfPIC and SmartS hunt are
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Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

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ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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All other trademarks mentioned herein are property of their
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© 2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC
8-bit MCUs, KEELOQ
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.

®

code hopping devices, Serial EEPROMs,

DS41302A-page ii Preliminary © 2006 Microchip Technology Inc.

®

PIC12F609/615/12HV609/615

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instr uction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency: 4 MHz or
8 MHz

• Power-Saving Sleep mode

• Volt age range:

- PIC12F609/615: 2.0V to 5.5V

- PIC12HV609/615: 2.0V to user defined
maximum (see note)

• Industrial and Extended Temperature range

• Power-on Reset (PO R)

• Power-up Time r (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Reset (BOR)

• Watchdog Timer (WDT) with independent
oscillator for reliable operation

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High Endurance Flash:

- 100,000 write Flash endurance

- Flash r etention: > 40 years

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

-11μA @ 32 kHz, 2.0V, typical

-260μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• Shunt Voltage Regulator (PIC12HV609/615 only):

- 5 volt regulation

- 4 mA to 50 mA shunt range

• 5 I/O pins and 1 input only

• High current source/sink for direct LED drive

- Interrupt-on-pin change or pins

- Individually programmable weak pull-ups

• Analog Comparator module with:

- One analog comparator

- Programmable on-chip voltage reference
(CV

REF) module (% of VDD)

- Comparator inputs and output externally
accessible

- Built-In Hysteresis (software selectable)

• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (cou nt enab le )

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode
selected

- Option to use system clock as Timer1

TM

• In-Circuit Serial Programming
pins

PIC12F615/HV615 ONLY:

• Enhanced Capture, Compare, PWM module:

- 16-bit Capture, max. resolution 12.5 ns

- Compare, max. resolution 200 ns

- 10-bit PWM with 1 or 2 output channels, 1

output channel programmable “dead time”,
max. frequency 20 kHz, auto-shutdown

• A/D Converter:

- 10-bit resolution and 4 channels, samples

internal voltage references

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

(ICSPTM) via two

Note: Voltage across the shunt regulator should

not exceed 5V.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 1

PIC12F609/615/12HV609/615

Program Memory Data Memory

Device

PIC12F609 1024 64 5 0 1 1/1 2.0V-5.5V
PIC12HV609 1024 64 5 0 1 1/1 2.0V-user defined
PIC12F615 1024 64 5 4 1 2/1 2.0V-5.5V
PIC12HV615 1024 64 5 4 1 2/1 2.0V-user defined

Flash

(words)

SRAM (bytes)

I/O

10-bit A/D

(ch)

Comparators

Timers

8/16-bit

Voltage Range

8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, TSSOP, DFN)

GP5/T1CKI/OSC1/CLKIN

GP4/CIN1-/T1G

/OSC2/CLKOUT

GP3/MCLR

VDD

/VPP

1
2

PIC12F609/

HV609

3
4

TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN)

I/O Pin Comparators Timer Interrupts Pull-ups Basic

GP0 7 CIN+ — IOC Y ICSPDAT
GP1 6 CIN0- — IOC Y ICSPCLK
GP2 5 COUT T0CKI INT/IOC Y —

GP3

(1)

4—
GP4 3 CIN1- T1G IOC Y OSC2/CLKOUT
GP5 2 — T1CKI IOC Y OSC1/CLKIN

— 1 — — — — VDD
—8— ——— VSS

Note 1: Input only.

2: Only when pin is configured for external MCLR.

—

IOC Y

V

8
7
6
5

SS

GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT

(2)

MCLR/VPP

DS41302A-page 2 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

8-Pin Diagram, PIC12F615/HV615 (PDIP, SOIC, TSSOP, DFN)

VDD

GP5/T1CKI/P1A*/OSC1/CLKIN

GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT

GP3/T1G

* Alternate pin function.

*/MCLR/VPP

1
2

PIC12F615/

HV615

3
4

V

8
7
6
5

SS

GP0/AN0/CIN+/P1B/ICSPDA T
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A

T ABLE 2: PIC12F615/HV615 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN)

I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic

GP0 7 AN0 CIN+ — P1B IOC Y ICSPDAT
GP1 6 AN1 CIN0- — — IOC Y ICSPCLK/VREF
GP2 5 AN2 COUT T0CKI CCP1/P1A INT/IOC Y —

(1)

GP3
GP4 3 AN3 CIN1- T1G P1B* IOC Y OSC2/CLKOUT
GP5 2 — — T1CKI P1A* IOC Y OSC1/CLKIN

— 1 — — — — — — VDD
—8 — — — — — — VSS

Note 1: Input only.

4— — T1G*— IOCY

* Alternate pin function.

2: Only when pin is configured for external MCLR

.

(2)

MCLR/VPP

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 3

PIC12F609/615/12HV609/615

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................... 9

3.0 Oscillator Module........................................................................................................................................................................ 25

4.0 I/O Ports................. ....................................................................................................................................................................31

5.0 Timer0 Module ........................................................................................................................................................................... 41

6.0 Timer1 Module with Gate Control.............................................................. .................................................................................45

7.0 Timer2 Module (PIC12F615/HV615 only).......................................................................... ........................................................51

8.0 Comparator Module....................................................................................................................................................................53

9.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/HV615 only) ....................................................................................... 65

10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)........................ 75

11.0 Special Features of the CPU....................................... ............................................................................................................... 93

12.0 Voltage Regulator............................................................................. .. .. .. .. .. ....... .. .. .. .. .. .. ........................................................... 111

13.0 Instruction Set Summary.......................................................................................................................................................... 113

14.0 Development Support. ..............................................................................................................................................................123

15.0 Electrical Specifications............................................................................................................................................................ 127

16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................149

17.0 Packaging Information..................................................... ......................................................................................................... 151

Appendix A: Data Sheet Revision History..........................................................................................................................................157

Appendix B: Migrating from other PIC® Devices...............................................................................................................................157

Index ........................................................................... ... .................................................................................................................... 159

The Microchip Web Site..................................................................................................................................................................... 163

Customer Change Notification Service ..................................... ...... ............. ...... ............... ...... ........................................................... 163

Customer Support.............................................................................................................................................................................. 163

Reader Response............................................................................ .................................................................................................. 164

Product Identification System............................................................................................................................................................. 165

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DS41302A-page 4 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

1.0 DEVICE OVERVIEW

Block Diagrams and pinout descriptions of the devices
are as follows:

The PIC12F609/615/12HV609/615 devices are covered
by this data sheet. They are available in 8-pin PDIP,
SOIC, TSSOP and DFN packages.

• PIC12F609/HV609 (Figure1-1, Table 1-1)

• PIC12F615/HV615 (Figure1-2, Table 1-2)

FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM

13

Program Counter

8-Level Stack

Direct Addr

INT

(13-Bit)

RAM Addr

7

Program

Bus

Configuration

Flash

1K X 14

Program

Memory

14

Instruction Reg

8

Data Bus

RAM

64 Bytes

File

Registers

Addr MUX

STATUS Reg

9

8

FSR Reg

Indirect

Addr

8

GPIO

GP0
GP1
GP2
GP3
GP4
GP5

OSC1/CLKIN

OSC2/CLKOUT

T1G

T1CKI

T0CKI

Internal

Oscillator

Block

Instruction

Decode &

Control

Timing

Generation

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VDD

MCLR

Timer0 Timer1

Comparator Voltage Reference

Absolute Voltage Reference

VSS

3

ALU

8

W Reg

Shunt Regulator

(PIC12HV609 only)

MUX

Analog Comparator

and Reference

CIN+

CIN0-

CIN1-

COUT

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 5

PIC12F609/615/12HV609/615

FIGURE 1-2: PIC12F615/HV615 BLOCK DIAGRAM

OSC1/CLKIN

OSC2/CLKOUT

T1G*

T1G

Program

Bus

Internal

Oscillator

Block

Configuration

Flash

1K X 14

Program

Memory

14

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

13

8

MCLR

INT

Program Counter

8-Level Stack

(13-Bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

VDD

VSS

7

RAM Addr

3

8

Data Bus

RAM

64 Bytes

File

Registers

9

Addr MUX

Indirect

8

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Shunt Regulator

(PIC12HV615 only)

8

GPIO

GP0
GP1
GP2
GP3
GP4
GP5

T1CKI

T0CKI

VREF

Analog-To-Digital Converter

AN0

AN1

AN2

AN3

* A lte rn ate pi n func ti on.

Timer0 Timer1

Comparator Voltage Reference

Absolute Voltage Reference

Timer2

Analog Comparator

and Reference

CIN1-

COUT

ECCP

CIN+

CIN0-

CCP1/P1A

P1B

P1A*

P1B*

DS41302A-page 6 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION

Name Function

GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

CIN+ AN — Comparator non-inverting input

ICSPDAT ST CMOS Serial Programming Data I/O

GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and int errupt-on-c hange

CIN0- AN — Comparator inverting input

ICSPCLK ST — Serial Programming Clock

GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change

T0CKI ST — Timer0 clock input

INT ST — External Interrupt

COUT — CMOS Comparator output

CLR/VPP GP3 TTL — General purpose input with interrupt-on-change

GP3/M

MCLR

PP HV — Programming voltage

V

GP4/CIN1-/T1G
CLKOUT

GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt -on-c hange

DD VDD Power — Positive supply

V

SS VSS Power — Ground reference

V
Legend: AN = Analog input or output CMOS= CMOS com patible input or output HV = High Voltage

/OSC2/

ST = Schmitt Trigger input with CMOS levels TTL = T TL compatible input XTAL = Crystal

GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change

CIN1-

T1G

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

T1CKI ST — Timer1 clock input
OSC1 XTAL — Crystal/Resonator
CLKIN ST — External clock input/RC oscillator connection

Input

Type

Output

Type

ST — Master Clear w/internal pull-up

AN — Comparator inverting input
ST — Timer1 gate (count enable)

OSC/4 output

Description

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 7

PIC12F609/615/12HV609/615

TABLE 1-2: PIC12F615/HV615 PINOUT DESCRIPTION

Name Function

GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN0 AN — A/D Channel 0 input

CIN+ AN — Comparator non-inverting input

P1B — CMOS PWM output

ICSPDAT ST CMOS Serial Programming Data I/O

GP1/AN1/CIN0-/V

GP2/AN2/T0CKI/INT/COUT/CCP1/
P1A

GP3/T1G

GP4/AN3/CIN1-/T1G
CLKOUT

GP5/T1CKI/P1A*/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

V
V

Legend: AN = Analog input or output CMOS=CMOS compatible input or output HV = High Voltage

*/MCLR/VPP GP3 TTL — G eneral purpose input with interrupt-on-change

DD VDD Power — Positive supply
SS VSS Power — Ground reference

* Alternate pin function.

REF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN1 AN — A/D Channel 1 input

CIN0- AN — Comparator inverting input

REF AN — External Voltage Reference for A/D

V

ICSPCLK ST — Serial Programming Clock

GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External Interrupt
COUT — CMOS Comparator output
CCP1 ST CMOS Capture input/Compare input/PWM output

P1A — CMOS PWM output

T1G

MCLR

V

PP HV — Programming voltage

/P1B*/OSC2/

ST = Schmitt Trigger input with CMOS levels TTL =T T L compatible input XTAL= Crystal

GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-

AN3 AN — A/D Channel 3 input

CIN1-

T1G

P1B* — CMOS PWM output, alternate pin

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

T1CKI ST — Timer1 clock input

P1A* — CMOS PWM output, alternate pin
OSC1 XTAL — Crystal/Resonator
CLKIN ST — External clock input/RC oscillator connection

Input

Type

* ST — Timer1 gate (count enable), alternate pin

Output

Type

change

change

change

ST — Master Clear w/internal pull-up

change

AN — Comparator inverting input
ST — Timer1 gate (count enable)

OSC/4 output

change

Description

DS41302A-page 8 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F609/615/12HV609/615 has a 13-bit pro­gram counter capable of addressing an 8K x 14 pro­gram memory space. Only the first 1K x 14 (0000h­03FFh) for the PIC12F609/615/12HV609/615 is physi­cally implemented. Accessing a location above these
boundaries will cause a wraparound within the first 1K
x 14 space. T he Rese t vec tor is at 0000 h and the int er­rupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC12F609/615/12HV609/615

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector

13

0000h

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations F0h-FFh in Bank 1 point
to addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read. The RP0 bit
of the STATUS register is the bank select bit.

RP0

0 → Bank 0 is selected
1 → Bank 1 is selected

Note: The IRP and RP1 bits of the STATUS

register are reserved and should always be
maintained as ‘0’s.

2.2.1 GENERAL PURPOSE REGISTER
FILE

The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers” ).

Interrupt Vector

On-chip Program

Memory

Wraps to 0000h-07FFh

0004h
0005h

03FFh
0400h

1FFFh

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table2-1). These
registers are static RAM.

The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 9

PIC12F609/615/12HV609/615

FIGURE 2-2: DATA MEMORY MAP OF

THE PIC12F609/HV609

Indirect Addr.

TMR0

PCL

STATUS

FSR

GPIO

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

VRCON

CMCON0

CMCON1

(1)

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

Indirect Addr.

OPTION_REG

PCL

STATUS

FSR

TRISIO

PCLATH
INTCON

PIE1

PCON

OSCTUNE

WPU

IOC

ANSEL

(1)

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

FIGURE 2-3: DATA MEMORY MAP OF

THE PIC12F615/HV615

Indirect Addr.

TMR0

PCL

STATUS

FSR

GPIO

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

PWM1CON

ECCPAS

VRCON

CMCON0

CMCON1

ADRESH
ADCON0

(1)

File

Address

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

Indirect Addr.

OPTION_REG

PCL

STATUS

FSR

TRISIO

PCLATH
INTCON

PIE1

PCON

OSCTUNE

PR2

APFCON

WPU

IOC

ADRESL

ANSEL

(1)

File

Address

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

3Fh

General
Purpose

Registers

64 Bytes

Bank 0

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

40h

7Fh

Accesses 70h-7Fh

Bank 1

EFh
F0h

FFh

General

Purpose

Registers

64 Bytes

Bank 0

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

3Fh
40h

7Fh

Accesses 70h-7Fh

Bank 1

EFh
F0h

FFh

DS41302A-page 10 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0

Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 100
01h TMR0 Timer0 Module’s Register xxxx xxxx 41, 100
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 100
03h STA TUS IRP
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 100
05h GPIO
06h — Unimplemented — —
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 100
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
11h — Unimplemented — —
12h — Unimplemented — —
13h — Unimplemented — —
14h — Unimplemented — —
15h — Unimplemented — —
16h — Unimplemented — —
17h — Unimplemented — —
18h — Unimplemented — —
19h VRCON CMVREN
1Ah CMCON0 CMON COUT CMOE CMPOL
1Bh — — — — —
1Ch CMCON1
1Dh — Unimplemented — —
1Eh — Unimplemented — —
1Fh — Unimplemented — —

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(1)

— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 100

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 100

— — — —CMIF— —TMR1IF---- 0--0 19, 100

— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 59, 101

(1)

RP1

— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101

RP0 TO PD ZDCC0001 1xxx 15, 100

TMR1CS TMR1ON 0000 0000 49, 100

—CMR—CMCH0000 -0-0 58, 101

Value on

POR, BOR

Page

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 11

PIC12F609/615/12HV609/615

TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
01h TMR0 Timer0 Module’s Register xxxx xxxx 41, 101
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101
03h STA TUS IRP
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101
05h GPIO
06h — Unimplemented — —
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 101
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
11h TMR2 Timer2 Module Register 0000 0000 51, 101
12h T2CON
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 76, 101
14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 76, 101
15h CCP1CON P1M
16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 91, 101
17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 88, 101
18h — Unimplemented — —
19h VRCON CMVREN
1Ah CMCON0 CMON COUT CMOE CMPOL
1Bh — — — — —
1Ch CMCON1
1Dh — Unimplemented — —
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 71, 101
1Fh ADCON0 ADFM VCFG

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(1)

— — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 101

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101

— ADIF CCP1IF —CMIF— TMR2IF TMR1IF -00- 0-00 19, 101

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 101

— — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 59, 101

(1)

RP1

— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 75, 101

— VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101

RP0 TO PD ZDCC0001 1xxx 15, 101

TMR1CS TMR1ON 0000 0000 49, 101

—CMR—CMCH0000 -0-0 58, 101

— CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 70, 101

Value on

POR, BOR

Page

DS41302A-page 12 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
81h OPTION_REG GPPU
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101
83h STATUS IRP
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101
85h TRISIO
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —
90h OSCTUNE
91h — Unimplemented — —
92h — Unimplemented — —
93h — Unimplemented — —
94h — Unimplemented — —
95h WPU
96h IOC
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ANSEL

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(2)

2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3: MCLR

exists.

4: TRISIO3 always reads as ‘1’ since it is an input only pin.

— — TRISIO5 TRISIO4 TRISIO3

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101

— — — —CMIE— —TMR1IE---- 0--0 18, 101

— — — — — —PORBOR ---- --qq 20, 101

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101

— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 34, 101
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101

— — — —ANS3— ANS1 ANS0 ---- 1-11 33, 101

and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101

(1)

RP1

(1)

RP0 TO PD ZDCC0001 1xxx 15, 101

(4)

TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101

Value on

POR, BOR

(3)

0000 0000 17, 101

Page

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 13

PIC12F609/615/12HV609/615

TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101
81h OPTION_REG GPPU
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101
83h STATUS IRP
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101
85h TRISIO
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON
8Fh — Unimplemented — —
90h OSCTUNE
91h — Unimplemented — —
92h PR2 Timer2 Module Period Register 1111 1111 51, 101
93h APFCON
94h — Unimplemented — —
95h WPU
96h IOC
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 71, 101
9Fh ANSEL

Legend: – = Unimplemented locations rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(2)

2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3: MCLR

4: TRISIO3 always reads as ‘1’ since it is an input only pin.

and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch

exists.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101

(1)

— — TRISIO5 TRISIO4 TRISIO3

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101

— ADIE CCP1IE —CMIE— TMR2IE TMR1IE -00- 0-00 18, 101

— — — — — —PORBOR ---- --qq 20, 101

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101

— — — T1GSEL — — P1BSEL P1ASEL ---0 --00 18, 101

— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 34, 101
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 101

RP1

(1)

RP0 TO PD ZDCC0001 1xxx 15, 101

(4)

TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101

Value on

POR, BOR

(3)

0000 0000 17, 101

Page

DS41302A-page 14 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

2.2.2.1 STATUS Register

The STATUS registe r, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)
The STATUS register can be the destination for any

instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS regis ter as destina tion may be differ ent than
intended.

For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect­ing any Status bits, see the Section 13.0 “Instruction

Set Summary”.

Note 1: Bits IRP and RP1 of the ST ATUS register

are not used by the PIC12F609/615/
12HV609/615 and should be maintained
as clear. Use of these bits is not recom­mended, since this may affect upward
compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.

REGISTER 2-1: STATUS: STATUS REGISTER

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 T O PD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: This bit is reserved and should be maintained as ‘0’
bit 6 RP1: This bit is reserved and should be maintained as ‘0’
bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h – FFh)
0 = Bank 0 (00h – 7Fh)

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is

bit 0 C: Carry/Bo

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or b y the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

reversed.

1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

(1)

rrow bit

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

Note 1: For Bo

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 15

rrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructi ons, this bit is loa ded with either the high-orde r or low-o rder
bit of the source register.

PIC12F609/615/12HV609/615

2.2.2.2 OPTION Register

The OPTION register is a readable and writable regis­ter, which contains various control bits to configure:

• Timer0/WDT prescaler

• External GP2/INT interrupt

•Timer0

• Weak pull-ups on GPIO

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 5.1.3 “Software
Programmable Prescaler”.

bit 7 GPPU

: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on GP2/T0CKI pin
0 = Internal instruction cyc le clock (F

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to -low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

BIT VALUE TIMER0 RATE WDT RATE

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

OSC/4)

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

DS41302A-page 16 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

2.2.2.3 INTCON Register

The INTCON register is a readable and writable
register , which c ontains the various en able and fl ag bit s
for TMR0 register ove rflo w, GPIO change and externa l
GP2/INT pin interrupts.

Note: Interrupt flag bits are set w hen an in terrupt

condition occurs, regar dless of the st ate of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interru pt Enab le bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt

bit 4 INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt

bit 3 GPIE: GPIO Change Interrupt Enable bit

1 = Enables the GPIO change interrupt
0 = Disables the GPIO change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit

1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow

bit 1 INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur

bit 0 GPIF: GPIO Change Interrupt Flag bit

1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software)
0 = None of the GPIO <5:0> pins have changed state

(1)

(2)

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 17

PIC12F609/615/12HV609/615

2.2.2.4 PIE1 Register

The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

—ADIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 4 Unimplemented: Read as ‘0’
bit 3 CMIE: Comp ara tor Interrupt Enable bit

1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow inter rupt

(1)

CCP1IE

(1)

—CMIE —TMR2IE

(1)

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

(1)

TMR1IE

(1)

(1)

Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

DS41302A-page 18 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

2.2.2.5 PIR1 Register

The PIR1 register cont ains the Peri pheral Interrup t flag
bits, as shown in Register 2-5.

REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

—ADIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D In terrupt Flag bit

1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register captu re occurred

Compare mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode
bit 4 Unimplemented: Read as ‘0’
bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator output has changed (must be cleared in software)

0 = Comparator output has not changed

bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

(1)

CCP1IF

:

:

(1)

—CMIF —TMR2IF

(1)

(1)

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

(1)

TMR1IF

(1)

Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 19

PIC12F609/615/12HV609/615

2.2.2.6 PCON Register

The Power Control (PCON) register (see Table 11-2)
contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR
The PCON register also co ntrols the software ena ble of

the BOR
The PCON register bits are shown in Register 2-6.

.

REGISTER 2-6: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

)

Reset

(1)

bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR

bit 0 BOR

Note 1 : Reads as ‘0’ if Brown-out Reset is disabled.

: Power-on Re set Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS41302A-page 20 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

2.2.2.7 APFCON Register
(PIC12F615/HV615 only)

The Alternate Pin Function Control (APFC ON) reg ist er
is used to steer specific peripheral input and output
functions between different pins. For this device, the
P1A, P1B and Timer1 Gate functions can be moved
between different pins.

The APFCON register bits are shown in Register 2-7.

REGISTER 2-7: APFCON: POWER CONTROL REGISTER

U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— — — T1GSEL — — P1BSEL P1ASEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’
bit 4 T1GSEL: TMR1 Input Pin Select bit

1 = T1G function is on GP3/T1G
0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B

bit 3-2 Unimplemented: Read as ‘0’
bit 1 P1BSEL: P1B Output Pin Select bit

1 = P1B function is on GP4/AN3/CIN1-/T1G
0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT

bit 0 P1ASEL: P1A Output Pin Select bit

1 = P1A function is on GP5/T1CKI/P1A
0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A

(2)

/MCLR/VPP

(2)

(2)

/OSC2/CLKOUT

(2)

/P1B

/OSC2/CLKOUT

/OSC1/CLKIN

(1)

Note 1: PIC12F615/HV615 only.

2: Alternate pin function.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 21

PIC12F609/615/12HV609/615

h

>

s
n

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The lo w byte
comes from the PCL register, which is a readable and
writable register . The hig h byte (PC<12:8>) is not directl y
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-4 shows the two
situations for the loading of the PC. The upper example
in Figure 2-4 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
Figure 2-4 shows h ow the PC is l oaded during a CALL or
GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-4: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PC

PCLATH<4:0>

5

PCLATH

PCH PCL

12 11 10 0

PC

2

87

PCLATH<4:3>

PCLATH

8

11

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC< 12:8> bits (PCH) to be replaced by the
contents of the PCLATH register . Th is allo ws the enti re
contents of the program counter to be changed by
writing the desired up per 5 bit s to the PCLATH register .
When the lower 8 bits are written to the PCL regis ter , all
13 bits of the program counter will chan ge to the values
contained in the PCLATH register and those being
written to the PCL register.

A computed GOTO is accomplish ed by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program b ranch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.

For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

Instruction wit

PCL a

Destinatio

ALU Result

GOTO, CALL

OPCODE <10:0

2.3.2 STACK

The PIC12F609/615/12HV609/615 Family has an 8­level x 13-bit wide hardware stack (see Figure 2-1).
The stack space is not part of either program or data
space and the S ta ck Pointer i s not rea dable or writa ble.
The PC is PUSHed onto the stack when a CALL
instruction is execute d or an interrupt ca uses a branc h.
The stack is POPed in the even t of a RETURN, RETLW
or a RETFIE instruction execution. PCLATH is not
affected by a P USH or POP operation.

The stack operat es as a circular buf fer . This means th at
after the stack has been PUSHed eight times, the ninth
push overwrites the va lue tha t was s tored fro m the first
push. The tenth pus h ov erwr i tes the se co nd push (and
so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.

2.4 Indirect Addressing, INDF and
FSR Registers

The INDF register is not a physica l register . Addr essing
the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-5.

A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESS ING

MOVLW 0x40 ;initialize pointer
MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer
BTFSS FSR,7 ;all done?
GOTO NEXT ;no clear next

CONTINUE ;yes continue

DS41302A-page 22 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

FIGURE 2-5: DIRECT/INDIRECT ADDRESSING PIC12F609/615/12HV609/615

Indirect AddressingDirect Addressing

RP1

(1)

RP0 6

From Opcode

0

IRP

(1)

7

File Select Register

0

Bank Select Location Select

00h

Data
Memory

7Fh

For memory map detail, see Figure 2-2.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

2: Accesses in this area are mirrored back into Bank 0 and Bank 1.

00 01 10 11

NOT USED

Bank 0 Bank 1 Bank 2 Bank 3

(2)

Bank Select

180h

1FFh

Location Select

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 23

PIC12F609/615/12HV609/615

NOTES:

DS41302A-page 24 Preliminary © 2006 Microchip Technology Inc.

PIC12F609/615/12HV609/615

3.0 OSCILLATOR MODULE

The Oscillator mod ule can be c onfigured in one of eig ht
clock modes.

3.1 Overview

The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applicati ons while maximiz ing perfor­mance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the Oscillator module.

Clock sources can be configured from external
oscillators, quartz cryst al resonators , ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured with a choice of
two selectable speeds: internal or external system clock
source.

1. EC – External clock w ith I/O on OSC2/C LKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator
mode.

5. RC – External Resistor-Capacitor (RC) with

OSC/4 output on OSC2/CLKOUT.

F

6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with F
on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FOSC <2:0>
bits in the Configuration Word register (CONFIG). The
Internal Oscillator mo dule provides a select able system
clock mode of either 4 MHz (Postscaler) or 8 MHz
(INTOSC).

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

OSC/4 output

OSC2

OSC1

External Oscillator

INTOSC

8 MHz

Sleep

Internal Oscillator

Postscaler

4 MHz

(Configuration Word Register)

LP, XT, HS, RC, RCIO, EC

INTOSC

FOSC<2:0>
IOSCFS<7>

MUX

System Clock

(CPU and Peripherals)

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 25

PIC12F609/615/12HV609/615

3.2 Clock Source Modes

Clock Source modes can be classified as external or
internal.

• External Clock mod es rely on e xternal circui try fo r
the clock source. Examples are: Oscillator mod­ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two selectable clock frequencies:
4 MHz and 8 M Hz

The system clock can be selected between external or
internal clock sources via the FOSC<2:0> bits of the
Configuration Word register.

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator o r ce ramic res onator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 3-1.

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR INTOSC 125 kHz to 8 MHz Oscillator Warm-Up Delay (T
Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

3.3.2 EC MODE

The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

®

MCU design is fully

WARM)

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from
Ext. System

I/O

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

DS41302A-page 26 Preliminary © 2006 Microchip Technology Inc.

OSC1/CLKIN

®

MCU

PIC

OSC2/CLKOUT

(1)

PIC12F609/615/12HV609/615

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz
crystal resonators or ceram ic resonators connected to
OSC1 and OSC2 (Figu re 3-3). The mod e selects a low ,
medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.

LP Oscillator mode selects the lowest gain setting of
the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. T his mode
is designed to drive only 32.768 kHz tuning-fork type
crystals (watch crystals).

XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medi um of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.

HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This
mode is best suited for resonato rs that req uire a hi gh
drive setting.

Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.

Note 1: Quartz crystal char acteristics vary a ccording

to type, package and manufacturer. The
user should consult the manu facturer data
sheets for sp ecifi catio ns an d reco mmen ded
application.

2: Always verify oscillator performance over

DD and temperature range that is

the V
expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC®

Devices” (DS00826)

®

• AN849, “Basic PIC

Oscillator Design”

(DS00849)

®

• AN943, “Practical PIC

Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”
(DS00949)

FIGURE 3-4: CERAMIC RESONATOR

OPERATION
(XT OR HS MODE)

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR
HS MODE)

PIC® MCU

OSC1/CLKIN

C1

Quartz
Crystal

C2

Note 1: A series resistor (RS) may be required for

2: The value of R

(1)

S

R

quartz crystals with low drive level.

selected (typically between 2 MΩ to 10 MΩ).

F varies with the Oscillator mode

(2)

RF

OSC2/CLKOUT

To Internal
Logic

Sleep

PIC® MCU

OSC1/CLKIN

C1

(3)

RP

C2

Ceramic
Resonator

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

selected (typically between 2 MΩ to 10 MΩ).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator
operation.

(1)

R

S

F varies with the Oscillator mode

(2)

RF

OSC2/CLKOUT

To Internal
Logic

Sleep

P)

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 27

PIC12F609/615/12HV609/615

3.3.4 EXT ERNAL RC MODES

The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1.
OSC2/CLKOUT outputs the RC oscillator frequency
divided by 4. This signal may be us ed to provide a cl ock
for external circuitry, synchronization, calibration, test
or other application requirements. Figure 3-5 shows
the external RC mode connections.

FIGURE 3-5: EXTERNAL RC MODES

REXT

CEXT

VSS

VDD

OSC/4 or

F

(2)

I/O

OSC1/CLKIN

OSC2/CLKOUT

PIC® MCU

Internal

Clock

(1)

3.4 Internal Clock Modes

The Oscillator module provides a selectable system
clock source of either 4 MHz or 8 MHz. The selectable
frequency is configured through the IOSCFS bit of the
Configuration Word.

The frequency of the int erna l os ci llator can be trimmed
with a calibration value in the OSCTUNE register.

3.4.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is progra mmed usi ng the osc illator se lectio n
or the FOSC<2:0> bits in the Configuration Word
register (CONFIG). See Section 11.0 “Special
Features of the CPU” for more information.

In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator fre quency divide d by 4. The CLKO UT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ R
C

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depends upon R C or RCIO Clock

mode.

EXT ≤ 100 kΩ, 3-5V

EXT > 20 pF, 2-5V

In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacito r (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance
The user also needs to take into account variation due

to tolerance of external RC components used.

DS41302A-page 28 Preliminary © 2006 Microchip Technology Inc.