MICROCHIP PIC12F683 DATA SHEET

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PIC12F683

Data Sheet

8-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

 2004 Microchip Technology Inc. Preliminary DS41211B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTE R , SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system cer t if i cat i on f or its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October

2003. The Com pany’s quality sy stem proces ses and pro cedures are for its PICmicro EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping devices, Serial

DS41211B-page ii Preliminary  2004 Microchip Technology Inc.

PIC12F683

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

nanoWatt Technology

High-Performance RISC CPU

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of 8 MHz to 31kHz

- Two-speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for power savings

• Power-saving Sleep mode

• Wide operating voltage range. (2.0V-5.5V)

• Industrial and Extended tempera ture range

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

Low-Power Features

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5µA @ 32 kHz, 2.0V, typical

-100µA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

-1µA @ 2.0V, typical

Peripheral Features

• 6 I/O pins with individual direction control:

- High current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

- Ultra Low-Power Wake-up on GP0

• Analog comparator module with:

- One analog comparator

- Programmable on-chip voltage reference (CV

REF) module (% of VDD)

- Comparator inputs and output externally accessible

• A/D Converter:

- 10-bit resolution and 4 channels

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode as

Timer1 oscillator if INTOSC mode selected

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Capture, Compare, PWM mo dul e:

- 16-bit Capture, max resolution 12.5 ns

- Compare, max resolution 200 ns

- 10-bit PWM, max frequency 20 kHz

• In-Circuit Serial Programming™ (ICSP™) via two pins

Device

PIC12F683 2048 128 256 6 4 1 2/1

 2004 Microchip Technology Inc. Preliminary DS41211B-page 1

Program Memory Data Memory

Flash (words) SRAM (bytes) EEPROM (bytes)

I/O 10-bit A/D (ch) Comparators

Timers

8/16-bit

PIC12F683

Pin Diagram

8-pin PDIP, SOIC, DFN-S

GP5/T1CKI/OSC1/CLKIN

GP4/AN3/T1G

/OSC2/CLKOUT

GP3/MCLR

VDD

/VPP

PIC12F683

8 7

6 5

VSS

GP0/AN0/CIN+/ICSPDAT/ULPWU

GP1/AN1/CIN-/V

GP2/AN2/T0CKI/INT/COUT/CCP1

REF/ICSPCLK

DS41211B-page 2 Preliminary  2004 Microchip Technology Inc.

PIC12F683

Table of Contents

1.0 Device Overview..........................................................................................................................................................................5

2.0 Memory Organization................................................................................................................................................................... 7

3.0 Clock Sources............................................................................................................................................................................ 19

4.0 GPIO Port...................................................................................................................................................................................31

5.0 Timer0 Module ........................................................................................................................................................................... 39

6.0 Timer1 Module with Gate Control............................................................................................................................................... 41

7.0 Timer2 Module ........................................................................................................................................................................... 45

8.0 Comparator Module....................................................................................................................................................................47

9.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 55

10.0 Data EEPROM Memory.................................. .............. .......................................... ................................................................... 65

11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 69

12.0 Special Features of the CPU....................................... .......................................... .....................................................................75

13.0 Instruction Set Summary............................................................................................................................................................ 95

14.0 Development Support............................................................................................................................................................... 103

15.0 Electrical Specifications............................................................................................................................................................ 109

16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 131

17.0 Packaging Information. ............... .............. ............... .......................................... ....................................................................... 133

Appendix A: Data Sheet Revision History.......................................................................................................................................... 137

Appendix B: Migrating From Other PICmicro® Devices .................................................................................................................... 137

Index ..................................................................................................................................................................................................139

On-line Support.................................................................................................................................................................................. 143

Systems Information and Upgrade Hot Line...................................................................................................................................... 143

Reader Response. ............................................................................................................................................................................. 144

Product Identification System............................................................................................................................................................ 145

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

 2004 Microchip Technology Inc. Preliminary DS41211B-page 3

PIC12F683

NOTES:

DS41211B-page 4 Preliminary  2004 Microchip Technology Inc.

PIC12F683

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the PIC12F683. Addition al informa tion may b e found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to

FIGURE 1-1: PIC12F683 BLOCK DIAGRAM

INT

Program Counter

8-Level Stack

(13-bit)

Direct Addr

Program

Bus

Configuration

Flash

2k x 14

Program

Memory

Instruction reg

this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

The PIC12F683 is covered by this data sheet. It is available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description.

Indirect

Addr

RAM Addr

Data Bus

RAM

128 bytes

File

Registers

Addr MUX

FSR reg

GP0 GP1 GP2 GP3 GP4 GP5

OSC1/CLKIN

OSC2/CLKOUT

T1G

T1CKI

T0CKI

VREF

Instruction

Decode &

Control

Timing

Generation

Internal

Oscillator

Timer0 Timer1

Analog-to-Digital Converter

AN0 AN1 AN2 AN3

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

VDD

Timer2

1 Analog Comparator

VSS

and Reference

CIN- CIN+ COUT

ALU

W reg

Status reg

MUX

CCP

EEDATA

256 bytes

Data

EEPROM

EEADDR

 2004 Microchip Technology Inc. Preliminary DS41211B-page 5

PIC12F683

TABLE 1-1: PIC12F683 PINOUT DESCRIPTION

Name Function

DD VDD Power — Positive supply

V GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change

T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection

GP4/AN3/T1G

GP3/MCLR

GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 ST CMOS GPIO I/O w/programmable pull-up and interrupt-on-change

GP1/AN1/CIN-/V

GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change

SS VSS Power — Ground reference

V Legend: AN = Analog input or output CMO S = CMOS compatible input or output

/OSC2/CLKOUT GP4 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change

AN3 AN — A/D Channel 3 input T1G

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS F

/VPP GP3 TTL — GPIO input with interrupt-on-change

MCLR

PP HV — Programming voltage

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External Interrupt COUT — CMOS Comparator 1 output CCP1 ST CMOS Capture input/Compare output/PWM output

REF/ICSPCLK GP1 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change

AN1 AN — A/D Channel 1 input CIN- AN — Comparator 1 input

REF AN — External Voltage Reference for A/D

ICSPCLK ST — Serial Programming Clock

AN0 AN — A/D Channel 0 input

CIN+ AN — Comparator 1 input

ICSPDAT ST CMOS Serial Programming Data I/O

ULPWU AN — Ultra Low-power Wake-up input

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal

Input

Type

Output

Type

ST — Timer1 gate

OSC/4 output

ST — Master Clear w/internal pull-up

Description

DS41211B-page 6 Preliminary  2004 Microchip Technology Inc.

PIC12F683

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 pr ogram mem ory spac e. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F683

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1 Stack Level 2

Stack Level 8

Reset Vector

000h

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are general purpose registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70 h-7Fh in Bank 0. All other RAM is u nimplemented and re turns ‘0’ when read. RP0 (Status<5>) is the bank select bit.

•RP0 = 0: Bank 0 is selected

•RP0 = 1: Bank 1 is selected Note: The IRP and RP1 bits (Status<7:6>) are

reserved and should always be maintained as ‘0’s.

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the Fi le Sel ec t Register FSR (see

Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

Interrupt Vector

On-chip Program

Memory

0004 0005

07FFh 0800h

1FFFh

 2004 Microchip Technology Inc. Preliminary DS41211B-page 7

PIC12F683

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.

The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

FIGURE 2-2: DATA MEMORY MAP OF

THE PIC12F683

File

Address

TMR0

PCL

FSR

GPIO

PIR1

TMR1L TMR1H T1CON

TMR2

T2CON CCPR1L

General Purpose

(1)

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h

Indirect addr.

OPTION_REG

STATUS

PCLATH INTCON

OSCCON

OSCTUNE

EECON1

EECON2

ADRESL

Registers

Indirect addr.

STATUS

PCLATH INTCON

CCPR1H

CCP1CON

WDTCON CMCON0 VRCON CMCON1

ADRESH ADCON0

Registers

96 Bytes

PCL

FSR

TRISIO

PIE1

PCON

PR2

WPU

IOC

EEDAT EEADR

ANSEL General Purpose

32 Bytes

File

Address

(1)

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch

(1)

9Dh 9Eh 9Fh

A0h

BFh

BANK 0

7Fh

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

Accesses 70h-7Fh

BANK 1

F0h FFh

DS41211B-page 8 Preliminary  2004 Microchip Technology Inc.

PIC12F683

TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this loca tion uses content s of FSR to address dat a memory (not a physical register) xxxx xxxx 17, 83 01h TMR0 Timer0 Module’s Register xxxx xxxx 39, 83 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 83 03h STATUS IRP 04h FSR Indirect Data Memory Addr ess Point er xxxx xxxx 17, 83 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 83 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 41, 83 0Fh T MR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 41, 83 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h

TMR2 Timer2 Module Register 0000 0000 45, 83

12h

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 45, 83 13h CCPR1L Cap ture/Com pare/PWM Register 1 Low Byte xxxx xxxx 70, 83 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 70, 83 15h CCP1CON 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 57,83 1Fh ADCON0 ADFM VCFG Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(1)

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 83

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 83

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 83

— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 69, 83

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 90, 83 —COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 47, 83 — — — — — — T1GSS CMSYNC ---- --10 50, 83

RP1

(1)

RP0 TO PD Z DC C 0001 1xxx 11, 83

TMR1CS TMR1ON 0000 0000 43, 83

— — CHS1 CHS0 GO/DONE ADON 00-- 0000 58,83

Value o n

POR, BOD

Page

 2004 Microchip Technology Inc. Preliminary DS41211B-page 9

PIC12F683

TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83

OPTION_RE G

81h 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 83 83h STATUS IRP 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 83 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 83 8Ch PIE1 EEIE ADIE CCP1IE 8Dh — Unimplemented — — 8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 45, 83 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 65, 83 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 65, 83 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 66, 84 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 57, 84 9Fh A NSEL

Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

(3)

shaded = unimplemented

2: OSCCON<OSTS> bit reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator. 3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 83

(1)

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 83

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 83

— — ULPWUE SBODEN — —PORBOD --01 --qq 16, 83 — IRCF2 IRCF1 IRCF0 OSTS — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 23, 83

— —WPU5WPU4— WPU2WPU1WPU0--11 -111 32, 83 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 33, 83

— — — — WRERR WREN WR RD ---- x000 66, 84

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 59, 84

(1)

RP1

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 53, 83

RP0 TO PD Z DC C 0001 1xxx 11, 83

— CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 83

(2)

HTS LTS SCS -110 x000 28, 83

Value o n

POR, BOD

Page

DS41211B-page 10 Preliminary  2004 Microchip Technology Inc.

PIC12F683

2.2.2.1 Status Register

The Status register, shown in Register 2-1, contains:

• Arithmetic status of the ALU

• Reset status

• Bank select bits for data memory (SRAM) The Status register can be the destination for any

instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the Status register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS, w ill c lear the upper three bits and set the Z bit. Thi s leav es the Status regis ter as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Stat us register , beca use these instru ctions do not af fect any Status bits. For other instructions not affecting any Status bits, see the “Instruction Set Summary”.

Note 1: Bits IRP and RP1 (Status<7:6>) are not

used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF

REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h OR 83h)

 2004 Microchip Technology Inc. Preliminary DS41211B-page 11

PIC12F683

2.2.2.2 Option Register

The Option register is a readable and writable register, which contains various control bits to configure:

• TMR0/WDT prescaler

• External GP2/INT interrupt

•TMR0

• Weak pull-ups on GPIO

REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU

bit 7 bit 0

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ (Option<3>). See Section 5.4 “Prescaler”.

bit 7 GPPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Sele ct bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values in WPU register

1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin

1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

(1)

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F683. See

Section 12.6 “Watchdog Timer (WDT)” for more information.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 12 Preliminary  2004 Microchip Technology Inc.

PIC12F683

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bit s for TMR0 register ove rflo w, GPIO chan ge a nd external GP2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regard less of the st ate of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt

bit 3 GPIE: GPIO Change Interrupt Enable bit

1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has over flowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur

bit 0 GPIF: GPIO Change Interrupt Flag bit

1 = When at least one of the GPIO<5:0> pins changed state (must be cleared in software) 0 = None of the GPIO<5:0> pins have changed state

Note 1: IOC register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing T0IF bit.

(1)

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 13

PIC12F683

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

REGISTER 2-5: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Interrupt Flag bit

1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mod

1 = A TMR1 register capture occurred (must be clea red in software) 0 = No TMR1 regi ster capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode. bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator 1 output has changed (must be cleared in software)

0 = Comparator 1 output has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscilla tor failed, clock inpu t h as ch ang ed to INTOSC (must be cleared in software)

0 = System clock operating

bit 1 TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit

1 = Timer 2 to PR2 match occurred (must be cleared in software)

0 = Timer 2 to PR2 match has not occurred

bit 0 TMR1IF: Timer 1 Overflow Interrupt Flag bit

1 = Timer 1 register overflowed (must be cleared in software)

0 = Timer 1 has not overflowed

Note: Interrupt f lag bit s are set when an in terrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 15

PIC12F683

2.2.2.6 PCON Regist er

The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a:

• Power-on Reset (POR

• Brown-out Detect (BOD)

• Watchdog Timer Reset (WDT)

• External MCLR The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOD The PCON register bits are shown in Register 2-6.

REGISTER 2-6: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)

bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

bit 4 SBODEN: Software BOD Enable bit

bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOD

)

Reset

U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x

— — ULPWUE SBODEN — —PORBOD

bit 7 bit 0

1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled

(1)

1 = BOD enabled 0 = BOD disabled

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Detect Status bit

1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

Note 1: BODEN<1:0> = 01 in the Configuration W ord register for this bit to control the BO D.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 16 Preliminary  2004 Microchip Technology Inc.

PIC12F683

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683

For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

DS41211B-page 18 Preliminary  2004 Microchip Technology Inc.

PIC12F683

3.0 CLOCK SOURCES

3.1 Overview

The PIC12F683 has a wide variety of clo ck sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC12F683 clock sources.

Clock sources can be configured from external oscillators, quartz crys ta l reso nat ors, cera mi c reson ato rs and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via softwar e. Additional clock feat ures include:

• Selectable system clock source between external or internal via software.

• Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execu t io n.

• Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.

The PIC12F683 can b e conf igured in one of ei ght cloc k modes.

1. EC – External clock with I/O on GP4.

2. LP – Low gain crystal or Ceramic Resonator Oscillator mode.

3. XT – Medium gain c rysta l or Cera mic Resonat or Oscillator mode.

4. HS – High gain crystal or Ceramic Resonator mode.

5. RC – External Resistor-Capacitor (RC) with

OSC/4 output on GP4

6. RCIO – External Resistor-Capacitor with I/O on GP4.

7. INTRC – Internal oscillator with F

OSC/4 output

on GP4 and I/O on GP5.

8. INTRCIO – Internal oscillator with I/O on GP4 and GP5.

Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 12.0 “Special Features of the CPU”). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator . The LFINTOSC is a low-frequency uncalibrated oscillator.

FIGURE 3-1: PIC12F683 CLOCK SOURCE BLOCK DIAGRAM

External Oscillator

OSC2

OSC1

Internal Oscillator

HFINTOSC

8 MHz

LFINTOSC

31 kHz

Sleep

Postscaler

(OSCCON<6:4>)

8 MHz 4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

31 kHz

IRCF<2:0>

111 110 101 100

011 010 001 000

LP, XT, HS, RC, RCIO, EC

MUX

Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)

FOSC<2:0>

(Configuration Word)

SCS

(OSCCON<0>)

MUX

(CPU and Peripherals)

System Clock

 2004 Microchip Technology Inc. Preliminary DS41211B-page 19

PIC12F683

3.2 Clock Source Modes

Clock source modes can be classified as external or internal.

• External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz cryst al res ona tors or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC mode) circuits.

• Internal clock sources are contained internally within the PIC12F683. The PIC12F683 has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3 .5 “Clock Switching”).

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER (OST)

If the PIC12F683 is co nfigured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from the OSC1 pin, followi ng a Power-on Res et (POR) and the Power-up T i mer (PWR T ) has ex pired ( if configured), or a wake -up from Sleep. D urin g this t ime, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has s tarted an d is provid ing a st able system clock to the PIC12F683. When switching between clock sources a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1.

In order to minimize latency between external oscillator start-up and code execution, the T wo-Speed Clock S tartup mode can be selected (see Section 3.6 “Two-Speed

Clock Start-up Mode”).

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR Sleep/POR EC, RC DC – 20 MHz

LFINTOSC (31 kHz) EC, RC DC – 20 MHz

Sleep/POR LP, XT, HS 31 kHz-20 MHz 1024 Clock Cycles (OST)

LFINTOSC (31 kHz) HFINTOSC 125 kHz-8 MHz 1 µs (approx .)

Note 1: The 5 µs–10 µs start-up delay is based on a 1 MHz system clock.

LFINTOSC

HFINTOSC

31 kHz

125 kHz-8 MHz

5 µs–10µs (approx.) CPU

Start-up

(1)

3.3.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the GP5 pin is available for general purpose I/ O. Figure 3-2 shows the pin connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F683 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

DS41211B-page 20 Preliminary  2004 Microchip Technology Inc.

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from Ext. System

GP4

OSC1/CLKIN

PIC12F683

I/O (OSC2)

PIC12F683

) r

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonator s with a low drive lev el specification, for example, tuning fork type crystals.

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suit e d t o dr i ve re so na tor s wi th a me dium drive level specification, for example, AT-cut quartz crystal resonators.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the thre e mo des . This mode is best suited for resonators that require a high drive setting, for example, AT-cut quartz crystal res onators or ceramic resonators.

Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

PIC12F683

OSC1

Quartz Crystal

OSC2

(1)

Note 1: A series resistor (R S) may be required for

2: The value of R

quartz crystals with low drive level.

mode selected (typically between 2 MΩ to 10 MΩ).

(2)

F varies with the oscillator

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sh eets for speci fications and recommended application.

2: Al ways veri fy os ci lla tor pe rform an ce over

DD and temperature range that is

the V expected for the application.

To Internal Logic

Sleep

FIGURE 3-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

PIC12F683

OSC1

(3)

Ceramic

Resonator

Note 1: A series resistor (RS) may be required fo

ceramic resonators with low drive level.

2: The value of R

mode selected (typically between 2 MΩ to 10 MΩ).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonato operation (typical value 1 MΩ).

OSC2

(1)

(2)

F varies with the oscillato

To Internal Logic

Sleep

3.3.4 EXTERNAL RC MODES

The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping cost s to a mi nimum w hen clock accuracy is not required. There are two modes, RC and RCIO.

In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator frequency divided by 4. Th is signal may be use d to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the RC mode connections.

FIGURE 3-5: RC MODE

VDD

REXT

OSC1

CEXT

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

OSC/4

OSC2/CLKOUT

EXT > 20 pF

In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an add itiona l general purpose I/O pin. The I/O pin becomes bit 4 of GPIO (GP4). Figure 3-6 shows the RCIO mode connections.

Internal

Clock

PIC12F683

 2004 Microchip Technology Inc. Preliminary DS41211B-page 21

PIC12F683

FIGURE 3-6: RCIO MODE

VDD

REXT

OSC1

CEXT

VSS

GP4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

I/O (OSC2)

EXT > 20 pF

Internal

Clock

PIC12F683

The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT)

values and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitances

3.4 Internal Clock Modes

The PIC12F683 has two independent, internal oscillators that can be configured or selected as the system clock source.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ±12% via software usi ng the OSCTUNE register (Register 3-1).

2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.

The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits.

The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3 .5 “Clock Switching”).

3.4.1 INTRC AND INTRCIO MODES

The INTRC and INTRCIO m odes conf igure the int ernal oscillators as th e sys tem cl ock so urce when the dev ice is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word register (Register 12-1).

In INTRC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal os ci lla tor freq uen cy div ide d by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application require me nt s .

In INTRCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.

3.4.2 HFINTOSC

The High-Frequency Int ernal Oscillato r (HFINT OSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately ± 12% via software using the OSCT UNE register (Register 3-1).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”).

The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF ≠ 000) as the system clock s ource (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF ≠ 000).

The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.

DS41211B-page 22 Preliminary  2004 Microchip Technology Inc.

PIC12F683

3.4.2.1 OSCTUNE Register

The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register3-1).

The OSCTUNE register has a tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonicity and frequency step cannot be specified.

When the OSCTUNE register is modified, the HFINTOSC freque ncy will be gin s hifting to th e new frequency . The HFINT OSC clock will st abilize with in 1 ms. Code execution contin ues duri ng thi s sh ift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

REGISTER 3-1: OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequenc y Tuning bits

01111 = Maximum frequen cy 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 23

PIC12F683

3.4.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock so urce (SCS = 1), or when any of the following are enabled:

• Two-Speed Start-up (IESO = 1 and IRCF = 000)

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.

3.4.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

•31 kHz

Note: Follow ing a ny Re set, the IRCF bit s are set

to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.

3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING

When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case , there is a 10µs delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows:

1. IRCF bits are modified.

2. If the new clock is shut down, a 10 µs clock

start-up delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits fo r a ris ing edge in the new clock.

5. CLKOUT is now connected with the new clock.

HTS/LTS bits are updated as required.

6. Clock switch is complete.

If the internal oscillator speed selected is between 8 M Hz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer.

3.5 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit.

3.5.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals.

• When SCS = 0, the system clock source is

determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG).

• When SCS = 1, the system clock source is

chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.

DS41211B-page 24 Preliminary  2004 Microchip Technology Inc.

PIC12F683

3.5.2 OSCILLAT OR START-UP TIME-OUT STATUS BIT

The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.

3.6 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy us e of the Sleep mode, Two-Speed Star t-up will remove the extern al oscillator start -up time from the time spent awake and can reduce the overall power consumption of the device.

This mode allows the application to wake-up from Sleep, perform a f ew inst ructio ns using th e I NTO SC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.

When the PIC12F683 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 “Oscillator Start-up Timer (OST)”). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.

3.6.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO = 1 (CONFIG<10>) Internal/External Switch

Over bit.

•SCS = 0.

• FOSC configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, afte r

PWRT has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is becaus e t he ex tern al cl oc k oscillator does not require any stabilization time after POR or an exit from Sleep.

3.6.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF bits (OSCCON<6:4>).

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next fal ling edg e

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 25

PIC12F683

3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS

Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F683 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator.

FIGURE 3-7: TWO-SPEED START-UP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

INTOSC

TOST

OSC1

OSC2

Program Counter

System Clock

0 1 1022 1023

PC PC + 1 PC + 2

DS41211B-page 26 Preliminary  2004 Microchip Technology Inc.

PIC12F683

3.7 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.

FIGURE 3-8: FSCM BLOCK DIAGRAM

Primary

Clock

LFINTOSC

Oscillator

The FSCM function is enabled by setting the FCMEN bit in the Confi guration Word regist er (CONFIG). It is applicable to all ex ternal clo ck options (LP, XT , HS, EC, RC or IO modes).

In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1< 2>) and g enerate an os cilla tor fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscill ator unless the external clock recovers and the Fail-Safe condition is exited.

The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is

÷ 64

Clock

Fail

Detector

Clock Failure Detected

active and the WDT is cleared. The SCS bit (OSCCON<0 >) is not upda ted. Enabling FSCM does not affect the LTS bit.

The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram.

On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a fal lin g e dge o f th e s am pl e clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is ena bled, as reflec ted by the IRCF.

Note: Two-Speed Start-up is automatically

enabled when the Fail-Safe Clock Mo nit or mode is enabled.

Note: Primary cl ocks with a freque ncy ≤

3.7.1 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock sourc e. The IRCF bits (OSCCON< 6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.

FIGURE 3-9: FSCM TIMING DIAGRAM

 2004 Microchip Technology Inc. Preliminary DS41211B-page 27

PIC12F683

3.7.2 RESET OR WAKE-UP FROM SLEEP

The FSCM is design ed to detect osc illator failu re at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events.

For LP, XT or HS mode the external oscillator may require a start-up time considerably longer than the FSCM sample cloc k time or a fals e clock fai lure may be detected (see Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stab le (the

OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.

Note: Due to the wide ran ge of osc illator st art-up

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the u se r sho uld check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.

REGISTER 3-2: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0

— IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC)

bit 2 HTS: HFINTOSC (High Frequency – 8MHz to 125 kHz) Status bit

1 =HFINTOSC is stable 0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

1 = LFINTOSC is stable 0 = LFINTOSC is not stable

bit 0 SCS: System Clock Select bit

1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0>

(1)

HTS LTS SCS

Note 1: Bit resets to ‘0’ w ith Two-Speed S t art-up an d LP, XT or HS selected as the osc illator

mode or Fail-Safe mode is enabled.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 28 Preliminary  2004 Microchip Technology Inc.

PIC12F683

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

0Ch PIR1 8Ch PIE1 8Fh OSCCON 90h OS CTUNE

(1)

2007h

Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: See Register 12-1 for operation of all Configuration Word register bits.

CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

2: See Register 3-2 for details.

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 0000 0000 EEIE ADIE CCP 1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000

— IRCF2 IRCF1 IRCF0 OSTS — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

HTS LTS SCS -110 x000 -110 x000

POR, BOD

Val ue on

all other

Resets

 2004 Microchip Technology Inc. Preliminary DS41211B-page 29

PIC12F683

NOTES:

DS41211B-page 30 Preliminary  2004 Microchip Technology Inc.

PIC12F683

4.0 GPIO PORT

There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be a vailable a s general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

Note: Addition al inf ormatio n o n I/O port s ma y be

found in the “PICmicro Family Reference Manual” (DS33023).

4.1 GPIO and the TRISIO Registers

GPIO is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISIO. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., put the contents of the output latch on the selected pin). The ex ception is GP3, which is input onl y and its TRISIO bit will always read as ‘1’. Example 4-1 shows how to initialize GPIO.

Reading the GPIO regis ter reads the st atus of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pin s are read, this value is modified and then written to the port data latch. GP3 reads ‘0’ when MCLRE = 1.

The TRISIO register controls the direction of the GPIO pins, even when they are be ing us ed as ana lo g inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’.

Mid-Range MCU

Note: The ANSEL (9Fh) and CMCON0 (19h)

registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

EXAMPLE 4-1: INITIALIZING GPIO

BCF STATUS,RP0 ;Bank 0 CLRF GPIO ;Init GPIO MOVLW 07h ;Set GP<2:0> to MOVWF CMCON0 ;digital I/O BSF STATUS,RP0 ;Bank 1 CLRF ANSEL ;digital I/O MOVLW 0Ch ;Set GP<3:2> as inputs MOVWF TRISIO ;and set GP<5:4,1:0>

BCF STATUS,RP0 ;Bank 0

;as outputs

4.2 Additional Pin Functions

Every GPIO pin on the PIC12F683 has an in terrupt-onchange option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions.

4.2.1 WEAK PULL-UPS

Each of the GPIO pins, exce pt GP3, has an individuall y configurable weak internal pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 4-3. Each weak pull-up is au tom at ica lly turned off when th e port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU (OPTION<7>). A w eak pull -up is automa tically enabled for GP3 when confi gure d a s M CLR GP3 is an I/O. There is no software control of the M CLR pull-up.

and disabled whe n

bit

REGISTER 4-1: GPIO – GENERAL PURPOSE I/O REGISTER (ADDRESS: 05h)

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0

— —

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: GPIO<5:0>: GPIO I/O pin

1 = Port pin is > V 0 = Port pin is < VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 31

GP5 GP4 GP3 GP2 GP1 GP0

PIC12F683

REGISTER 4-2: TRISIO – GPIO TRI-STATE REGISTER (ADDRESS: 85h)

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISIO<5:0>: GPIO Tri-State Control bit

1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output

Note 1: TRISIO<3> always reads ‘1’.

2: TRISIO<5:4> reads ‘1’ in XT, LP and HS modes.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 4-3: WPU – WEAK PULL-UP REGISTER (ADDRESS: 95h)

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPU5 WPU4 — WPU2 WPU1 WPU0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up register bit

1 = Pull-up enabled 0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up register bit

1 = Pull-up enabled 0 = Pull-up disabled

Note 1: Global GPPU

2: The weak pull-up device is automatically disabled if the pin is in output mode

(TRISIO = 0).

3: The GP3 pull-up is enabled when configured as MCLR

the Configuration Word.

4: WPU<5:4> reads ‘1’ in XT, LP and HS modes.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

must be enabled for individual pull-ups to be enabled.

and disabled as an I/O in

DS41211B-page 32 Preliminary  2004 Microchip Technology Inc.

PIC12F683

4.2.2 INTERRUPT-ON-CHANGE

Each of the G PIO pins i s individ ually configu rable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 4-4. The interrupt-on-change is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the values are compared with the old value la tched on the last rea d of GPIO. The ‘mismatch’ o utputs of t he last read are OR’d together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register.

This interrupt can wake the device from Sleep. The user , in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of GPIO. This will end the

mismatch condition, then

b) Clear the flag bit GPIF. A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After these resets , the G PIF fla g will c ontinue to be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when the read operation is being ex ecuted (start of the Q2 cycle), then the GPIF interrupt flag may not get set.

nor BOD

REGISTER 4-4: IOC – INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bit

1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be

recognized.

2: IOC<5:4> reads ‘1’ in XT, LP and HS modes.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

4.2.3 ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on GP0 allows a slow falling voltage to generate an interrupton-change on GP0 without excess current consumption. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on GP0.

To use this feature, the GP0 pin is configured to output ‘1’ to charge the capacitor, interrupt-on-change for GP0 is enabled and GP0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on GP0 drops below V cause the device to wake-up. Depending on the state of the GIE bit (INTCON<7>), the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.2

“Interrupt-on-change” and Section 12.4.3 “GPIO Interrupt” for more information.

IL, an interrupt will be generated which w ill

This feature provides a low- power technique for perio dically waking up the de vic e from Sleep. The time-out is dependent on the discharge time of the RC circuit on GP0. See Example 4-2 for initializing the Ultra Low-Power Wake-up module.

The series resistor provides overcurrent protection for the GP0 pin and can allow for software calibration of the timeout (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adj ust ed to p rovid e t he d esi re d interrupt delay. This technique will com pensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temp erat ur e sen sor.

Note: For more i nforma tion , ref er to the Appl ic a-

tion Note AN879, “Using the Microchip

Ultra Low-Power Wake-up Module”

(DS00879).

 2004 Microchip Technology Inc. Preliminary DS41211B-page 33

PIC12F683

EXAMPLE 4-2: ULTRA LOW-POWER

WAKE-UP INITIALIZATION

BCF STATUS,RP0 ;Bank 0 BSF GPIO,0 ;Set GP0 data latch MOVLW H’7’ ;Turn off MOVWF CMCON0 ; comparator BSF STATUS,RP0 ;Bank 1 BCF ANSEL,0 ;GP0 to digital I/O BCF TRISIO,0 ;Output high to CALL CapDelay ; charge capacitor BSF PCON,ULPWUE ;Enable ULP Wake-up BSF IOC,0 ;Select GP0 IOC BSF TRISIO,0 ;GP0 to input MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON ; and clear flag SLEEP ;Wait for IOC

FIGURE 4-1: BLOCK DIAGRAM OF GP0

Data Bus

WPU

4.2.4 PIN DESCRIPTIONS AND DIAGRAMS

Each GPIO pin is m ul tipl ex ed w ith o the r fu nc tio ns. Th e pins and their c om bi ned f unc tions are briefly des c ribe d here. For specific inform ation about indivi dual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet.

4.2.4.1 GP0/AN0/CIN+/ICSPDAT/ULPWU

Figure 4-1 shows the diagram for this pin . The GP0 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• an analog input to the comparator

• an analog input to the Ultra Low-Power Wake-up

• In-Circuit Seria l Programming data

Analog

Input Mode

(1)

VDD

Weak

GPPU

VDD

GPIO

TRISIO

GPIO

IOC

Interrupt-on-

Note 1: Comparator mode and ANSEL determines Analog Input mode.

Change

To Comparator To A/D Converter

Analog

Input Mode

RD GPIO

(1)

ULPWUE

I/O pin

VSS

IULP

DS41211B-page 34 Preliminary  2004 Microchip Technology Inc.

PIC12F683

4.2.4.2 GP1/AN1/CIN-/VREF/ICSPCLK

Figure 4-1 shows the diagram for this pin. T he GP1 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• a analog input to the comparator

• a voltage reference input for the A/D

• In-Circuit Serial Programming clock

FIGURE 4-2: BLOCK DIAGRAM OF GP1

Data

Bus

WPU

GPIO

TRISIO

GPIO

IOC

Interrupt-on-

change

To Comparator

To A/D Converter

Analog

Input Mode

RD GPIO

(1)

GPPU

Analog

VDD

Weak

VDD

I/O pin

VSS

(1)

4.2.4.3 GP2/AN2/T0CKI/INT/COUT/CCP1

Figure 4-3 shows the diagram for this pin . The GP2 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• the clock input for TMR0

• an external edge triggered interrupt

• a digital output from the comparator

• a digital input/output for the CCP (refer to

Section 11.0 “Capture/Compare/PWM (CCP) Module”).

FIGURE 4-3: BLOCK DIAGRAM OF GP2

Data

Bus

WPU

GPIO

TRISIO

GPIO

WR IOC

IOC

Interrupt-on-

change

Analog

Input Mode

GPPU

COUT

Enable

COUT

Input Mode

Analog

Mode

1 0

Analog

RD GPIO

Input

VDD

Weak

VDD

I/O pin

VSS

Note 1: Comparator mode and ANSEL determines Analog

Input mode.

Note 1: Comparator mod e and ANSEL determine s Analog

To TMR0 To INT

To A/D Converter

Input mode.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 35

PIC12F683

4.2.4.4 GP3/MCLR/VPP

Figure 4-4 shows the diagram for this pin. T he GP3 pin is configurable to function as one of the following:

• a general purpose input

• as Master Clear Reset with weak pull-up

FIGURE 4-4: BLOCK DIAGRAM OF GP3

VDD

Data

Bus

TRISIO

GPIO

IOC

Interrupt-on-

change

MCLRE

Reset

VSS

MCLRE

RD GPIO

Weak

Input

4.2.4.5 GP4/AN3/T1G

/OSC2/CLKOUT

Figure 4-5 shows the diagram for this pin . The GP4 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• a TMR1 gate input

• a crystal/resona tor connec tio n

• a clock output

FIGURE 4-5: BLOCK DIAGRAM OF GP4

Analog

Data

Bus

WPU

GPIO

TRISIO

GPIO

WR IOC

IOC

Input Mode

OSC1

Fosc/4

CLKOUT

INTOSC/

RC/EC

CLKOUT

Enable

Input Mode

CLK

Modes

GPPU

Oscillator

Circuit

CLKOUT

Enable

1 0

(2)

Analog

(1)

VDD

Weak

VDD

I/O pin

VSS

Interrupt-on-

change

To T1G To A/D Converter

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option.

RD GPIO

DS41211B-page 36 Preliminary  2004 Microchip Technology Inc.

4.2.4.6 GP5/T1CKI/OSC1/CLKIN

Figure 4-6 shows the diagram for this pin. T he GP5 pin is configurable to function as one of the following:

• a general purpose I/O

•a TMR1 clock input

• a crystal/resonator connection

• a clock input

FIGURE 4-6: BLOCK DIAGRAM OF GP5

INTOSC

Data

Bus

WPU

GPIO

Mode

TMR1LPEN

GPPU

Oscillator

Circuit

OSC2

(1)

VDD

Weak

VDD

PIC12F683

TRISIO

GPIO

IOC

Interrupt-on-

change

To TMR1 or CLKGEN

Note 1: Timer1 LP oscillator enabled.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

INTOSC

Mode

RD GPIO

I/O pin

VSS

(1)

 2004 Microchip Technology Inc. Preliminary DS41211B-page 37

PIC12F683

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Addr Na m e B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h GPIO 0Bh/8Bh INTCON GIE 19h CMCON0 81h OPTION_REG GPPU 85h TRISIO 95h WPU 96h IOC 9Fh ANSEL Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xx00 --uu uu00

PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

— COUT — CINV CIS C M2 CM1 CM0 -0-0 0000 -0-0 0000

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 — —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 --11 -111 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111

Value on:

POR, BOD

Value on

all other

Resets

DS41211B-page 38 Preliminary  2004 Microchip Technology Inc.

PIC12F683

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock Figure 5-1 is a block diagram of the T ime r0 module an d

the prescaler shared with the WDT.

Note: Additional information on the Timer0

module is available in the “PICmicro

Mid-Range MCU Family Reference Manual” (DS33023).

5.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written , the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge.

Note: Counter mode has specific external clock

requirements. Additional information on these requirements is available in the

”PICmicro

Mid-Range MCU Family

Reference Manual (DS33023).

5.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCO N<5 >). The T0IF bit must be cleared in softwa re by the T i mer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT

(= FOSC/4)

T0CKI

T0SE

WDTE

SWDTEN

31 kHz INTRC

Note 1: T0SE, T0CS, PSA and PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.

T0CS

Watchdog

Timer

PSA

16-bit

Prescaler

8-bit

Prescaler

WDTPS<3:0>

PSA

PS<2:0>

PSA

SYNC 2

Cycles

WDT

Time-out

Data Bus

TMR0

Set Flag bit T0IF

on Overflow

 2004 Microchip Technology Inc. Preliminary DS41211B-page 39

PIC12F683

5.3 Using Timer0 with an External Clock

When no pr escal er is us ed, t he ex ternal clock inpu t is the same as the prescaler outp ut. Th e synchronization of T0CKI, with the internal phase clocks, is accomplished by sampli ng the prescale r output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CK I to b e high for at leas t 2 T a small RC delay of 20 ns) and low for at least 2 T

OSC (and

OSC

(and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.

Note: The ANSEL (9Fh) and CMCON0 (19h)

registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

5.4 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as “prescaler” throughout this data sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>).

The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.

5.4.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 5-1 and Example 5-2) must be executed when changing the prescaler assignment from Timer0 to WDT.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0 → WDT)

BCF STATUS,RP0 ;Bank 0 CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and

; prescaler

BSF STATUS,RP0 ;Bank 1

MOVLW b’00101111’ ;Required if desired MOVWF OPTION_REG ; PS2:PS0 is CLRWDT ; 000 or 001

; MOVLW b’00101xxx’ ;Set postscaler to MOVWF OPTION_REG ; desired WDT rate BCF STATUS,RP0 ;Bank 0

To change prescaler from the WDT to the TMR0 module, use the se quence show n in Examp le 5-2. This precaution must be t aken even if the WDT is disabl ed.

EXAMPLE 5-2: CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT ;Clear WDT and

; prescaler

BSF STATUS,RP0 ;Bank 1

MOVLW b’xxxx0xxx’ ;Select TMR0,

MOVWF OPTION_REG ; BCF STATUS,RP0 ;Bank 0

; prescale, and ; clock source

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE 81h OPTION_REG 85h TRISIO Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

Value on

POR, BOD

Value on all other

Resets

DS41211B-page 40 Preliminary  2004 Microchip Technology Inc.

PIC12F683

6.0 TIMER1 MODULE WITH GATE CONTROL

The PIC12F683 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features:

• 16-bit timer/counter (TMR1H:TMR1L)

The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module.

Note: Addition al i nfo rma t io n o n ti me r m odu les i s

available in the PICmicro

MCU Family Reference Manual

(DS33023).

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input

- Selectable gate source: T1G

or COUT

(T1GSS)

- Selectable gate polarity (T1GINV)

• Optional LP oscillat or

FIGURE 6-1: TIMER1 ON THE PIC12F683 BLOCK DIAGRAM

Set Flag bit TMR1IF on Overflow

TMR1H

TMR1

(1)

TMR1L

To Comparator Module TMR1 Clock

TMR1ON TMR1GE

Synchronized

Clock Input

Mid-Range

T1GINV

Oscillator

OSC1/T1CKI

OSC2/T1G

INTOSC

without CLKOUT

T1OSCEN

Note 1: Timer1 increments on the rising edge.

2: ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI.

(2)

OSC/4

Internal Clock

TMR1CS

T1SYNC

Prescaler

1, 2, 4, 8

T1CKPS<1:0>

COUT

Synchronize

det

Sleep Input

T1GSS

 2004 Microchip Technology Inc. Preliminary DS41211B-page 41

PIC12F683

6.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every

instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the micr oc ont roll er sy ste m cl oc k or run asynchronously.

In Counter and Timer modules, the counter/t imer cl oc k can be gated by the Timer 1 gate, which can be selected as either the T1G output.

If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source.

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first incrementing rising edge.

pin or the comparator

6.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the inte rrupt on rollo ver , you must set these bits :

• Timer1 interrupt enable bit (PIE1<0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

6.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.

6.4 Timer1 Gate

Timer1 gate source is software configurable to be the T1G

pin or the output of the comparator. This allows the device to directly time external events using T1G analog events using the comparator. See CMCON1 (Register 8-2) for selecting the Timer1 gate source. This feature can si mplify the softwa re for a Delta-Si gma A/D converter and many other applications. For more information on Delta-Sigma A/D Converters, see the Microchip web site (www.microchip.com).

Note: TMR1GE bit (T1CON<6>) must be set to

use either T1G gate source. See Register 8-2 for more information on selecting the Timer1 gate source.

Timer1 gate can be inverted by using the T1GINV bit (T1CON<7>), whether it origin ates fro m the T1G the comparator output. This configures Timer1 to measure either the active-high or active-low time between events.

or COUT as the Timer1

pin or

Note: The TMR1 H:TTMR1L reg ister pair and the

TMR1IF bit should be cleared before enabling interrupts.

FIGURE 6-2: TIMER1 INCREMENTING EDGE

T1CKI = 1 when TMR1 Enabled

T1CKI = 0 when TMR1 Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the

clock.

DS41211B-page 42 Preliminary  2004 Microchip Technology Inc.

PIC12F683

REGISTER 6-1: T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

bit 7 bit 0

TMR1CS TMR1ON

bit 7 T1GINV: Timer1 Gate Invert bit

1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = This bit is ignored.

If TMR1ON =

1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off

Else: This bit is ignored.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (F

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

OSC/4)

(1)

(2)

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G

bit (CMCON1<1>), as a Timer1 gate source.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 43

pin or COUT , as selected by the T1GSS

PIC12F683

6.5 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and ca n generate an interrupt on overflow, which will wake-up the processor. H owever , special precautions in software are needed to read/write the timer (see Section 6.5.1

“Reading and Writing Timer1 in Asynchronous Counter Mode”).

Note: The ANSEL (9Fh) and CMCON0 (19h)

registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

6.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asy nchronous cl ock will ens ure a valid read (taken care of in hardware). However, the user should keep in min d that re ading t he 16-b it time r in tw o 8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recomm ended that the us er simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementi ng. This may pro duce an unpredictable value in the timer register.

Reading the 16-bit value requires some care. Examples in the “PICmicro Reference M anual (DS33023) show how to read and write Ti mer1 wh en it i s runni ng in Async hronou s mode.

Mid-Range MCU Family

6.6 Timer1 Oscillator

A crystal oscilla tor circuit is built-in between pin s OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 32 kHz. It will continue to run during Sleep. It i s primaril y inten ded for a 32 kHz crystal. Table 3-1 shows the capacitor selection for the T im er1 osc il lat or.

The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up.

TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is enabled. GP5 and GP4 read as ‘0’ and TRISIO5 and TRISIO4 bits read as ‘1’.

Note: The oscillator requires a start-up and

stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.

6.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in Asynchronous Counte r mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit

(INTCON<7>) is set, the devi ce w il l wake -up and jump to the Interrupt Service Routine (0004h) on an overflow . If the GIE bit is clear, executio n will contin ue with the next instruction.

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/

INTCON GIE PEIE

8Bh 0Ch PIR1 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR 1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 1Ah CMCON1 8Ch PIE1 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

DS41211B-page 44 Preliminary  2004 Microchip Technology Inc.

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

— — — — — —T1GSSCMSYNC ---- --10 ---- --10

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Value on

POR, BOD

Val ue on all other

Resets

PIC12F683

7.0 TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 7-1.

TMR2 can be shut off by cleari ng control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 7-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register.

7.1 Timer2 Operation

Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The in put cl ock (F of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS<1:0> (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).

The prescaler and postscaler counters are cleared when any of the following occurs:

• A write to the TMR2 register

• A write to the T2CON register

• Any device Reset (Power-on Reset, MCLR Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

OSC/4) has a prescale option

REGISTER 7-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 T OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Reset,

bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits

0000 = 1:1 postscale 0001 = 1:2 postscale

•

• 1111 = 1:16 postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 45

PIC12F683

7.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

OSC/4

Prescaler

1:1, 1:4, 1:16

T2CKPS<1:0>

TMR2

Comparator

PR2

Reset

TMR2 Output

Postscaler

1:1 to 1:16

TOUTPS<3:0>

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2

Addr Name Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/

INTCON GIE PEIE

8Bh 0Ch PIR1 11h TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 12h T2CON 8Ch PIE1 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

Val ue on

POR, BOD

Value o n all other

Resets

DS41211B-page 46 Preliminary  2004 Microchip Technology Inc.

PIC12F683

8.0 COMPARATOR MODULE

The comparator module contains one analog comparator. The inputs to the comparator are multiplexed with I/O port pins, GP0 and GP1, while the outputs are multiplexed to GP2. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparator.

The CMCON0 register (Register 8-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 8-3.

REGISTER 8-1: CMCON0 – COMPARATOR CONTROL REGISTER 0 (ADDRESS: 19h)

U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—COUT— CINV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’ bit 6 COUT: Comparator Output bit

When CINV = 1 = VIN+ > VIN-

IN+ < VIN-

0 = V When CINV = 1:

1 = VIN+ < VIN- 0 = V

IN+ > VIN-

bit 5 Unimplemented: Read as ‘0’ bit 4 CINV: Comparator Output Inversion bit

1 = Output inverted 0 = Output not inverted

bit 3 CIS: Comparator Input Sw itch bit

When CM<2:0> = 1 = VIN- connects to CIN+

IN- connects to CIN-

0 = V

bit 2 CM<2:0>: Comparator Mode bits

Figure 8-3 shows the Comparator modes and CM<2:0> bit settings.

110 or 101:

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 47

PIC12F683

8.1 Comparator Operation

A single comparator is shown in Figure8-1 along with the relationship between the analog input levels and the digital output . When the analo g input at V than the analog input V

IN-, the output of the compara tor

is a digital low level. When the analog input at V greater than the analog input V

IN-, the output of the

comparator is a digital high level. The shaded areas of the output of the comparator in Figure 8-1 represent the uncertainty due to input offsets and response time.

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be programmed in the CMCON0 (19h) register.

The polarity of the comparator output can be inverted by setting the CINV bit (CMCON0<4>). Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1.

TABLE 8-1: OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions CINV COUT

IN- > VIN+ 00

IN- < VIN+ 01

V VIN- > VIN+ 11 VIN- < VIN+ 10

IN+ is less

IN+ is

FIGURE 8-1: SINGLE COMPARATOR

VIN-

IN–

VIN+

IN+

Output

utput

VIN+ VIN-

Output

–

8.2 Analog Input Connection Considerations

A simplified circuit for an analog input is shown in Figure 8-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, th erefore, must be b etween

SS and VDD. If the input voltage deviates from this

V range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source i mpedance of 10 k Ω is recommended for the analog sources. Any external component connected to an analog inpu t pin , suc h as a capaci tor or a Zener diode, should have very little leakage current.

Note 1: When reading the GPIO register, all pins

configured as anal og inp uts will read as a ‘0’. Pins configured as digital inputs will convert as analog inpu t s acc ord ing to th e input specification.

2: Analog levels on any pin defined as a

digital input may cau se the in put bu ffer to consume more current than is specified.

FIGURE 8-2: ANALOG INPUT MODEL

Rs < 10K

CPIN

5 pF

VT = 0.6V

T = 0.6V

ILEAKAGE ±500 nA

Vss

Legend:CPIN = Input Capacitance

T = Threshold Voltage

V I

LEAKAGE = Leakage Current at the pin due to various junctions

IC = Interconnect Resistance

S = Source Impedance

R VA = Analog Voltage

DS41211B-page 48 Preliminary  2004 Microchip Technology Inc.

RIC

PIC12F683

8.3 Comparator Configuration

There are eight mod es of operat ion fo r the comp arato r. The CMCON0 register is used to select these modes.

Note: Comparator interr upts sh ould be dis abled

during a Comparator mode change.

Otherwise, a false interrupt may occur. Figure 8-3 shows the eight possible modes. If the Comparator mode is changed, the comparator

output level may not be valid for the specified mode change delay shown in Section 15.0 “Electrical

Specifications”.

FIGURE 8-3: COMPARATOR I/O OPERATING MODES

Comparator Reset (POR Default Value – Low Power) Comparator Off (Lowest Power) CM<2:0> = 000 CM<2:0> = 111

GP1/CINGP0/CIN+

GP2/COUT D

A A

Off (Read as ‘0’)

Comparator without Output Comparator w/o Output and with Internal Reference CM<2:0> = 010 CM<2:0> = 100

GP1/CINGP0/CIN+

A A

COUT

GP1/CINGP0/CIN+

GP2/COUT D

GP1/CINGP0/CIN+

D D

A D

Off (Read as ‘0’)

COUT

GP2/COUT D

From CVREF Module

Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output CM<2:0> = 011 CM<2:0> = 101

GP1/CINGP0/CIN+

GP2/COUT D

A D

From CVREF Module

COUT

GP1/CINGP0/CIN+

GP2/COUT D

CIS = 0

CIS = 1

From CVREF Module

COUT

Comparator with Output Multiplexed Input with Internal Reference CM<2:0> = 001 CM<2:0> = 110

GP1/CINGP0/CIN+

GP2/COUT D

A A

COUT

GP1/CINGP0/CIN+

GP2/COUT D

CIS = 0

CIS = 1

From CVREF Module

COUT

Legend: A = Analog Input, ports always read ‘0’ CIS = Comparator Input Switch (CMCON0<3>)

D = Digital Input

 2004 Microchip Technology Inc. Preliminary DS41211B-page 49

PIC12F683

FIGURE 8-4: COMPARATOR OUTPUT BLOCK DIAGRAM

MULTIPLEX

Port Pins

CMSYNC

To TMR1

To COUT pin

CINV

To Data Bus

RD CMCON

Set CMIF bit

Note 1: Comparator output is latched on falling edge of T1 clock source.

Clock Source

Reset

TMR1

(1)

RD CMCON

REGISTER 8-2: CMCON1 – COMPARATOR CONTROL REGISTER 1 (ADDRESS: 1Ah)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

— — — — — — T1GSS CMSYNC

bit 7 bit 0

bit 7-2: Unimplemented: Read as ‘ 0’ bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is T1G

pin (GP4 must be configured as digital input)

0 = Timer1 gate source is comparator output

bit 0 CMSYNC: Comparator Synchronize bit

1 = COUT output synchronized with falling edge of Time r1 clo ck 0 = COUT output not synchronized with Timer1 clock

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 50 Preliminary  2004 Microchip Technology Inc.

PIC12F683

8.4 Comparator Output

The comparator output is read through the CMCON0 register. This bit is read-on ly. The comparator output may also be directly output to the GP2 pin. When enabled, multiplexors in the output path of the GP2 pin will switch and th e output will b e the unsync hronized output of the comparator. The uncertainty of the comparator is relat ed to the input offset voltage and the response time given in the specifications. Figure 8-4 shows the output block diagram for the comparator.

The TRISIO bit will still function as an output enable/ disable for the GP2 pin while in this mode.

The polarity of the comparator outputs can be changed using the CINV bit (CMCON0<4>).

Timer1 gate source can be configured to use the T1G pin or the comparator output as selected by the T1GSS bit (CMCON1<1>). This featu re can be used to time the duration or interval of analog events. The output of the comparator can also be synchro nized with Timer1 by setting the CMSYNC bit (CMCON1<0>). When enabled, the output of th e comp arat or is latc hed on the falling edge of the T imer1 clock source. I f a prescal er is used with Timer1, the comparator is latched after the prescaler. To prevent a race condition, the comparator output is latched on the fall ing edge o f the T imer1 clock source and Timer1 increments on the rising edge of its clock source. See Figure 8-4, Comparator Output Block Diagram and Figure 6-1, Timer1 on the PIC12F683 Block Diagram for more information.

It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment.

8.5 Comparator Interrupt

The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Software will need to maintain information about the status of the output bit, as read from CMCON0<6>, to determine the actual change that has occurred. The CMIF bit (PIR1<3>) is the Comparator Interrupt Flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, th e interrupt is n ot enabled, th ough the CMIF bit will still be set if an interrupt condition occurs.

The user , in the Interru pt Service Routi ne, can cle ar the interrupt in the following manner:

a) Any read or write of CMCON0. This will end the

mismatch condition.

b) Clear flag bit CMIF. A mismatch condition will co nti nue to set flag bit CMIF.

Reading CMCON0 w ill end the m ismatch co ndition and allow flag bit CMIF to be cleared.

Note: If a change in the CMCON0 register

(COUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CMIF (PIR1<3>)

interrupt flag may not get set.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 51

PIC12F683

8.6 Comparator Reference

The comparato r m od ule al so allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-5.

8.6.2 VOLTAGE REFERENCE ACCURACY/ERROR

The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom o f the resistor ladder netw ork (Figure 8 -5) keep CV

REF from approaching VSS or VDD. The excep-

tion is when the module is disabled by clearing the VREN

8.6.1 CONFIGURING THE VOLTAGE REFERENCE

The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range.

The following equation determines the output volt ages:

EQUATION 8-1:

VRR = 1 (Low Range): CVREF = (VR3:VR0/24) x VDD VRR = 0 (High Range):

REF = ( VDD/4) + (VR3:VR0 X VDD/32)

bit (VRCON<7>) . When disa bled, the r eferenc e voltage

SS when VR<3:0> is ‘0000’ and the VRR

is V (VRCON<5>) bi t is set. This allows the comparator to detect a zero- c ro ss in g and n ot cons um e CV current.

The voltage referen ce is VDD derived and therefore, the

REF output changes with fluctuations in VDD. The

CV tested absolute accuracy of the comparator voltage reference can be found in Section 15.0 “Electrical

Specifications”.

FIGURE 8-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8RRR RR

VDD

REF module

VREN

CVREF to

Comparator

Input

16-1 Analog

MUX

VR<3:0>

VREN VR<3:0> = 0000 VRR

VRR

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PIC12F683

8.7 Comparator Response Time

Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator output. Otherwise, the maximum delay of the comparator should be used (Table 15-8).

8.8 Operation During Sleep

The comparator and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep curre nts than sh own in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power cons umption whil e in Sleep mod e, turn off the comparator, CM<2:0> = 111 and voltage reference, VRCON<7> = 0.

While the comp arator is enabl ed during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h) and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected.

8.9 Effects of a Reset

A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.

REGISTER 8-3: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN

bit 7 bit 0

—VRR— VR3 VR2 VR1 VR0

bit 7 VREN: CV

1 = CV 0 = CV

bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit

1 = Low range 0 = High range

bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CV

When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REF Enable bit

REF circuit powered on REF circuit powered down, no IDD drain and CVREF = VSS

REF Value Selection 0 ≤ VR <3:0> ≤ 15

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TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/8Bh INTCON GIE PEIE 0Ch PIR1 19h CMCON0 1Ah CMCON1 85h TRISIO 8Ch PIE1 99h VRCON VREN Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or

comparator voltage reference module.

EEIF ADIF CCP1IF —CMIFOSFIF TMR2IF TMR1IF 000- 0000 000- 0000

—COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

EEIE ADIE CCPIE —CMIEOSFIE TMR2IE TMR1IE 000- 0000 000- 0000

—VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

Value on

POR, BOD

Val ue on

all other

Resets

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PIC12F683

9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC12F683 has four analog inputs, multiplexed into one sample and hold

FIGURE 9-1: A/D BLOCK DIAGRAM

VDD

VREF

GP0/AN0

GP1/AN1/VREF

GP2/AN2

GP4/AN3

CHS<1:0>

VCFG = 0 VCFG = 1

GO/DONE

ADON

circuit. The output of the sam ple and hold is conne cted to the input of the converter. The con verter gen erates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either

DD or a voltage applied by the VREF pin. Figure 9-1

V shows the block dia gram of the A/D on the PIC12 F683.

A/D

ADFM

VSS

ADRESH ADRESL

9.1 A/D Configuration and Operation

There are two registers available to control the functionality of the A/D module:

1. ADCON0 (Register 9-1)

2. ANSEL (Register 9-2)

9.1.1 ANALOG PORT PINS

The ANS<3:0> bits (ANSEL<3:0 >) and the TRISIO bit s control the operation of the A/D port pins. Set the corresponding TRISIO bits to set the pin output drive r to it s high-impedance st ate. Likewi se, set the corres pondin g ANSEL bit to disable the digital input buffer.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input buffer to conduct excess current.

9.1.2 CHANNEL SELECTION

There are four analog channels on the PIC12F683, AN0 through AN3. The CHS bits (ADCON0<3:2>) control which channel is connected to the sample and hold circuit.

9.1.3 VOLTAGE REFERENCE

There are two options for the voltage reference to the A/D converter: either V applied to V

REF is used. The VCFG bit (ADCON0<6>)

DD is used, or an analog volt age

controls the volt age reference s election. If VC FG is set, then the voltage on the VREF pin is the reference; otherwise, V

DD is the reference.

9.1.4 CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ANSEL<6:4>). There are seven possible clock options:

OSC/2

•F

•FOSC/4

•F

OSC/8

•FOSC/16

•FOSC/32

•F

OSC/64

•FRC (dedicated internal oscillator) For correct conversion, the A/D conversion clock

AD) must be selecte d to ensure a minimum TAD of

(1/T

1.6 µs. Table 9-1 shows a few T selected frequencies.

AD calculations for

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TABLE 9-1: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD) Device Frequency

Operation ADCS<2:0> 20 MHz 5 MHz 4 MHz 1.25 MHz

2 T

OSC 000 100 ns

4 TOSC 100 200 ns 8 TOSC 001 400 ns

OSC 101 800 ns

16 T

(2) (2) (2) (2)

32 TOSC 010 1.6 µs6.4 µs 8.0 µs 64 TOSC 110 3.2 µs 12.8 µs

A/D RC x11 2-6 µs

(1,4)

Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be performed during Sleep.

400 ns 800 ns

(2) (2)

500 ns

1.0 µs

(2)

1.6 µs

3.2 µs

1.6 µs2.0 µs6.4 µs

3.2 µs4.0 µs 12.8 µs

2-6 µs

(3)

(1,4)

16.0 µs 2-6 µs

(3)

(1,4)

25.6 µs

51.2 µs

2-6 µs

(3) (3) (3)

(1,4)

DS41211B-page 56 Preliminary  2004 Microchip Technology Inc.

PIC12F683

9.1.5 STARTING A CONVERSION

The A/D conversion is initiated by setting the GO/DONE

bit (ADCON0 <1> ). W hen th e co nvers ion is

complete, the A/D module:

• Clears the GO/DONE

bit

• Sets the ADIF flag (PIR1<6>)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE

bit can be cleared in software. The ADRESH:ADRESL registers will not be u pdated with th e pa rtiall y comple te

FIGURE 9-2: A/D CONVERSION TAD CYCLES

TCY to TAD

Set GO bit

TAD1 TAD2

b9 b8 b7 b6 b5 b4 b3 b2

Conversion Starts

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

TAD3

TAD4

TAD5 TAD6

A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of th e previous conversion. After an aborted conversion, a

AD delay is required before another acquisition can

2T be initiated. Following the delay, an input acquisition is automatically started on the selected channel.

Note: The GO/DONE bi t shou ld n ot be set in the

same instruction that turns on the A/D.

TAD10 TAD11

TAD7 TAD8

ADRESH and ADRESL registers are Loaded, GO bit is Cleared, ADIF bit is Set, Holding Capacitor is Connected to Analog Input

TAD9

b1 b0

9.1.6 CONVERSION OUTPUT

The A/D conversion can be s upplied in two forma ts: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure9-3 shows the output format s.

FIGURE 9-3: 10-BIT A/D RESULT FORMAT

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7bit 0bit 7bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)

bit 7bit 0bit 7bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

MSB LSB

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REGISTER 9-1: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh)

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

bit 7 ADFM: A/D Result Formed Select bit

1 = Right justified 0 = Left justified

bit 6 VCFG: Voltage Reference bit

1 = VREF pin 0 = V

bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS<1:0>: Analog Channel Select bits

00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3)

bit 1 GO/DONE

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. 0 = A/D conversion completed/not in progress

bit 0 ADON: A/D Conversion Status bit

1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current

: A/D Conversion Status bit

This bit is automatically cleared by hardware when the A/D conversion has completed.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 58 Preliminary  2004 Microchip Technology Inc.

PIC12F683

REGISTER 9-2: ANSEL – ANALOG SELECT REGISTER (ADDRESS: 9Fh)

U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 = F 001 = F 010 = F x11 = F 100 = F 101 = F 110 = F

bit 3-0 ANS<3:0>: Analog Select bits

Analog select between analog or digital function on pins ANS<3:0>, respectively.

1 = Analog input. Pin is assigned as analog input 0 = Digital I/O. Pin is assigned to port or special function.

OSC/2 OSC/8 OSC/32 RC (clock derived from a dedicated internal oscillator = 500 kHz max) OSC/4 OSC/16 OSC/64

(1)

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-ups and interrupt-on-change if available. The corresponding TRISIO bit must be set to input mode in order to al low external cont rol of the voltage on the pin.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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9.1.7 CONFIGURING THE A/D

After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRISIO bits selected as inputs.

To determine sample time, see Section 15.0 “Electri- cal Specifications”. After this sample time has elapsed, the A/D conversion can be started.

These steps sh ou ld be followed for an A/D c onv ers io n:

1. Configure the A/D module:

• Configure analog/digital I/O (ANSEL)

• Configure voltage reference (ADCON0)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ANSEL)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit (PIR1<6>)

• Set ADIE bit (PIE1<6>)

• Set PEIE and GIE bits (INTCON<7:6>)

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

(with interrupts disabled); OR

• Waiting for the A/D interrupt

6. Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required.

7. For nex t conversion, go to step 1 or s tep 2 as required. The A/D conversion time per bit is defined as T required before the next acquisiti on starts.

bit (ADCON0<1>)

bit to be cleared

AD. A minimum wait of 2 TAD is

EXAMPLE 9-1: A/D CONVERSION

;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and GP0 input. ; ;Conversion start & wait for complete ;polling code included. ; BSF STATUS,RP0 ;Bank 1 MOVLW B’01110001’ ;A/D RC clock MOVWF ANSEL ;Set GP0 to analog BSF TRISIO,0 ;Set GP0 to input BCF STATUS,RP0 ;Bank 0 MOVLW B’10000001’ ;Right, Vdd Vref, AN0 MOVWF ADCON0 CALL SampleTime ;Wait min sample time BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI BSF STATUS,RP0 ;Bank 1 MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO

DS41211B-page 60 Preliminary  2004 Microchip Technology Inc.

PIC12F683

9.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy , the charge holding capacitor (C fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (R impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (V

The maximum recommended impedance for analog sources is 10 kΩ.

S) and the internal sampling switch (RSS)

EQUATION 9-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= T = 2 µs + TC + [(Temperature – 25°C)(0.05 µs/°C)]

C = CHOLD (RIC + RSS + RS) In(1/2047)

= -120 pF (1 k = 16.47

ACQ = 2

HOLD) must be allowed to

DD), see Figure 9-4.

AMP + TC = TCOFF

Ω

+ 7 kΩ +10 kΩ) In(0.0004885)

s + 16.47

As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started.

To calculate th e m ini mu m acquisition time , Equ ati on91 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allo w ed fo r the A/D to me et its specified resolution.

To calculate the minimum acquisition time, T the “PICmicro

Manual” (DS33023).

Mid-Range MCU Family Reference

ACQ, see

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

HOLD) is not discharged after each conversion.

FIGURE 9-4: ANALOG INPUT MODEL

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9.3 A/D Operation During Sleep

The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the internal oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion . T his a llows the SLEEP instruction to be executed, thus elim inating much of the swi tc hin g n ois e from the conversion. When the conversion is complete, the GO/DONE into the ADRESH:ADRESL registers.

bit is cleared and the result is loaded

If the A/D interrupt is enabled, the device awakens from Sleep. If the GIE bit (INTCON<7>) is set, the program counter is set to the interrupt vector (0004h); if GIE is clear, the next instruction is executed. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set.

When the A/D clock source is something other than RC, a SLEEP instruction causes the presen t conversion to be aborted and the A/D module is turned off. The ADON bit remains set.

FIGURE 9-5: PIC12F683 A/D TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh 3FDh 3FCh 3FBh

004h

A/D Output Code

003h 002h 001h 000h

1 LSB ideal

Full-Scale Transition

Analog Input Voltage

Zero-Scale Transition

REF

DS41211B-page 62 Preliminary  2004 Microchip Technology Inc.

9.4 Effects of Reset

A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.

TABLE 9-2: SUMMARY OF A/D REGISTERS

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h GPIO

—n5()-99T

PIC12F683

Val ue on:

POR, BOD

Value o n

all other

Resets

 2004 Microchip Technology Inc. Preliminary DS41211B-page 63

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NOTES:

DS41211B-page 64 Preliminary  2004 Microchip Technology Inc.

PIC12F683

10.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDA T

• EEADR EEDAT holds the 8-bit data for read/write and EEADR

holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of dat a EEPROM with an address range from 0h to FFh.

DD range). This memory

The EEPROM data memory allows b yte read and write. A byte write automatically erases the location and writes the new data (erase be fore write). The EEPROM data memory is rated fo r high er ase/writ e cycles. T he write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to AC Specifications in Section 15.0 “Electrical Specifications” for exact limits.

When the data memory is code protected, the CPU may continue to read and write the data EEPROM memory . The device progra mmer can no longer access the data EEPROM data and will read zeroes.

Additional information on the data EEPROM is available in the “PICmicro

Reference Manual” (DS33023).

Mid-Range MCU Family

REGISTER 10-1: EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT 1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte Value to Write to or Read From Data EEPROM bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 10-2: EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

bit 7 bit 0

bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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10.1 EECON1 and EECON2 Registers

EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as ‘0’.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or wr i t e ope r a tio n. T he ina bi l it y t o cl ea r t he WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is c lear . The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation.

In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initializ ed.

Interrupt flag, EEIF bit (PIR1<7>), is set when write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence.

Note: The EECON1, EEDAT and EEADR

registers should not be modified during a data EEPROM write (WR bit = 1).

REGISTER 10-3: EECON1 – EEPROM CONTROL REGISTER (ADDRESS: 9Ch)

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit

1 = A write oper ation is pr ematurely terminated (any MCLR

normal operation or BOD detect)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles 0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit

can only be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

Reset, any WDT Reset during

Legend:

S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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10.2 Reading the EEPROM Data Memory

T o read a d ata memory loca tion, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 10-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).

EXAMPLE 10-1: DATA EEPROM READ

BSF STATUS,RP0 ;Bank 1 MOVLW CONFIG_ADDR ; MOVWF EEADR ;Address to read BSF EECON1,RD ;EE Read MOVF EEDAT,W ;Move data to W

10.3 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 10-2.

EXAMPLE 10-2: DAT A EEPROM WRITE

BSF STATUS,RP0 ;Bank 1 BSF EECON1,WREN ;Enable write BCF INTCON,GIE ;Disable INTs MOVLW 55h ;Unlock write MOVWF EECON2 ; MOVLW AAh ; MOVWF EECON2 ;

Required

Sequence

BSF EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS

The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. A ny number th at is not equa l to the required cycles to execute the required sequence will prevent the data from being writte n into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the WREN bit will not af fect this writ e cycle. The WR bit will be inhibited from being s et u nle ss the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR1<7>) must be cleared by software.

10.4 Write Verify

Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example10-3) to the desired value to be written.

EXAMPLE 10-3: WRITE VERIFY

BSF STATUS,RP0 ;Bank 1 MOVF EEDAT,W ;EEDAT not changed

;from previous write

BSF EECON1,RD ;YES, Read the

;value written XORWF EEDAT,W BTFSS STATUS,Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue

10.4.1 USING THE DATA EEPROM

The data EEPROM is a hi gh-endu rance, byte a ddress able array that has been optimized for the storage of frequently changing information. The maximum endurance for any EEPROM cell is specified as Dxxx. D120 or D120A specify a maximum number of writes to any EEPROM location before a refresh is required of infrequently changing memory locations.

10.4.1.1 EEPROM Endurance

A hypothetical data EEPROM i s 6 4 b yt es lon g a nd ha s an endurance of 1M w rites. It also h as a refresh p arameter of 10M writes. If every memory location in the cell were written the maximum number of times, the data EEPROM would fail after 64M write cycles. If every memory location, save one , were writt en the ma ximum number of times, the data EEPROM would fail after 63M write cycles but the one remaining location could fail after 10M cycles. If proper re freshes occurred , the n the lone memory location would have to be refreshed six times for the data to remain correct.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 67

PIC12F683

10.5 Protection Against Spurious Write

There are c onditions when the user may no t want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Als o, the Power-up Timer (64 ms duration) prevents EEPROM write.

The write initiate se quence and the WREN bit togeth er help preven t an acciden tal write during:

• brown-out

• power glitch

• software malfunction

10.6 Data EEPROM Operation During Code-Protect

Data memory can be code-p rotected by progr amming the CPD bit in the Co nfigur ation Word (Regis ter 12-1) to ‘0’.

When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached.

TABLE 10-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/8Bh INT CON GIE PEIE 0Ch PIR1 EEIF 8Ch PIE1 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 9Dh EECON2 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by data EEPROM module.

Note 1: EECON2 is not a physical register.

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

(1)

EEPROM Control Register 2 ---- ---- ---- ----

ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

— — — — WRERR WREN WR RD ---- x000 ---- q000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

Value on

POR, BOD

Value on

all other

Resets

DS41211B-page 68 Preliminary  2004 Microchip Technology Inc.



PIC12F683

11. 1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 regi ster when an event occu rs on pin GP2/AN2/T0CKI/INT/COUT/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge When a capture is made, the interrupt request flag bit,

CCP1IF (PIR1<5>), is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.

11.1.1 CCP1 PIN CONFIGURATION

In Capture mode, the GP2/AN2/T0CKI/INT/COUT/ CCP1 pin should be configured as an input by setting the TRISIO<2> bit.

Note: If the GP2/AN2/T0CKI/INT/COUT/CCP1

pin is configured as an output, a write to the port can cause a capture condition.

FIGURE 11-1: CAPTURE MODE

OPERATION BLOCK DIAGRAM

Set Flag bit CCP1IF

(PIR1<5>)

CCPR1H CCPR1L

Capture Enable

TMR1H TMR1L

GP2/CCP1 pin

Prescaler ÷ 1, 4, 16

and

Edge Detect

CCP1CON<3:0>

Q’s

11.1.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.

11.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<5>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.

11.1.4 CCP PRESCALER

There are four prescaler settings specified by bits CCP1M<3:0> (CCP1CON<3:0>). Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler co unter is cleared. Any R eset will clear the prescaler counter.

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first cap ture may be from a non-zero prescaler. Example11-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 11-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with

;the new prescaler ;move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

;value

DS41211B-page 70 Preliminary  2004 Microchip Technology Inc.

PIC12F683

11.2 Compare Mode

In Compare mo de, th e 16- bit CCP R1 re gist er valu e is constantly compared against the TMR1 register pair value. When a match occ urs, the GP2/AN2/ T0CKI/INT/ COUT/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged The action on the pin is based on the value of control

bits, CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit, CCP1IF (PIR1<5>), is set.

FIGURE 11-2: COMPARE MODE

OPERATION BLOCK DIAGRAM

CCP1CON<3:0>

Mode Select

Set Flag bit CCP1IF

Output

Logic

(PIR1<5>)

Match

CCPR1H CCPR1L

Comparator

TMR1H TMR1L

GP2/CCP1

TRISIO<2>

Output Enable

Special Event Trigger

Special Event Trigger will:

• Clear TMR1H and TMR1L registers

• NOT set interrupt flag bit TMR1F (PIR1<0>)

• Set the GO/DONE

bit (ADCON0<1>)

11.2.1 CCP1 PIN CONFIGURATION

The user must configure the GP2/AN2/T0CKI/INT/ COUT/CCP1 pin as an output by clearing the TRISIO<2> bit.

Note: Clearing the CCP1CON register will

force the GP2/AN2/T0CKI/INT/COUT/ CCP1 compare output latch to the default low level. This is not the GPIO data latch.

11.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

11.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CC P1 pin is not affected. The CCP1IF (PIR1<5>) bit is set, causing a CCP interrupt (if enabled). See Register 11-1.

11.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is gene rated, which may be used to initiate an action.

The special event trigger output of CCP1 resets the TMR1 register pair and starts A/D conversion, if enabled. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.

Note: The special event trigger from the CCP1

modules will not set interrupt flag bit TMR1IF (PIR1<0>).

TABLE 11-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Addr Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/

INTCON GIE PEIE

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 1Ah CMCON1 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu 15h CCP1CON — — DC1B1 DC1B 0 CCP1M3 CCP1M2 CCP1M1 CCP1M 0 0000 0000 0000 0000 8Ch PIE1 Legend: — = unimplemented locations, read as ‘0’, u = unchanged, x = unknown.

Shaded cells are not used by the Capture, Compare or Timer1 module.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 71

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

— — — — — —T1GSSCMSYNC ---- --10 ---- --10

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Value on

POR, BOD

Value on

all other

Resets

PIC12F683

11.3 PWM Mode (PWM)

In Pulse Width Modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the GPIO data latch, the TRISIO<2> bit must be cleared to make the CCP1 pin an output.

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to th e de fau lt low level. This is not the GPIO data latch.

Figure 11-3 shows a simplified block diagram of the CCP module in PWM mode.

For a step-by-step procedure on how to set up the C CP module for PWM operation, see Section 11.3.3

“Setup for PWM Operation”.

FIGURE 11-3: SIMPLIFIED PWM BLOCK

DIAGRAM

Duty Cycle Registers CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

Note 1: The 8-bit timer i s concatenated with 2-bit inte rnal Q

(Note 1)

Clear Timer, CCP1 pin and latch D.C.

clock, or 2 bits of the prescaler, to create 10-bit time base.

CCP1CON<5:4>

TRISIO<2>

GP2/CCP1

FIGURE 11-4: PWM OUTPUT

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

11.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula.

EQUATION 11-1:

PWM Period = [(PR2) + 1] • 4 • To sc • TMR2 Pr escale Value

PWM frequency is defined as 1/[PWM period]. When TMR2 is eq ual to PR2, t he following three event s

occur on the next increment cycle:

• TMR2 is cleared.

• The CCP1 pin is set (Exception: If PWM duty

cycle = 0%, the CCP1 pin will not be set).

• The PWM duty cycle is latc hed from CC PR1L into

CCPR1H.

Note: The Timer2 postscaler (see Section 7.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.

A PWM output (Figure 11-4) has a time base (pe riod) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

DS41211B-page 72 Preliminary  2004 Microchip Technology Inc.

PIC12F683

11.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time.

EQUATION 11-2:

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> •

OSC • TMR2 Prescale Value

CCPR1L and CCP1CON <5:4> c an be wr itten to at an y time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitch-free PWM operation.

When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.

The maximum PWM r esolu tion ( bits ) for a g iven P WM frequency is given by the following formula.

EQUATION 11-3:



log

FPWM • TMR2 Prescale Value

Resolution =

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCP1 pin will not be cleared.



FOSC

log(2)

 

bits

11.3.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP1 module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the TRISIO<2> bit.

4. Set the TMR2 prescale val ue and enable T imer2 by writing to T2CON.

5. Configure the CCP1 modu le for PWM operation.

Note: The PWM modu le may gen erate a prema-

ture pulse when changing the duty cycle. For sensitive applications, disable the PWM module prior to modifying the duty cycle.

TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h Maximum Resolution (bits) 10 10 10 8 7 6.6

 2004 Microchip Technology Inc. Preliminary DS41211B-page 73

PIC12F683

TABLE 11-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/

INTCON GIE PEIE

8Bh 0Ch PIR1 11h

TMR2 Timer2 Module Register 0000 0000 0000 0000

12h

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu 15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 8Ch PIE1 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 Legend: — = unimplemented locations, read as ‘0’, u = unchanged, x = unknown.

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

Shaded cells are not used by the PWM or Timer2 module.

T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000

Value on

POR, BOD

Value o n

all other

Resets

DS41211B-page 74 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.0 SPECIAL FEATURES OF THE CPU

The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection.

These features are:

• Reset

- Power-on Reset (P OR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Detect (BOD)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator Selection

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming

The PIC12F683 has two timers that offer necessary delays on power-up. One is the Os cillator S t art-up T imer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry.

The Sleep mode is des igned to offer a very low-curre nt Power-down mode. The user can wake-up from Sleep through:

•External Reset

• Watchdog Timer Wake-up

• An interrupt Several oscillator options are also made available to

allow the part to f it th e a ppl ic ati on. The IN T O SC op tio n saves system co st while the LP crystal opti on saves power. A set of configuration bits are used to select various options (see Re gister 12-1).

 2004 Microchip Technology Inc. Preliminary DS41211B-page 75

PIC12F683

12.1 Configuration Bits

The configuration bits can be programmed (read as ‘0’), or left unpro grammed (r ead as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h.

REGISTER 12-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)

— — F CMEN IESO BODEN1 BODEN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 13 bit 0

bit 13-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit

bit 10 IESO: Internal External Switchover bit

bit 9-8 BODEN<1:0>: Brown-out Detect Selection bits

bit 7 CPD

bit 6 CP

bit 5 MCLRE: GP3/MCLR

bit 4 PWRTE: Power-up Timer Enable bit

bit 3 WDTE: Watchdog Timer Enable bit

bit 2-0 FOSC<2:0>: Oscillator Selection bits

1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled

1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled

11 = BOD enabled 10 = BOD enabled during operation and disabled in Sleep 01 = BOD controlled by SBODEN bit (PCON<4>) 00 = BOD disabled

: Data Code Protection bit

1 = Data memory code protection is disabled 0 = Data memory code protection is enabled

: Code Protection bit

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

pin function select bit

1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR

1 = PWRT disabled 0 = PWRT enabled

1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)

111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT functi on on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

Note 1: Enabling Brown-out Detect does not automatically enable Power-up Timer.

pin function is digital input, MCLR internally tied to VDD

2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. When MCLR

in INTOSC or RC mode, the internal clock oscillator is disabled.

(2)

(3)

(1)

(4)

Note: Address 2007h is beyond the user

program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Program- ming Specification” (DS41204) for more information.

is asserted

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41211B-page 76 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.2 Calibration Bits

The Brown-out Detect (BOD), Power-on Reset (POR)

Specification” (DS41204). Therefore, it is not necessary to store and reprogram these values when the device is erased.

and 8 MHz internal oscillator (HFINTOSC) are factory calibrated. These calibration values are stored in the Calibration Word register, as shown in Register 12-2 and are mapped in program memory location 2008h.

The Calibration Word register is not erased when the device is erased when using the procedure described in the “PIC12F6XX/16F6XX Memory Programming

Note: Address 2008h is beyond the user program

memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX

Memory Programming Specification”

(DS41204) fo r mor e inf ormation .

REGISTER 12-2: CALIB – CALIBRATION WORD (ADDRESS: 2008h)

— FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0 — POR1 POR0 BOD2 BOD1 BOD0

bit 13 bit 0

bit 13 Unimplemented: Read as ‘0’ bit 12-6 FCAL<6:0>: Internal Oscillator Calibration bits

0111111 = Maximum frequency . .

0000001 0000000 = Center frequency 1111111

. .

1000000 = Minimum frequency bit 5 Unimplemented: Read as ‘0’ bit 4-3 POR<1:0>: POR Calibration bits

00 = Lowest POR voltage

11 = Highest POR voltage

bit 2-0 BOD<2:0>: BOD Calibration bits

000 = Reserved

001 = Lowest BOD voltage

111 = Highest BOD voltage

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41211B-page 77

PIC12F683

12.3 Reset

The PIC12F683 diffe rentiates between various kinds of Reset:

a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR e) MCLR f) Brown-out Detect (BOD)

Some registers are no t af fected in a ny Reset co ndition; their status is un kn own on POR and unchanged in an y

Reset during normal operation Reset during Sleep

They are not affected by a WDT wake-up since this is viewed as the resump tio n of no rm al op era tion . TO PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. These bits are used in software to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers.

A simplified block di agram of the On-Chip Reset Circu it is shown in Figure 12-1.

The MCLR

Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 “Electrical Specifications” for pulse width specifications.

other Reset. Most other registers are reset to a “Reset state” on:

• Power-on R eset

•MCLR

Reset Reset during Sleep

•WDT Reset

• Brown-out Detect (BOD)

FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

and

MCLR/VPP pin

OSC1/

WDT

Module

DD Rise

Detect

Brown-out

Detect

OST/PWRT

LFINTOSC

SLEEP

WDT Time-out

Reset

Power-on Reset

(1)

OST

10-bit Ripple Counter

PWRT

11-bit Ripple Counter

Chip_Reset

Enable PWRT Enable OST

DS41211B-page 78 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.3.1 POWER-ON RESET

The on-chip POR circuit holds the chip in Reset until

DD has reached a high enough level for proper

V operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for V

is required. See Section 15.0 “Electrical Specifica- tions” for details. If the BOD is ena ble d, th e ma xi mu m rise time specification does not apply. The BOD circuitry will keep the d evice in Reset u ntil V

BOD (see Section 12.3.4 “Brown-out Detect

DD reaches

(BOD)”).

Note: The POR circuit does not produce an

internal Reset when V re-enable the POR, V

DD declines. To

DD must reach Vss

for a minimum of 100µs.

When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

For additional inform ation, refer to the Ap plica tion No te AN607, “Power-up Trouble Shooting” (DS00607).

12.3.2 MCLR

PIC12F683 has a noise filter in the MCLR Reset path. The filter will detec t and ignore small pul s es.

It should be noted that a WDT Reset does not drive

pin low.

MCLR The behavior of the ESD protection on the MCLR

has been altered from early devices of this family. Volt a ges app lied to the pin th at exce ed it s spe cific ation can result in both MCLR

Resets and excessiv e c urre nt beyond the de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt . For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested.

An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR weak pull-u p is enabled for the MCLR

is internally tied to VDD and an internal

pin. In-Cir cuit Serial Programming is not affected by selecting the internal MCLR

option.

FIGURE 12-2: RECOMMENDED MCLR

CIRCUIT

VDD

R1 1kΩ (or greater)

0.1 µF (optional, not critical)

PIC12F683

MCLR

12.3.3 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Detect. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.4 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the V uration bit, PWRTE cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Detect is enabled, although it is not required.

The Power-up Timer delay will vary from chip-to-chip and vary due to:

DD variation

•V

• Temperature variation

• Process variation See DC parameters for details (Section 15.0 “Electrical

Specifications”).

DD to rise to an acceptable level. A config-

, can disable (if set) or enable (if

 2004 Microchip Technology Inc. Preliminary DS41211B-page 79

PIC12F683

12.3.4 BROWN-OUT DETECT (BOD)

The BODEN0 and BODEN1 bits in the Configuration Word register select one of four BOD modes. Two modes have been ad ded to allo w software or hardwa re control of the BOD enable. When BODEN<1:0> = 01, the SBODEN bit (PCON<4>) enables/disables the BOD allowing it to be controlled in software. By selecting BODEN<1:0>, the BOD is automatic ally dis abled in Sleep to conserve power and enabled on wake-up. In this mode, the SBODEN bit is disabled. See Register 12-1 for the Configuration Word register definition.

DD falls below VBOD for greater than parameter

If V

BOD (see Section 15.0 “Electric al Spe cifi cati ons” ),

T the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to oc cur if V parameter (T

BOD).

On any Reset (Power-on, Brown-ou t Detect, W atchdog Timer, etc.), the chip will remain in Res et until V above V

BOD (see Figure 12-3). The Power-up Timer

will now be invoked , if enabled an d will keep the c hip in Reset an additional 64 ms.

DD falls below VBOD for less th an

DD rises

DD drops below VBOD while the Power-up Timer is

If V running, the chip will go back into a Brown-out Detect and the Power-up Tim er will be re-initialized. Onc e VDD rises above VBOD, the Power-up Timer will execute a 64 ms Reset.

12.3.4.1 BOD Calibration

The PIC12F683 stores the BOD calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word reg ister is not erased when usin g the specified bulk erase sequence in the “PIC12F6XX/

16F6XX Memory Programming Specification”

(DS41204) and thus, do es not require reprogramm ing.

Note: Address 2008h is beyond the user

Note: The Power-up Timer is enabled by the

PWRTE

bit in the Configuration Word

FIGURE 12-3: BROWN-OUT SITUATIONS

Internal

Reset

Internal

Reset

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

64 ms

< 64 ms

(1)

64 ms

VBOD

BOD

VBOD

(1)

VBOD

(1)

DS41211B-page 80 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.3.5 TIME-OUT SEQUENCE

On power-up, the time-ou t sequenc e is as foll ows: firs t, PWRT time-out is invoke d after PO R has expire d, then OST is activated after the PWR T ti me -out has exp ire d. The total time-out wil l vary bas ed on os ci lla tor configuration and PWRTE with PWRTE no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The devic e can execute code from the INTOSC while OST is active by enabling T wo -Spee d Start-up or Fail -Safe Mo nitor (se e

Section 3.6 “Two-Speed Clock Start-up Mode” and Section 3.7 “Fail-Safe Clock Monitor”).

Since the time-outs occur from the PO R pulse, if MCLR is kept low long enough, the tim e-outs will expi re. Then, bringing MCL R (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel.

Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers.

bit status. For exam ple, in EC mode

bit erased (PWRT disable d), the re will be

high will begin execution immediately

12.3.6 POWER CONTROL (PCON) REGISTER

The Power Control register PCON (address 8Eh) has two status bits to indicate what type of Reset that last occurred.

Bit 0 is BOD on Reset. It must then be set by the user and checked on subsequent Reset s to see if BOD = 0, indicati ng that a Brown-out has occurred. The BOD “don’t care” and is not necessarily predictable if the brown-out circuit is disabl ed (BODEN<1:0> = 00 in the Configuration Word register).

Bit 1 is POR Reset and unaffec ted oth erwise. T he user m ust write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR Power-on Reset has occurred (i.e., V gone too low).

For more information, see Section 4.2.3 “Ultra Low-

Power Wake-up” and Section 12.3.4 “Brown-out Detect (BOD)”.

(Brown-out). BOD is unknown on Power-

status bit is a

(Power-on Reset). It is a ‘0’ on Power-on

is ‘0’, it will ind icate that a

DD may have

TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

XT, HS, LP T

PWRTE

PWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC

RC, EC, INTOSC TPWRT —TPWRT ——

Power-up Brown-out Detect

= 0 PWRTE = 1 PWRTE = 0 PWRTE = 1

Wake-up from

Sleep

TABLE 12-2: PCON BITS AND THEIR SIGNIFICANCE

POR

0u11Power-on Reset 1011Brown-out Detect uu0uWDT Reset uu00WDT Wake-up uuuuMCLR uu10MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

BOD TO PD Condition

Reset during normal operation

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

03h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 8Eh PCON

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.

Shaded cells are not used by BOD.

Note 1: Other (non Power-up) Resets include MCLR

— — ULPWUE SBODEN — —PORBOD --01 --qq --0u --uu

Reset and Watchdog Timer Res et during normal operation.

Value on

POR, BOD

Val ue on

all other

Resets

(1)

 2004 Microchip Technology Inc. Preliminary DS41211B-page 81

PIC12F683

FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR

VDD

MCLR

Internal POR

PWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

)

FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

DS41211B-page 82 Preliminary  2004 Microchip Technology Inc.

TOST

WITH VDD)

PIC12F683

TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS

MCLR

Reset

WDT Reset

Brown-out Detect

(1)

W—xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1 STATUS 03h/83h 0001 1xxx 000q quuu

(4)

FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --xx xx00 --00 0000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 15h 0000 0000 0000 0000 uuuu uuuu WDTCON 18h ---0 1000 ---0 1000 ---u uuuu CMCON0 19h 0000 0000 0000 0000 uuuu uuuu CMCON1 20h ---- --10 ---- --10 ---- --uu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PCON 8Eh --01 --0x --0u --uu

(1,5)

OSCCON 8Fh -110 x000 -110 x000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 WPU 95h --11 -111 --11 -111 uuuu uuuu IOC 96h --00 0000 --00 0000 --uu uuuu VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If V

DD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

Wake-up from Sleep

through Interrupt

Wake-up from Sleep through

WDT Time-out

(3)

uuuq quuu

(4)

(2) (2)

--uu --uu

 2004 Microchip Technology Inc. Preliminary DS41211B-page 83

PIC12F683

TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

MCLR

Reset

EECON1 9Ch ---- x000 ---- q000 ---- uuuu EECON2 9Dh ---- ---- ---- ---- ---- ---ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh 1111 1111 1111 1111 uuuu uuuu

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

WDT Reset

Brown-out Detect

(1)

TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 000h 0001 1xxx --01 --0x

Reset during Normal Operation 000h 000u uuuu --0u --uu

MCLR

Reset during Sleep 000h 0001 0uuu --0u --uu

MCLR WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Detect 000h 0001 1uuu --01 --10 Interrupt Wake-up from Sleep PC + 1

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is du e to an interrupt and Global Interru pt En abl e b it, GIE, is se t, th e PC i s loa ded with

the interrupt vector (0004h) after execution of PC + 1.

Program

Counter

(1)

Status

uuu1 0uuu --uu --uu

Wake-up from Sleep

through Interrupt

Wake-up from Sleep through

WDT Time-out

PCON

DS41211B-page 84 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.4 Interrupts

The PIC12F683 has 11 sources of interrupt:

• External Interrupt GP2/INT

• TMR0 Overflow Interrupt

• GPIO Change Interrupts

• 2 Comparator Interrupts

• A/D Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt The Interrupt Control regis ter (INTCON) and Periphera l

Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset.

The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked inte rrupts.

The following interrupt flags are contained in the INTCON register:

• INT Pin Interrupt

• GPIO Change Interrupt

• TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the

special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1.

The following interrupt flags are contained in the PIR1 register:

• EEPROM Data Write Interrupt

• A/D Interrupt

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• Timer 2 Match Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt .

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again.

For additional information on Timer1, Timer2, comparators, A/D, data EEPROM or CCP modules, refer to the respective peripheral section.

12.4.1 GP2/INT INTERRUPT

External interrupt on GP2/INT pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the I NTE contro l bit (INTCON <4>). The INT F bit must be cleared in software in the Interrupt Service Routine before re-enabli ng thi s in terru pt. The GP2 /INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior t o going int o Sleep. The s tatus of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 12.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure12-10 for timing of wake-up from Sleep through GP2/INT interrupt.

Note: The ANSEL (91h) and CMCON0 (19h)

registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 85

PIC12F683

12.4.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module.

FIGURE 12-7: INTERRUPT LOGIC

IOC-GP0

IOC0

IOC-GP1

IOC1

IOC-GP2

IOC2

IOC-GP3

IOC3

IOC-GP4

IOC4

IOC-GP5

IOC5

12.4.3 GPIO INTERRUPT

An input change on GPIO change sets the GPIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the GPIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOC register.

Note: If a change on the I/O pin should occur

when the read operation is bei ng executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set.

TMR2IF TMR2IE

TMR1IF TMR1IE

CMIF CMIE

ADIF ADIE

EEIF

EEIE

OSFIF OSFIE

CCP1IF CCP1IE

T0IF T0IE

INTF

INTE GPIF GPIE

PEIE

GIE

Wake-up (If in Sleep mode)

Interrupt to C PU

DS41211B-page 86 Preliminary  2004 Microchip Technology Inc.

FIGURE 12-8: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

PIC12F683

CLKOUT

(INTCON<1>)

(INTCON<7>)

Instruction Flow

Note 1: INTF flag is sampled here (every Q1).

(3)

(4)

INT pin

INTF Flag

GIE bit

Instruction

Fetched

Instruction

Executed

2: Asynchr onous in terru pt latency = 3-4 T

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOU T is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

Inst (PC)

Inst (PC – 1)

(5)

(1)

Interrupt Latency

PC + 1

Inst (PC + 1)

Inst (PC)

CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

PC + 1

—

Dummy Cycle

(2)

0004h

Inst (0004h)

Dummy Cycle

0005h

Inst (0005h)

Inst (0004h)

TABLE 12-6: SUMMARY OF INTERRUPT REGISTERS

AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0

0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 0Ch PIR1 8Ch PIE1 EEIE ADIE CCP1IE Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the interrupt module.

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

— CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

Val ue on

POR, BOD

Value on

all other

Resets

 2004 Microchip Technology Inc. Preliminary DS41211B-page 87

PIC12F683

12.5 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software.

Since the lower 16 bytes of all ban ks are common in th e PIC12F683 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 l oc ati ons d o n ot require banking and therefore, makes it easier to context save and restore. The same code shown in Example 12-1 can be used to:

• Store the W register.

• Store the Status register.

• Execute the ISR code.

• Restore the Status (and Bank Select Bit register).

• Restore the W register.

EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state) MOVWF STATUS ;Move W into Status register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

Note: The PIC12F6 83 norm ally d oes not re quire

saving the PCLATH. However, if computed GOTOs are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.

DS41211B-page 88 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.6 Watchdog Timer (WDT)

For PIC12F683, the WDT has been modified from previous PIC12F683 devices. The new WDT is code and functionally compatible with previous PIC12F683 WDT modules and add s a 16-bit prescaler t o the WDT. This allows the user to have a scale r value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in T able 12-7.

12.6.1 WDT OSCILLATOR

The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Rese ts. This gives a n ominal ti me base of 16ms, which is compatible with the time base generated with previous PIC12F683 microcontrol ler versions.

Note: When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset, because th e W DT R ipp le C ount er is use d by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).

A new prescaler has been added to the path between the INTRC and the m ultipl exers used t o sele ct the p ath for the WDT. This prescaler is 16 bits and can be programmed to divid e the INTRC by 1 28 to 6 5536, giving the time base used for the WDT a nomina l range of 1 m s to 268s.

12.6.2 WDT CONTROL

The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously.

When the WDTE bit in the Configuration Word register is set, the SWDTE N bit (WDT CON<0>) ha s no effect. If WDTE is clear, then the SWDTEN bit ca n be used to enable and disabl e the WDT. Setting the bit will enable it and clearing the bit will disable it.

The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC12F683 family of m icrocontrollers . See Section 5.0

“Timer0 Module” for more information.

FIGURE 12-9: WATCHDOG TIMER BLOCK DIAGRAM

(1)

PSA

Prescaler

WDT Time-out

PS<2:0>

To TMR0

PSA

31 kHz

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

From TMR0 Clock Source

16-bit WDT Prescaler

WDTPS<3:0>

WDTE from Configuration Word regis ter SWDTEN from WDTCON

TABLE 12-7: WDT STATUS

Conditions WDT

WDTE = 0 CLRWDT Command

Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

Cleared

 2004 Microchip Technology Inc. Preliminary DS41211B-page 89

PIC12F683

REGISTER 12-3: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved

(1)

bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer

1 = WDT is turned on 0 = WDT is turned off (Reset value)

Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this

control bit. If WDTE confi guratio n bit= 0, then i t is possible to turn WDT on/off wi th this control bit.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TABLE 12-8: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

18h WDTCON 81h OPTION_REG

(1)

2007h

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits.

CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

— — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

DS41211B-page 90 Preliminary  2004 Microchip Technology Inc.

PIC12F683

12.7 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

• PD bit in the Status register is cleared. bit is set.

•TO

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high-impedance).

For lowest current consumption in this mode, all I/O pins should be either at V circuitry drawing current from the I/O pin and the comparators and CV that are high-impedance inputs should be pulled high or low externally to av oid sw it ch ing currents caused by floating inputs. The T0CKI input should also be at V or VSS for lowest current consumption. The contribution from on-chip pull-ups on GPIO should be considered.

The MCLR

Note: It should be noted that a Reset generated

pin must be at a logic high level.

by a WDT time-out does not drive MCLR pin low.

12.7.1 WAKE-UP FROM SLEEP

The device can wake -up from Sleep through one of th e following events:

1. External Reset input on MCLR

2. Watchdog Timer wake-up (if WDT was

enabled).

3. Interrupt from GP2/INT pin, GPIO change or a

peripheral interrupt.

The first event wi ll cause a devic e Reset. The two lat ter events are considered a continuation of program execution. The T O used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO

The following periph eral interrupt s can wake the device from Sleep:

1. TMR1 interrupt. T imer1 must be operati ng as an

asynchronous counter.

2. ECCP Capture mode interrupt.

3. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

4. A/D conversion (when A/D clock source is RC).

5. EEPROM write operation completion.

6. Comparator output changes state.

7. Interrupt-on-change.

8. External Interrupt from INT pin.

and PD bits in the Status register can be

bit is cleared if WDT wake-up occurred.

DD or VSS, with no external

REF should be disabled. I/O pins

pin.

Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present.

When the SLEEP instruc tion is being e xecuted, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrup t eve nt, the co rres pon din g interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

Note: If the glob al inte rrupt s are di sable d (GIE i s

cleared), but any interrup t source has bo th its interrupt enabl e bit and the corres ponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

12.7.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bi t set, one of the fo llow ing wil l occu r:

• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO will not be cleared.

• If the interrupt occurs during or after the execution of a SLEEP instruc tio n, the dev ic e will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if ena bled) wi ll be c leared , the T O bit will be set and the PD bit will be cleared.

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set befo re the SLEEP instruct ion completes . To determine whether a SLEEP instruction exe cuted, te st the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.

T o ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.

bit will not be set and the PD bit

 2004 Microchip Technology Inc. Preliminary DS41211B-page 91

PIC12F683

FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

OSC1

(4)

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Note 1: XT, HS or LP Oscillator mode assumed.

Instruction

Fetched

Instruction

Executed

2: T 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will conti nue in-l ine. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

OST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.

Inst(PC + 1)

Sleep

Processor in

Sleep

12.8 Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes.

Note: The entire data EEPROM and Flash

program memory will be erased when the code protection is turned off. See the PIC12F6XX/16F6XX Memory Program- ming Specification (DS41204) for more information.

12.9 ID Locations

Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution b ut are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.

12.10 In-Circuit Serial Programming

The PIC12F683 microcontrollers can be serially programmed while in t he en d app licati on c ircuit. This is simply done with two lines for clock and dat a and thre e other lines for:

•Power

•Ground

• Programming Voltage

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(2)

OST

Interrupt Latency

PC + 2

Inst(PC + 2) Inst(PC + 1)

(3)

PC + 2 0004h 0005h

Inst(0004h)

Dummy Cycle

This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

The device i s placed into a Program/ Verify mode by holding the GP0 and GP1 pins low, while raising the

(VPP) pin from VIL to VIHH. See the “PIC12F6XX/

MCLR

16F6XX Memory Programming Specification”

(DS41204) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in this mode.

After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204).

A typical In-Circuit Serial Programming connection is shown in Figure 12-11.

Inst(0005h)

Inst(0004h)

DS41211B-page 92 Preliminary  2004 Microchip Technology Inc.

PIC12F683

FIGURE 12-11: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING CONNECTION

To Norma l Connections

External Connector Signals

+5V

VPP

CLK

Data I/O

PIC12F683

VDD VSS

MCLR/VPP/GP3 GP1 GP0

* * *

To Normal Connections

*Isolation devices (as required).

12.1 1 In-Circuit Debugger

Since in-circuit debugging requires the loss of clock, data and MCLR an 8-pin device is not practical. A special 14-pin PIC12F683 ICD device is used with MPLAB ICD 2 to provide separat e cl oc k, data and MCLR all normally available pins to the user.

A special debugging adapter allows the ICD device to be used in place of a PIC12F683 device. The debugging adapte r is the only sou rce of the ICD dev ice.

pins, MPLAB® ICD 2 development with

pins and frees

When the ICD

pin on the PIC12F 683 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcon troller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger:

TABLE 12-9: DEBUGGER RESOURCES

Resource Description

I/O pins ICDCLK, ICDDATA Stack 1 level Program Memor y Address 0h must be NOP

700h-7FFh

For more information, see “MPLAB ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web si te (www.microchip.com).

FIGURE 12-12: 14-PIN ICD PINOUT

14-Pin PDIP

In-Circuit Debug Device

ICDMCLR

/VPP

VDD GP5 GP4 GP3

ICD

PIC12F683-ICD

2 3 4 5 6 7

ICDCLK ICDDATA

13 12

Vss GP0

GP1

GP2

 2004 Microchip Technology Inc. Preliminary DS41211B-page 93

PIC12F683

NOTES:

DS41211B-page 94 Preliminary  2004 Microchip Technology Inc.

PIC12F683

13.0 INSTRUCTION SET SUMMARY

The PIC12F683 ins truction set is highly o rthogonal and is comprised of three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations Each PIC16 instruction is a 14-bit word divided into an

opcode, which spec ifies the instru ction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1.

Table 13-2 lists the instructions recognized by the MPASM™ Assembler. A complete description of each instruction is also available in the “PICmicro MCU Family Reference Manual” (DS33023).

For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction.

The destination des ignator specifies w here the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W re gister . I f ‘d’ is one, the resul t is placed in the file register specified in the instruction.

For bit-oriented instr uctions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ repre sen t s t he address of the file i n which the bit is located.

For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value.

One instruction cyc le consist s of four oscillator peri ods; for an oscilla tor frequency o f 4 MHz , this gives a normal instruction execution time of 1 µs. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an in struction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP.

Note: To maintain upward compatibility with

future products, do not use and TRIS instructions.

All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit.

Mid-Range

the OPTION

For example, a CLRF GPIO in st ruc t ion wi ll read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended result of clearing the condition that set the GPIF flag.

TABLE 13-1: OPCODE FIELD

DESCRIPTIONS

Field Description

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1.

Program Counter

Time-out bit

Power-down bit

FIGURE 13-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file regi s ter operations

13 8 7 6 0

OPCODE d f (FILE #) d = 0 for destination W

d = 1 for destination f f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit file register address

Literal and control operations

General

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13.1 READ-MODIFY-WRITE OPERATIONS

Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W)

CALL and GOTO instructions only

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

operation. The regis ter is read, the data is m odified and the result is stored acco rding to eithe r the instruc tion or the destination designator ‘d’. A read operation is performed on a register even if the ins truction writes to that register.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 95

PIC12F683

TABLE 13-2: PIC12F683 INSTRUCTION SET

Mnemonic,

Operands

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BCF BSF BTFSC BTFSS

ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

f, d

Add W and f

f, d

AND W with f

Clear f

Clear W

f, d

Complement f

f, d

Decrement f

f, d

Decrement f, Skip if 0

f, d

Increment f

f, d

Increment f, Skip if 0

f, d

Inclusive OR W with f

f, d

Move f

Move W to f

No Operation

f, d

Rotate Left f through Carry

f, d

Rotate Right f through Carry

f, d

Subtract W from f

f, d

Swap nibbles in f

f, d

Exclusive OR W with f

f, b

Bit Clear f

f, b

Bit Set f

f, b

Bit Test f, Skip if Clear

f, b

Bit Test f, Skip if Set

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

Description Cycles

BYTE-ORIENTED FILE REGISTER OPERATIONS

1 1 1 1 1 1

1 (2)

1 1 1 1 1 1 1 1 1

BIT-ORIENTED FILE REGISTER OPERATIONS

1 1 (2) 1 (2)

LITERAL AND CONTROL OPERATIONS

14-Bit Opcode

MSb LSb

0111

dfff

ffff

0101

dfff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01 01 01 01

11 11 10 00 10 11 11 00 11 00 00 11 11

0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

00bb 01bb 10bb 11bb

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

lfff

0xxx

dfff

lfff

0xx0

dfff

bfff

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

Status

Affected

C, DC, Z

Z Z Z Z Z

Z Z

C C

C, DC, Z

, PD

C, DC, Z

Notes

1,2 1,2

1,2,3

1,2

1,2,3

1,2 1,2

1,2 1,2 1,2 1,2 1,2

1,2 1,2

3 3

Note: Additional info rmation on the mid -range instruction set is available i n the “PICmicro® Mid-Range MCU

Family Reference Manual” (DS33023).

DS41211B-page 96 Preliminary  2004 Microchip Technology Inc.

13.2 Instruction Descriptions

PIC12F683

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are

added to the eight-bit literal ‘k’ and the result is placed in the W register.

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) + (f) → (destination) Status Affected: C, DC, Z Description: Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

BCF Bit Clear f

Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.

ANDLW AND Literal with W

Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Description: The contents of W register are

AND’ed with the eight-bit literal ‘k’. The result is placed in the W register.

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in registe r ‘f’.

BTFSC Bit Test, Skip if Clear

Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is discarded and a NOP

is executed instead, m aking this a

2-cycle instruction.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 127

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, m ak ing thi s a

2-cycle instruction.

 2004 Microchip Technology Inc. Preliminary DS41211B-page 97

PIC12F683

CALL Call Subroutine

Syntax: [ label ] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC) + 1 → TOS,

k → PC<10:0>,

(PCLA TH<4:3>) → PC<12:11> Status Affected: None Description: Call subroutine. First, return address

(PC + 1) is pushed onto the stack. The

eleven-bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f)

1 → Z Status Affected: Z Description: The contents of register ‘f’ are

cleared and the Z bit is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT

0 → WDT prescaler, 1 → TO

1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the

Watchdo g Time r. It also resets the

prescaler of the WDT.

Status bits TO

COMF Complement f

Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f Status Affected: Z Description: The contents of register ‘f’ are

) → (destination)

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

and PD are set.

CLRW Clear W

Syntax: [ label ] CLRW Operands: None Operation: 00h → (W)

1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z)

is set.

DECF De crement f

Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) – 1 → (destination) Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

DS41211B-page 98 Preliminary  2004 Microchip Technology Inc.

MICROCHIP PIC12F683 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU

Special Microcontroller Features

Low-Power Features

Peripheral Features

Pin Diagram

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC12F683 BLOCK DIAGRAM

TABLE 1-1: PIC12F683 PINOUT DESCRIPTION

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

2.2 Data Memory Organization

2.2.2 SPECIAL FUNCTION REGISTERS

TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0

TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h OR 83h)

REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h)

REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)

REGISTER 2-5: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)

REGISTER 2-6: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683

3.0 CLOCK SOURCES

3.1 Overview

FIGURE 3-1: PIC12F683 CLOCK SOURCE BLOCK DIAGRAM

3.2 Clock Source Modes

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER (OST)

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

3.3.2 EC MODE

3.3.3 LP, XT, HS MODES

3.3.4 EXTERNAL RC MODES

FIGURE 3-5: RC MODE

FIGURE 3-6: RCIO MODE

3.4 Internal Clock Modes

3.4.1 INTRC AND INTRCIO MODES

3.4.2 HFINTOSC

REGISTER 3-1: OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)

3.4.3 LFINTOSC

3.4.4 FREQUENCY SELECT BITS (IRCF)

3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING

3.5 Clock Switching

3.5.1 SYSTEM CLOCK SELECT (SCS) BIT

3.5.2 OSCILLAT OR START-UP TIME-OUT STATUS BIT

3.6 Two-Speed Clock Start-up Mode

3.6.1 TWO-SPEED START-UP MODE CONFIGURATION

3.6.2 TWO-SPEED START-UP SEQUENCE

3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS

FIGURE 3-7: TWO-SPEED START-UP

3.7 Fail-Safe Clock Monitor

FIGURE 3-8: FSCM BLOCK DIAGRAM

3.7.1 FAIL-SAFE CONDITION CLEARING

FIGURE 3-9: FSCM TIMING DIAGRAM

3.7.2 RESET OR WAKE-UP FROM SLEEP

REGISTER 3-2: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

4.0 GPIO PORT

4.1 GPIO and the TRISIO Registers

EXAMPLE 4-1: INITIALIZING GPIO

4.2 Additional Pin Functions

4.2.1 WEAK PULL-UPS

REGISTER 4-1: GPIO – GENERAL PURPOSE I/O REGISTER (ADDRESS: 05h)

REGISTER 4-2: TRISIO – GPIO TRI-STATE REGISTER (ADDRESS: 85h)

REGISTER 4-3: WPU – WEAK PULL-UP REGISTER (ADDRESS: 95h)

4.2.2 INTERRUPT-ON-CHANGE

REGISTER 4-4: IOC – INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)

4.2.3 ULTRA LOW-POWER WAKE-UP

FIGURE 4-1: BLOCK DIAGRAM OF GP0

4.2.4 PIN DESCRIPTIONS AND DIAGRAMS

FIGURE 4-2: BLOCK DIAGRAM OF GP1

FIGURE 4-3: BLOCK DIAGRAM OF GP2

FIGURE 4-4: BLOCK DIAGRAM OF GP3

FIGURE 4-5: BLOCK DIAGRAM OF GP4

FIGURE 4-6: BLOCK DIAGRAM OF GP5

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO