How it Works
MICROCHIP
Loading...
PIC12F683
DATA SHEET
148 pgs2.48 Mb0
Table of contents
Loading...

MICROCHIP PIC12F683 DATA SHEET

PIC12F683
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2004 Microchip Technology Inc. Preliminary DS41211B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTE R , SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system cer t if i cat i on f or its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October
2003. The Com pany’s quality sy stem proces ses and pro cedures are for its PICmicro EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping devices, Serial
PIC12F683
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
nanoWatt Technology

High-Performance RISC CPU

• Only 35 instructions to learn:
- All single-cycle instructions except branches
• Operating speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features

• Precision Internal Oscillator:
- Factory calibrated to ±1%
- Software selectable frequency range of 8 MHz to 31kHz
- Two-speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for power savings
• Power-saving Sleep mode
• Wide operating voltage range. (2.0V-5.5V)
• Industrial and Extended tempera ture range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Multiplexed Master Clear with pull-up/input pin
• Programmable code protection
• High Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years

Low-Power Features

• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
-8.5µA @ 32 kHz, 2.0V, typical
-100µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
-1µA @ 2.0V, typical

Peripheral Features

• 6 I/O pins with individual direction control:
- High current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up on GP0
• Analog comparator module with:
- One analog comparator
- Programmable on-chip voltage reference (CV
REF) module (% of VDD)
- Comparator inputs and output externally accessible
• A/D Converter:
- 10-bit resolution and 4 channels
• Timer0: 8-bit timer/counter with 8-bit programmable prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode as
Timer1 oscillator if INTOSC mode selected
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Capture, Compare, PWM mo dul e:
- 16-bit Capture, max resolution 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM, max frequency 20 kHz
• In-Circuit Serial Programming™ (ICSP™) via two pins
Device
PIC12F683 2048 128 256 6 4 1 2/1
2004 Microchip Technology Inc. Preliminary DS41211B-page 1
Program Memory Data Memory
Flash (words) SRAM (bytes) EEPROM (bytes)
I/O 10-bit A/D (ch) Comparators
Timers
8/16-bit
PIC12F683

Pin Diagram

8-pin PDIP, SOIC, DFN-S
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G
/OSC2/CLKOUT
GP3/MCLR
VDD
/VPP
1
2
3
4
PIC12F683
8 7
6 5
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/V
GP2/AN2/T0CKI/INT/COUT/CCP1
REF/ICSPCLK
DS41211B-page 2 Preliminary 2004 Microchip Technology Inc.
PIC12F683
Table of Contents
1.0 Device Overview..........................................................................................................................................................................5
2.0 Memory Organization................................................................................................................................................................... 7
3.0 Clock Sources............................................................................................................................................................................ 19
4.0 GPIO Port...................................................................................................................................................................................31
5.0 Timer0 Module ........................................................................................................................................................................... 39
6.0 Timer1 Module with Gate Control............................................................................................................................................... 41
7.0 Timer2 Module ........................................................................................................................................................................... 45
8.0 Comparator Module....................................................................................................................................................................47
9.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 55
10.0 Data EEPROM Memory.................................. .............. .......................................... ................................................................... 65
11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 69
12.0 Special Features of the CPU....................................... .......................................... .....................................................................75
13.0 Instruction Set Summary............................................................................................................................................................ 95
14.0 Development Support............................................................................................................................................................... 103
15.0 Electrical Specifications............................................................................................................................................................ 109
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 131
17.0 Packaging Information. ............... .............. ............... .......................................... ....................................................................... 133
Appendix A: Data Sheet Revision History.......................................................................................................................................... 137
Appendix B: Migrating From Other PICmicro® Devices .................................................................................................................... 137
Index ..................................................................................................................................................................................................139
On-line Support.................................................................................................................................................................................. 143
Systems Information and Upgrade Hot Line...................................................................................................................................... 143
Reader Response. ............................................................................................................................................................................. 144
Product Identification System............................................................................................................................................................ 145
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
2004 Microchip Technology Inc. Preliminary DS41211B-page 3
PIC12F683
NOTES:
DS41211B-page 4 Preliminary 2004 Microchip Technology Inc.
PIC12F683

1.0 DEVICE OVERVIEW

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the PIC12F683. Addition al informa tion may b e found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to

FIGURE 1-1: PIC12F683 BLOCK DIAGRAM

INT
Program Counter
8-Level Stack
(13-bit)
Direct Addr
7
Program
Bus
Configuration
13
Flash
2k x 14
Program
Memory
14
Instruction reg
this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
The PIC12F683 is covered by this data sheet. It is available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description.
Indirect
Addr
8
RAM Addr
Data Bus
RAM
128 bytes
File
Registers
Addr MUX
8
9
FSR reg
GP0 GP1 GP2 GP3 GP4 GP5
OSC1/CLKIN
OSC2/CLKOUT
T1G
T1CKI
T0CKI
VREF
Instruction
Decode &
Control
Timing
Generation
Internal
Oscillator
Timer0 Timer1
Analog-to-Digital Converter
AN0 AN1 AN2 AN3
8
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Detect
VDD
Timer2
1 Analog Comparator
3
8
VSS
and Reference
CIN- CIN+ COUT
ALU
W reg
Status reg
MUX
CCP
8
EEDATA
256 bytes
Data
EEPROM
EEADDR
2004 Microchip Technology Inc. Preliminary DS41211B-page 5
PIC12F683

TABLE 1-1: PIC12F683 PINOUT DESCRIPTION

Name Function
DD VDD Power — Positive supply
V GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change
T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection
GP4/AN3/T1G
GP3/MCLR
GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 ST CMOS GPIO I/O w/programmable pull-up and interrupt-on-change
GP1/AN1/CIN-/V
GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change
SS VSS Power — Ground reference
V Legend: AN = Analog input or output CMO S = CMOS compatible input or output
/OSC2/CLKOUT GP4 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change
AN3 AN — A/D Channel 3 input T1G
OSC2 — XTAL Crystal/Resonator
CLKOUT — CMOS F
/VPP GP3 TTL — GPIO input with interrupt-on-change
MCLR
V
PP HV — Programming voltage
AN2 AN — A/D Channel 2 input
T0CKI ST — Timer0 clock input
INT ST — External Interrupt COUT — CMOS Comparator 1 output CCP1 ST CMOS Capture input/Compare output/PWM output
REF/ICSPCLK GP1 TTL CMOS GPIO I/O w/programmable pull-up and interrupt-on-change
AN1 AN — A/D Channel 1 input CIN- AN — Comparator 1 input
REF AN — External Voltage Reference for A/D
V
ICSPCLK ST — Serial Programming Clock
AN0 AN — A/D Channel 0 input
CIN+ AN — Comparator 1 input
ICSPDAT ST CMOS Serial Programming Data I/O
ULPWU AN — Ultra Low-power Wake-up input
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal
Input
Type
Output
Type
ST — Timer1 gate
OSC/4 output
ST — Master Clear w/internal pull-up
Description
PIC12F683

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 pr ogram mem ory spac e. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE PIC12F683
PC<12:0>
CALL, RETURN RETFIE, RETLW
Stack Level 1 Stack Level 2
Stack Level 8
Reset Vector
13
000h

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Regis­ters (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are general purpose registers, implemented as static RAM. Register loca­tions F0h-FFh in Bank 1 point to addresses 70 h-7Fh in Bank 0. All other RAM is u nimplemented and re turns ‘0’ when read. RP0 (Status<5>) is the bank select bit.
•RP0 = 0: Bank 0 is selected
•RP0 = 1: Bank 1 is selected Note: The IRP and RP1 bits (Status<7:6>) are
reserved and should always be maintained as ‘0’s.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the Fi le Sel ec t Register FSR (see
Section 2.4 “Indirect Addressing, INDF and FSR Registers”).
Interrupt Vector
On-chip Program
Memory
0004 0005
07FFh 0800h
1FFFh
2004 Microchip Technology Inc. Preliminary DS41211B-page 7
PIC12F683

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.
The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F683
File
Address
TMR0
PCL
FSR
GPIO
PIR1
TMR1L TMR1H T1CON
TMR2
T2CON CCPR1L
General Purpose
(1)
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
Indirect addr.
OPTION_REG
STATUS
PCLATH INTCON
OSCCON
OSCTUNE
EECON1
EECON2
ADRESL
Registers
Indirect addr.
STATUS
PCLATH INTCON
CCPR1H
CCP1CON
WDTCON CMCON0 VRCON CMCON1
ADRESH ADCON0
Registers
96 Bytes
PCL
FSR
TRISIO
PIE1
PCON
PR2
WPU
IOC
EEDAT EEADR
ANSEL General Purpose
32 Bytes
File
Address
(1)
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch
(1)
9Dh 9Eh 9Fh
A0h
BFh
BANK 0
7Fh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
Accesses 70h-7Fh
BANK 1
F0h FFh
PIC12F683
TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 00h INDF Addressing this loca tion uses content s of FSR to address dat a memory (not a physical register) xxxx xxxx 17, 83 01h TMR0 Timer0 Module’s Register xxxx xxxx 39, 83 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 83 03h STATUS IRP 04h FSR Indirect Data Memory Addr ess Point er xxxx xxxx 17, 83 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 83 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 41, 83 0Fh T MR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 41, 83 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h
TMR2 Timer2 Module Register 0000 0000 45, 83
12h
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 45, 83 13h CCPR1L Cap ture/Com pare/PWM Register 1 Low Byte xxxx xxxx 70, 83 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 70, 83 15h CCP1CON 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 57,83 1Fh ADCON0 ADFM VCFG Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
(1)
— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 83
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 83
EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 83
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 69, 83
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 90, 83 —COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 47, 83 — — — — — — T1GSS CMSYNC ---- --10 50, 83
RP1
(1)
RP0 TO PD Z DC C 0001 1xxx 11, 83
TMR1CS TMR1ON 0000 0000 43, 83
— — CHS1 CHS0 GO/DONE ADON 00-- 0000 58,83
Value o n
POR, BOD
Page
2004 Microchip Technology Inc. Preliminary DS41211B-page 9
PIC12F683
TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83
OPTION_RE G
81h 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 83 83h STATUS IRP 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 83 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 83 8Ch PIE1 EEIE ADIE CCP1IE 8Dh — Unimplemented — — 8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 45, 83 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU 96h IOC 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 65, 83 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 65, 83 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 66, 84 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 57, 84 9Fh A NSEL
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
(3)
shaded = unimplemented
2: OSCCON<OSTS> bit reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator. 3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 83
(1)
— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 83
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 83
— — ULPWUE SBODEN — —PORBOD --01 --qq 16, 83 — IRCF2 IRCF1 IRCF0 OSTS — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 23, 83
— —WPU5WPU4— WPU2WPU1WPU0--11 -111 32, 83 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 33, 83
— — — — WRERR WREN WR RD ---- x000 66, 84
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 59, 84
(1)
RP1
—VRR— VR3 VR2 VR1 VR0 0-0- 0000 53, 83
RP0 TO PD Z DC C 0001 1xxx 11, 83
— CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 83
(2)
HTS LTS SCS -110 x000 28, 83
Value o n
POR, BOD
Page
PIC12F683
2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains:
• Arithmetic status of the ALU
• Reset status
• Bank select bits for data memory (SRAM) The Status register can be the destination for any
instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the Status register as destination may be different than intended.
and PD bits are not
For example, CLRF STATUS, w ill c lear the upper three bits and set the Z bit. Thi s leav es the Status regis ter as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Stat us register , beca use these instru ctions do not af fect any Status bits. For other instructions not affecting any Status bits, see the “Instruction Set Summary”.
Note 1: Bits IRP and RP1 (Status<7:6>) are not
used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h OR 83h)
2004 Microchip Technology Inc. Preliminary DS41211B-page 11
PIC12F683
2.2.2.2 Option Register
The Option register is a readable and writable register, which contains various control bits to configure:
• TMR0/WDT prescaler
• External GP2/INT interrupt
•TMR0
• Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU
bit 7 bit 0
INTEDG T0CS T0SE PSA PS2 PS1 PS0
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ (Option<3>). See Section 5.4 “Prescaler”.
bit 7 GPPU
bit 6 INTEDG: Interrupt Edge Select bit
bit 5 T0CS: TMR0 Clock Source Sele ct bit
bit 4 T0SE: TMR0 Source Edge Select bit
bit 3 PSA: Prescaler Assignment bit
bit 2-0 PS<2:0>: Prescaler Rate Select bits
: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values in WPU register
1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin
1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)
1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin
1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
Bit Value TMR0 Rate WDT Rate
000 001 010 011 100 101 110 111
1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
(1)
1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F683. See
Section 12.6 “Watchdog Timer (WDT)” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC12F683
2.2.2.3 INTCON Register
The INTCON register is a readable and writable register , which c ontains the various en able and fl ag bit s for TMR0 register ove rflo w, GPIO chan ge a nd external GP2/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regard less of the st ate of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts 0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt
bit 3 GPIE: GPIO Change Interrupt Enable bit
1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 regis ter has over flowed (must be cleared in software) 0 = TMR0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: GPIO Change Interrupt Flag bit
1 = When at least one of the GPIO<5:0> pins changed state (must be cleared in software) 0 = None of the GPIO<5:0> pins have changed state
Note 1: IOC register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing T0IF bit.
(1)
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41211B-page 13
PIC12F683
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started
bit 5 CCP1IF: CCP1 Interrupt Flag bit
Capture mod
1 = A TMR1 register capture occurred (must be clea red in software) 0 = No TMR1 regi ster capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode. bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator 1 output has changed (must be cleared in software)
0 = Comparator 1 output has not changed
bit 2 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscilla tor failed, clock inpu t h as ch ang ed to INTOSC (must be cleared in software)
0 = System clock operating
bit 1 TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit
1 = Timer 2 to PR2 match occurred (must be cleared in software)
0 = Timer 2 to PR2 match has not occurred
bit 0 TMR1IF: Timer 1 Overflow Interrupt Flag bit
1 = Timer 1 register overflowed (must be cleared in software)
0 = Timer 1 has not overflowed
e:
:
Note: Interrupt f lag bit s are set when an in terrupt
condition occurs, regar dless of the st ate of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41211B-page 15
PIC12F683
2.2.2.6 PCON Regist er
The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a:
• Power-on Reset (POR
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOD The PCON register bits are shown in Register 2-6.
REGISTER 2-6: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
bit 4 SBODEN: Software BOD Enable bit
bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR
bit 0 BOD
)
Reset
.
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — ULPWUE SBODEN — —PORBOD
bit 7 bit 0
1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled
(1)
1 = BOD enabled 0 = BOD disabled
: Power-on Reset Status bit
1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Detect Status bit
1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Note 1: BODEN<1:0> = 01 in the Configuration W ord register for this bit to control the BO D.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC12F683

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683

For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
PIC12F683

3.0 CLOCK SOURCES

3.1 Overview

The PIC12F683 has a wide variety of clo ck sources and selection features to allow it to be used in a wide range of applications while maximizing performance and mini­mizing power consumption. Figure 3-1 illustrates a block diagram of the PIC12F683 clock sources.
Clock sources can be configured from external oscilla­tors, quartz crys ta l reso nat ors, cera mi c reson ato rs and Resistor-Capacitor (RC) circuits. In addition, the sys­tem clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via softwar e. Additional clock feat ures include:
• Selectable system clock source between external or internal via software.
• Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execu t io n.
• Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.
The PIC12F683 can b e conf igured in one of ei ght cloc k modes.
1. EC – External clock with I/O on GP4.
2. LP – Low gain crystal or Ceramic Resonator Oscillator mode.
3. XT – Medium gain c rysta l or Cera mic Resonat or Oscillator mode.
4. HS – High gain crystal or Ceramic Resonator mode.
5. RC – External Resistor-Capacitor (RC) with
OSC/4 output on GP4
F
6. RCIO – External Resistor-Capacitor with I/O on GP4.
7. INTRC – Internal oscillator with F
OSC/4 output
on GP4 and I/O on GP5.
8. INTRCIO – Internal oscillator with I/O on GP4 and GP5.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 12.0 “Special Features of the CPU”). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator . The LFINTOSC is a low-frequency uncalibrated oscillator.

FIGURE 3-1: PIC12F683 CLOCK SOURCE BLOCK DIAGRAM

External Oscillator
OSC2
OSC1
Internal Oscillator
HFINTOSC
8 MHz
LFINTOSC
31 kHz
Sleep
Postscaler
(OSCCON<6:4>)
8 MHz 4 MHz 2 MHz
1 MHz 500 kHz 250 kHz 125 kHz
31 kHz
IRCF<2:0>
111 110 101 100
011 010 001 000
LP, XT, HS, RC, RCIO, EC
MUX
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
FOSC<2:0>
(Configuration Word)
SCS
(OSCCON<0>)
MUX
(CPU and Peripherals)
System Clock
2004 Microchip Technology Inc. Preliminary DS41211B-page 19
PIC12F683

3.2 Clock Source Modes

Clock source modes can be classified as external or internal.
• External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz cryst al res ona tors or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC mode) circuits.
• Internal clock sources are contained internally within the PIC12F683. The PIC12F683 has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).
The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3 .5 “Clock Switching”).

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER (OST)

If the PIC12F683 is co nfigured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscil­lations from the OSC1 pin, followi ng a Power-on Res et (POR) and the Power-up T i mer (PWR T ) has ex pired ( if configured), or a wake -up from Sleep. D urin g this t ime, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has s tarted an d is provid ing a st able system clock to the PIC12F683. When switching between clock sources a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1.
In order to minimize latency between external oscillator start-up and code execution, the T wo-Speed Clock S tart­up mode can be selected (see Section 3.6 “Two-Speed
Clock Start-up Mode”).
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
Switch From Switch To Frequency Oscillator Delay
Sleep/POR Sleep/POR EC, RC DC – 20 MHz
LFINTOSC (31 kHz) EC, RC DC – 20 MHz
Sleep/POR LP, XT, HS 31 kHz-20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz-8 MHz 1 µs (approx .)
Note 1: The 5 µs–10 µs start-up delay is based on a 1 MHz system clock.
LFINTOSC
HFINTOSC
31 kHz
125 kHz-8 MHz
5 µs–10µs (approx.) CPU
Start-up
(1)

3.3.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the GP5 pin is available for general purpose I/ O. Figure 3-2 shows the pin connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F683 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
Clock from Ext. System
GP4
OSC1/CLKIN
PIC12F683
I/O (OSC2)
PIC12F683
r
r
) r

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the inter­nal inverter-amplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current con­sumption is the least of the three modes. This mode is best suited to drive resonator s with a low drive lev el specification, for example, tuning fork type crystals.
XT Oscillator mode selects the intermediate gain set­ting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suit e d t o dr i ve re so na tor s wi th a me dium drive level specification, for example, AT-cut quartz crystal resonators.
HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current con­sumption is the highest of the thre e mo des . This mode is best suited for resonators that require a high drive setting, for example, AT-cut quartz crystal res onators or ceramic resonators.
Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR HS MODE)
PIC12F683
OSC1
C1
Quartz Crystal
OSC2
(1)
S
C2
Note 1: A series resistor (R S) may be required for
2: The value of R
R
quartz crystals with low drive level.
mode selected (typically between 2 MΩ to 10 MΩ).
(2)
RF
F varies with the oscillator
Note 1: Quartz crystal characteristics vary
according to type, package and manufac­turer. The user should consult the manu­facturer data sh eets for speci fications and recommended application.
2: Al ways veri fy os ci lla tor pe rform an ce over
DD and temperature range that is
the V expected for the application.
To Internal Logic
Sleep
FIGURE 3-4: CERAMIC RESONATOR
OPERATION (XT OR HS MODE)
PIC12F683
OSC1
C1
(3)
RP
C2
Ceramic
Resonator
Note 1: A series resistor (RS) may be required fo
ceramic resonators with low drive level.
2: The value of R
mode selected (typically between 2 MΩ to 10 MΩ).
3: An additional parallel feedback resistor (R
may be required for proper ceramic resonato operation (typical value 1 MΩ).
OSC2
R
S
(1)
(2)
RF
F varies with the oscillato
To Internal Logic
Sleep
P

3.3.4 EXTERNAL RC MODES

The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping cost s to a mi nimum w hen clock accuracy is not required. There are two modes, RC and RCIO.
In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator fre­quency divided by 4. Th is signal may be use d to provide a clock for external circuitry, synchronization, calibra­tion, test or other application requirements. Figure 3-5 shows the RC mode connections.
FIGURE 3-5: RC MODE
VDD
REXT
OSC1
CEXT
VSS
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
OSC/4
OSC2/CLKOUT
EXT > 20 pF
C
In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an add itiona l general pur­pose I/O pin. The I/O pin becomes bit 4 of GPIO (GP4). Figure 3-6 shows the RCIO mode connections.
Internal
Clock
PIC12F683
2004 Microchip Technology Inc. Preliminary DS41211B-page 21
PIC12F683
FIGURE 3-6: RCIO MODE
VDD
REXT
OSC1
CEXT
VSS
GP4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
I/O (OSC2)
C
EXT > 20 pF
Internal
Clock
PIC12F683
The RC oscillator frequency is a function of the supply voltage, the resistor (R
EXT) and capacitor (CEXT)
values and the operating temperature. Other factors affecting the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitances

3.4 Internal Clock Modes

The PIC12F683 has two independent, internal oscilla­tors that can be configured or selected as the system clock source.
1. The HFINTOSC (High-Frequency Internal Oscil­lator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ±12% via software usi ng the OSCTUNE register (Register 3-1).
2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits.
The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3 .5 “Clock Switching”).

3.4.1 INTRC AND INTRCIO MODES

The INTRC and INTRCIO m odes conf igure the int ernal oscillators as th e sys tem cl ock so urce when the dev ice is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word register (Register 12-1).
In INTRC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal os ci lla tor freq uen cy div ide d by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application require me nt s .
In INTRCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.

3.4.2 HFINTOSC

The High-Frequency Int ernal Oscillato r (HFINT OSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approxi­mately ± 12% via software using the OSCT UNE register (Register 3-1).
The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven fre­quencies can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”).
The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF ≠ 000) as the system clock s ource (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF ≠ 000).
The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.
PIC12F683
3.4.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register3-1).
The OSCTUNE register has a tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to pro­cess variation, the monotonicity and frequency step cannot be specified.
When the OSCTUNE register is modified, the HFINTOSC freque ncy will be gin s hifting to th e new fre­quency . The HFINT OSC clock will st abilize with in 1 ms. Code execution contin ues duri ng thi s sh ift. There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 3-1: OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequenc y Tuning bits
01111 = Maximum frequen cy 01110 =
•
•
•
00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =
•
•
• 10000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41211B-page 23
PIC12F683

3.4.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock so urce (SCS = 1), or when any of the following are enabled:
• Two-Speed Start-up (IESO = 1 and IRCF = 000)
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.

3.4.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software:
•8 MHz
• 4 MHz (Default after Reset)
•2 MHz
•1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
•31 kHz
Note: Follow ing a ny Re set, the IRCF bit s are set
to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.

3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING

When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case , there is a 10µs delay after the IRCF bits are modified before the fre­quency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows:
1. IRCF bits are modified.
2. If the new clock is shut down, a 10 µs clock
start-up delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. CLKOUT is held low and the clock switch
circuitry waits fo r a ris ing edge in the new clock.
5. CLKOUT is now connected with the new clock.
HTS/LTS bits are updated as required.
6. Clock switch is complete.
If the internal oscillator speed selected is between 8 M Hz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer.

3.5 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit.

3.5.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals.
• When SCS = 0, the system clock source is
determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG).
• When SCS = 1, the system clock source is
chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail­Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.
PIC12F683

3.5.2 OSCILLAT OR START-UP TIME-OUT STATUS BIT

The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from internal clock source. In partic­ular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.

3.6 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy us e of the Sleep mode, Two-Speed Star t-up will remove the extern al oscillator start -up time from the time spent awake and can reduce the overall power consumption of the device.
This mode allows the application to wake-up from Sleep, perform a f ew inst ructio ns using th e I NTO SC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.
When the PIC12F683 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 “Oscillator Start-up Timer (OST)”). The OST timer will suspend program execu­tion until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.

3.6.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:
• IESO = 1 (CONFIG<10>) Internal/External Switch
Over bit.
•SCS = 0.
• FOSC configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, afte r
PWRT has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be any­thing other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is becaus e t he ex tern al cl oc k oscillator does not require any stabilization time after POR or an exit from Sleep.

3.6.2 TWO-SPEED START-UP SEQUENCE

1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF bits (OSCCON<6:4>).
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next fal ling edg e
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
2004 Microchip Technology Inc. Preliminary DS41211B-page 25
PIC12F683

3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS

Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F683 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
INTOSC
T
TOST
OSC1
OSC2
Program Counter
System Clock
0 1 1022 1023
PC PC + 1 PC + 2
PIC12F683

3.7 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.

FIGURE 3-8: FSCM BLOCK DIAGRAM

Primary
Clock
LFINTOSC
Oscillator
The FSCM function is enabled by setting the FCMEN bit in the Confi guration Word regist er (CONFIG). It is applicable to all ex ternal clo ck options (LP, XT , HS, EC, RC or IO modes).
In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1< 2>) and g enerate an os cilla tor fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscill ator unless the external clock recovers and the Fail-Safe condition is exited.
The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automati­cally cleared to reflect that the internal oscillator is
÷ 64
Clock
Fail
Detector
Clock Failure Detected
active and the WDT is cleared. The SCS bit (OSCCON<0 >) is not upda ted. Enabling FSCM does not affect the LTS bit.
The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a fal lin g e dge o f th e s am pl e clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscil­lator is enabled when FSCM is ena bled, as reflec ted by the IRCF.
Note: Two-Speed Start-up is automatically
enabled when the Fail-Safe Clock Mo nit or mode is enabled.
Note: Primary cl ocks with a freque ncy ≤

3.7.1 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock sourc e. The IRCF bits (OSCCON< 6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-9: FSCM TIMING DIAGRAM
2004 Microchip Technology Inc. Preliminary DS41211B-page 27
PIC12F683

3.7.2 RESET OR WAKE-UP FROM SLEEP

The FSCM is design ed to detect osc illator failu re at any point after the device has exited a Reset or Sleep con­dition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events.
For LP, XT or HS mode the external oscillator may require a start-up time considerably longer than the FSCM sample cloc k time or a fals e clock fai lure may be detected (see Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stab le (the
OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.
Note: Due to the wide ran ge of osc illator st art-up
times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the u se r sho uld check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
REGISTER 3-2: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC (High Frequency – 8MHz to 125 kHz) Status bit
1 =HFINTOSC is stable 0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit
1 = LFINTOSC is stable 0 = LFINTOSC is not stable
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0>
(1)
HTS LTS SCS
Note 1: Bit resets to ‘0’ w ith Two-Speed S t art-up an d LP, XT or HS selected as the osc illator
mode or Fail-Safe mode is enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Loading...
+ 118 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use