MICROCHIP PIC12F635, PIC16F636, PIC16F639 DATA SHEET

PIC12F635/PIC16F636/639

Data Sheet

8/14-Pin Flash-Based,

8-Bit CMOS Microcontrollers

with nanoWatt Technology

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programmin g, IC SP, ICEPIC, MPASM, MPLIB, MPLI N K , MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC12F635/PIC16F636/639

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers

With nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 n s instruction cy cle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of 8 MHz to 31 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

• Clock mode switching for low power operation

• Power-saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended Temperature range

• Power-on Reset (POR)

• Wake-up Reset (WUR)

• Independent weak pull-up/pull-down resistors

• Programmable Low-Voltage Detect (PLVD)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Detect (BOD) with software control option

• Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection (program and data independent)

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

Low Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V , typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• 6/12 I/O pins with individual dire ct ion contro l:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups/ pull-downs

- Ultra Low-Power Wake-up

• Analog comparator module with:

- Up to tw o analog comparators

- Programmable on-chip voltage reference

REF) module (% of VDD)

(CV

- Comparator inputs and outputs externally accessible

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode selected

EELOQ

•K module

• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

compatible hardware Cryptographic

Low Frequency Analog Front-End Features (PIC16F639 only):

• Three input pins for 125 kHz LF input signals

• High input detection sensitivity (3mV

• Demodulated data, Carrier clock or RSSI output selection

• Input carrier frequency: 125 kHz, typical

• Input modulation frequency: 4 kHz, maximum

• 8 internal configuration regi st ers

• Bidirectional transponder communication (LF talk back)

• Programmable antenna tuning capacitance (up to 63 pF, 1 pF/step)

• Low standby current: 5 μA (with 3 channels enabled), typical

• Low operating current: 15 μA (with 3 channels enabled), typical

• Serial Peripheral Interface (SPI™) with internal MCU and external devices

• Supports Battery Back-up mode and batteryless operation with external circuits

PP, typical)

PIC12F635/PIC16F636/639

Device

Program Memory Data Memory

I/O Comparators

Flash (words) SRAM (bytes) EEPROM (bytes)

Low Frequency

Analog

Front-End

PIC12F635 1024 64 128 6 1 N PIC16F636 2048 128 256 12 2 N PIC16F639 2048 128 256 12 2 Y

Pin Diagrams

8-Pin PDIP, SOIC, DFN-S

GP5/T1CKI/OSC1/CLKIN

GP4/T1G

14-Pin PDIP, SOIC, TSSOP

RA5/T1CKI/OSC1/CLKIN

RA4/T1G

/OSC2/CLKOUT

GP3/MCLR

/OSC2/CLKOUT

RA3/MCLR

/VPP

DD VSS

/VPP RC5

RC4/C2OUT

RC3

1 2

PIC12F635

PIC16F636

VSSVDD GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT

RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V

RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2

REF/ICSPCLK

20-Pin SSOP

RA5/T1CKI/OSC1/CLKIN

/OSC2/CLKOUT

RA4/T1G

RC3/LFDATA/RSSI/CCLK/SDIO

RA3/MCLR

VDD

/VPP RC5

RC4/C2OUT

DDT

LCZ

LCY

(3)

PIC16F639

VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT VSST LCCOM LCX

REF/ICSPCLK

(4)

Note 1: Any references to PORT A, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.

2: Additional information on I/O ports may be found in the “PICmicro

Mid-Range MCU Family Reference

Manual” (DS33023).

DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

3: V

this document unless otherwise stated.

SST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated

4: V

as V

SS in this document unless otherwise stated.

PIC12F635/PIC16F636/639

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................. 11

3.0 Clock Sources............................................................................................................................................................................29

4.0 I/O Ports................................ ........................................ ............................ ................................................................................. 39

5.0 Timer0 Module ........................................................................................................................................................................... 53

6.0 Timer1 Module with Gate Control............................................................................................................................................... 56

7.0 Comparator Module.................................................................................................................................................................... 61

8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 71

9.0 Data EEPROM Memory................... ........................... ............................ ........................... ........................................................ 73

10.0 KeeLoq Compatible Cryptographic Module................................................................................................................................77

11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 79

12.0 Special Features of the CPU......................... ........................... ........................................ ........................................................ 111

13.0 Instruction Set Summary.......................................................................................................................................................... 131

14.0 Development Support............................................................................................................................................................... 141

15.0 Electrical Specifications............................................................................................................................................................147

16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 173

17.0 Packaging Information............................ ........................................ ........................... ...............................................................175

On-Line Support 185

Systems Information and Upgrade Hot Line..................................................................................................................................... 185

Reader Response. ............................................................................................................................................................................ 186

Appendix A: Data Sheet Revision History......................................................................................................................................... 187

Appendix B: Product Identification System....................................................................................................................................... 193

Worldwide Sales and Service ............................................. ........................................ ...................................................................... 19

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Most Current Data Sheet

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

1.0 DEVICE OVERVIEW

This document contains device specific information for the PIC12F635/PIC16F636/639 devices. Additional information may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023), which m ay be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

Program

Bus

Configuration

Flash 1K x 14 Program

Memory

Instruction reg

Program Counter

8-level Stack

(13-bit)

Direct Addr

RAM Addr

The PIC12F635/PIC16F636/639 devices are covered by this data sh eet. Figure 1-1 shows a block diagram of the PIC12F635/PIC16F636/639 devices. Table 1-1 shows the pinout description.

Data Bus

RAM

64 bytes

File

Registers

Addr MUX

FSR reg

Indirect

Addr

GPIO

GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT GP3/MCLR GP4/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN

/VPP

OSC1/CLKIN

OSC2/CLKOUT

Oscillator

T1G

T1CKI

T0CKI

Cryptographic

Instruction

Decode and

Control

Timing

Generation

8 MHz

Internal

Timer0 Timer1

Module

31 kHz Internal

Oscillator

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-Voltage Detect

Wake-up

Reset

VDD

MCLR

Comparator

and Referen ce

C1IN- C1IN+ C1OUT

VSS

1 Analog

Status re g

MUX

ALU

W reg

EEDAT

128 bytes

Data

EEPROM EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

8 MHz

Internal

Oscillator

Configuration

Flash 2K x 14 Program

Memory

Instruction reg

Instruction

Decode and

Control

Timing

Generation

31 kHz Internal

Oscillator

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-Voltage Detect

Wake-up

Reset

RAM Addr

Data Bus

RAM 128

bytes

File

Registers

Addr MUX

FSR reg

Status reg

MUX

ALU

W reg

T1CKI

Indirect

Addr

T1G

PORTA

PORTC

RA0/C1IN+/ICSPDA T/ ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN

RC0/C2IN+ RC1/C2INRC2 RC3 RC4/C2OUT RC5

/VPP

T0CKI

VDD

MCLR

Timer0 Timer1

Cryptographic

Module

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

2 Analog Comparators

and Refere nce

VSS

EEDAT

256 bytes

Data

EEPROM EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

OSC1/CLKIN

OSC2/CLKOUT

T0CKI

Configuration

Flash

2K x 14

Program

Memory

Program

8 MHz

Internal

Oscillator

Bus

Instruction reg

Instruction

Decode and

Control

Timing

Generation

31 kHz

Internal

Oscillator

Timer0 Timer1

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-voltage Detect

Wake-up

Reset

VDD

MCLR

RAM Addr

VSS

Data Bus

RAM

128

bytes

File

Registers

(1)

Addr MUX

FSR reg

Status reg

MUX

ALU

W reg

T1CKI T1G

Indirect

Addr

PORTA

PORTC

VDDT V

SST

LCCOM

RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN

RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT RC3/LFDATA/RSSI/CCLK/SDIO RC4/C2OUT RC5

125 kHz

Analog Front-End

LCX

/VPP

(AFE)

LCY LCZ

KEELOQ Module

2 Analog

Comparators

and Reference

C1IN- C1IN+ C1OUTC2IN-

C2IN+C2OUT

EEDAT

256 bytes

DATA

EEPROM EEADDR

PIC12F635/PIC16F636/639

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

Name Function

VDD VDD D — Power supply for microcontroller. GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection. CLKIN ST — T

GP4/T1G

GP3/MCLR

GP2/T0CKI/INT/C1OUT GP2 ST CMOS General purpose I/O. Individually controlled

GP1/C1IN-/ICSPCLK GP1 TTL CMOS General purpose I/O. Individually controlled

GP0/C1IN+/ICSPDAT/ULPWU GP0 TTL — General purpose I/O. Individually controlled

SS VSS D — Ground reference for microcontroller.

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/OSC2/CLKOUT GP4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

T1G

OSC2 — XTAL XTAL co nnection.

CLKOUT — CMOS T

/VPP GP3 TTL — General purpose input. Individually control led

MCLR

VPP HV — Programming voltage.

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

C1IN- AN — Comparator 1 input – negative.

ICSPCLK ST — Serial programming clock.

C1IN+ AN — Comparator 1 input – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

Input Type

Output

Type

change. Individually enabled pull-up/pull-down.

OSC reference clock.

change. Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

interrupt-on-change.

ST — Master Clear Reset. Pull-up enabled when confi gured a s

MCLR

interrupt-on-change. Individually enabled pull-up/pull-down.

interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

Description

PIC12F635/PIC16F636/639

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

Name Function

VDD VDD D — Power supply for microcontroller. RA5/T1CKI/OSC1/ CLKIN RA5 TTL CMOS General purpose I/O. Ind iv i dua ll y c on tro ll ed

T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection.

CLKIN ST — T

RA4/T1G

RA3/MCLR

RC5 RC5 TTL CMOS General purpose I/O. RC4/C2OUT RC4 TTL CMOS General purpose I/O.

RC3 RC3 TTL CMOS General purpose I/O. RC2 RC2 TTL CMOS General purpose I/O. RC1/C2IN- RC1 TTL CMOS General purpose I/O.

RC0/C2IN+ RC0 TTL CMOS General purpose I/O.

RA2/T0CKI/INT/C1OUT RA2 ST CMOS G e neral p urpose I/O. I n dividu ally c o ntroll e d

RA1/C1IN-/V

RA0/C1IN + / I C S P DAT/ULPWU RA0 TTL — General purpose I/O. Ind iv i dua ll y c on tro ll ed

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Ind iv i dua ll y c on tro ll ed

T1G

OSC2 — XTAL XTAL con ne cti on.

CLKOUT — CMOS T

/VPP RA3 TTL — General purpose input. Individually controlled

MCLR

VPP HV — Programming voltage.

C2OUT — CMOS Comparator 2 output.

C2IN- AN — Comparator 1 input – negative.

C2IN+ AN — Comparator 1 in put – positive.

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individua ll y c on tro ll ed

C1IN- AN — Comparator 1 input – negative.

ICSPCLK ST — Serial programming clock.

C1IN+ AN — Comparator 1 in put – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

SS VSS D — Ground reference for microcontroller.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

Input

Type

Output

Type

interrupt-on-change. Individually enabled pull-up/pull-down.

OSC reference clock.

interrupt-on-change. Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

interrupt-on-change.

ST — Master Clear Reset. Pull-up enabled when

configured as MCLR

interrupt-on-change. Individually enabled pull-up/pull-down.

interrupt-on-c hange . Indivi duall y enab led pu ll-up /pull -dow n.

interrupt-on-change. Individually enabled pull-up/pull-down.

Selectable Ultra Low-Power Wake-up pin.

Description

PIC12F635/PIC16F636/639

TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS

Name Function

DD VDD D — Power supply for microcontroller

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1CKI ST — Timer1 clock OSC1 XTAL — XTAL connection

CLKIN ST — T

RA4/T1G/OSC2/CLKOUT

RA3/MCLR

RC5 RC5 TTL CMOS General purpose I/O RC4/C2OUT RC4 TTL CMOS General purpose I/O

RC3/LFDATA/RSSI/CCLK/SDIO RC3 TTL CMOS General purpose I/O

DDT VDDT D — P owe r supply for Analog Front-End. In this document, VDDT is treated

LCZ LCZ AN — 125 kHz analog Z channel input LCY LCY AN — 125 kHz analog Y channel input LCX LCX AN — 125 kHz analog X channel input LCCOM LCCOM AN — Common reference for analog inputs

SST VSST D — Ground reference for Analog Front-End. In this document, VSST is

RC2/SCLK/ALERT

RC1/C2IN-/CS

RC0/C2IN+ RC0 TTL CMOS

RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.

RA1/C1IN-/V

RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change.

SS VSS D — Ground reference for microcontroller

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/VPP

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Direct TTL = TTL compatible input XTAL = Crystal

RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1G

OSC2 — X TAL XTAL connecti on

CLKOUT — CMOS TOSC reference clock

RA3 TTL

MCLR

PP HV — Programming voltage

C2OUT — CMOS Comparator2 output

LFDATA — CMOS Digital output representation of analog input signal to LC pins.

RSSI — Current Received signal strength indicator. Analog current that is proportional

CCLK — — Carrier clock output

SDIO TTL CMOS Input/Output for SPI communication

RC2 TTL CMOS General purpose I/O

SCLK TTL — Digital clock input for SPI communica tion

ALERT

RC1 TTL CMOS

C2IN- AN —

C2IN+ AN —

T0CKI ST — External clock fo r Timer0

INT ST — External Interrupt

C1OUT — CMOS Comparator1 output

C1IN- AN — Comparator1 input – negative

ICSPCLK ST — Serial Programming Clock

C1IN+ AN — Comparator1 inpu t – positive

ICSPDAT TTL CMOS Serial Programming Data IO

ULPWU AN — Ultra Low-Power Wake-up input

Input Type

TTL —

Output

Type

Individually enabled pull-up/pull-down.

OSC/4 reference clock

Individually enabled pull-up/pull-down.

ST — Timer1 gate

General purpose input. Individually controlled interrupt-on-change.

—

ST —

—OD

Master Clear Reset. Pull-up enabled when configured as MCLR

to input amplitude.

the same as VDD, un less otherwis e stated.

treated the same as V

Output with internal pull-up resistor for AFE error signal General purpose I/O Comparator1 input - negative Chip select input for SPI communication with internal pull-up resistor

General purpose I/O Comparator1 input - positive

Individually enabled pull-up/pull-down.

Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

Description

SS, unless otherwise stated.

PIC12F635/PIC16F636/639

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, reg ister locat ions 4 0h throug h 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit.

TABLE 2-1: BANK SELECTION

RP0 RP1 Bank

000 101 012 113

FIGURE 2-1: PROGRAM MEM O R Y M AP AND

STAC K OF THE PIC12F635

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Access 0-3FFh

0000h

0004h 0005h

Memory

03FFh 0400h

1FFFh

FIGURE 2-2: PROGRAM MEMORY MAP AND

ST AC K OF T HE PIC16F636/639

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

Access 0-7FFh

0000h

0004h 0005h

07FFh 0800h

1FFFh

PIC12F635/PIC16F636/639

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select R egister, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM.

The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

PIC12F635/PIC16F636/639

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h STATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

GPIO 05h TRISIO 85h 105h 185h

06h 86h 106h 186h 07h 87h 107h 187h 08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h CRCON 110h

11h 91h 12h 92h 13h 93h 14h LVDCON 94h 15h WPUDA 95h 115h 195h 16h IOCA 96h 116h 196h 17h WDA 97h 117h 197h

WDTCON 18h 98h 118h 198h

CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah

1Bh EEADR 9Bh 11Bh 19Bh 1Ch EECON1 9Ch 11Ch 19Ch 1Dh EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h

Address

(1)

80h

File

Accesses

00h-0Bh

File

Address

100h

Accesses

80h-8Bh

10Ch 18Ch

(2)

CRDAT0 CRDAT1 CRDAT2 CRDAT3

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

119h 199h

(1)

9Dh 11Dh 19Dh

A0h 120h 1A0h

File

Address

180h

190h

3Fh

General Purpose Register 64 Bytes

40h

EFh 16Fh 1EFh

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

F0h

Accesses

70h-7Fh

170h

Accesses

Bank 0

1F0h

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> are K

“K

EELOQ

Encoder License Agreement ” regarding imp lemen tat ion of the mo dule and access to relate d

registers. The “K

EELOQ

located at www.microchip.co m/K

hardware peripheral related registers and require the execution of the

Encoder License Agree ment” may be accesse d through the Microc hip web site

EELOQ or by contacting your local Microchip Sales Representative.

PIC12F635/PIC16F636/639

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h STATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

PORTA 05h TRISA 85h 105h 185h

06h 86h 106h 186h

PORTC 07h TRISC 87h 107h 187h

08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh TMR1H 0Fh OSCCON 8Fh T1CON 10h OSCTUNE 90h CRCON 110h 190h

11h 91h

12h 92h

13h 93h

14h LVDCON 94h

15h WPUDA 95h 115h 195h

16h IOCA 96h 116h 196h

17h WDA 97h 117h 197h

WDTCON 18h 98h 118h 198h

CMCON0 19h VRCON 99h 119h 199h CMCON1 1Ah EEDAT 9Ah

1Bh EEADR 9Bh 11Bh 19Bh

1Ch EECON1 9Ch 11Ch 19Ch

1Dh

EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h

General

Purpose

General

Purpose

32 Bytes

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> are K

EELOQ hardware peripheral related registers and require the execution of the “KEELOQ

Encoder License Agreem ent” regarding im plement ation of the modu le and access to related registe rs. Th “KEELOQ® Encoder License Agreement” may be accessed through the Microchip web site located a www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.

Address

(1)

80h

File

Accesses

00h-0Bh

File

Address

100h

Accesses

80h-8Bh

10Ch 18Ch

10Eh 18Eh 10Fh 18Fh

(2)

CRDAT0 CRDAT1 CRDAT2 CRDAT3

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

11Ah 19Ah

(1)

9Dh 11Dh 19Dh

A0h

120h 1A0h

BFh C0h

EFh 16Fh 1EFh F0h

Accesses

70h-7Fh

170h

Accesses

Bank 0

File

Address

180h

1F0h

PIC12F635/PIC16F636/639

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

PD ZDCC0001 1xxx 000q quuu

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xx00 --uu uu00

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

EEIF LVDIF CRIF —C1IFOSFIF—TMR1IF000- 00-0 000- 00-0

TMR1CS TMR1ON 0000 0000 uuuu uuuu

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 —C1OUT— C1INV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 — — — — — — T1GSS CMSYNC ---- --10 ---- --10

shaded = unimplemented

Reset and Watchdog Timer Reset during normal operation.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(2)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS IRP RP1 RP0 TO 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON2 EEPROM Cont rol Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: GP3 pull-up is enabled when pin is configured as MCLR 3: MCLR

again if the mismatch exists.

(not a physical register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

—C1IEOSFIE—TMR1IE000- 00-0 000- 00-0

— — ULPWUE SBODEN WUR —PORBOD --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 O STS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — WDA5 WDA4 — WDA2WDA1WDA0--11 -111 --11 -111

—VRR—VR3VR2VR1VR00-0- 0000 0-0- 0000

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

— — — — WRERR WRE N WR RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(3)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS IRP RP 1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuxx 05h PORTA 06h — Unimplemented — — 07h PORTC 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 C2OUT C1OUT 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

PD ZDCC0001 1xxx 000q quuu

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 --uu uu00

— — R C5 RC4 RC3 RC2 RC1 RC0 --xx xx00 --uu uu00

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

EEIF LVDIF CRIF C2IF C1IF OSFIF —TMR1IF0000 00-0 0000 00-0

TMR1CS TMR1ON 0000 0000 uuuu uuuu

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

— — — — — — T1GSS C2SYNC ---- --10 ---- --10

shaded = unimplemented

Reset and Watchdog Timer Reset during normal operation.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

Val ue on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(2)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-5: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS IRP RP1 RP0 TO 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA 86h — Unimplemented — — 87h TRISC 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE C2IE C1IE OSFIE 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: RA3 pull-up is enabled when pin is configured as MCLR 3: MCLR

again if the mismatch exists.

(not a physical register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

—TMR1IE0000 00-0 0000 00-0

— — ULPWUE SBODEN WUR —PORBOD --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

— — — — WRERR WREN WR RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(3)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-6: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2 10Ch — Unim plemented — — 10Dh — Unim plemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — —

110h CRCON GO/DONE 111h CRDAT0 112h CRDAT1 113h CRDAT2 114h CRDAT3 115h — Unimplemented — — 116h — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: CRDAT<3:0> are KEELOQ® hardware peri ph era l rel ate d reg iste rs and requ ir e the ex ec utio n of the “KEELOQ Encoder Lice nse Agre emen t”

(2)

Cryptographic Data Register 0 0000 0000 0000 0000

(2)

Cryptographic Data Register 1 0000 0000 0000 0000

(2)

Cryptographic Data Register 2 0000 0000 0000 0000

(2)

Cryptographic Data Register 3 0000 0000 0000 0000

shaded = unimplemented

regarding implementation of the module and access to related registers. The “K through the Microchip web site located at www.microchip.com/K

ENC/DEC — — — — CRREG1 CRR EG0 00-- --00 00-- --00

Reset and Watchdog Timer Reset during normal operation.

EELOQ Encoder License Agreement” may be a ccessed

EELOQ or by contacting your local Microchip Sales Representative.

Value on

POR/BOD/

WUR

Value on all other

Resets

(1)

PIC12F635/PIC16F636/639

2.2.2.1 Status Register

The Status register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM) The Status register can be the destination for any

instruction, like any other register . If the S tatus register is the destination for an instruction that affects the Z, D C or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO Therefore, the result of an instruction with the Status register as destination may be different than intended.

and PD bits are not writable.

For example, CLRF STATUS, w ill c lear the upper three bits and set the Z bit. Thi s leaves the Status regis ter as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see Section 13.0 “Instruction Set Summary”.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indire ct addressing)

1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh)

Each bank is 128 bytes.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/B

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

orrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

For Borrow, the polarity is reversed.

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

PD ZDCC

Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.2 Option Register

The Option register is a readable and writable register which contains various control bits to configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

•TMR0

• Weak pull-up/pull-downs on PORTA

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU

bit 7 bit 0

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by setting the PSA bit to ‘1’ (OPTION_REG<3>). See Section 5.4 “Prescaler”.

bit 7 RAPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: PORTA Pull-up/Pull-down Enable bit

1 = PORTA pull-ups/pull-downs are disabled 0 = PORTA pull-ups/pull-downs are enabled by individual port latch values

1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin

1 = Transition on RA 2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit V alue TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register which co nta ins th e vari ous e nable and fl ag bit s for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regard less of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensu re the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE RAIE

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit

1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has over flowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interru pt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state

(2)

(3)

(1)

T0IF

(2)

INTF RAIF

(3)

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing the T0IF bit.

3: MCLR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

and WDT Reset do not af fect the prev ious va lue dat a latc h. The R AIF bit w ill

be cleared upon Reset but will set again if the mismatch exists.

PIC12F635/PIC16F636/639

2.2.2.4 PIE1 Register

The PIE1 register contai ns th e in terru pt enable bits, as shown in Register 2-4.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIE LVDIE CRIE C2IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt

bit 6 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enables the LVD interrupt 0 = Disables the LVD interrupt

bit 5 CRIE: Cryptographic Interrupt Enable bit

1 = Enables the cryptographic interrupt 0 = Disables the cryptographic interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Interrupt Enable bit

1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

(1)

C1IE OSFIE —TMR1IE

Note 1: PIC16F636/639 only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIF LVDIF CRIF C2IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = The supply voltage has crossed selected LVD voltage (must be cleared in software) 0 = The supply voltage has not crossed selected LVD voltage

bit 5 CRIF: Cryptographic Interrupt Flag bit

1 = The Cryptographic module has completed an operation (must be cleared in software) 0 = The Cryptographic module has not completed an operation or is Idle

bit 4 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed

bit 3 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed INTOSC (must be cleared in software) 0 = System clock operating

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: Timer1 Interrupt Flag bit

1 = Timer1 rolled ov er (must be cleared in software) 0 = Timer1 has not rolled over

Note: Interrupt flag bits are set when an interrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

(1)

C1IF OSFIF —TMR1IF

Note 1: PIC16F636/639 only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.6 PCON Register

The Power Control (PCON) register (see Table 12-3) contains flag bit s to differentiate between a:

• Power-on Reset (POR

• Wake-up Reset (WUR)

• Brown-out Detect (BOD

• Watchdog Timer Reset (WDT)

• External MCLR Reset

)

The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD

The PCON register bits are shown in Register 2-6.

U-0 U-0 R/W-0 R/W-1 R/W-x U-0 R/W-0 R/W-x

— — ULPWUE SBODEN

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled

bit 4 SBODEN: Software BOD Enable bit

1 = BOD enabled 0 = BOD disabled

bit 3 WUR

bit 2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOD

: Wake-up Reset Status bit

1 = No Wake-up Reset occurred 0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Detect Status bit

1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

(1)

WUR —PORBOD

Note 1: BODEN<1:0> = 01 in the Configuration Word register for SBODEN to control the

Brown-out Detect module.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

PCLATH

Instruction with

PCL as

Destination

ALU Result

GOTO, CALL

Opcode<10:0>

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556).

2.3.2 STACK

The PIC12F635/PIC16F636/639 family has an 8level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the S ta ck Pointer i s not rea dable or writa ble. The PC is PUSHed onto the stack when a CALL instruction is execute d or an interrupt ca uses a branc h. The stack is POP ed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a P USH or POP operation.

The stack operat es as a circular buf fer . This means th at after the stack has been PUSHed eight times, the ninth push overwrites the va lue tha t was s tored fro m the first push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the exec ution of the CALL, RETURN, RETLW and RETFIE instru ction s or the vectoring to an interrupt address.

PIC12F635/PIC16F636/639

2.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physi cal register. Addres sing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be

A simple program to clear RAM lo catio n 20h-2Fh usin g indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;INC POINTER BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (STATUS<7>), as shown in Figure 2-6.

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

Indirect A ddressingDirect Addressing

From Opcode

RP1 RP0

Bank Select Location Select

00h

00 01 10 11

IRP File Select Register

Bank Select

180h

Location Select

Data Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Note: For memory map det ail, see Figure2-2.

1FFh

PIC12F635/PIC16F636/639

NOTES:

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