MICROCHIP PIC12F635, PIC16F636, PIC16F639 DATA SHEET

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PIC12F635/PIC16F636/639

Data Sheet

8/14-Pin Flash-Based,

8-Bit CMOS Microcontrollers

with nanoWatt Technology

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programmin g, IC SP, ICEPIC, MPASM, MPLIB, MPLI N K , MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC12F635/PIC16F636/639

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers

With nanoWatt Technology

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 n s instruction cy cle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of 8 MHz to 31 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

• Clock mode switching for low power operation

• Power-saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended Temperature range

• Power-on Reset (POR)

• Wake-up Reset (WUR)

• Independent weak pull-up/pull-down resistors

• Programmable Low-Voltage Detect (PLVD)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Detect (BOD) with software control option

• Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection (program and data independent)

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

Low Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V , typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Features:

• 6/12 I/O pins with individual dire ct ion contro l:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups/ pull-downs

- Ultra Low-Power Wake-up

• Analog comparator module with:

- Up to tw o analog comparators

- Programmable on-chip voltage reference

REF) module (% of VDD)

(CV

- Comparator inputs and outputs externally accessible

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode selected

EELOQ

•K module

• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

compatible hardware Cryptographic

Low Frequency Analog Front-End Features (PIC16F639 only):

• Three input pins for 125 kHz LF input signals

• High input detection sensitivity (3mV

• Demodulated data, Carrier clock or RSSI output selection

• Input carrier frequency: 125 kHz, typical

• Input modulation frequency: 4 kHz, maximum

• 8 internal configuration regi st ers

• Bidirectional transponder communication (LF talk back)

• Programmable antenna tuning capacitance (up to 63 pF, 1 pF/step)

• Low standby current: 5 μA (with 3 channels enabled), typical

• Low operating current: 15 μA (with 3 channels enabled), typical

• Serial Peripheral Interface (SPI™) with internal MCU and external devices

• Supports Battery Back-up mode and batteryless operation with external circuits

PP, typical)

PIC12F635/PIC16F636/639

Device

Program Memory Data Memory

I/O Comparators

Flash (words) SRAM (bytes) EEPROM (bytes)

Low Frequency

Analog

Front-End

PIC12F635 1024 64 128 6 1 N PIC16F636 2048 128 256 12 2 N PIC16F639 2048 128 256 12 2 Y

Pin Diagrams

8-Pin PDIP, SOIC, DFN-S

GP5/T1CKI/OSC1/CLKIN

GP4/T1G

14-Pin PDIP, SOIC, TSSOP

RA5/T1CKI/OSC1/CLKIN

RA4/T1G

/OSC2/CLKOUT

GP3/MCLR

/OSC2/CLKOUT

RA3/MCLR

/VPP

DD VSS

/VPP RC5

RC4/C2OUT

RC3

1 2

PIC12F635

PIC16F636

VSSVDD GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT

RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V

RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2

REF/ICSPCLK

20-Pin SSOP

RA5/T1CKI/OSC1/CLKIN

/OSC2/CLKOUT

RA4/T1G

RC3/LFDATA/RSSI/CCLK/SDIO

RA3/MCLR

VDD

/VPP RC5

RC4/C2OUT

DDT

LCZ

LCY

(3)

PIC16F639

VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/V RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT VSST LCCOM LCX

REF/ICSPCLK

(4)

Note 1: Any references to PORT A, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.

2: Additional information on I/O ports may be found in the “PICmicro

Mid-Range MCU Family Reference

Manual” (DS33023).

DDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

3: V

this document unless otherwise stated.

SST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated

4: V

as V

SS in this document unless otherwise stated.

PIC12F635/PIC16F636/639

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................. 11

3.0 Clock Sources............................................................................................................................................................................29

4.0 I/O Ports................................ ........................................ ............................ ................................................................................. 39

5.0 Timer0 Module ........................................................................................................................................................................... 53

6.0 Timer1 Module with Gate Control............................................................................................................................................... 56

7.0 Comparator Module.................................................................................................................................................................... 61

8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 71

9.0 Data EEPROM Memory................... ........................... ............................ ........................... ........................................................ 73

10.0 KeeLoq Compatible Cryptographic Module................................................................................................................................77

11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 79

12.0 Special Features of the CPU......................... ........................... ........................................ ........................................................ 111

13.0 Instruction Set Summary.......................................................................................................................................................... 131

14.0 Development Support............................................................................................................................................................... 141

15.0 Electrical Specifications............................................................................................................................................................147

16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 173

17.0 Packaging Information............................ ........................................ ........................... ...............................................................175

On-Line Support 185

Systems Information and Upgrade Hot Line..................................................................................................................................... 185

Reader Response. ............................................................................................................................................................................ 186

Appendix A: Data Sheet Revision History......................................................................................................................................... 187

Appendix B: Product Identification System....................................................................................................................................... 193

Worldwide Sales and Service ............................................. ........................................ ...................................................................... 19

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

1.0 DEVICE OVERVIEW

This document contains device specific information for the PIC12F635/PIC16F636/639 devices. Additional information may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023), which m ay be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

Program

Bus

Configuration

Flash 1K x 14 Program

Memory

Instruction reg

Program Counter

8-level Stack

(13-bit)

Direct Addr

RAM Addr

The PIC12F635/PIC16F636/639 devices are covered by this data sh eet. Figure 1-1 shows a block diagram of the PIC12F635/PIC16F636/639 devices. Table 1-1 shows the pinout description.

Data Bus

RAM

64 bytes

File

Registers

Addr MUX

FSR reg

Indirect

Addr

GPIO

GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT GP3/MCLR GP4/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN

/VPP

OSC1/CLKIN

OSC2/CLKOUT

Oscillator

T1G

T1CKI

T0CKI

Cryptographic

Instruction

Decode and

Control

Timing

Generation

8 MHz

Internal

Timer0 Timer1

Module

31 kHz Internal

Oscillator

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-Voltage Detect

Wake-up

Reset

VDD

MCLR

Comparator

and Referen ce

C1IN- C1IN+ C1OUT

VSS

1 Analog

Status re g

MUX

ALU

W reg

EEDAT

128 bytes

Data

EEPROM EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN

OSC2/CLKOUT

8 MHz

Internal

Oscillator

Configuration

Flash 2K x 14 Program

Memory

Instruction reg

Instruction

Decode and

Control

Timing

Generation

31 kHz Internal

Oscillator

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-Voltage Detect

Wake-up

Reset

RAM Addr

Data Bus

RAM 128

bytes

File

Registers

Addr MUX

FSR reg

Status reg

MUX

ALU

W reg

T1CKI

Indirect

Addr

T1G

PORTA

PORTC

RA0/C1IN+/ICSPDA T/ ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN

RC0/C2IN+ RC1/C2INRC2 RC3 RC4/C2OUT RC5

/VPP

T0CKI

VDD

MCLR

Timer0 Timer1

Cryptographic

Module

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

2 Analog Comparators

and Refere nce

VSS

EEDAT

256 bytes

Data

EEPROM EEADDR

PIC12F635/PIC16F636/639

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

OSC1/CLKIN

OSC2/CLKOUT

T0CKI

Configuration

Flash

2K x 14

Program

Memory

Program

8 MHz

Internal

Oscillator

Bus

Instruction reg

Instruction

Decode and

Control

Timing

Generation

31 kHz

Internal

Oscillator

Timer0 Timer1

Program Counter

8-level Stack

(13-bit)

Direct Addr

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Detect

Programmable

Low-voltage Detect

Wake-up

Reset

VDD

MCLR

RAM Addr

VSS

Data Bus

RAM

128

bytes

File

Registers

(1)

Addr MUX

FSR reg

Status reg

MUX

ALU

W reg

T1CKI T1G

Indirect

Addr

PORTA

PORTC

VDDT V

SST

LCCOM

RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN

RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT RC3/LFDATA/RSSI/CCLK/SDIO RC4/C2OUT RC5

125 kHz

Analog Front-End

LCX

/VPP

(AFE)

LCY LCZ

KEELOQ Module

2 Analog

Comparators

and Reference

C1IN- C1IN+ C1OUTC2IN-

C2IN+C2OUT

EEDAT

256 bytes

DATA

EEPROM EEADDR

PIC12F635/PIC16F636/639

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

Name Function

VDD VDD D — Power supply for microcontroller. GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection. CLKIN ST — T

GP4/T1G

GP3/MCLR

GP2/T0CKI/INT/C1OUT GP2 ST CMOS General purpose I/O. Individually controlled

GP1/C1IN-/ICSPCLK GP1 TTL CMOS General purpose I/O. Individually controlled

GP0/C1IN+/ICSPDAT/ULPWU GP0 TTL — General purpose I/O. Individually controlled

SS VSS D — Ground reference for microcontroller.

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/OSC2/CLKOUT GP4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-

T1G

OSC2 — XTAL XTAL co nnection.

CLKOUT — CMOS T

/VPP GP3 TTL — General purpose input. Individually control led

MCLR

VPP HV — Programming voltage.

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

C1IN- AN — Comparator 1 input – negative.

ICSPCLK ST — Serial programming clock.

C1IN+ AN — Comparator 1 input – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

Input Type

Output

Type

change. Individually enabled pull-up/pull-down.

OSC reference clock.

change. Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

interrupt-on-change.

ST — Master Clear Reset. Pull-up enabled when confi gured a s

MCLR

interrupt-on-change. Individually enabled pull-up/pull-down.

interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

Description

PIC12F635/PIC16F636/639

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

Name Function

VDD VDD D — Power supply for microcontroller. RA5/T1CKI/OSC1/ CLKIN RA5 TTL CMOS General purpose I/O. Ind iv i dua ll y c on tro ll ed

T1CKI ST — Timer1 clock. OSC1 XTAL — XTAL connection.

CLKIN ST — T

RA4/T1G

RA3/MCLR

RC5 RC5 TTL CMOS General purpose I/O. RC4/C2OUT RC4 TTL CMOS General purpose I/O.

RC3 RC3 TTL CMOS General purpose I/O. RC2 RC2 TTL CMOS General purpose I/O. RC1/C2IN- RC1 TTL CMOS General purpose I/O.

RC0/C2IN+ RC0 TTL CMOS General purpose I/O.

RA2/T0CKI/INT/C1OUT RA2 ST CMOS G e neral p urpose I/O. I n dividu ally c o ntroll e d

RA1/C1IN-/V

RA0/C1IN + / I C S P DAT/ULPWU RA0 TTL — General purpose I/O. Ind iv i dua ll y c on tro ll ed

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Ind iv i dua ll y c on tro ll ed

T1G

OSC2 — XTAL XTAL con ne cti on.

CLKOUT — CMOS T

/VPP RA3 TTL — General purpose input. Individually controlled

MCLR

VPP HV — Programming voltage.

C2OUT — CMOS Comparator 2 output.

C2IN- AN — Comparator 1 input – negative.

C2IN+ AN — Comparator 1 in put – positive.

T0CKI ST — External clock for Timer0.

INT ST — External interrupt.

C1OUT — CMOS Comparator 1 output.

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individua ll y c on tro ll ed

C1IN- AN — Comparator 1 input – negative.

ICSPCLK ST — Serial programming clock.

C1IN+ AN — Comparator 1 in put – positive.

ICSPDAT TTL CMOS Serial programming data I/O.

ULPWU AN — Ultra Low-Power Wake-up input.

SS VSS D — Ground reference for microcontroller.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

Input

Type

Output

Type

interrupt-on-change. Individually enabled pull-up/pull-down.

OSC reference clock.

interrupt-on-change. Individually enabled pull-up/pull-down.

ST — Timer1 gate.

OSC/4 reference clock.

interrupt-on-change.

ST — Master Clear Reset. Pull-up enabled when

configured as MCLR

interrupt-on-change. Individually enabled pull-up/pull-down.

interrupt-on-c hange . Indivi duall y enab led pu ll-up /pull -dow n.

interrupt-on-change. Individually enabled pull-up/pull-down.

Selectable Ultra Low-Power Wake-up pin.

Description

PIC12F635/PIC16F636/639

TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS

Name Function

DD VDD D — Power supply for microcontroller

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1CKI ST — Timer1 clock OSC1 XTAL — XTAL connection

CLKIN ST — T

RA4/T1G/OSC2/CLKOUT

RA3/MCLR

RC5 RC5 TTL CMOS General purpose I/O RC4/C2OUT RC4 TTL CMOS General purpose I/O

RC3/LFDATA/RSSI/CCLK/SDIO RC3 TTL CMOS General purpose I/O

DDT VDDT D — P owe r supply for Analog Front-End. In this document, VDDT is treated

LCZ LCZ AN — 125 kHz analog Z channel input LCY LCY AN — 125 kHz analog Y channel input LCX LCX AN — 125 kHz analog X channel input LCCOM LCCOM AN — Common reference for analog inputs

SST VSST D — Ground reference for Analog Front-End. In this document, VSST is

RC2/SCLK/ALERT

RC1/C2IN-/CS

RC0/C2IN+ RC0 TTL CMOS

RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.

RA1/C1IN-/V

RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change.

SS VSS D — Ground reference for microcontroller

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output D = Direct

/VPP

REF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

HV = High Voltage ST = Schmitt Trigger input with CMOS levels OD = Direct TTL = TTL compatible input XTAL = Crystal

RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

T1G

OSC2 — X TAL XTAL connecti on

CLKOUT — CMOS TOSC reference clock

RA3 TTL

MCLR

PP HV — Programming voltage

C2OUT — CMOS Comparator2 output

LFDATA — CMOS Digital output representation of analog input signal to LC pins.

RSSI — Current Received signal strength indicator. Analog current that is proportional

CCLK — — Carrier clock output

SDIO TTL CMOS Input/Output for SPI communication

RC2 TTL CMOS General purpose I/O

SCLK TTL — Digital clock input for SPI communica tion

ALERT

RC1 TTL CMOS

C2IN- AN —

C2IN+ AN —

T0CKI ST — External clock fo r Timer0

INT ST — External Interrupt

C1OUT — CMOS Comparator1 output

C1IN- AN — Comparator1 input – negative

ICSPCLK ST — Serial Programming Clock

C1IN+ AN — Comparator1 inpu t – positive

ICSPDAT TTL CMOS Serial Programming Data IO

ULPWU AN — Ultra Low-Power Wake-up input

Input Type

TTL —

Output

Type

Individually enabled pull-up/pull-down.

OSC/4 reference clock

Individually enabled pull-up/pull-down.

ST — Timer1 gate

General purpose input. Individually controlled interrupt-on-change.

—

ST —

—OD

Master Clear Reset. Pull-up enabled when configured as MCLR

to input amplitude.

the same as VDD, un less otherwis e stated.

treated the same as V

Output with internal pull-up resistor for AFE error signal General purpose I/O Comparator1 input - negative Chip select input for SPI communication with internal pull-up resistor

General purpose I/O Comparator1 input - positive

Individually enabled pull-up/pull-down.

Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.

Description

SS, unless otherwise stated.

PIC12F635/PIC16F636/639

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, reg ister locat ions 4 0h throug h 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit.

TABLE 2-1: BANK SELECTION

RP0 RP1 Bank

000 101 012 113

FIGURE 2-1: PROGRAM MEM O R Y M AP AND

STAC K OF THE PIC12F635

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Access 0-3FFh

0000h

0004h 0005h

Memory

03FFh 0400h

1FFFh

FIGURE 2-2: PROGRAM MEMORY MAP AND

ST AC K OF T HE PIC16F636/639

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

Access 0-7FFh

0000h

0004h 0005h

07FFh 0800h

1FFFh

PIC12F635/PIC16F636/639

2.2.1 GENERAL PURPOSE REGISTER

The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select R egister, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM.

The special re gisters can be classifi ed into two sets: core and peripheral. The Special Function Registers associated with the “c ore” are des cribed in this sect ion. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

PIC12F635/PIC16F636/639

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h STATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

GPIO 05h TRISIO 85h 105h 185h

06h 86h 106h 186h 07h 87h 107h 187h 08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h CRCON 110h

11h 91h 12h 92h 13h 93h 14h LVDCON 94h 15h WPUDA 95h 115h 195h 16h IOCA 96h 116h 196h 17h WDA 97h 117h 197h

WDTCON 18h 98h 118h 198h

CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah

1Bh EEADR 9Bh 11Bh 19Bh 1Ch EECON1 9Ch 11Ch 19Ch 1Dh EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h

Address

(1)

80h

File

Accesses

00h-0Bh

File

Address

100h

Accesses

80h-8Bh

10Ch 18Ch

(2)

CRDAT0 CRDAT1 CRDAT2 CRDAT3

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

119h 199h

(1)

9Dh 11Dh 19Dh

A0h 120h 1A0h

File

Address

180h

190h

3Fh

General Purpose Register 64 Bytes

40h

EFh 16Fh 1EFh

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

F0h

Accesses

70h-7Fh

170h

Accesses

Bank 0

1F0h

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> are K

“K

EELOQ

Encoder License Agreement ” regarding imp lemen tat ion of the mo dule and access to relate d

registers. The “K

EELOQ

located at www.microchip.co m/K

hardware peripheral related registers and require the execution of the

Encoder License Agree ment” may be accesse d through the Microc hip web site

EELOQ or by contacting your local Microchip Sales Representative.

PIC12F635/PIC16F636/639

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr.

(1)

00h Indirect addr.

TMR0 01h OPTION_REG 81h 101h 181h

PCL 02h PCL 82h 102h 182h

STATUS 03h STATUS 83h 103h 183h

FSR 04h FSR 84h 104h 184h

PORTA 05h TRISA 85h 105h 185h

06h 86h 106h 186h

PORTC 07h TRISC 87h 107h 187h

08h 88h 108h 188h

09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah 10Ah 18Ah INTCON 0Bh INTCON 8Bh 10Bh 18Bh

PIR1 0Ch PIE1 8Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh TMR1H 0Fh OSCCON 8Fh T1CON 10h OSCTUNE 90h CRCON 110h 190h

11h 91h

12h 92h

13h 93h

14h LVDCON 94h

15h WPUDA 95h 115h 195h

16h IOCA 96h 116h 196h

17h WDA 97h 117h 197h

WDTCON 18h 98h 118h 198h

CMCON0 19h VRCON 99h 119h 199h CMCON1 1Ah EEDAT 9Ah

1Bh EEADR 9Bh 11Bh 19Bh

1Ch EECON1 9Ch 11Ch 19Ch

1Dh

EECON2 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h

General

Purpose

General

Purpose

32 Bytes

Accesses

7Fh FFh 17Fh 1FFh

70h-7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> are K

EELOQ hardware peripheral related registers and require the execution of the “KEELOQ

Encoder License Agreem ent” regarding im plement ation of the modu le and access to related registe rs. Th “KEELOQ® Encoder License Agreement” may be accessed through the Microchip web site located a www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.

Address

(1)

80h

File

Accesses

00h-0Bh

File

Address

100h

Accesses

80h-8Bh

10Ch 18Ch

10Eh 18Eh 10Fh 18Fh

(2)

CRDAT0 CRDAT1 CRDAT2 CRDAT3

111h 191h

(2)

112h 192h

(2)

113h 193h

(2)

114h 194h

11Ah 19Ah

(1)

9Dh 11Dh 19Dh

A0h

120h 1A0h

BFh C0h

EFh 16Fh 1EFh F0h

Accesses

70h-7Fh

170h

Accesses

Bank 0

File

Address

180h

1F0h

PIC12F635/PIC16F636/639

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h GPIO 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

PD ZDCC0001 1xxx 000q quuu

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xx00 --uu uu00

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

EEIF LVDIF CRIF —C1IFOSFIF—TMR1IF000- 00-0 000- 00-0

TMR1CS TMR1ON 0000 0000 uuuu uuuu

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 —C1OUT— C1INV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 — — — — — — T1GSS CMSYNC ---- --10 ---- --10

shaded = unimplemented

Reset and Watchdog Timer Reset during normal operation.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(2)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS IRP RP1 RP0 TO 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISIO 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON2 EEPROM Cont rol Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: GP3 pull-up is enabled when pin is configured as MCLR 3: MCLR

again if the mismatch exists.

(not a physical register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

—C1IEOSFIE—TMR1IE000- 00-0 000- 00-0

— — ULPWUE SBODEN WUR —PORBOD --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 O STS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — WDA5 WDA4 — WDA2WDA1WDA0--11 -111 --11 -111

—VRR—VR3VR2VR1VR00-0- 0000 0-0- 0000

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

— — — — WRERR WRE N WR RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(3)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS IRP RP 1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuxx 05h PORTA 06h — Unimplemented — — 07h PORTC 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0Ch PIR1 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON 19h CMCON0 C2OUT C1OUT 1Ah CMCON1 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: MCLR

(not a physical register)

PD ZDCC0001 1xxx 000q quuu

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 --uu uu00

— — R C5 RC4 RC3 RC2 RC1 RC0 --xx xx00 --uu uu00

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

EEIF LVDIF CRIF C2IF C1IF OSFIF —TMR1IF0000 00-0 0000 00-0

TMR1CS TMR1ON 0000 0000 uuuu uuuu

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

— — — — — — T1GSS C2SYNC ---- --10 ---- --10

shaded = unimplemented

Reset and Watchdog Timer Reset during normal operation.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

Val ue on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(2)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-5: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory

81h OPTION_REG RAPU 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS IRP RP1 RP0 TO 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA 86h — Unimplemented — — 87h TRISC 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 8Ch PIE1 EEIE LVDIE CRIE C2IE C1IE OSFIE 8Dh — Unimplemented — —

8Eh PCON 8Fh OSCCON 90h OSCTUNE 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h LVDCON 95h WPUDA 96h IOCA 97h WDA 9Bh — Unimplemented — — 99h VRCON VREN 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---9Eh — Unimplemented — — 9Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

(2)

shaded = unimplemented

2: RA3 pull-up is enabled when pin is configured as MCLR 3: MCLR

again if the mismatch exists.

(not a physical register)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000

—TMR1IE0000 00-0 0000 00-0

— — ULPWUE SBODEN WUR —PORBOD --01 q-qq --0u u-uu — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

(2)

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

— — — — WRERR WREN WR RD ---- x000 ---- q000

Reset and Watchdog Timer Res et during normal operation.

in the Configuration Word register.

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

Value on

POR/BOD/

WUR

xxxx xxxx xxxx xxxx

(3)

0000 0000 0000 0000

Value on

all other

Resets

(1)

PIC12F635/PIC16F636/639

TABLE 2-6: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2 10Ch — Unim plemented — — 10Dh — Unim plemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — —

110h CRCON GO/DONE 111h CRDAT0 112h CRDAT1 113h CRDAT2 114h CRDAT3 115h — Unimplemented — — 116h — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

Note 1: Other (non Power-up) Resets include MCLR

2: CRDAT<3:0> are KEELOQ® hardware peri ph era l rel ate d reg iste rs and requ ir e the ex ec utio n of the “KEELOQ Encoder Lice nse Agre emen t”

(2)

Cryptographic Data Register 0 0000 0000 0000 0000

(2)

Cryptographic Data Register 1 0000 0000 0000 0000

(2)

Cryptographic Data Register 2 0000 0000 0000 0000

(2)

Cryptographic Data Register 3 0000 0000 0000 0000

shaded = unimplemented

regarding implementation of the module and access to related registers. The “K through the Microchip web site located at www.microchip.com/K

ENC/DEC — — — — CRREG1 CRR EG0 00-- --00 00-- --00

Reset and Watchdog Timer Reset during normal operation.

EELOQ Encoder License Agreement” may be a ccessed

EELOQ or by contacting your local Microchip Sales Representative.

Value on

POR/BOD/

WUR

Value on all other

Resets

(1)

PIC12F635/PIC16F636/639

2.2.2.1 Status Register

The Status register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM) The Status register can be the destination for any

instruction, like any other register . If the S tatus register is the destination for an instruction that affects the Z, D C or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO Therefore, the result of an instruction with the Status register as destination may be different than intended.

and PD bits are not writable.

For example, CLRF STATUS, w ill c lear the upper three bits and set the Z bit. Thi s leaves the Status regis ter as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see Section 13.0 “Instruction Set Summary”.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indire ct addressing)

1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh)

Each bank is 128 bytes.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/B

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

orrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

For Borrow, the polarity is reversed.

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

PD ZDCC

Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.2 Option Register

The Option register is a readable and writable register which contains various control bits to configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

•TMR0

• Weak pull-up/pull-downs on PORTA

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU

bit 7 bit 0

INTEDG T0CS T0SE PSA PS2 PS1 PS0

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by setting the PSA bit to ‘1’ (OPTION_REG<3>). See Section 5.4 “Prescaler”.

bit 7 RAPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: PORTA Pull-up/Pull-down Enable bit

1 = PORTA pull-ups/pull-downs are disabled 0 = PORTA pull-ups/pull-downs are enabled by individual port latch values

1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin

1 = Transition on RA 2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit V alue TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register which co nta ins th e vari ous e nable and fl ag bit s for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regard less of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensu re the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE RAIE

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit

1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 regis ter has over flowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interru pt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state

(2)

(3)

(1)

T0IF

(2)

INTF RAIF

(3)

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing the T0IF bit.

3: MCLR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

and WDT Reset do not af fect the prev ious va lue dat a latc h. The R AIF bit w ill

be cleared upon Reset but will set again if the mismatch exists.

PIC12F635/PIC16F636/639

2.2.2.4 PIE1 Register

The PIE1 register contai ns th e in terru pt enable bits, as shown in Register 2-4.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIE LVDIE CRIE C2IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt

bit 6 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enables the LVD interrupt 0 = Disables the LVD interrupt

bit 5 CRIE: Cryptographic Interrupt Enable bit

1 = Enables the cryptographic interrupt 0 = Disables the cryptographic interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Interrupt Enable bit

1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

(1)

C1IE OSFIE —TMR1IE

Note 1: PIC16F636/639 only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

EEIF LVDIF CRIF C2IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started

bit 6 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = The supply voltage has crossed selected LVD voltage (must be cleared in software) 0 = The supply voltage has not crossed selected LVD voltage

bit 5 CRIF: Cryptographic Interrupt Flag bit

1 = The Cryptographic module has completed an operation (must be cleared in software) 0 = The Cryptographic module has not completed an operation or is Idle

bit 4 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed

bit 3 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed INTOSC (must be cleared in software) 0 = System clock operating

bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: Timer1 Interrupt Flag bit

1 = Timer1 rolled ov er (must be cleared in software) 0 = Timer1 has not rolled over

Note: Interrupt flag bits are set when an interrupt

condition occurs, regar dless of the st ate of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

(1)

C1IF OSFIF —TMR1IF

Note 1: PIC16F636/639 only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.2.2.6 PCON Register

The Power Control (PCON) register (see Table 12-3) contains flag bit s to differentiate between a:

• Power-on Reset (POR

• Wake-up Reset (WUR)

• Brown-out Detect (BOD

• Watchdog Timer Reset (WDT)

• External MCLR Reset

)

The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD

The PCON register bits are shown in Register 2-6.

U-0 U-0 R/W-0 R/W-1 R/W-x U-0 R/W-0 R/W-x

— — ULPWUE SBODEN

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled

bit 4 SBODEN: Software BOD Enable bit

1 = BOD enabled 0 = BOD disabled

bit 3 WUR

bit 2 Unimplemented: Read as ‘0’ bit 1 POR

bit 0 BOD

: Wake-up Reset Status bit

1 = No Wake-up Reset occurred 0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Detect Status bit

1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

(1)

WUR —PORBOD

Note 1: BODEN<1:0> = 01 in the Configuration Word register for SBODEN to control the

Brown-out Detect module.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

PCLATH

Instruction with

PCL as

Destination

ALU Result

GOTO, CALL

Opcode<10:0>

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556).

2.3.2 STACK

The PIC12F635/PIC16F636/639 family has an 8level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the S ta ck Pointer i s not rea dable or writa ble. The PC is PUSHed onto the stack when a CALL instruction is execute d or an interrupt ca uses a branc h. The stack is POP ed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a P USH or POP operation.

The stack operat es as a circular buf fer . This means th at after the stack has been PUSHed eight times, the ninth push overwrites the va lue tha t was s tored fro m the first push. The tenth pus h ov erwr i tes the se co nd push (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the exec ution of the CALL, RETURN, RETLW and RETFIE instru ction s or the vectoring to an interrupt address.

PIC12F635/PIC16F636/639

2.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physi cal register. Addres sing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be

A simple program to clear RAM lo catio n 20h-2Fh usin g indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;INC POINTER BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (STATUS<7>), as shown in Figure 2-6.

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

Indirect A ddressingDirect Addressing

From Opcode

RP1 RP0

Bank Select Location Select

00h

00 01 10 11

IRP File Select Register

Bank Select

180h

Location Select

Data Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Note: For memory map det ail, see Figure2-2.

1FFh

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

3.0 CLOCK SOURCES

3.1 Overview

The PIC12F635/PIC16F636/639 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications, while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC12F635/PIC16F636/639 clock sources.

Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In add ition, the system clock source can be configured from one of two in ternal oscillators, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external

or internal via software.

• Two-Speed Clock Start-up mode, which

minimizes latency between external oscillator start-up and code execu t io n.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.

The PIC12F635/PIC16F636/639 can be configured in one of eight clock modes.

1. EC – External clock with I/O on RA4.

2. LP – Low gain crystal or Ceramic Resonator Oscillator mode.

3. XT – Medium gain c rysta l or Ce ramic Resonat or Oscillator mode.

4. HS – High gain crystal or Ceramic Resonator mode.

5. RC – External Resistor-Capacitor (RC) with

OSC/4 out put on RA4.

6. RCIO – External Resistor-Capacitor (RC) with I/O on RA4.

7. INTOSC – Internal oscillator with F

OSC/4 output

on RA4 and I/O on RA5.

8. INTOSCIO – Internal oscillator with I/O on RA4 and RA5.

Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 12.0 “Special Features of the CPU”). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator . The LFINTOSC is a low-frequency uncalibrated oscillator.

FIGURE 3-1: PIC12F635/PIC16F636 /639 CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

External Oscillator

OSC2

Sleep

OSC1

IRCF<2:0>

(OSCCON<6:4>)

8 MHz

Internal Oscillator

HFINTOSC

LFINTOSC

Note 1: HFINTOSC = High-Frequency Calibrated Internal Oscillator.

2: LFINTOSC = Low-Frequency Internal Oscillator is not calibrated.

(1)

8 MHz

(2)

31 kHz

Postscaler

4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

31 kHz

111

110

101

100

011

010

001

000

LP, XT, HS, RC, RCIO, EC

MUX

(Configuration Word)

SCS

(OSCCON<0>)

MUX

(CPU and Peripherals)

Power-up Timer (PWRT) Watchdog Time r (WDT) Fail-Safe Clock Monitor (FSCM)

System Clock

PIC12F635/PIC16F636/639

3.2 Clock Source Modes

Clock source modes can be classified as external or internal.

External cloc k modes rely on exter nal circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal re sonators or c eramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC mode) circuits.

Internal clock sources are contained internally within PIC12F635/PIC16F636 /63 9. The devic e has two in ternal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between extern al or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 “Clock Switching”).

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER (OST)

If the PIC12F635/PIC16F636/639 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from the OSC1 pin following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC12F635/ PIC16F636/639.

When switching between clock sources, a delay is required to allow the new clock to stabilize. Table 3-1 shows oscillator delay examples.

In order to minimize latency between external oscillator start-up and code execution, the T wo-Speed Clock S tartup mode can be selected (see Section 3.6 “T wo-Speed

Clock Start-up Mode”).

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay

Sleep/POR

LFINTOSC (31 kHz) EC, RC DC – 20 MHz

Sleep/POR LP, XT, HS 31 kHz-20 MHz 1024 Clock Cycles (OST)

LFINTOSC (31 kHz) HFINTOSC 125 kHz-8 MHz 1 μs (approx.)

LFINTOSC

HFINTOSC

31 kHz

125 kHz-8 MHz

5 μs-10 μs (approx.)

CPU Start-upSleep/POR EC, RC DC – 20 MHz

PIC12F635/PIC16F636/639

3.3.2 EC MODE

The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the RA5 pin is available for general purpose I/ O. Figure 3-2 shows the pin connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F635/PIC16F636/639 design is full y static, stoppi ng the extern al clock input will have the ef fect of halting th e device while leaving all data intact. Upon restarting the external clock, the device will resum e ope ration as if no ti me ha d elap se d.

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from Ext. System

RA4

OSC1/CLKIN

PIC12F635/PIC16F636/639

I/O (OSC2)

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. T his mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals.

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medi um of the three modes. This mode is better suited to drive resonators with a medium drive level specification, for example, lowfrequency AT-cut quartz crystal resonators.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is better suited for resonat ors that requ ire a hig h drive setting, for example, high-frequency AT-cut quartz crystal resonators or ceramic resonators.

Figure 3-3 and Figure3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR HS MODE)

PIC12F635/PIC16F636/639

OSC1

Quartz Crystal

OSC2

(1)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of R

mode selected (typically between 2 MΩ to 10 MΩ).

(2)

F varies with the Oscillator

Sleep

To Internal

Logic

Note 1: Quartz crystal characteristics vary

according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2: Always verify oscillator performance over

DD and temperature range that is

the V expected for the application.

FIGURE 3-4: CERAMIC RESONATOR

OPERATION (XT OR HS MODE)

PIC12F635/PIC16F636/639

OSC1

(3)

OSC2

(1)

Ceramic Resonator

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of R

mode selected (typically between 2 MΩ to 10 MΩ).

3: An additional parallel feedback resistor (R

may be required for proper ceramic resonator operation (typical value 1 MΩ).

(2)

F varies with the Oscillator

To Internal

Logic

Sleep

PIC12F635/PIC16F636/639

3.3.4 EXTERNAL RC MODES

The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes, RC and RCIO.

In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the RC mode connections.

FIGURE 3-5: RC MODE

VDD

REXT

OSC1

CEXT

VSS

OSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

PIC12F635/PIC16F636/639

OSC2/CLKOUT

EXT > 20 pF

Internal

Clock

In RCIO mode, the RC circuit is connecte d to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of PORTA (RA4). Figure 3-6 shows the RCIO mode connections.

FIGURE 3-6: RCIO MODE

VDD

REXT

OSC1

CEXT

VSS

RA4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

PIC12F635/PIC16F636/639

I/O (OSC2)

EXT > 20 pF

The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT)

values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal threshold voltage. Furthermore, the difference in le ad fram e c apacitance be twee n package types will also a ffe ct the oscil lation fre quency o r for low

EXT values. The user also needs to take into account

C variation due to tolerance of external RC components used.

Internal

Clock

3.4 Internal Clock Modes

The PIC12F635/PIC16F6 36/639 has two i ndepen dent, internal oscillators that can be configured or selected as the system clock source.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of t he HFINT OSC can be user adjusted ±12% via software using the OSCTUNE register (Reg ister3-1).

2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.

The system cloc k speed ca n be selec ted via sof tware using the Internal Oscillator Frequency Select (IRCF) bits.

The system clock ca n be se lec ted betw ee n external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 “Clock Switching”).

3.4.1 LFINTOSC AND LFINTOSCIO

MODES

The LFINTOSC and LFINTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection (FOSC) bits in the Configuration Word register (Register 12-1).

In LFINTOSC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be us e d t o provi de a clock for external circuitry, synchronization, calibration, test or other application require me nt s .

In LFINTOSCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.

3.4.2 HFINTOSC

The High-Frequency Int ernal Oscillato r (HFINT OSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately ±12% via software using the OSCTU NE register (Register 3-1).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”).

The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF ≠ 000) as the system clock s ource (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF ≠ 000).

The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.

PIC12F635/PIC16F636/639

3.4.2.1 OSCTUNE Register

The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register3-1).

The OSCTUNE register has a tuning range of approximately ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonici ty and frequency step cannot be specified.

When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequency 01110 =

•

00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

3.4.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The LFINTOSC is also the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock sourc e (SCS = 1), or when any of the following are enabled:

• Two-Speed Start-up (IESO = 1 and IRCF = 000)

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit (OSCCON<1>)

indicates whether the LFINTOSC is stable or not.

3.4.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

•31 kHz Note: Following any Reset, the IR CF bits are set

to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.

3.4.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING

When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case , there is a 10μs delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows:

1. IRCF bits are modified.

2. If the new clock is sh ut down, a 10 μs clock start-

up delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits fo r a ris ing edge in the new clock.

5. CLKOUT is now connected with the new clock.

HTS/LTS bits are updated as required.

6. Clock switch is complete.

If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer.

Note: Care must be taken to ensure a valid

voltage or frequency selection is chosen. See voltage vs. frequency diagrams (Figure 15-2, Figure 15-3 and Figure 15-4) for more detail.

PIC12F635/PIC16F636/639

3.5 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit.

3.5.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals.

When SCS = 0, the s y ste m cl oc k so urc e i s determined by configuration of the FOSC<2:0> bits in the Configuration Word register (Register12-1).

When SCS = 1, the system clock sourc e is c hos en by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.

3.5.2 OSCILLAT OR START-UP TIME-OUT STATUS BIT

The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.

3.6 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy us e of the Sleep mode, Two-Speed Star t-up will remove the extern al oscillator start -up time from the time spent awake and can reduce the overall power consumption of the device.

This mode allows the application to wake-up from Sleep, perform a f ew inst ructio ns using th e I NTO SC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.

When the PIC12F635/PIC 16F636/639 is c onfigured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 “Oscillator Start- up Timer (OST)”). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit ( OSCC O N<3> ) is se t, pro gram execution switches to the external oscillator.

3.6.1 TWO-SPEED START-UP MODE CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO = 1 (CONFIG<10>) Internal/External

Switchover bit.

•SCS = 0.

• FOSC configured for LP, XT or HS mode.

• Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, afte r

PWRT has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then TwoSpeed Start-up is disabled. This is beca use the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.

3.6.2 TWO-SPEED START-UP SEQUENCE

The Two-Speed Start-up sequence is listed below.

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF bits (OSCCON<6:4>).

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next fal ling edg e

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS

Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F635/PIC16F636/639 is running from the external clock source, as defined by the FOSC bits in the Configuration Word register (Register 12-1) or the internal oscillator.

PIC12F635/PIC16F636/639

FIGURE 3-7: TWO-SPEED START-UP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

INTOSC

TOST

OSC1

0 1 1022 1023

OSC2

Program Counter

PC PC + 1 PC + 2

System Clock

3.7 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.

FIGURE 3-8: FSCM BLOCK DIAGRAM

Clock Monitor

Latch (CM)

Primary

Clock

LFINTOSC

Oscillator

31 kHz

(~32 μs)

÷ 64

488 Hz

(~2 ms)

The FSCM function is enabled by setting the FCMEN bit in the Configu ration W ord regis ter (Regist er 12-1). It is applicable to all external clock options (LP, XT, HS, EC, RC or I/O modes).

In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1< 2>) and g enerate an oscil lator fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscill ator unless the external cloc k recovers and the Fail-Safe condition is exited.

(edge-triggered)

Clock

Failure

Detected

The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit.

The FSCM sample clock is generated by dividing the LFINTOSC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram.

On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a fal lin g e dg e o f th e s am pl e clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled, as reflected by the IRCF.

Note 1: Two-Speed Start-up is automatically

enabled when the Fail-Safe Clock Monitor mode is enabled.

2: Primary clocks with a frequency of

≤ ~488 Hz will be considered failed by FSCM. A slow starting oscillator can cause an FCSM interrupt.

PIC12F635/PIC16F636/639

3.7.1 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F635/ PIC16F636/639 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.

FIGURE 3-9: FSCM TIMING DIAGRAM

Sample Clock

System

Clock

Output

CM Output

(Q)

OSCFIF

CM Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative

frequencies in this example have been chosen for clarity.

Oscillator Failure

Failure

Detected

CM Test CM Test

3.7.2 RES E T OR WAKE-UP FR OM SLEE P

The FSCM is design ed to detect osc illator failu re at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events.

For LP, XT or HS mode, the external oscillator may require a start-up time considerably longer than the FSCM sample cloc k time or a fa lse clock failure may b e detected (see Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stab le (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.

Note: Due to the wide range of oscillator st art-u p

times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the u se r sho uld check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.

PIC12F635/PIC16F636/639

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0

— IRCF2 IRCF1 IRCF0 OSTS

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Nominal Internal Oscillator Frequency Select bits

000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz

bit 3 OSTS: Oscillator Start-up Time-out Status bit

(1)

1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC)

bit 2 HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit

1 =HFINTOSC is stable 0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

1 = LFINTOSC is stable 0 = LFINTOSC is not stable

bit 0 SCS: System Clock Select bit

1 = Internal oscillator is used for system clock 0 = Clock source def ined by FOSC<2:0>

(1)

HTS LTS SCS

Note 1: Bit resets to ‘0’ with T wo-Spee d S tart-up and LP, XT or HS selected as the Osc illator

mode or Fail-Safe mode is enabled.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Address Na m e B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Ch PIR1 8Ch PIE1 8Fh OSCCON 90h OSCTUNE

(1)

2007h

Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: S ee Register 12-1 for operation of all Configuration Word register bits.

CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

EEIF LVDIF CRIF C2IF C1IF OSFIF — TMR1IF 0000 00-0 0000 00-0 EEIE LVDIE CRIE C2IE C1IE OSFIE — TMR1IE 0000 00-0 0000 00-0

— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

Value on:

POR, BOD,

WUR

Value on

all other

Resets

PIC12F635/PIC16F636/639

4.0 I/O PORTS

There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be a vailable a s general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

4.1 PORTA and the TRISA Registers

PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and it s TRIS bit will always read as ‘1’. Example4-1 shows how to initialize PORT A.

Reading the PORTA register (Register 4-3) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified a nd then written to the port data latch. RA3 reads ‘0’ when MCLRE = 1.

The TRISA register controls the direction of the PORT A pins, even when they are being us ed as analog inputs. The user must ensure the bits in the TRISA register are maint ai ned set when using the m as an alog inputs. I/O pins configured as analog inputs always read ‘0’.

4.2 Additional Pin Functions

Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/ pull-down option. RA0 has an Ultra Low-Power Wakeup option. The next three sections describe these functions.

4.2.1 WEAK PULL-UP/PULL-DOWN

Each of th e PORTA pins, excep t RA3, has a n inte rnal weak pull-up and pull-down . The WDA bits select either a pull-up or pull-down for an individual port bit. Individual control bits can turn on the pull-up or pulldown. These pull-ups/pull-downs are automatically turned off when the port pin is configured as an output, as an alternate function or on a Power-on Reset, setting the RAPU up on RA3 is enabl ed whe n con fig ured a s MCLR Configuration Word register and disabled when high voltage is detected, to reduce current consumption through RA3, while in Programming mode.

Note: PORTA = GPIO

bit (OPTION_REG <7>). A we ak pul l-

in the

TRISA = TRISIO

Note: The CMCON0 (19h) register must be

initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

EXAMPLE 4-1: INITIALIZING PORTA

BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; CLRF PORTA ;Init PORTA MOVLW 07h ;Set RA<2:0> to MOVWF CMCON0 ;digital I/O BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW 0Ch ;Set RA<3:2> as inputs MOVWF TRISA ;and set RA<5:4,1:0>

BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ;

;as outputs

PIC12F635/PIC16F636/639

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WDA5 WDA4 — WDA2 WDA1 WDA0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WDA<5:4>: Pull-up/Pull-down Selection bits

1 = Pull-up selected 0 = Pull-down selected

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WDA<2:0>: Pull-up/Pull-down Selection bits

1 = Pull-up selected 0 = Pull-down selected

Note 1: The weak pull-up/pull-down device is enabled only when the global RAPU

enabled, the pin is in Input mode (TRIS = 1), the individual WDA bit is enabled (WDA = 1) and the pin is not configured as an analog input or clock function.

2: RA3 pull-up is enabled when the pin is configured as MCLR

Word register and the device is not in Programming mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

in the Configuration

bit is

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPUDA5

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits

1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits

1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled

(3)

WPUDA4

(3)

— WPUDA2 WPUDA1 WPUDA0

(3)

Note 1: The weak pull-up/pull-down direction device is enabled only when the global RAPU

is enabled, the pin is in Input mode (TRIS = 1), the individual WPUDA bit is enabled (WPUDA = 1) and the pi n is not configur e d a s an an al og i np ut or cl oc k fu nc ti on .

2: RA3 pull-up is enabled when the pin is configured as MCLR

Word register and the device is not in Programming mode.

3: WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled;

otherwise, the bit can not be written and reads as ‘1’. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

in the Configuration

bit

PIC12F635/PIC16F636/639

U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-0 R/W-0

— — RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: RA<5:0>: PORTA I/O pins

1 = Port pin is > V 0 = Port pin is < VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISA5

bit 7 bit 0

(2)

TRISA4

(2)

TRISA3

(1)

TRISA2 TRISA1 TRISA0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISA<5:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1,2)

PIC12F635/PIC16F636/639

4.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as an interrupt-on-chang e pin. Control bit s, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the values are compared with the old value la tched on the last rea d of PORTA. The ‘mismatch’ outputs of the last read are OR’d together to set t he PORT A C hange Interrupt Flag bit (RAIF) in the INTCON r egister (Register 2 -3).

This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of PORTA. This will end the

mismatch condition, then

b) Clear the flag bit RAIF.

A mismatch c ond it i on wi ll cont i n ue to s et f lag bi t RA IF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After these Resets, the RAIF flag will continue to be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when the read operation is bei ng executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.

nor BOD

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— —IOCA5

bit 7 bit 0

(2)

IOCA4

(2)

IOCA3

(3)

IOCA2 IOCA1 IOCA0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bits

1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be

recognized.

2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes. 3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

(2,3)

PIC12F635/PIC16F636/639

4.2.3 ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on RA0.

To use this feature, the RA0 pin is configured to output ‘1’ to charge the capacitor, interrupt-on-change for RA0 is enabled and RA0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on RA0 drops below V the device to wake-up. Depending on the state of the GIE bit (INTCON<7>), the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.2

“Interrupt-on-change” and Section 12.9.3 “PORTA Interrupt” for more information.

This feature provides a low power technique for periodically wakin g up the device from Sleep. Th e timeout is dependent on the disch arge time of the RC circuit on RA0. See Example 4-2 for initializing the Ultra Low Power Wake-up module.

The series resistor provides overcurrent protection for the RA0 pin and can allow for software calibration of the timeout (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor.

IL, an interrupt will be generated which will cause

Note: For more information, refer to the

Application Note AN879, “Using the

Microchip Ultra Low-Power Wake-up Module” (DS00879).

EXAMPLE 4-2: ULTRA LOW-POWER

WAKE-UP INITIALIZATION

BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; BSF PORTA,0 ;Set RA0 data latch MOVLW H’7’ ;Turn off MOVWF CMCON0 ; comparators BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; BCF TRISA,0 ;Output high to CALL CapDelay ; charge capacitor BSF PCON,ULPWUE ;Enable ULP Wake-up BSF IOCA,0 ;Select RA0 IOC BSF TRISA,0 ;RA0 to input MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON ; and clear flag SLEEP ;Wait for IOC

PIC12F635/PIC16F636/639

4.2.4 PIN DESCRIPTIONS AND DIAGRAMS

Each PORT A pin is multiplexed with other functio ns. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator , refe r to the appropriate section in this data sheet.

FIGURE 4-1: BLOCK DIAGRAM OF RA0

Analog

(1)

RAPU

Data Bus

WPUDA

WDA

Input Mode

4.2.4.1 RA0/C1IN+/ICSPDAT/ULPWU

Figure 4-2 shows the diagra m for this pi n. The RA 0 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Programming™ data

• an analog input for the Ultra Low-Power Wake-up

VDD

Weak

VDD

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

Change

–

Analog

Input Mode

RD PORTA

(1)

ULPWUE

IULP

I/O pin

VSS

Note 1: Comparator mode determines Analog Input mode.

PIC12F635/PIC16F636/639

4.2.4.2 RA1/C1IN-/VREF/ICSPCLK

Figure 4-2 shows the diagr am for thi s pin. Th e RA1 pi n is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Programming clock

FIGURE 4-2: BLOCK DIAGRAM OF RA1

Analog

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

To Comparator

Input Mode

(1)

RAPU

Analog

Input Mode

RD PORTA

VDD

Weak

VSS

VDD

I/O pin

VSS

(1)

4.2.4.3 RA2/T0CKI/INT/C1OUT

Figure 4-3 shows the diagra m for this pi n. The RA 2 pin is configurable to function as one of the following:

• a general purpose I/O

• the clock input for TMR0

• an external edge-triggered interrupt

• a digital output from the comparator

FIGURE 4-3: BLOCK DIAGRAM OF RA2

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

RAPU

C1OUT Enable

C1OUT

RD PORTA

VDD

Weak

VSS

VDD

I/O pin

VSS

Note 1: Comparator mode determines Analog Input mode.

To TMR0 To INT

PIC12F635/PIC16F636/639

4.2.4.4 RA3/MCLR/VPP

Figure 4-4 shows the diagr am for thi s pin. Th e RA3 pin is configurable to function as one of the following:

• a general purpose input

• as Master Clear Reset with weak pull-up

• a high-voltage detect for Program mode entry

FIGURE 4-4: BLOCK DIAGRAM OF RA3

VDD

Data Bus

TRISA

PORTA

IOCA

Program

Mode

VSS

MCLRE

Reset

HV Detect

MCLRE

RD PORTA

Weak

Input pin

Interrupt-on-

change

WURE Sleep

PIC12F635/PIC16F636/639

4.2.4.5 RA4/T1G/OSC2/CLKOUT

Figure 4-5 shows the diagr am for thi s pin. Th e RA4 pi n is configurable to function as one of the following:

• a general purpose I/O

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 4-5: BLOCK DIAGRAM OF RA4

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

T1G To T imer1

OSC1

RAPU

Fosc/4

CLKOUT

INTOSC/

RC/EC

CLKOUT

(1)

CLK

Modes

Oscillator

Circuit

CLKOUT

Enable

(2)

Enable

XTAL

RD PORTA

VDD

Weak

VSS

VDD

I/O pi

VSS

4.2.4.6 RA5/T1CKI/OSC1/CLKIN

Figure 4-6 shows the diagra m for this pi n. The RA 5 pin is configurable to function as one of the following:

• a general purpose I/O

•a TMR1 clock input

• a crystal/resona tor connec tio n

• a clock input

FIGURE 4-6: BLOCK DIAGRAM OF RA5

Data Bus

WPUDA

WDA

PORTA

TRISA

PORTA

IOCA

Interrupt-on-

change

T1G T o Timer1

OSC2

(1)

CLK

RAPU

Oscillator

Circuit

INTOSC

Mode

RD PORTA

Modes

VDD

Weak

VSS

VDD

I/O pin

VSS

(2)

Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and

CLKOUT Enable.

2: With CLKOUT option.

Note 1: Oscillator modes are XT, HS, LP and LPTMR1.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

PIC12F635/PIC16F636/639

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Add

05h PORTA 0Bh/

8Bh 0Eh T MR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 1Ah CMCON1 19h CMCON0 81h OPTION_REG RAPU 85h TRISA 95h WPUDA 96h IOCA 97h WDA

Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 --uu uu00

INTCON GIE

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

— — — — — —T1GSSC2SYNC ---- --10 ---- --10

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 — — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 — — WDA5 WDA4 — WDA2 WDA1 WDA0 --11 -111 --11 -111

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Value on:

POR, BOD,

WUR

Value on

all other

Resets

PIC12F635/PIC16F636/639

4.3 PORTC

PORTC is a general purpose I/O port consisting of 6 bidirectional pins . The pins can be con figured for e ither digital I/O or analog input to comparator. For specific information about individual functions, refer to the appropriate section in this data sheet.

Note: The CMCON0 (19h) registe r must be ini-

tialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

EXAMPLE 4-3: INITIALIZING PORTC

BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; CLRF PORTC ;Init PORTC MOVLW 07h ;Set RC<4,1:0> to MOVWF CMCON0 ;digital I/O BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 MOVLW 0Ch ;Set RC<3:2> as inputs MOVWF TRISC ;and set RC<5:4,1:0>

;as outputs BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ;

4.3.1 RC0/C2IN+

The RC0 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

4.3.2 RC1/C2IN-

The RC1 pin is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

FIGURE 4-7: BLOCK DIAGRAM OF RC0

AND RC1

Data Bus

VDD

I/O pin

VSS

PORTC

TRISC

PORTC

To Comparators

Analog Input

Mode

4.3.3 RC2

The RC2 pin is configurable to function as a general purpose I/ O.

4.3.4 RC3

The RC3 pin is configurable to function as a general purpose I/ O.

4.3.5 RC5

The RC5 pin is configurable to function as a general purpose I/ O.

FIGURE 4-8: BLOCK DIAGRAM OF

RC2, RC3 AND RC5

Data Bus

PORTC

TRISC

PORTC

VDD

I/O pin

VSS

PIC12F635/PIC16F636/639

4.3.6 RC4/C2OUT

The RC4 pin is configurable to function as one of the following:

• a general purpose I/O

• a digital output from the comparator

FIGURE 4-9: BLOCK DIAGRAM OF RC4

C2OUT Enable

C2OUT

Data Bus

PORTC

TRISC

PORTC

VDD

I/O pin

VSS

PIC12F635/PIC16F636/639

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0

— — RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: RC<5:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is > V 0 = Port pin is < VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISC<5:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

07h PORTC 19h CMCON0 87h TRISC Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx xx00 --uu uu00

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Value on:

POR, BOD,

WUR

Value on all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock Figure 5-1 is a block diagram of th e Ti mer0 module and

the prescaler shared with the WDT.

Note: Additional information on the Timer0

module is available in the “PICmicro

Range MCU Family Reference Manual”

(DS33023).

5.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written , the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Mid-

Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge.

Note: Counter mode has specific external clock

requirements. Additional information on these requirements is available in the

“PICmicro

Mid-Range MCU Family

Reference Manual” (DS33023).

5.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in softwa re by the T i mer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT

(= FOSC/4)

T0CKI

T0SE

WDTE

SWDTEN

LFINTOSC

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.

T0CS

Watchdog

Timer

PSA

16-bit

Prescaler

8-bit

Prescaler

WDTPS<3:0>

PSA

PS<2:0>

PSA

SYNC/2

Cycles

WDT

Time-out

Data Bus

TMR0

Set Flag bit T0IF

on Overflow

PIC12F635/PIC16F636/639

5.3 Using Timer0 with an External Clock

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the in ternal phase clock s, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be hi gh for a t least 2 T small RC delay of 20ns) and low for at least 2 T a small RC delay of 20 ns). Refer to the electrical specification o f th e desired device.

Note: The CMCON0 (19h) registe r must be ini-

tialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU

bit 7 bit 0

INTEDG T0CS T0SE PSA PS2 PS1 PS0

OSC (and a

OSC (and

bit 7 RAPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual values in the WPUDA register

1 = Interrupt on rising edge of RA2/T0CKI/INT/C1OUT pin 0 = Interrupt on falling edge of RA2/T0CKI/INT/C1OUT pin

1 = Transition on RA2/T0CKI/INT/C1OUT pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA2/T0CKI/INT/C1OUT pin 0 = Increment on low-to-high transition on RA2/T0CKI/INT/C1OUT pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

Note 1: A dedicated 16-bit WDT postsca ler is available for the PIC12F6 35/PIC16F636/63 9.

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

See Section 12.11 “Watchdog Timer (WDT)” for more information.

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

5.4 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as “prescaler” throughout this data sheet. The prescaler assignment is controlled in software by the control bit, PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>).

The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e .g., CLRF 1, MOVWF 1, BSF 1,

x....etc.) wil l clear t he pres caler. When ass igned t o

WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.

5.4.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 5-1 and Example 5-2) must be executed when changing the prescaler assignment from Timer0 to WDT.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0

BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and

BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW b’00101111’ ;Required if desired MOVWF OPTION_REG ; PS2:PS0 is CLRWDT ; 000 or 001

MOVLW b’00101xxx’ ;Set postscaler to MOVWF OPTION_REG ; desired WDT rate BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ;

To change prescaler from the WDT to the TMR0 module, use the se quence sh own in Examp le 5-2. This precaution must be t aken even if the WDT is disabled.

→ WDT)

; prescaler

;

EXAMPLE 5-2: CHANGING PRESCALER

(WDT

→ TIMER0)

CLRWDT ;Clear WDT and

BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW b’xxxx0xxx’ ;Select TMR0,

MOVWF OPTION_REG ; BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ;

;prescaler

;prescale, and ;clock source

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE

81h OPTION_REG 85h TRISA Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

Value on

POR, BOD,

WUR

Value on

all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

6.0 TIMER1 MODULE WITH GATE

CONTROL

The PIC12F635/PIC16F636/639 has a 16-bit timer. Figure 6-1 shows the bas ic block dia gram of the T imer1 module. Timer1 has the following features:

• 16-bit timer/counter (TMR1H:TMR1L)

The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module.

Note: Additional information on timer modu les i s

available in the “PICmicro

MCU Family Reference Manual”

(DS33023).

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input:

- Selectable gate source: T1G

or C2 output

(T1GSS)

- Selectable gate polarity (T1GINV)

• Optional LP oscillat or

FIGURE 6-1: TIMER1 ON THE PIC12F635/PIC16F636/639 BLOCK DIAGRAM

TMR1ON TMR1GE

TMR1ON

Set Flag bit TMR1IF on Overflow

TMR1H

TMR1

(1)

TMR1L

To C2 Comparator Module TMR1 Clock

TMR1GE

Synchronized

Clock Input

Mid-Range

T1GINV

Oscillator

OSC1/T1CKI

OSC2/T1G

INTOSC

No CLKOUT

T1OSCEN

Note 1: Timer1 increments on the rising edge.

2: C2OUT for PIC16F636/639, C1OUT for PIC12F635. 3: ST Buffer is low-power type when using LP oscillator, or high-speed type when using T1CKI.

(3)

F Internal Clock

OSC/4

TMR1CS

T1SYNC

Prescaler

1, 2, 4, 8

T1CKPS<1:0>

C2OUT

Sleep Input

(2)

T1GSS

Synchronize

det

PIC12F635/PIC16F636/639

6.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every

instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously .

In Counter and Timer modules, the counter/timer clock can be gated by the T imer1 gate, w hich can be selected as either the T1G

If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source.

Note: In Counter mode, a falling edge must be

pin or the Comparator 2 output.

registered by the counter prior to the first incrementing rising edge.

6.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the inte rrupt on rollo ver , you must set these bits :

• Timer1 interrupt enable bit (PIE1<0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note: The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before enabling interrupts.

6.3 Timer1 Prescaler

Timer1 has four pre scale r opti ons , all owin g 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.

6.4 Timer1 Gate

Timer1 gate source is software configurable to be the T1G

pin or the output of Comp ara t or 2. This all ows th e device to directly time external events using T1G analog events using Comparator 2. See CMCON1 (Register 7-2) for selecting the Timer1 gate source. This feature can simplify the software for many other applications.

Note: TMR1GE bit (T1CON<6>) must be set to

use either T1G gate source. See Register 7-2 for more information on selecting the Timer1 gate source.

Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it origin ates fro m the T1G Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.

or C2OUT as the Timer1

pin or

FIGURE 6-2: TIMER1 INCREMENTING EDGE

T1CKI = 1 when TMR1 Enabled

T1CKI = 0 when TMR1 Enabled

Note 1: Arrows indicate counter increments.

2: In C ounter mode, a falling edge must be registered by the counter prior to the first increm enting rising edge of

the clock.

PIC12F635/PIC16F636/639

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

bit 7 bit 0

TMR1CS TMR1ON

bit 7 T1GINV: Timer1 Gate Invert bit

1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted

bit 6 TMR1GE: Timer1 Gate Enable bit

f TMR1ON = 0:

This bit is ignored. If TMR1ON =

1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

f INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off

Else

This bit is ignored.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (F

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

OSC/4)

(1)

(2)

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G

T1GSS bit (CMCON1<1>), as a Timer1 gate source.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

pin or C2OUT, as selected by the

PIC12F635/PIC16F636/639

6.5 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, w hich will wake-up the processor. H owever , special precautions in software are needed to read/write the timer (see Section 6.5.1

“Reading and Writing Timer1 in Asynchronous Counter Mode”).

Note: The CMCON0 (19h) register must be

initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.

6.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asy nchronous cl ock will ens ure a valid read (taken care of in hardware). However, the user should keep in min d that re ading t he 16-b it time r in tw o 8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recomm ended that the us er simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementi ng. This may pro duce an unpredictable value in the timer register.

Reading the 16-bit value requires some care. Examples in the “PICmicro Reference Manual” (DS33023) show how to read and write Ti mer1 wh en it i s runni ng in Async hronou s mode.

Mid-Range MCU Fami ly

6.6 Timer1 Oscillator

A crystal oscilla tor circuit is built-in between pin s OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-p ower oscil lator rated up to 31 kHz . It will continue to run durin g Sleep. It is primarily intended for a 32 kHz crystal. Table 3-1 shows the capacitor selection for the T im er1 osc il lat or.

The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up.

TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bit s rea d a s ‘0’ an d TRISA5 and TRISA4 bits read as ‘1’.

Note: The oscillator requires a start-up and

stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.

6.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when set up in Asynchronous Counte r mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit

(INTCON<7>) is set, the devi ce w il l wake -up and jump to the Interrupt Service Routine (0004h) on an overflow . If the GIE bit is clear, executio n will contin ue with the next instruction.

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/

INTCON GIE PEIE

8Bh 0Ch PIR1 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 1Ah CMCON

1 8Ch PIE1 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

EEIF LVDIF CRIF C2IF C1IF OSFIF —TMR1IF0000 00-0 0000 00-0

— — — — — —T1GSSC2SYNC ---- --10 ---- --10

EEIE LVDIE CRIE C2IE C1IE OSFIE —TMR1IE0000 00-0 0000 00-0

T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

TMR1CS TMR1ON 0000 0000 uuuu uuuu

Value on

POR, BOD,

WUR

Value on all other

Resets

PIC12F635/PIC16F636/639

7.0 COMPARATOR MODULE

The CMCON0 register (Register 7-1) controls the comparator input and output multiplexers. A block

The comparator module contains two analog comparators. The inputs to the comparators are

diagram of the various comparator configurations is shown in Figure 7-4.

multiplexed with I /O port pins RA0 , RA1, RC0 and R C1, while the output s are multi plexed to pin s RA2 and RC4. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparators.

Note: The PIC12F635 has only 1 comparator.

The comparator on the PIC12F635 behaves like comparator 2 of the PIC16F636/639.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

C2OUT

C1OUT

bit 7 bit 0

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN0 = C2 V

IN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN0 = C2 V

IN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN0 = C1 V

IN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN0 = C1 V

IN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted 0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output inverted 0 = C1 output not inverted

bit 3 CIS: Compar ator Input Switch bit

When CM<2:0> = 1 =C1 VIN- connects to RA0

C2 V

IN- connects to RC0

0 =C1 V

IN- connects to RA1 IN- connects to RC1

C2 V

When CM<2:0> = 001:

1 =C1 VIN- connects to RA0 0 =C1 V

IN- connects to RA1

bit 2-0 CM<2:0>: Comparator Mode bits

Figure 7-4 shows the Comparator modes and CM<2:0> bit settings.

(2)

010:

C2INV

(1)

(2)

C1INV

(1)

(2)

CIS CM2 CM1 CM0

Note 1: PIC16F636/639 only. Reads as ‘0’ for PIC12F635.

2: PIC12F635 bit names are COUT and CINV.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F635/PIC16F636/639

7.1 Comparator Operation

A single comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output . When the analo g input at V than the analog input V

IN-, the output of the compara tor

is a digital low level. When the analog input at V greater than the analog input V

IN-, the output of the

comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-1 represent the uncertainty due to input offsets and response time.

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be programmed in the CMCON0 (19h) register.

The polarity of the comparator output can be inverted by setting the CxINV bits (CMCON0<5:4>). Clearing CxINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 7-1.

TABLE 7-1: OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions CINV CxOUT

IN- > VIN+ 00

IN- < VIN+ 01

V VIN- > VIN+ 11 VIN- < VIN+ 10

IN+ is less

IN+ is

FIGURE 7-1: SINGLE COMPARATOR

VIN-

IN–

VIN+

IN+

Output

utput

VIN+ VIN-

Output

–

7.2 Analog Input Connection Considerations

A simplified circuit for an analog input is shown in Figure 7-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between

SS and VDD. If the input voltage deviates from this

V range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a cap acitor or a Zener diode, should have very little leakage current.

Note 1: When reading the Port register, all pins

configured as anal og inp uts will read as a ‘0’. Pins configured as digital inputs will convert as analog inpu t s acc ord ing to th e input specification.

2: Analog levels on any pin defined as a

digital input may cau se the in put bu ffer to consume more current than is specified.

FIGURE 7-2: ANALOG INPUT MODEL

Rs < 10 kΩ

CPIN 5 pF

VT = 0.6V

T = 0.6V

ILEAKAGE ±500 nA

Vss

Legend:CPIN = Input Capacitance

T = Threshold Voltage

V I

LEAKAGE = Leakage Current at the pin due to various junctions

IC = Interconnect Resistance

S = Source Impedance

R VA = Analog Voltage

RIC

PIC12F635/PIC16F636/639

7.3 Comparator Configuration

There are eight modes of operation for the comp arators. The CMCON0 register is used to select these modes. Figure 7-3 and Figure 7-4 show the eight possible modes. The TRISA and TRISC registers control the data direction of the comparator output pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 15.0 “Electrical

Specifications”.

Note: Comparator interrupts should be disabled

during a Comparator mode change. Otherwise, a false interrupt may occur.

FIGURE 7-3: COMPARATOR I/O OPERATING MODES FOR PIC12F635

Comparator Reset (POR Default Value – Low Power) CM<2:0> = 000 CM<2:0> = 111

Comparator Off (Lowest Power)

(1)

GP1/CINGP0/CIN+

GP2/C1OUT D

A A

Off (Read as ‘0’)

GP1/CINGP0/CIN+

GP2/C1OUT D

D D

Off (Read as ‘0’)

Comparator without Output Comparator w/o Output and with Internal Reference CM<2:0> = 010 CM<2:0> = 100

GP1/CINGP0/CIN+

GP2/C1OUT D

A A

C1OUT

GP1/CINGP0/CIN+

GP2/C1OUT D

A D

From CVREF Module

C1OUT

Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output CM<2:0> = 011 CM<2:0> = 101

GP1/CINGP0/CIN+

GP2/C1OUT D

A D

From CVREF Module

C1OUT

GP1/CINGP0/CIN+

GP2/C1OUT D

CIS = 0

CIS = 1

From CVREF Module

C1OUT

Comparator with Output Multiplexed Input with Internal Reference CM<2:0> = 001 CM<2:0> = 110

GP1/CINGP0/CIN+

GP2/C1OUT D

A A

C1OUT

GP1/CINGP0/CIN+

GP2/C1OUT D

CIS = 0

CIS = 1

From CVREF Module

C1OUT

Legend: A = Analog Input, ports always read ‘0’ CIS = Comparator Input Switch (CMCON0<3>)

D = Digital Input

Note 1: Lowest power statement assures valid digital stats on GPO, GP1 and GP2.

PIC12F635/PIC16F636/639

FIGURE 7-4: COMPARATOR I/O OPERATING MODES FOR PIC16F636/639

Comparator Reset (POR Default Value) CM<2:0> = 000

RA1 RA0

A A

IN-

IN+

Off (Read as ‘0’)

Comparators Off (Lowest Power) CM<2:0> = 111

RA1 RA0

D D

IN-

IN+

(1)

Off

(Read as ‘0’)

RC1 RC0

A A

IN-

IN+

Two Independent Comparators CM<2:0> = 100

RA1 RA0

RC1 RC0

A A

IN-

IN+

IN-

IN+

Two Common Reference Comparators CM<2:0> = 011

RA1 RA0

RC1 RC0

A D

A A

IN-

IN+

IN-

IN+

(Read as ‘0’)

Off

C1OUT

C2OUT

C1OUT

C2OUT

RC1 RC0

D D

IN-

(Read as ‘0’)

IN+

Off

Four Inputs Multiplexed to Two Comparators CM<2:0> = 010

RA1 RA0

RC1 RC0

CIS = 0

CIS = 1

CIS = 0

CIS = 1

IN-

IN+

IN-

IN+

C1OUT

C2OUT

From CVREF Module

Two Common Reference Comparators with Outputs CM<2:0> = 110

RA1

RA2/C1OUT

RC1 RC0

A D

A A

IN-

IN+

IN-

IN+

C1OUT

C2OUT

One Independent Comparator CM<2:0> = 101

RA1 RA0

RC1 RC0

Legend:

D D

A A

A = Analog Input, ports always read ‘0’

IN-

IN+

IN-

IN+

D = Digital Input

Off

(Read as ‘0’)

C2OUT

RC4/C2OUT

Three Inputs Multiplexed to Two Comparators CM<2:0> = 001

RA1 RA0

RC1 RC0

CIS = 0

CIS = 1

A A

IN-

IN+

IN-

IN+

CIS = Comparator Input Switch (CMCON0<3>)

C1OUT

C2OUT

PIC12F635/PIC16F636/639

FIGURE 7-5: PIC12F635 COMPARATOR C1 OUTPUT BLOCK DIAGRAM

MULTIPLEX

Port Pins

C1SYNC

To TMR1

To C1OUT pin

C1INV

To Data Bus

RD CMCON

Set C2IF bit

Note 1: Comparator 1 output is latched on falling edge of T1 clock source.

TMR1

Clock Source

Reset

(1)

RD CMCON

FIGURE 7-6: PIC16F636/6 39 COMPARATOR C1 OUTPUT BLOCK DIAGRAM

MULTIPLEX

Port Pins

C1INV

To C1OUT pin To Data Bus

RD CMCON

Set C1IF bit

RD CMCON

NRESET

PIC12F635/PIC16F636/639

FIGURE 7-7: PIC16F636/639 COMPARATOR C2 OUTPUT BLOCK DIAGRAM

MULTIPLEX

Port Pins

C2SYNC

To TMR1

To C2OUT pin

C2INV

To Data Bus

RD CMCON

Set C2IF bit

Note 1: Comparator 2 output is latched on falling edge of T1 clock source.

TMR1

Clock Source

Reset

(1)

RD CMCON

U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

— — — — — —T1GSS

bit 7 bit 0

C2SYNC

(1)

bit 7-2: Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is T1G 0 = Timer1 gate source is Comparator 2 output

bit 0 C2SYNC: Comparator 2 Synchronize bit

1 = C2 output synchronized with falling edge of Timer1 clock 0 = C2 output not synchronized with Timer1 clock

Note 1: C2SYNC is C1SYNC in PIC12F635.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

pin (RA4 must be configured as digital input)

(2)

PIC12F635/PIC16F636/639

7.4 Comparator Outputs

The comparator outputs are read through the CMCON0 register. These bits are read-only. The comparator outputs may also be directly output to the RA2 and RC 4 I /O pins . W he n en abl ed, mul tip le xer s i n the output path of the RA2 and RC4 pins will switch and the output of each pin will be the unsynchronized output of the com parator. The uncertainty of each of the comparators is related to t he input offset vo ltage and the response time given in the specifications. Figure 7-5 and Figure 7-6 show the output block diagrams for Co mparator 1 and 2.

The TRIS bits will still function as an output enable/ disable for the RA2 and RC4 pins while in this mode.

The polarity of the comparator outputs can be changed using the C1INV and C2INV bits (CMCON0<5:4>).

Timer1 gate source can be configured to use the T1G pin or Comparator 2 output as selected b y the T1GSS bit (CMCON1<1>). This feature can be used to time the duration or interval of analog events. The output of Comparator 2 can also be synchronized with Timer1 by setting the C2SYNC bit (CMCON1<0>). When enabled, the output of Comparator 2 is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, Comparator 2 is latched after the prescaler. To prevent a race condition, the Comparator 2 output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See Figure 7-6, Comparator C2 Output Block Diagram and Figure 5-1, Timer1 on the PIC12F635/ PIC16F636/639 Block Diagram for more information.

It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not mi ss an inc rement if Comparator 2 changes during an increment.

The CxIE bits (PIE1<4:3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, th e interrupt is n ot enabled, th ough the CxIF bits will still be se t if an interru pt condi tion occ urs.

The user , in the Interru pt Service Routi ne, can cle ar the interrupt in the following manner:

a) Any read or write of CMCON0. This will end the

mismatch condition.

b) Clear flag bits CxIF. A mismatch conditi on will co ntinue to se t flag bit s CxIF.

Reading CMCON0 w ill end the m ismatch co ndition and allow flag bits CxIF to be cleared.

Note: If a change in the CMCON0 register

(CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR1<4:3>) interrupt flags may not get set.

7.5 Comparator Interrupts

The comparator interrupt flags are set whenever there is a change in the output value of its respective comparator. Software will need to maintain information about the status of the output bits, as read from CMCON0<7:6>, to determine the actual change that has occurred. The CxIF bits (PIR1<4:3>) are the Comparator Interrupt Flags. These bits must be reset in software by clearing them to ‘0’. Sin ce it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated.

PIC12F635/PIC16F636/639

7.6 Comparator Reference

The comparato r m od ule al so allows the selec tio n of a n internally generated voltage reference for one of the comparator input s. The VRCON reg ister (R egister7-3) controls the voltage reference module shown in Figure 7-8.

EQUATION 7-1:

VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range):

REF = ( VDD/4) + (VR<3:0> x VDD/32)

7.6.2 VOLTAGE REFERENCE

7.6.1 CONFIGURING THE VOLTAGE REFERENCE

The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range.

The following equation de termines the outp ut volta ges:

The voltage referen ce is VDD derived and therefore, the CV

REF output changes with fluctuations in VDD. The

tested absolute accuracy of the comparator voltage reference can be found in Section 15.0 “Electrical Specifications”.

ACCURACY/ERROR

FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8RRR RR

VDD

16-1 Analog

MUX

VREN

CVREF to

Comparator

Input

VRR

VR<3:0>

PIC12F635/PIC16F636/639

7.7 Comparator Response Time

Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 15-7).

7.8 Operation During Sleep

The comparators and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep curre nts than sh own in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power cons umption whil e in Sleep mod e, turn off the comparator, CM<2:0> = 111 and voltage reference, VRCON<7> = 0.

While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h) and if clear, continues execution with the next instruction. If the device wakes up from Sleep, th e content s of the C MCON0, CMCO N1 and VRCON registers are not affected.

7.9 Effects of a Reset

A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its OFF state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN —VRR— VR3 VR2 VR1 VR0

bit 7 bit 0

bit 7 VREN: CV

1 = CVREF circuit powered on 0 = CV

bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit

1 = Low range 0 = High range

bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CV

hen VRR = 1:

REF = (VR<3:0>/24) * VDD

When VRR = 0: CV

REF = VDD/4 + (VR<3:0>/32) * VDD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REF Enable bit

REF circuit powered down, no IDD drain and CVREF = VSS

REF Value Selection bits 0 ≤ VR<3:0> ≤ 15

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE

The Programmable Low-Voltage Detect module is an

8.1 Voltage Trip Points

The PIC12F635/PIC16F63 6/6 39 de vi ce supp ort s eig ht internal PL VD tri p points. Se e Register 8-1 for available PLVD trip point voltages.

interrupt driven supply level detection. The voltage detection monitors the internal power supply.

U-0 U-0 R-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit

1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt should not be enabled

bit 4 LVDEN: Low-Voltage Detect Power Enable bit

1 = Enables PLVD, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD, powers down PLVD and supporting circuitry

bit 3 Unimplemented: Read as ‘0’ bit 2-0 LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values)

111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V 000 = 1.9V

Note 1: Not tested and below minimum VDD.

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

TABLE 8-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

94h LVDCON 0Bh/8Bh INTCON GIE PEIE 0Ch PIR1 8Ch PIE1 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or

comparator voltage reference module.

Note 1: P IC 16F636/639 only.

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000

T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 EEIF LVDIF CRIF C2IF C1IF OSFIF — TMR1IF 0000 00-0 0000 00-0 EEIE LVDIE CRIE C2IE

(1)

C1IE OSFIE — TMR1IE 0000 00-0 0000 00-0

Value on

POR, BOD,

WUR

Value on

all other

Resets

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

9.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable during normal operation (full V is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDA T

• EEADR EEDAT holds the 8-bit data for read/write and EEADR

holds the address of the EEPROM location being accessed. PIC16F636/639 has 256 bytes of data EEPROM and the PIC12F635 has 64 bytes.

DD range). This memory

The EEPROM data memory allows b yte read and write. A byte write automatically erases the location and writes the new data (erase be fore write). The EEPROM data memory is rated fo r high er ase/writ e cycles. T he write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to A/C specifications in Section 15.0 “Electrical Specifications” for exact limits.

When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory . The device progra mmer can no longer access the data EEPROM data and will read zeroes.

Additional information on the data EEPROM is available in the “PICmicro Reference Manual” (DS33023).

Mid-Range MCU Family

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte Value to Write to or Read From Data EEPROM bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

EEADR7

bit 7 bit 0

bit 7-0 EEADR: Specifies 1 of 256 Locations for EEPROM Read/Write Operation bits

Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

PIC12F635/PIC16F636/639

9.1 EECON1 AND EECON2 Registers

EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as ‘0’s.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or wr i t e ope r a tio n. T he ina bi l it y t o cl ea r t he WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is c lear . T he WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situ ations, fol lowing Re set, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized.

Interrupt flag, EEIF bit (PIR1<7>), is set when write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence.

Note: The EECON1, EEDAT and EEADR

registers should not be modified during a data EEPROM write (WR bit = 1).

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit

1 = A wri te operation is prematurely terminated (any MCLR

normal operation or BOD detect)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles 0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit

can only be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

Legend:

S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Reset, any WDT Reset during

PIC12F635/PIC16F636/639

9.2 Reading the EEPROM Data Memory

T o read a d ata memory loca tion, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Exam ple 9-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).

EXAMPLE 9-1: DATA EEPROM READ

BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW CONFIG_ADDR ; MOVWF EEADR ;Address to read BSF EECON1,RD ;EE Read MOVF EEDAT,W ;Move data to W

9.3 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 9-2.

EXAMPLE 9-2: DATA EEPROM WRITE

BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; BSF EECON1,WREN ;Enable write BCF INTCON,GIE ;Disable INTs MOVLW 55h ;Unlock write MOVWF EECON2 ; MOVLW AAh ; MOVWF EECON2 ;

Required

Sequence

BSF EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS

The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. A ny number th at is not equa l to the required cycles to execute the required sequence will prevent the data from being writte n into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the WREN bit will not af fect this writ e cycle. The WR bit will be inhibited from being s et u nle ss the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR1<7>) must be cleared by software.

9.4 Wri te Verify

Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9-3) to the desired value to be written.

EXAMPLE 9-3: WRITE VERIFY

BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVF EEDAT,W ;EEDAT not changed

;from previous write

BSF EECON1,RD ;YES, Read the

;value written XORWF EEDAT,W BTFSS STATUS,Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue

9.4.1 USING THE DATA EEPROM

The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). The maximum endurance for any EEPROM cell is specified as D120. D124 specifies a maximum number of writes to any EEPROM location before a refresh is required of infrequently changing memory locations.

9.4.2 EEPROM ENDURANCE

As an example, hypothetically, a data EEPROM is 64 bytes long and has an endurance of 1M writes. It also has a re fresh parameter of 10 M writes. If every memory location in the cell were written the maximum number of times, the data EEPROM would fail after 64M write cycles. If every memory location, save 1, were written the maximum number of times, the data EEPROM would fail after 63M writ e cyc les, but the on e remaining location could fail afte r 10M cycles . If proper refreshes occurred, then the lone memory location would have to be refreshed 6 times for the data to remain correct.

PIC12F635/PIC16F636/639

9.5 Protection Against Spurious Write

There are c onditions when the user may no t want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Als o, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write.

The write initiate se quence and the WREN bit together help preven t an acciden tal write during:

• Brown-out

• Power glitch

• Software malfunction

9.6 Data EEPROM Operation During Code Protection

Data memory can be code-p rotected by progr amming the CPD bit in the Co nfigur ation Word (Regis ter 1 2-1) to ‘0’.

When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached.

TABLE 9-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Bh/8Bh INTCON GIE PEIE 0Ch PIR1 EEIF 8Ch PIE1 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 9Ch EECON1 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the data EEPROM module.

Note 1: P IC1 6F636/639 only.

EEIE LVDIE CRIE C2IE

— — — — WRERR WREN WR RD ---- x000 ---- q000

LVDIF CRIF C2IF

(1)

EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

(1)

C1IF OSFIF — TMR1IF 0000 00-0 0000 00-0

(1)

C1IE OSFIE —TMR1IE0000 00-0 0000 00-0

POR, BOD,

WUR

Value on

all other

Resets

PIC12F635/PIC16F636/639

10.0 KEELOQ® COMPATIBLE CRYPTOGRAPHIC MODULE

To obtain information regarding the implementation of

EELOQ module, Microchip Technology requires

the K the execution of the “K Agreement”.

The “KEELOQ® Encoder Lice nse Agreement” may be accessed through the Microchip web site located at www.microchip.com/K be obtained by contacting you r local Microc hip Sales Representative.

EELOQ. Further information may

EELOQ

Encoder License

PIC12F635/PIC16F636/639

NOTES:

PIC12F635/PIC16F636/639

11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)

The PIC16F639 device consists of the PIC16F636 device and low frequency (LF) Analog Front-End (AFE), with the AFE section containing three analoginput channels for signal detection and LF talk-back. This section describes the Analog Front-End (AFE) in detail.

The PIC16F639 device can detect a 125 kHz input signal as low as 1 mVpp and transmit data by using internal LF talk-back modulation or via an external transmitter. The PIC16F639 can also be used for various bidirectional communication applications. Figure 11-3 and Figure 11-4 show application examples of the device.

Each analog input channel has internal tuning capacitance, sensitivity control circuits, an input signal strength limiter and an LF talk-back modulation transistor. An Automatic Gain Control (AGC) loop is used for all three input channel gains. The output of each channel is OR'd and fed into a demodulator. The digital output is passed to the LFDATA pin. Figure 11-1 shows the block diagram of the AFE and Figure 11-2 shows the LC input path.

There are a total of eig ht Confi guratio n regis ter s. Six of them are used for AFE operation options, one for column parity bits and one for status indication of AFE operation. Each register has 9 bits including one row parity bit. These regis te rs are readable and writab le by SPI (Serial Protocol Interface) commands except for the Status register, which is read-only.

11.1 RF Limiter

The RF Limiter limits LC pin input voltage by de-Q’ing the attached LC resonant circuit. The absolute voltage limit is defined by the silicon process’s maximum allowed input voltage (see Section 15.0 “Electrical Specifications”). The limiter begins de-Q’ing the external LC antenna when the input voltage exceeds

VDE_Q, progressively de-Q’ing harder to reduce the

antenna input voltage. The signal levels from all 3 channels are combined

such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal.

11.2 Modulation Circuit

The modulation circuit consists of a modulation transistor (FET), internal tunin g capacitors and ext ernal LC antenna components. The modulation transistor and the internal tuning capacitors are connected between the LC input pin and LCCOM pin. Each LC input has its own modulation transistor.

When the modulation transistor turns o n, it s low T urn-on Resistance (R voltage. The coil voltage is minimized when the modulation transistor turns-on and maximized when the modulation transistor turns-off. The modulation transistor’s low Turn-on Resistance (R high modulation depth.

The LF talk-back is achieved by turning on and off the modulation transistor.

The modulation data comes from the microcontroller section via the digital SPI interface as “Clamp On”, “Clamp Off” commands. Only those inputs that are enabled will execute the clamp command. A basic block diagram of the modulation circuit is shown in Figure 11-1 and Figure 11-2.

The modulation FET is also shorted momentarily after Soft Reset and Inactivity timer time-out.

M) clamps the induced LC antenna

M) results in a

11.3 Tuning Capacitor

Each channel has internal tuning capacitors for external antenna tuning. The capacitor values are programmed by the Configuration registers

Note: The user can con trol the tu ning capaci tor

by programming the AFE Configuration registers.

up to 63 pF , 1 pF per step.

11.4 Variable Attenuator

The variable attenuator is used to attenuate, via AGC control, the input signal voltage to avoid saturating the amplifiers and demodulators.

Note: The variable attenuator function is

accomplished by the device itself. The user cannot control its function.

11.5 Sensitivity Control

The sensitivity of each channel can be reduced by the channel’s Configuration register sensitivity setting. This is used to desensitize the channel from optimum.

Note: The user can desensitize the channel

sensitivity by programming the AFE Configura tion registers.

PIC12F635/PIC16F636/639

11.6 AGC Control

The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 “Varia ble A ttenu ator”).

The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal.

Note: The AGC control function is accompli shed

by the device itself. The user cannot control its function .

11.7 Fixed Gain Amplifiers 1 and 2

FGA1 and FGA2 provides a maximum two-stage gain of 40 dB.

Note: The user cannot control the gain of these

two amplifiers.

11.8 Auto Channel Selection

The Auto Channel Selection feature is enabled if the Auto Channel Select bit AUTOCHSEL<8> in Configuration Register 5 (Register 11-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (T it allows this channel to pass data, otherwise it is blocked.

The status of this operation is monitored by AFE Status Register 7 bits <8:6> (Register 1 1-8). These bits indicate the current status of the channel selection activity, and automatically updates for every Soft Reset period. The auto channel selection function resets after each Soft Reset (or after Inactivity timer time- out) . Ther efor e, th e blocked channels are reenabled after Soft Reset.

This feature can make the output signal cleaner by blocking any channel that was not high at the end of

AGC. This function works only for demodulated data

T output, and is not applied for carrier clock or RSSI output.

STAB). If the output is hig h,

11.10 Demodulator

The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal.

11. 11 Data Slicer

The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The reference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are OR’d together and sent to the output enable filter.

11.12 Output Enable Filter

The Output Enable Filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 11.15 “Configurable

Output Enable Filter”).

11. 1 3 RSSI (Received Signal Strength Indicator)

The RSSI provides a current which is propo rtional to the input signal amplitude (see Section 11.31.3 “Received

Signal Strength Indicator (RSSI) Output”).

11.14 Analog Front-End Timers

The AFE has an internal 32 kHz RC oscillator. The oscillator is used in several timers:

• Inactivity timer

• Alarm timer

• Pulse Width timer

• Period timer

• AGC settling timer

11.14.1 RC OSCILLATOR

The RC oscillator is low power, 32 kHz ± 10% over temperature and volta ge variations.

11. 9 Carrier Clock Detector

The Detector senses the input carrier cycles. The output of the Detector switches di gitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in the AFE Configuration Register 1 (Register 11-2).

PIC12F635/PIC16F636/639

11.14.2 INACTIVITY TIMER

The Inactivity Timer is used to automatically return the AFE to Standby mode, if there is no input signal. The time-out period is approximately 16 ms (T on the 32 kHz internal clock.

The purpose of the Inactivity Timer is to minimize AFE current draw by automatically returning the AFE to the lower current Standby mode, if there is no input signal for approximately 16ms.

The timer is reset when:

• An amplitude change in LF input signal, either high-to-low or low-to-high

pin is low (any SPI™ command)

•CS

• Timer-related Soft Reset

The timer starts when:

• AFE receives any LF signal

The timer causes an AFE Soft Reset when:

• A previously received LF signal does not change either high-to-low or low-to-high for T

The Soft Reset re turns the AFE t o St andby mo de where most of the analog circuits, such as the AGC, demodulator and RC oscillator, are powered down. This returns the AFE to the lower Standby Current mode.

INACT), based

INACT

11.14.3 ALARM TIMER

The Alarm Timer is used to notify the MC U that the AFE is receiving LF signal that does not pass the output enable filter requirement. The time-out period is approximately 32 ms (T continuing noise.

The Alarm Timer time-out occurs if there is an input signal for longer than 32 ms that does not meet the output enable filter requirements. The Alarm Timer time-out causes:

a) The ALERT b) The ALARM bit to set in the AFE Status

Configuration 7 register (Register 11-8).

The MCU is infor med of the Alarm timer time-out by monitoring the ALERT occurs, the MCU can take appropriate actions such as lowering channel sensitivity or disabling channels. If the noise source is ignored, the AFE can return to a lower standby current draw state.

pin to go low.

ALARM) in the presence of

pin. If the Alarm timer time-out

The timer is reset when the:

pin is low (any SPI command).

•CS

• Output enable filter is disabled.

• LFDATA pin is enabled (signal passed output enable filter).

The timer starts when:

• Receiving a LF signal.

The timer causes a low output o n the ALER T

• Output enable filter is enabled and modulated input signal is present for T pass the output enable filter requirement.

Note: The Alarm timer is disabled if the output

enable filter is disabled.

ALARM, but does not

pin when:

11.14.4 PULSE WIDTH TIMER

The Pulse Width Timer is used to verify that the received output enable sequence meets both the minimum T

OEH and minimum TOEL requirements.

11.14.5 PERIOD TIMER

The Period Timer is used to verify that the received output enable sequence meets the maximum T requirement.

OET

11.14.6 AGC SETTLING TIMER (TAGC)

This timer is used to keep the output enab le filter in Reset while the AGC settles on the input signal. The time-out period is approximately 3.5 ms. At end of this

AGC), the input should remain high (TPAGC),

time (T otherwise the counting is aborted and a Soft Reset is issued. See Figure 11-6 for details.

Note 1: The AFE needs continuous and

uninterrupted high input signal during AGC settling time (TAGC). Any absence of signal during this tim e may reset the timer and a new input signa l is neede d for AGC settling time, or may result in improper AGC gain settings which will produce invalid output.

2: The rest of the A FE section wa kes up if any

of these input channels receive the AGC settling time c orrec tly. AFE Status Registe r 7 bits <4:2> ( Reg ist e r 11-8) indicate w hich input channels have waken up the AFE first. V alid inp ut signal on mu ltiple input pi ns can cause more than one channel's indicator bit to b e se t.

PIC12F635/PIC16F636/639

FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END

LCX

LCY

LCZ

LCCOM

Lim

LCCOM

Lim

LCCOM

Lim

Mod

Tune X

Tune Y

Tune Z

Sensitivity

Control X

Sensitivity

Control Y

Sensitivity

Control Z

To Sensitivity X To Sensitivity Y To Sensitivity Z

AGC

Modulation

Depth

Detector

32 kHZ

Oscillator

Watchdog

AGC

Timer

÷ 64

WAKEY

÷ 64

WAKEX

WAKEZ

Output Enable

Filter

AGC Preserve

To Modulation

Transistors

To Tuning Cap X To Tuning Cap Y To Tuning Cap Z

SST

VDDT

Command Decoder/Controller

Configuration

Registers

RSSI

CS LFDATA/RSSI/SCLK/ALERT

MCU

CCLK/SDIO

FIGURE 11-2: LC INPUT PATH

PIC12F635/PIC16F636/639

32 kHz

WAKEX

Clock/AGC

WAKEY

RSSI

Timer

WAKEZ

AGCSIG

0.1V

≈

0.4V

≈

AGCACT

ACT

CHZ

CHX

–

AGC

Feedback

Amplifier

CHY

MOD Depth Control

Data Slicer

Selector

Auto Channel

–

AUTOCHSEL

LFDATA

CLKDIV

/1 OR /4

Filter

LFDATA

Output Enable

÷ 64

Detector

Carrier

DETX

–

DATOUT

RSSI GEN

DETZ

DETY

Peak

Detector

FGA1 FGA2

Filter

Low-Pass

AGC

Var

Atten

Rectifier

Full-Wave

Sens.

Control

Tuning

Capacitor

FET

MOD

LCX/

LCY/

>4VPP

Limiter

LCZ

LCCOM

Configuration

Decode

Registers

REF GEN

Demodulator

Legend:

FGA = Fixed Gain Amplifier

FWR = Full-wave Rectifier

LPF = Low-pass Filter

PD = Peak Detector

PIC12F635/PIC16F636/639

FIGURE 11-3: BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE

)

Microcontroller

(MCU)

LED

UHF

Receiver

Transmitter/

Receiver

(

Transmitter

Ant. X

(

)

Ant. Y

PIC16F639

MCU

(PIC16F636)

Ant. Z

3 Input

Analog Front-End

(

)

LED

UHF

Base Station Transponder

FIGURE 11-4: PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE

air-core

coil

+3V

RFEN

LFDATA/RSSI/CCLK/SDIO

S0 S1 S2

Data

DDT

LCX LCY

ferrite-core

coil

1 2 3 4 5 6 7 8 9 10

PIC16F639

LED

SCLK/ALERT

VSST

LCCOM

LCZ

ferrite-core

coil

+3V +3V

315 MHz

RF Circuitry

(UHF TX)

+3V

PIC12F635/PIC16F636/639

11.15 Configurable Output Enable Filter

The purpose of this filter is to enable the LFDATA output and wake the microcontroller only after receiving a specific sequence of pulses on the LC input pins. Therefore, it prevents the AFE from waking up the microcontroller due to noise or unwanted input signals. The circuit compares the timing of the demodulated header waveform with a pre-defined value, and enables the demodulated LFDATA output when a match occurs.

The output enable filter consists of a high (T low duration (T

OEL) of a pulse immediately after the

AGC settling gap time. The selection of high and low times further implies a max period time. The output enable high and low times are determined by SPI interface programming. Figure 11-5 and Figure11-6 show the output enable filter waveform s .

There should be no missing cycles during T Missing cycles may result in failing the output enable condition.

FIGURE 11-5: OUTPUT ENABLE FILTER TIMING

OEH) and

OEH.

Demodulator

Output

STAB

(TAGC + TPAGC)

AFE Wake-up

and AGC Stabilization

TGAP

AGC

Gap Pulse

Required Output Enable Sequence

t ≥ TOEH

t ≤ TOET

t ≥ TOEL

Data Packet

Start bit

LFDATA output is enabled

on this rising edge

PIC12F635/PIC16F636/639

FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)

LFDATA Output

3.5 ms

Low

Current

Standby

Mode

Legend: TAGC = AGC stabilization time

TAGC

(AGC settling time)

TSTAB

(AFE Stabilization)

E = Time element of pulse

T T

GAP = AGC stabilization gap

OEH = Minimum output enable filter high time

OEL = Minimum output enable filter low time

T T

OET = Maximum output enable filter period

PAGC = High time after TAGC

T TSTAB =TAGC + TPAGC

LF Coil Input

TPAGC

(need

“high”)

TGAP

Gap

Pulse

Filter starts

t ≥ TOEH

t ≤ TOET

t ≥ TOEL

Filter is passed and LFDATA is enabled

Start bit

t ≥ TE

PIC12F635/PIC16F636/639

TABLE 11-1: TYPICAL OUTPUT ENABLE

FILTER TIMING

OEH

<1:0>

OEL

<1:0>

OEH

(ms)

01 00 113 01 01 113 01 10 124 01 11 146

10 00 214 10 01 214 10 10 225 10 11 248

11 00 416 11 01 416 11 10 428 11 11 4410

XX Filter Disabled

Note 1: Typical at room temperature and

DD = 3.0V, 32 kHz oscillator.

TOEH is measured from the rising edge of the demodulator output to the first falling edge. The pulse width must fall within TOEH ≤ t ≤ TOET.

OEL is measured from the falling edge of the

T demodulator output to the rising edge of the ne xt pulse. The pulse width must fall within TOEL ≤ t ≤ TOET.

OET is measured from rising edge to the next rising

T edge (i.e., the sum of T must be t ≤ T

OEH and TOEL). The pulse wid th

OET. If the Configuration Register 0

(Register 11-1), OEL<8:7> is set to ‘00’, then T must not exceed TOET and TOEL must not exceed

INACT.

T The filter will reset, requiring a complete new successive

high and low period to enable LFDATA, under the following conditions.

• The received high is not greater than the configured minimum T

OEH value.

•During TOEH, a loss of signal > 56 μs. A loss of signal < 56 μs may or may not cause a filter Reset.

• The received low is not greater than the configured minimum T

OEL value.

• The received sequence exceeds the maximum T

OET value:

-T

OEH + TOEL > TOET

-or TOEH > TOET

-or TOEL > TOET

• A Soft Reset SPI command is received.

OEL

T (ms)

OET

T (ms)

OEH

If the filter resets due to a long high (T

OEH > TOET), the

high-pulse timer will not begin timing again until after a gap of TE and another low-to-high transition occurs on the demodulator output.

Disabling the output enable filter disables the T

OEL requirement and the A FE passes all received LF

OEH and

data. See Fi gure 11-10, Figu re 11-11 and Figure 11-12 for examples.

When viewed from an appl ication perspe ctive, f rom the pin input, the actual output ena ble filter timin g must factor in the analog delays in the input path (such as demodulator charge and discharge times).

OEH - TDR + TDF

• T

• TOEL + TDR - TDF The output enable filter starts immediately after TGAP,

the gap after AGC stabilization period.

11.16 Input Sensitivity Control

The AFE is designed to have typical input sensitivity of

PP. This means any input signal with amplitude

3mV greater than 3 mV AGC loop regulates the detecting signal amplitude when the input level is greater than approximately 20 mV This signal amplitude is called “AGC-active level”. The AGC loop regulates the input voltage so that the input signal amplitude range w ill be kept within the linear rang e of the detection circuits without saturation. The AGC Active Status bit (AGCACT<5>) in the AFE Status Register 7 (Register 11-8) is set if the AGC loop regulates the input vo lt ag e.

Table 11-2 shows the input sensitivity comparison when the AGCSIG option is used. When AGCSIG option bit is set, the demodulated output is available only when the AGC loop is active (see Table 11-1). The AFE has also input sensitivity reduction options per each channel. The Configuration Register 3 (Register 11-4), Configuration Register 4 (Register 11-5) and Configuration Register 5 (Register 11-6) have the option to reduce the channel gains from 0 dB to approximately -30 dB.

PP can be detected. The AFE’s internal

PP.

PIC12F635/PIC16F636/639

TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)

AGCSIG<7>

(Config. Register 5 )

0 Disabled – the AFE passes signal of any amplitude level it is capable of

1 Enabled – No output until AGC Status = 1 (i.e., VPEAK ≈ 20 mVPP)

Description

detecting (demodulated data and carrier clock).

(demodulated data and carrier clock).

• Provides the best signal to noise ratio.

Input

Sensitivity

(Typical)

3.0 mV

20 mV

11. 17 Input Channels (Enable/Disable)

Each channel can be individually enabled or disabled by programming bits in Configuration Register 0<3:1> (Register 11-1).

The purpose of having an option to disable a pa rtic ul ar channel is to minimize current draw by powering down as much circuitry as possible, if the channel is not needed for operatio n. The exact ci rcuit s di sable d when an input is disabled are amplifiers, detector, full-wave rectifier, data slicer, and modulation FET. However, the RF input limiter remains active to protect the silicon from excessive antenna input voltages.

11.18 AGC Amplifier

The circuit automatically amplifies input signal voltage levels to an acceptable level for the data slicer. Fast attack and slow release by nature, the AGC tracks the carrier signal level and not the modulated data bits.

The AGC inherently tracks the strongest of the three antenna input signals. The AGC requires an AGC stabilization time (T

The AGC will attempt to regulate a channel’s peak signal voltage into the data slicer to a des ired regulated AGC voltage – reducing the input path’s gain as the signal level atte mp t s t o increase above regulated AGC voltage, and allowing full amplification on signal levels below the regulated AGC voltage.

The AGC has two modes of operation:

1. During the AGC settling time (T time constant is fast, allowing a reasonably short acquisition time of the continuous input signal.

2. After T

Also, the AGC is froze n when the input signal envelop e is low. The AGC tracks only high envelope levels.

AGC, the AGC switches to a slower time

constant for data slicing.

AGC).

AGC), the AGC

11.19 AGC Preserve

The AGC preserve feature allows the AFE to preserve the AGC value during the AGC settling time (T apply the value to the data slicing circuit for the following data streams instead of using a new tracking value. This feature is useful to demodulate the input signal correctly when the input has random amplitude variations at a given time period. This feature is enabled when the AFE receives an AGC Preserve On command and disabled if it receives an AGC Preserve Off command. Once the AGC Preserve On command is received, the AFE acquires a new AGC value during each AGC settling time and preserves the value until a Soft Reset or an AGC Preserve Off command is issued. Therefore, it does not need to issue another AGC Preserve On command. An AGC Preserve Off command is needed to disable the AGC preserve feature (see

Section 11.32.2.5 “AGC Preserve On Command” and Section 11.32.2.6 “AGC Preserve Off Command” for AGC Preserve commands).

AGC) and

PIC12F635/PIC16F636/639

11.20 Soft Reset

The AFE issues a Soft Reset in the following events: a) After Power-on Reset (POR),

b) After Inactivity timer time-out, c) If an “Abort” occurs, d) After receiving SPI Soft Reset command.

The “Abort” occurs if there is no positive signal detected at the end of the AGC stabilization period

AGC). The Soft Reset initializes internal circuits and

(T brings the AFE into a low current Standby mode operation. The intern al circuits that are initial ized by the Soft Reset include:

• Output Enable Filter

•AGC circuits

• Demodulator

• 32 kHz Internal Oscillator The Soft Reset has no effect on the Configuration register

setup, except for some of the AFE Status Register 7 bits. (Register 11-8).

The circuit initialization takes one internal clock cycle (1/32 kHz = 31.25 μs). During the initialization, the modulation transistors between each input and LCCOM pins are turned-on to discharge any internal/ external para sitic char ges. The modu lation tra nsistors are turned-off immediately after the initialization time.

The Soft Reset is executed in Active mode only . It is not valid in Standby mode.

TABLE 11-3: SETTING FOR MINIMUM

MODULATION DEPTH REQUIREMENT

MODMIN Bits

(Config. Register 5)

Bit 6 Bit 5

Modulation Depth

50% (default)

75% 25% 12%

11. 21 Minimum Modulation Depth

Requirement for Input Signal

The AFE demodulates the modulated input signal if the modulation depth of the input signal is greater than the minimum requirement that is programmed in the AFE Configuration Register 5 (Register 11-6). Figure 11-7 shows the definition of the modulation depth and examples. MODMIN<6:5> of the Configuration Register 5 offer four options. They are 75%, 50%, 25% and 12%, with a default setting of 50%.

The purpose of this feature is to enhance the demodulation integrity of the input signal. The 12% setting is the best choice for the in put si gn al with weak modulation depth, which is typically observed near the high-voltage base station antenna and also at fardistance from the base station antenna. It gives the best demodulation sensitivity, but is very susceptible to noise spikes that can res ult in a bi t detect ion error. The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings.

PIC12F635/PIC16F636/639

FIGURE 11-7: MODULATION DEPTH EXAMPLES

(a) Modulation Depth Definition

Amplitude

(b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting

Modulation Depth (%) =

A - B

X 100%

Amplitude

7 mVPP

10 mV

Coil Input Strength

Modulation Depth (%) =

Input signal with modulation depth = 30%

Demodulated LFDATA Output when MODMIN Setting = 25%

(LFDATA output = toggled)

Demodulated LFDATA Output if MODMIN Setting = 50%

(LFDATA output = not toggled)

10 - 7

X 100% = 30%

PIC12F635/PIC16F636/639

11. 22 Low Current Sleep Mode

The Sleep command from the microcontroller, via an SPI Interface command, places the AFE into an ultra Low-current mode. All c irc ui ts including the RF Lim ite r, except the minimum circui try requ ired to re tain register memory and SPI capability, will be powered down to minimize the AFE current draw . Pow er-on Reset or any SPI command, other than Sleep comm and , is require d to wake the AFE from Sleep.

11. 23 Low Current Standby Mode

The AFE is in Standby mode when no LF signal is present on the antenna inputs but the AFE is powered and ready to receive any incoming signals.

11. 24 Low Current Operating Mode

The AFE is in Low-current Operating mode when a LF signal is present on an LF antenna input and internal circuitry is switching with the received data.

11.25 Error Detection of AFE Configuration Register Data

The AFE's Configurati on regis ters ar e vo latile memo ry. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect. To ensure the data integrity, the AFE has an error detection mechanism using row and column parity bi ts of the Confi guration regi ster memor y map. The bit 0 of each reg is ter i s a ro w p arity bit which is calculated over the eight configuration bits (from bit 1 to bit 8). The Column Parity Register (Configuration Register 6) holds column parity bits; each bit is calculated over the respective columns (Configuration registers 0 to 5) of the Configuration bits. The Status register is not included for the column parity bit calculation. Parity is to be odd. The parity bit set or cleared makes an odd number of set bits. The user needs to calcula te the ro w and colum n p arity b its usin g the contents of the registers and program them. Durin g operation, the AFE co ntinuously c alculates the row and column parity bits of the configuration memory map. If a parity error occu rs, the AFE lowe rs the SCLK/AL ER T pin (interrupting the microcontroller section) indicating the configuration memory has been corrupted or unloaded and needs to be reprogrammed.

At an initial condition after a Power-On-Reset, the values of the registers are all clear (default condition). Therefore, the AFE will issue the parity bit error by lowering the SCLK/ALERT registers with correct parity bits, the SCLK/ALERT will be toggled to logic high level immediatel y.

The parity bit errors do not change or affect the AFE's functional operation.

Table 11-4 shows an example of the register values and corresponding parity bits.

pin. If user reprograms the

TABLE 11-4: AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE

Configurat ion Register 010101000 0 Configurat ion Register 1 00000000 1 Configurat ion Register 2 00000000 1 Configurat ion Register 3 00000000 1 Configurat ion Register 4 00000000 1 Configurat ion Register 5 10000000 0

Configuration Register 6 (Column Parity Register)

11010111 1

Bit 0

(Row Parity)

PIC12F635/PIC16F636/639

11.26 Factory Calibration

Microchip calibrates the AFE to reduce the device-todevice variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation.

11.27 De-Q’ing of Antenna Circuit

When the transponder is close to the base station, the transponder coil may develop coil voltage higher than

DE_Q. This condition is called “near field”. The AFE

V detects the strong near field signal through the AGC control, and de-Q’ing the antenna circuit to reduce the input signal amplitude.

11.28 Battery Back-up and Batteryless Operation

The device supports both battery back-up and batteryless operation by the addition of external components, allowing the device to be partially or completely powered from the field.

Figure 11-8 shows an example of the external circuit for the battery back-up.

Note: Voltage on LCCOM combined wi th coil input

voltage must n ot ex ce ed the maximum LC input voltage.

FIGURE 11-8: LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE

VBAT

DBLOCK

DLIM

VDD

CPOOL

DFLAT1

Air Coil

RLIM

LCX

LCY

LCZ

FLAT2

Legend: CCOM = LCCOM charging capacitor.

POOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device.

BLOCK = Battery protection from reverse charge.

Schottky for low forward bias drop.

DFLAT = Field rectifier diodes.

LIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields .

COM = Ccom discharge path.

LIM = Current limiting resistor, required for air coil in strong fields.

RCOM

CCOM

LCCOM

PIC12F635/PIC16F636/639

11.29 Demodulator

The demodulator r ecovers the modula tion data from the received si gnal, containing carrier plus data, by appropriate envelope detection. The demodulator has a fast rise (charge) time (T appropriate to an envelope of input signal (see Section 15.0 “Electrical Specifications” for T and TDF specifications). The demodulator contains the full-wave rectifier, low-pass filter, peak detector and data slicer.

FIGURE 11-9: DEMODULATOR CHARGE AND DISCHARGE

Signal into LC input pins

Full-wave Rectifier output

DR) and a fall time (TDF)

Data Slicer output

(demodulator output)

TDR

11.30 Power-On Reset

This circuit remains in a Reset state until a sufficient supply voltage is applied to the AFE. The Reset releases when the supply is sufficient for correct AFE operation, nominally

The Configuration regis ters a re all cle ared o n a Pow eron Reset. A s the Co nf i gu ra t io n r eg i ster s a re pr o tec t ed by odd row an d column parit y, the ALERT pulled down – indicating to the microcontroller section that the AFE configuration memory is cleared and requires loading.

VPOR of AFE.

pin will be

11.31 LFDATA Output Selection

The LFDATA output can be configured to pass the Demodulator output, Received Signal Strength Indicator (RSSI) output, or Carrier Clock. See Configuration Register 1 (Register 1 1-2) for more details.

11.31.1 DEMODULATOR OUTPUT

The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output.

TDF

For a clean data output or to save operating power, the input channels can be individua lly enabled or disabl ed. If more than one cha nnel i s enab led, th e outpu t is the su m of each output of all enabled channels. There will be no valid output if all three channels are disabled. When the demodulated output is sele cted, the output is available in two different con ditions depend ing on how the options of Configuration Register 0 (Register 11-1) are set: Output Enable Filter is disabled or enabled.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2), DATOUT <8:7>:

bit 7

-bit 8

00: Demodulator Output 01: Carrier Clock Output 10: RSSI Output 01: RSSI Output

• Configuration Register 0 (Register 11-1): all bits

PIC12F635/PIC16F636/639

Case I. When Output Enable Filter is disabled: Demodula ted output is available immediately after the AGC stabiliz ation

AGC). Figure 11-10 shows an example of demodulated output when the Output Enabl e Filter is disa bled.

time (T

FIGURE 11-10: INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE

FILTER IS DISABLED

Input Signal

LFDATA Output

Case II. When Output Enable Filter is enable d: Demodulat ed output is available only if the inc oming sig nal meets the

enable filter timi ng crit eria that is defin ed in th e Config urat ion R egist er 0 (Regi ster11-1). If the crit eria is met, th e outp ut is available after the low timing (TOEL) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of demodulated output when the Output Enable Filter is enabled.

FIGURE 11-11: INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE

FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS)

Input Signal

LFDATA Output

PIC12F635/PIC16F636/639

FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED

BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS)

Input Signal

No LFDATA Output

PIC12F635/PIC16F636/639

11.31.2 CARRIER CLOCK OUTPUT

When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC st abilization time (T completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT<7> of Configuration Register 2 (Register 11-3). The carrier clock output is available immediately after the AGC settling time. The Output Enable Filter, AGCSIG, and MODMIN options are applicable for the carrier clock output in the same way as the demodulated output. The input channel can be individually enabl ed or disabled for the output. If more than one channel is enabled, the output is the sum of each output of all enabled channels. Therefore, the carrier clock output waveform is not as precise as when only one channel is enabled. It is recommended to enable one channel only if a precise output waveform is desired.

There will be no valid output if all three channels are disabled. See Figure 11-13 for carrier clock output examples.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2), DATOUT <8:7>:

bit 8

• Configuration Register 2 (Register 11-3),

• Configuration Register 0 (Register 11-1): all bits

• Configuration Register 5 (Register 11-6)

bit 7

00: Demodulator Output 01: Carrier Clock Output 10: RSSI Output 11: RSSI Output

CLKDIV<7>:

0: Carrier Clock/1 1: Carrier Clock/4

are affected

AGC) is

PIC12F635/PIC16F636/639

FIGURE 11-13: CARRIER CLOCK OUTPUT EXAMPLES

(A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION

Carrier Clock Output

Carrier Input

(B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION

Carrier Clock Output

Carrier Input

PIC12F635/PIC16F636/639

11.31.3 RECEIVED SIGNAL STRENGTH

INDICATOR (RSSI) OUTPUT

An analog cu rrent is availabl e at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE’s Configuration register. The analog current is lin early pro portion al to t he inpu t signal strengt h (see Figure 11-15).

All timers in the circuit, such as inactivity timer, alarm timer, and AGC settling time, are disabled during the RSSI mode. Therefore, the RSSI ou tpu t is not a f fe cte d by the AGC settling time, and available immediately when the RSSI option is selected. The AFE enters Active mode immediately when the RSSI output is selected. The MCU I/O pin (RC3) connected to the LFDATA pin, must be set to high-impedance state during the RSSI Output mode.

When the AFE receives an SPI command during the RSSI output, the RSSI mode is temporary disabled until the SPI interface communication is completed. It returns to the RSSI mode again after the SPI interface communication is compl ete d. The AFE holds the RSSI mode until another output type is selected (CS turns off the RSSI signal). To obtain the RSSI output for a particular input channel, or to save operating power, the input channel can be individually enabled or disabled. If more than one channel is enabled, the RSSI output is from the strongest signal channel. There will be no valid output if all three channels are disabled.

Related AFE Configuration register bits:

• Configuration Register 1 (Register 11-2), DATOUT<8:7>:

bit 8

bit 7

00: Demodulated Output 01: Carrier Clock Output 10: RSSI Output 11: RSSI Output

• Configuration Register 2 (Register 11-3), RSSIFET<8>:

0: Pull-Down MOSFET off 1: Pull-Down MOSFET on.

Note: The pull-down MOSFET option is valid

only when the RSSI output is selected. The MOSFET is not controllable by users when Demodulated or Carrier Clock output option is selected.

• Configuration Register 0 (Register 11-1): all bits are affected.

low

FIGURE 11-14: RSSI OUTPUT PATH

RSSI Output Current

Generator

VDD

Off if RSSI active

RSSIFET

RSSI Pull-down MOSFET

(controlled by Config. 2, bit 8)

Current Output

RC3/LFDATA/RSSI/CCLK Pin

MICROCHIP PIC12F635, PIC16F636, PIC16F639 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC12F635 BLOCK DIAGRAM

FIGURE 1-2: PIC16F636 BLOCK DIAGRAM

FIGURE 1-3: PIC16F639 BLOCK DIAGRAM

TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS

TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS

TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS

2.0 MEMORY ORGANIZATION

TABLE 2-1: BANK SELECTION

FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS

FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

TABLE 2-5: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

TABLE 2-6: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

3.0 CLOCK SOURCES

FIGURE 3-1: PIC12F635/PIC16F636 /639 CLOCK SOURCE BLOCK DIAGRAM

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

FIGURE 3-5: RC MODE

FIGURE 3-6: RCIO MODE

FIGURE 3-7: TWO-SPEED START-UP

FIGURE 3-8: FSCM BLOCK DIAGRAM

FIGURE 3-9: FSCM TIMING DIAGRAM

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

4.0 I/O PORTS

FIGURE 4-1: BLOCK DIAGRAM OF RA0

FIGURE 4-2: BLOCK DIAGRAM OF RA1

FIGURE 4-3: BLOCK DIAGRAM OF RA2

FIGURE 4-4: BLOCK DIAGRAM OF RA3

FIGURE 4-5: BLOCK DIAGRAM OF RA4

FIGURE 4-6: BLOCK DIAGRAM OF RA5

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

FIGURE 4-9: BLOCK DIAGRAM OF RC4

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

5.0 TIMER0 MODULE

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

FIGURE 6-1: TIMER1 ON THE PIC12F635/PIC16F636/639 BLOCK DIAGRAM

FIGURE 6-2: TIMER1 INCREMENTING EDGE

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1

7.0 COMPARATOR MODULE

FIGURE 7-1: SINGLE COMPARATOR

FIGURE 7-2: ANALOG INPUT MODEL

FIGURE 7-3: COMPARATOR I/O OPERATING MODES FOR PIC12F635

FIGURE 7-4: COMPARATOR I/O OPERATING MODES FOR PIC16F636/639

FIGURE 7-5: PIC12F635 COMPARATOR C1 OUTPUT BLOCK DIAGRAM

FIGURE 7-6: PIC16F636/6 39 COMPARATOR C1 OUTPUT BLOCK DIAGRAM

FIGURE 7-7: PIC16F636/639 COMPARATOR C2 OUTPUT BLOCK DIAGRAM

FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE

TABLE 8-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

9.0 DATA EEPROM MEMORY

TABLE 9-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

10.0 KEELOQ® COMPATIBLE CRYPTOGRAPHIC MODULE

11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)

FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END

FIGURE 11-3: BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE

FIGURE 11-5: OUTPUT ENABLE FILTER TIMING

FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)

TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)

TABLE 11-4: AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE

FIGURE 11-8: LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE