MICROCHIP PIC12F510, PIC16F506 DATA SHEET

PIC12F510/16F506

Data Sheet

8/14-Pin, 8-Bit Flash Microcontroller

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC12F510/16F506

8/14-Pin, 8-Bit Flash Microcontroller

Devices Included In This Data Sheet:

•PIC16F506

•PIC12F510

High-Performance RISC CPU:

• Only 33 single-word instructions to learn

• All single-cycle instructions except for program

branches, which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 10 Special Function Hardware registers

(PIC12F510)

• 13 Special Function Hardware registers

(PIC16F506)

• Operating speed:

- DC – 8 MHz Crystal Oscillator (PIC12F510)

- DC – 500 ns instruction cycle (PIC12F510)

- DC – 20 MHz Crystal Oscillator (PIC16F506)

- DC – 200 ns instruction cycle (PIC16F506)

Special Microcontroller Features:

• 4 or 8 MHz selectable precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR)

• Device Reset Tim er (DRT)

- Short DRT (1.125 ms, typical) for INTOSC, EXTRC and EC

- DRT (18 ms, typical) for HS, XT and LP

• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR

• Selectable internal weak pull-ups on I/O pins

• Power-saving Sleep mode

• Wake-up from Sleep on pin change

• Wake-up from Sleep on comparator change

input pin

• Selectable oscil la tor opti ons :

- INTOSC: 4/8 MHz precision Internal oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator (PIC16F506 only)

- LP: Power-saving, low-frequenc y cry stal

- EC: High-speed external clock input (PIC16F506 only)

• Analog-to-Digital (A/D) Converter

- 8-bit resolution

- 4-input channels (1 channel is dedicated to conversion of the internal 0.6V absolute voltage reference)

• High current sink/source for direct LED drive

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

Low-Power Features/CMOS Technology:

• Operating Current:

- < 350 μA @ 2V, 4 MHz

• Standby Current:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

- 100,000 cycle Flash endurance

- > 40-year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features (PIC12F510):

• 6 I/O pins:

- 5 I/O pins with individual direction control

- 1 input only pin

• 1 Analog Comparator with absolute refe renc e

Peripheral Features (PIC16F506):

• 12 I/O pins:

- 11 I/O pins w ith ind iv idu al dire ct ion contro l

- 1 input only pin

• 2 Analog Comparators with absolute reference and programmable reference

PIC12F510/16F506

Device

Program Memory Data Memory

I/O

Timers

Flash (words) SRAM (bytes)

PIC16F506 1024 67 12 1 PIC12F510 1024 38 6 1

Pin Diagrams

PDIP, SOIC and TS SOP

VSS RB0/AN0/C1IN+/ICSPDAT RB1/AN1/C1IN-/ICSPCLK RB2/AN2/C1OUT RC0/C2IN+ RC1/C2IN-

REF

RC2/CV

VSS GP0/AN0/C1IN+/ICSPDAT GP1/AN1/C1IN-//ICSPCLK GP2/AN2/T0CKI/C1OUT

PDIP, SOIC, MSOP

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR

GP5/OSC1/CLKIN

GP3/MCLR

/VPP

RC5/T0CKI

RC4/C2OUT

RC3

VDD

GP4/OSC2

/VPP

1 2 3 4 5 6 7

1 2 3 4

PIC16F506

PIC12F510

14 13

12 11 10

9 8

8 7 6 5

8-bit

PIC12F510/16F506

Table of Contents

1.0 General Description............................................................................ ....... .... .. .... .. .... ................................................................... 7

2.0 PIC12F510/16F506 Device Varieties ..........................................................................................................................................9

3.0 Architectural Overview...............................................................................................................................................................11

4.0 Memory Organization................................................................................................................................................................. 17

5.0 I/O Port................................ ............. ........................................................... ............................................................................... 29

6.0 TMR0 Module and TMR0 Register.............................................................................................................................................41

7.0 Comparator(s)............................................................................................................................................................................ 45

8.0 Comparator Voltage Reference Module..................................................................................................................................... 51

9.0 Analog-to-Digital (A/D) Converter...............................................................................................................................................53

10.0 Special Features Of The CPU............ ............. ............ ............. ............ ...................................................................................... 57

11.0 Instruction Set Summary ............................................................................................................................................................ 73

12.0 Development Support.................................................................................................................................................................81

13.0 Electrical Characteristics............................................................................................................................................................ 85

14.0 DC and AC Characteristics Graphs and Charts.............................................. .... .... ........... .... .... .... ............................................ 97

15.0 Packaging................................................................................................................................................................................... 99

Index ..................................................................................................................................................................................................109

The Microchip Web Site........................... .......................................................................................................................................... 111

Customer Change Notification Service .............................................................................................................................................. 111

Customer Support.............................................................................................................................................................................. 111

Reader Response. .............................................................................................................................................................................112

Product Identification System............................................................................................................................................................ 113

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC12F510/16F506

NOTES:

PIC12F510/16F506

1.0 GENERAL DESCRIPTION

The PIC12F510/16F506 devices from Microchip T ec hnology are lo w-cost, hig h-performance , 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are singlecycle except for program branches, which take two cycles. The PIC12F510/16F506 devices deliver performance in an o rder of m agnitu de hig her than their competitors in the same pric e category . The 12-bi t wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in i ts class . The easy-to-use a nd easyto-remember instr ucti on se t reduc es de velop ment time significantly.

The PIC12F510/16F506 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F506), including INTOSC Internal Oscillator mode and the power-saving LP (Low-pow er) Osci llator mode. Po wer-sa ving Sle ep mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC12F510/16 F506 de vi ce s a ll ow th e c us tom er to take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibi lit y.

The PIC12F510/16F506 products are supported by a full-featured macr o assembl er , a s oftware simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM compatible machines.

PC and

1.1 Applications

The PIC12F510/16F506 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footpri nt p ackag es, for t hrough h ole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low-cost, lowpower, high-performance, ease-of-use and I/O flexibility make the PIC12F510/16F506 devices very versatile, even in areas where no microcontroller use has been considered b efore (e.g., tim er functions, lo gic and PLDs in larger system s and co processor applications ).

T ABLE 1-1: PIC12F510/16F506 DEVICES

PIC16F506 PIC12F510

Clock Maximum Frequency of Operation (MHz) 20 8 Memory Flash Program Memory 1024 1024

Data Memory (bytes) 67 38

Peripherals Timer Module(s) TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes

Features I/O Pins 11 5

Input Only Pin 1 1 Internal Pull-ups Yes Yes In-Circuit Serial Programming Yes Yes Number of Instructions 33 33 Packages 14-pin PDIP, SOIC,

TSSOP

The PIC12F510/16F506 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F510/16F506 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.

8-pin PDIP, SOIC, MSOP

PIC12F510/16F506

NOTES:

PIC12F510/16F506

2.0 PIC12F510/16F506 DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in th is section. Wh en placing orde rs, please use the PIC12F510/16F506 Product Identification System at the back of this data sheet to specify the correct part number.

2.1 Quick Turn Programming (QTP) Devices

Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices, bu t w ith all Fla sh l oc ati ons and fus e options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your loc al Microchi p Techn ology sales office for more details.

2.2 Serialized Quick Turn Programming

Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.

(SQTPSM) Devices

PIC12F510/16F506

NOTES:

PIC12F510/16F506

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12F510/16F506 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. The PIC12F510/16F506 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetch ed on the sa me bu s. Separating progra m and data memor y further allow s instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bit s wide, making it p ossible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a si ngle cycle (200 ns @ 20 MHz, 1 μs @ 4 MHz) except for program branches.

Table 3-1 lists program memory (Flash) and data memory (RAM) for the PIC12F510/16F506 devices.

T ABLE 3-1: PIC12F510/16F506 MEMORY

Memory

Device

Program Data

PIC12F510 1024 x 12 38 x 8 PIC16F506 1024 x 12 67 x 8

The PIC12F510/16F506 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F510/ 16F506 devices have a highly orthogonal (symmetrical) instruc tion set that makes it possible to carry ou t any operat ion, on any regis ter, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC12F510/16F506 devices simple, yet efficient. In addition, the learning curve is reduced significantly.

The PIC12F510/16F506 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between d ata in the worki ng register and an y register file.

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typica lly t he W (working) regis ter. T he oth er operand is either a file register or an immediate constant. In sing le-operand instr uctions, the operan d is either the W register or a file register.

The W register is an 8-bit workin g register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the ST ATUS register . The C and DC bit s operate as a borrow tively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1 for PIC12F510 with the corresponding device pins described in Table 3-2. A simplified block diagram for PIC16F506 is shown in Figure 3-2 with the corresponding device pins described in T able 3-3.

and digit borrow out bit, respec-

PIC12F510/16F506

FIGURE 3-1: PIC12F510 SERIES BLOCK DIAGRAM

OSC2/OSC1/CLKIN

Program

Bus

Flash

1K x 12

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

10-11

Program Counter

Direct Addr

Device Reset

Watchdog

Internal RC

MCLR

STACK 1 STACK 2

Timer

Power-on

Reset

Timer

Clock

VDD, VSS

RAM Addr

Data Bus

RAM

38 bytes

File

Registers

Addr MUX

5-7 FSR Reg

STATUS Reg

ALU

W Reg

Timer0

MUX

Indirect

Addr

GPIO

Comparator

VREF

8-bit ADC

GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN

C1IN+ C1INC1OU

AN0 AN1 AN2

PIC12F510/16F506

T ABLE 3-2: PIN DESCRIPTIONS – PIC12F510

Name I/O/P Type Input Type Output Type Description

GP0/AN0/C1IN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O port. Can be software programmed

AN0 AN — ADC channel input.

C1IN+ AN — Comparator input.

ICSPDAT ST CMOS In-Circuit Serial Programming data pin.

GP1/AN1/C1IN-/ICSPCLK GP1 TTL CMOS Bidirectional I/O port. Can be software programmed

AN1 AN — ADC channel input.

C1IN- AN — Comparator input.

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

GP2/AN2/T0CKI/C1OUT GP2 TTL CMOS Bidirectional I/O port.

AN2 AN — ADC channel input.

T0CKI ST — Timer0 clock input.

C1OUT CMOS — Comparator output.

GP3/MCLR/

GP4/OSC2 GP4 TTL CMOS Bidirectional I/O port.

GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O port.

DD VDD P — Positive supply for logic and I/O pins.

SS VSS P — Ground reference for logic and I/O pins.

V Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input,

VPP GP3 TTL — Standard TTL input. Can be software programmed

ST — MCLR input – weak pull-up always enabled in this

AN = Analog Voltage

MCLR

PP High Voltage — Program ming Voltage input.

OSC2 — XTAL XTAL oscillator output pin.

OSC1 XTAL — XTAL oscillator input pin.

CLKIN ST — E XTRC Sc hmitt Trigger input.

for internal weak pull-up and wake-up from Sleep on pin change.

mode.

PIC12F510/16F506

FIGURE 3-2: PIC16F506 SERIES BLOCK DIAGRAM

OSC1/CLKIN OSC2/CLKOUT

Program

Bus

Flash 1K x 12 Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

Program Counter

Direct Addr

Device Reset

Watchdog

Internal RC

MCLR

STACK 1 STACK 2

Timer

Power-on

Reset

Timer

Clock

VDD, VSS

RAM Addr

Data Bus

RAM

67 bytes

File

Registers

Addr MUX

5-7 FSR Reg

STATUS Reg

ALU

W Reg

Timer0

MUX

Indirect

Addr

PORTB

PORTC

Comparator 1

VREF

Comparator 2

CVREF

8-bit ADC

RB0/ICSPDAT RB1/ICSPCLK RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN

RC0 RC1 RC2 RC3 RC4 RC5/T0CKI

C1IN+ C1INC1OUT

C2IN+ C2INC2OUT

CVREF

AN0 AN1 AN2

VREF

PIC12F510/16F506

T ABLE 3-3: PIN DESCRIPTIONS – PIC16F506

Name Function Input Type Output Type Description

RB0/AN0/C1IN+/ICSPDAT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for

AN0 AN — ADC channel input.

C1IN+ AN — Comparator 1 input.

ICSPDAT ST CMOS In-Circuit Serial Programming data pin.

RB1/AN1/C1IN-/ICSPCLK RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for

AN1 AN — ADC channel input.

C1IN- AN — Comparator 1 input.

ICSPCLK ST — In-Circuit Serial Programming data pin.

RB2/AN2/C1OUT RB2 TTL CMOS Bidirectional I/O port.

AN2 AN — ADC channel input.

C1OUT — CMOS Comparator 1 output.

RB3/MCLR

RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O port. Can be software programmed for

RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O port.

RC0/C2IN+ RC0 TTL CMOS Bidirectional I/O port.

RC1/C2IN- RC1 TTL CMOS Bidirectional I/O port.

RC2/CV

RC3 RC3 TTL CMOS Bidirectional I/O port. RC4/C2OUT RC4 TTL CMOS Bidirectional I/O port.

RC5/T0CKI RC5 TTL CMOS Bidirectional I/O port.

DD VDD P — Positive supply for logic and I/O pins.

SS VSS P — Ground reference for logic and I/O pins.

V Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input,

/VPP RB3 TTL — Standard TTL input. Can be software programmed for

MCLR

PP High Voltage — Test mode High Voltage pin.

OSC2 — XTA L XTAL oscillator output pin.

CLKOUT — CMOS EXTRC/INTOSC CLKOUT pin (F

OSC1 XTAL — XTAL oscillator input pin.

CLKIN ST — EXTR C/EC Schmitt Trigger input.

C2IN+ AN — Comparator 2 input.

C2IN- AN — Comparator 2 input.

REF RC2 TTL CMOS Bidirectional I/O port.

REF — AN Programmable Voltage Reference output.

C2OUT — CMOS Comparator 2 output.

T0CKI ST — Timer0 Schmitt Trigger input pin.

AN = Analog Voltage

ST — MCLR input – weak pull-up always enabled in this mode.

internal weak pull-up and wake-up from Sleep on pin change.

OSC/4).

PIC12F510/16F506

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is s hown in Figure3-3 and Example 3-1.

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4

3.2 Instruction Flow/Pipelining

An instruction cy cle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g ., GOTO), t hen two c yc le s are required to complete the ins tructi on (Exampl e 3-1).

A fetch cycle begins with the PC incrementing in Q1. In the execution cy cle, the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

PC + 1 PC + 2

Q2 Q3 Q4

Internal Phase Clock

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTB, BIT1 Fetch 4

All instructions are si ngle cycle, except for any program bra nches. These tak e two cycles, since th e fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

Flush

Fetch SUB_1 Execute SUB_1

PIC12F510/16F506

4.0 MEMORY ORGANIZATION

The PIC12F510/16F506 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one ST A TUS regi ster bit. For the PIC12F510 and PIC16F506, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization for the PIC12F510/16F506

The PIC12F510/16F506 devices have a 10-bit Program Counter (PC) c apable o f addressing a 2K x 12 program memory space.

Only the first 1K x 12 (0000 h-03FFh) are physically implemented (see Figure 4- 1). Accessing a location above these boundaries will cause a wraparound within the 1K x 12 space. The effective Reset vector is a 0000h (see Figure 4-1). Location 03FFh contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F510/16F506

PC<11:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

On-chip Program

Memory

512 Word

Space

User Memory

On-chip Program

Memory

1024 Word

(1)

0000h

01FFh 0200h

03FFh 0400h

7FFh

Note 1: Address 0000h becomes the effective

Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value.

PIC12F510/16F506

4.2 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, d ata memory for a device is spec ifie d by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Registers include the TMR0 register, the Program Counter (PCL), the STATUS register, the I/O registers (ports) and the File Select Register (FSR). In addition, Specia l Function Registe rs are used to control the I/O port configuration and prescaler options.

The General Purpose Registers are used for data and control information under com mand of the instructions .

For the PIC12F510, the register file is composed of 10 Special Function Registers, 6 General Purpose Registers and 32 General Purpose Registers acces sed by banking (see Figure 4-5).

For the PIC16F506, the register file is composed of 13 Special Function Registers, 3 General Purpose Registers and 64 General Purpose Registers acces sed by banking (see Figure 4-6).

4.2.1 GENERAL PURPOSE REGISTER FILE

The General Pu rpose Registe r file is accessed either directly or indirectly through the File Select Register (FSR). See Section 4.8 “Indirect Data Addressing:

INDF and FSR Registers”.

FIGURE 4-2: PIC12F510 REGISTER

FILE MAP

FSR<5> 0 1

File Address

00h 01h 02h 03h 04h 05h 06h 07h

08h 09h 0Ah

0Fh

10h

1Fh

Note 1: Not a physical register.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

CM1CON0

ADCON0

ADRES

General Purpose Registers

Bank 0 Bank 1

20h

Addresses map back to addresses in Bank 0.

2Fh

30h

General Purpose Registers

3Fh

FIGURE 4-3: PIC16F506 REGISTER FILE MAP

FSR<6:5> 00 01 10 11

File Address

00h 01h

02h 03h 04h

05h 06h 07h 08h 09h

0Ah 0Bh

0Ch 0Dh

0Fh 10h

1Fh

Note 1: Not a physical register.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB PORTC

CM1CON0

ADCON0

ADRES

CM2CON0

VRCON

General Purpose Registers

Bank 0 Bank 1 Bank 2 Bank 3

20h

Addresses map back to addresses in Bank 0.

2Fh 4Fh 6Fh

30h

General Purpose Registers

3Fh

40h

50h

5Fh

General Purpose Registers

60h

70h

7Fh

General Purpose Registers

PIC12F510/16F506

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and per ipheral functio ns to con trol the operation of the device (see Table 4-1).

The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY – PIC12F510

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS I/O Control Registers (TRISGPIO) --11 1111 N/A OPTION Contains control bits to configure Ti mer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Regis t er xxxx xxxx

(1)

02h 03h STATUS GPWUF CWUF PA0 TO 04h FSR Indirect Data Memory Address Pointer

05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 06h GPIO

07h CM1CON0 C1OUT C1OUTEN 08h ADCON0 ANS1 ANS0 ADCS 1 ADCS0 CHS1 CHS0 GO/D ONE

09h ADRES ADC Conversion Result xxxx xxxx

Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of th e Program Counter is not directly accessible. See Section 4.4 “OPTION Register” for an explanation of

PCL Low Order 8 bits of PC 1111 1111

PD ZDCC0001 1xxx

— 1111 111-

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx

C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111

ADON 1111 1100

how to access these bits.

Value on

Power-on

Reset

110x xxxx

TABLE 4-2: SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS I/O Control Registers (TRISB, TRISC) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx

(1)

02h 03h STATUS RBWUF CWUF PA0 TO

04h FSR Indirect Data Memory Address Pointer 100x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 06h PORTB 07h PORTC

08h CM1CON0 C1OUT C1OUTEN 09h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE

0Ah ADRES ADC Conversion Result xxxx xxxx 0Bh CM2CON0 C2OUT C2OUTEN

0Ch VRCON VREN VROE VRR

PCL Low Order 8 bits of PC 1111 1111

PD ZDCC0001 1xxx

— 1111 111- — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx

C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111

ADON 1111 1100

C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111

—VR3VR2VR1VR0001- 1111

how to access these bits.

Value on

Power-on

Reset

PIC12F510/16F506

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO

and PD bits are not

For example, CLRF STATUS, will c lea r the up per three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. The se in structions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 11.0 “Instruction Set Summary”.

writable. Therefore, the result of an instruction with the STATUS regis ter as destina tion may be differ ent than intended.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-X R/W-X R/ W-X

GPWUF CWUF PA0 TO

bit 7 bit 0

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 CWUF: Comparator Reset bit

1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset

bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for prog ram page preselect is not recommended, since this may affect upward compatibility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instructi on

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF: SUBWF: RRF or RLF:

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

PD ZDCC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F510/16F506

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-X R/W-X R/W-X

RBWUF CWUF PA0 TO

bit 7 bit 0

bit 7 RBWUF: PORTB Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 CWUF: Comparator Reset bit

1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset

bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instructi on

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF: SUBWF: RRF or 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

PD ZDCC

RLF:

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F510/16F506

4.4 OPTION Register

The OPTION re gister is a 8-bit wid e, write-only register , that contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executin g the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits.

Note 1: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU and GPWU/RBWU).

2: If the T0CS bit is set to ‘1’, it wil l ove r ri de

the TRIS function on the T0CKI pin.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit 7 bit 0

GPPU T0CS T0SE PSA PS2 PS1 PS0

/RBPU

bit 7 GPWU

bit 6 GPPU

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU

bit 7 bit 0

RBPU T0CS T0SE PSA PS2 PS1 PS0

PIC12F510/16F506

bit 7 R

bit 6 R

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

BWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

BPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F510/16F506

4.5 OSCCAL Register

The Oscillator Calibrati on (OSCCAL) register is used to calibrate the internal precision 4/8 MHz oscillator. It contains seven bit s for cal ibra tio n

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogramm ed correctly later.

After you move in the calibration constant, do not change the value. See Section 10.2.5 “Internal 4/8 MHz RC

Oscillator”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0

bit 7 bit 0

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 = Maximum frequency

•

0000001 0000000 = Center frequency

1111111

•

• 1000000 = Minimum frequency

bit 0 Unimplemented: Read as ‘0’

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F510/16F506

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure4-4).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruct ion word, but is alway s cleared (Figure 4-4).

Instructions where t he PCL is the des tinati on or modif y PCL instructi ons include MOVWF PC, ADDWF PC and BSF PC, 5.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program me mory page (512 words long).

FIGURE 4-4: LOADING OF PC

BRANCH INSTRUCTIONS

GOTO Instruction

87 0

STATUS

PCL

Instruction Word

PA0

4.6.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code.

The STATUS register page preselect bits are cleared upon a Reset, which m eans that p age0 is preselected.

Therefore, upon a Reset, a GOTO instruction will automatically c ause the program t o jump to page0 until the value of the page bits is altered.

4.7 Stack

The PIC12F510/16F 506 de vi ce s h av e a 2-d ee p, 12-bit wide hardware PUSH/POP stack.

A CALL instru ction will PUSH the curre nt value of S t ack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored.

A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into S t ack Level 1. If more tha n two sequentia l RETLWs are execute d, the stack will be fi lled with the address previously stored in Stack Level 2.

Note 1: The W register will be loaded with the lit-

eral value spec ified in the ins truction. This is particularly useful for the implementation of data look-up tables within the program memory.

2: There are no Status bits to indicate stack

overflows or stack underflow conditions.

3: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the e xecution of the CALL and RETLW instructions.

CALL or Modify PCL Instruction

87 0

Reset to ‘0’ PA0

STATUS

PCL

Instruction Word

PIC12F510/16F506

4.8 Indirect Data Addressing: INDF

EXAMPLE 4-1: HOW TO CLEAR RAM

and FSR Registers

The INDF register is not a physi cal register. Addressing INDF actually address es the reg ister whos e addres s is contained in the FSR regis ter (FSR is a pointer). This is indirect addressing.

NEXT CLRF INDF ;clear INDF register

4.8.1 INDIRECT ADDRESSING EXAMPLE

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF regi ster will return the value of 10h

• Increment the value of the FSR register by one (FSR = 08)

• A read of the INDR register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addres sing is shown in Example 4-1.

CONTINUE

The FSR is a 5-bit wide register. It is used in conjunction with the INDF regis ter to indirectly a ddress the dat a memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC16F506 – Uses FSR<6:5>. Selects from Bank 0 to Bank 3. FSR<7> is unimplemented, read as ‘1’.

PIC12F510 – Uses FSR<5>. Selects from Bank 0 to Bank 1. FSR<7:6> are unimplemented, read as ‘11’.

FIGURE 4-5: DIRECT/INDIRECT ADDRESSING (PIC12F510)

Direct Addressing

(FSR) 6

(opcode)

321

MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM

INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next

USING INDIRECT ADDRESSING

: ;YES, continue :

Indirect Addressing

(FSR)

bank select

Note 1: For register map detail, see Figure 4-2.

location select

Data Memory

00 01

00h

0Fh

(1)

10h

1Fh 3Fh

Bank 0 Bank 1

Addresses map back to addresses in Bank 0.

bank select

location select

PIC12F510/16F506

FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC16F506)

Direct Addressing

(FSR)

65 43210

Bank Select Location Select

Note 1: For register map detail, see Figure 4-3.

(opcode)

Data Memory

00 01 10 11

00h

0Fh

(1)

10h

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Addresses map back to addresses in Bank 0.

Indirect Addressing

(FSR)

6543210

Bank

Location Select

PIC12F510/16F506

NOTES:

PIC12F510/16F506

5.0 I/O PORT

As with any other register, the I/O register(s) can be written and read under pro gram contro l. However, read instructions (e.g., MOVF PORTB, W) always read th e I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set.

Note: On the PIC12F510, I/O PORTB is refer-

enced as GPIO. On the PIC16F506, I/O PORTB is referenced as PORTB.

5.1 PORTB/GPIO

PORTB/GPIO is an 8-bit I/O register. Only the loworder 6 bits a re used ( RB/GP<5: 0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Please note that RB3/ GP3 is an input only pin. The Configuration Word can set several I/O ’ s t o a lte rnate fu nc tio ns. When acting as alternate function s, the pins wil l read as ‘0’ during a port read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4 (PIC16F506 only) can be configured with weak pull-up and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If RB3/GP3/MCLR pull-up is always on and wake-u p on change for this pin is not enabled.

5.2 PORTC (PIC16F506 Only)

PORTC is an 8-bit I/O register . Only the lo w-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s.

is configured as MCLR, weak

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except RB3/GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding directio n contro l bit in TR IS must be c leared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3/GP3) can be programmed individually as input or output.

FIGURE 5-1: PIC12F510/16F506

Data Bus

Data

Bus

Interface

Reset

EQUIVALENT CIRCUIT FOR PIN DRIVE

VDD

(2)

VDD

(1)

I/O pin

VSS

5.3 TRIS Registers

The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f

Note 1: GP3/RB3 has protection diode to V

2: For pin specific information, see Figure 5-2

through Figure 5-1 3.

SS only.

instruction. A ‘1’ from a TRIS register bi t puts the corresponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, e nabling the outp ut buffer . The exception is RB3/GP3, which are input only, and the T0CKI pin, which may be controlled by the OPTION register. See Register 4-3.

Note: A read of the port reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high but the external system is holding it low, a read of the port will indicate that the pin is low.

Note: The TRIS registers are “write-only” and

are set (output drivers disabled) upon Reset.

PIC12F510/16F506

)

FIGURE 5-2: BLOCK DIAGRAM OF

GP0/RB0 AND GP1/RB1

GPPU RBPU

Data Bus

WR Port

W Reg

TRIS ‘f’

ADC pin Ebl COMP pin Ebl

Data Latch

TRIS Latch

Reset

I/O Pin

FIGURE 5-3: BLOCK DIAGRAM OF

GP3/RB3 (With Weak Pull-up And Wake-up On Change)

GPPU

RBPU

MCLRE

(1)

Reset

I/O Pin

Data Bus

RD Port

Mis-Match

ADC

COMP

Note 1: I/O pins have protection diodes to VDD and

SS.

Mis-match

Note 1: GP3/MCLR pin has a protection diode to VSS

only.

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