MICROCHIP PIC12F508, PIC12F509, PIC16F505 DATA SHEET

PIC12F508/509/16F505

Data Sheet

8/14-Pin, 8-Bit Flash Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MP SIM, PICkit , PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC12F508/509/16F505

8/14-Pin, 8-Bit Flash Microcontroller

Devices Included In This Data Sheet:

•PIC12F508

•PIC12F509

•PIC16F505

High-Performance RISC CPU:

• Only 33 single-word instructions to learn

• All single-cycle instructions except for program

branches, which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 8 Special Function Hardware registers

• Operating speed:

- DC – 20 MHz clock input (PIC16F505 only)

- DC – 200 ns instruction cycle (PIC16F505 only)

- DC – 4 MHz clock input

- DC – 1000 ns instruction cycle

Special Microcontroller Features:

• 4 MHz precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR)

• Device Reset Tim er (DRT)

• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR

• Internal weak pull-ups on I/O pins

• Power-saving Sleep mode

• Wake-up from Sleep on pin change

• Selectable oscillator options:

- INTRC: 4 MHz precision Internal oscillator

- EXTRC: Ext ernal low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

input pin

(PIC16F505 only)

- LP: Power-saving, low-frequency crystal

- EC: High-speed external clock input (PIC16F505 only)

Low-Power Features/CMOS Technology:

• Operating Current:

- < 350 μA @ 2V, 4 MHz

• Standby Current:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

- 100,000 Flash endurance

- > 40 year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features (PIC12F508/509):

• 6 I/O pins:

- 5 I/O pins with individual direction control

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

Peripheral Features (PIC16F505):

• 12 I/O pins:

- 11 I/O pins w ith ind iv idu al dire ct ion contro l

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

PIC12F508/509/16F505

Pin Diagrams

PDIP, SOIC, TSSOP

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR

/VPP

RC5/T0CKI

RC4 RC3

1 2 3 4

5 6 7

14 13 12 11

PIC16F505

9 8

VSS RB0/ICSPDAT RB1/ICSPCLK

RB2 RC0

RC1 RC2

PDIP, SOIC, MSOP

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR

/VPP

1 2 3 4

8 7 6 5

PIC12F508/509

VSS GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI

Device

Program Memory Data Memory

I/O

Timers

Flash (words) SRAM (bytes)

PIC12F508 512 25 6 1 PIC12F509 1024 41 6 1 PIC16F505 1024 72 12 1

8-bit

PIC12F508/509/16F505

Table of Contents

1.0 General Description............................................................................ ....... .... .. .... .. .... ................................................................... 5

2.0 PIC12F508/509/16F505 Device Varieties ......................................................................... .. .... .... ................................................ 7

3.0 Architectural Overview................................................................................................................................................................. 9

4.0 Memory Organization.................................................................................................................................................................15

5.0 I/O Port................................ ............. ............. ............ ............. ............ ............. ...........................................................................29

6.0 Timer0 Module and TMR0 Register........................................................................................................................................... 33

7.0 Special Feature s Of The CPU.......... ......................... ............. ............ .......................... .............................................................. 39

8.0 Instruction Set Summary............................................................................................................................................................ 55

9.0 Development Support................................................................................................................................................................. 63

10.0 Electrical Characteristics............................................................................................................................................................67

11.0 DC and AC Characteristics Graphs and Charts................................................................... .... .... .............................................. 79

12.0 Packaging Information. ............. ......................... ............ ............. ............. ............ .......................................................................81

Index .................................................................................................................................................................................................... 91

The Microchip Web Site........................... ............ ............. ............. ............ ............. ............ ... .............................................................. 93

Customer Change Notification Service ................................................................................................................................................ 93

Customer Support................................................................................................................................................................................ 93

Reader Response. ............................................................................................................................................................................... 94

Product Identification System.............................................................................................................................................................. 95

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Customer Notification System

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

1.0 GENERAL DESCRIPTION

The PIC12F508/509/16F505 devices from Microchip T ec hnology are lo w-cost, hig h-performance , 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (200 μs) except for program branches, which take two cycles. The PIC12F508/509/16F505 devices deliver performanc e an order of magnit ude high er than their competitors in t he same price c ategory. Th e 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly.

The PIC12F508/509/16F505 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset T imer (DR T) elimina te the need for external Reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F 50 5), inclu din g INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC12F508/509/16F505 devices are available in the cost-e ffective Fl ash progr ammable ver sion, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility.

The PIC12F508/509/16F505 products are supported by a full-featured mac ro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM compatible machines.

PC and

1.1 Applications

The PIC12F508/509/16F505 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footpri nt p ackag es, for t hrough h ole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low cost, low power , high pe rformance, ea se of use and I/O fl exibilit y make the PIC12F508/509/16F505 devices very versatile even in areas where no microcontroller use has been considered b efore (e.g., tim er functions, lo gic and PLDs in larger system s and co processor applications ).

T ABLE 1-1: PIC12F508/509/16F505 DEVICES

PIC12F508 PIC12F509 PIC16F505

Clock Maximum Frequency of Operation (MHz) 4 4 20 Memory Flash Program Memory 512 1024 1024

Data Memory (bytes) 25 41 72

Peripherals Timer Module(s) TMR0 TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes Yes

Features I/O Pins 5 5 11

Input Pins 1 1 1 Internal Pull-ups Yes Yes Yes In-Circuit Serial Programming Yes Yes Yes Number of Instructions 33 33 33 Packages 8-pin PDIP, SOIC,

MSOP

The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F508/509/16F505 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.

8-pin PDIP, SOIC,

MSOP

14-pin PDIP, SOIC,

TSSOP

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

2.0 PIC12F508/509/1 6F5 05 DEVIC E VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in th is section. Wh en placing orde rs, please use the PIC12F508/509/16F505 Product Identification System at the back of this data sheet to specify the correct part number.

2.1 Quick Turn Programming (QTP) Devices

Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your loc al Microchi p Technology sales off ice for more details.

2.2 Serialized Quick Turn Programming

Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.

(SQTPSM) Devices

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

3.0 ARCHITECTURAL OVERVIEW

The high perfor ma nce of t he P IC 12F 508/ 509 /1 6F 505 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F508/509/16F505 devices use a Harvard ar chit ectur e in whi ch progr am and da ta are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separati ng pro gr am an d data mem or y fur ther allows instructions to be sized differently than the 8-bit wide data w ord. Instr uction opcode s are 12 b its wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycl e (200 ns @ 20 MHz, 1 μs @ 4 MHz) except for program branches.

T abl e 3-1 below list s program m emory (Flash) a nd data memory (RAM) for the PIC12F508/509/16F505 devices.

TABLE 3-1: PIC12F508/509/16F505

MEMORY

The PIC12F508/509/16F505 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions be tween dat a in the work ing regist er and any register file.

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typica lly t he W (working) register. T he oth er operand is either a file register or an immediate constant. In sing le ope ran d inst ruction s, the operan d is either the W register or a file register.

The W register is an 8-bit workin g register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the ST ATUS register . The C and DC bit s operate as a borrow tively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure3-2, with the corresponding device pins described in Table 3-3.

and digit borrow out bit, respec-

Device

Program Data

PIC12F508 512 x 12 25 x 8 PIC12F509 1024 x 12 41 x 8 PIC16F505 1024 x 12 72 x 8

The PIC12F508/509/16F505 devices can directly or indirectly address its reg ister file s and dat a mem ory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F508/509/ 16F505 devices have a highly orthogonal (symmetrical) instruc tion set that makes it possible to carry ou t any operat ion, on any regis ter, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC12F508/509/16F505 devices simple, yet efficient. In addition, the learning curve is reduced significantly.

Memory

PIC12F508/509/16F505

FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM

OSC1/CLKIN

OSC2

Program

Bus

Flash

512 x 12 or

1024 x 12

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

Internal RC

OSC

Program Counter

Stack 1 Stack 2

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD, VSS

RAM Addr

Data Bus

Addr MUX

RAM

25 x 8 or

File

Registers

5-7

FSR Reg

Status Reg

MUX

ALU

W Reg

Timer0

Indirect

Addr

GPIO

GP0/ISCPDAT GP1/ISCPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN

PIC12F508/509/16F505

TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION

Name Function

GP0/ICSPDA T GP0 TTL CMOS Bidirectional I/O pin. Can b e software prog rammed for inte rnal

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

GP1\ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be so ftware program med for internal

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak

MCLR

PP HV — Programming voltage input.

GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin.

OSC2 — XTAL Oscillator cr ystal output. C onnection s to cr ystal or resonato r in

GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Oscillator crystal input. CLKIN ST — External clock source input.

DD VDD — P Positive supply for logic and I/O pins.

SS VSS — P Ground reference for logic and I/O pins.

V Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input

Input

Type

Output

Type

weak pull-up and wake-up from Sleep on pin change.

pull-up and wake-up from Sleep on pin change.

ST — Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device . V ol tage on MCLR not exceed V will enter Programming mode. Weak pull-up always on if configured as MCLR

Crystal Oscill ator mode (XT and LP m odes only, GPIO in other modes).

DD during normal device operation or the device

Description

/VPP must

PIC12F508/509/16F505

FIGURE 3-2: PIC16F505 BLOCK DIAGRAM

Program

OSC1/CLKIN OSC2/CLKOUT

Bus

Instruction Reg

Instruction

Decode &

Generation

Flash

1K x 12

Program

Memory

Control

Timing

Program Counter

Stack 1 Stack 2

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Internal RC

OSC

RAM Addr

Data Bus

Addr MUX

RAM

File

Registers

5-7

FSR Reg

Status Reg

MUX

ALU

W Reg

Timer0

Indirect

Addr

PORTB

RB0/ICSPCLK RB1/ICSPDAT RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN

PORTC

RC0 RC1 RC2 RC3 RC4 RC5/T0CKI

MCLR

VDD, VSS

PIC12F508/509/16F505

TABLE 3-3: PIC16F505 PINOUT DESCRIPTION

Name Function

RB0/ICSPDA T RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for i nternal

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

RB1/ICSPCLK RB1 TTL CMOS Bid irectional I/O pin. Can be so ftware program med for internal

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin. RB2 RB2 TTL CMOS Bidirectional I/O pin. RB3/MCLR

RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can b e software prog rammed for inte rnal

RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin.

RC0 RC0 TTL CMOS Bidirectional I/O pin. RC1 RC1 TTL CMOS Bidirectional I/O pin. RC2 RC2 TTL CMOS Bidirectional I/O pin. RC3 RC3 TTL CMOS Bidirectional I/O pin. RC4 RC4 TTL CMOS Bidirectional I/O pin. RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin.

DD VDD — P Positive supply for logic and I/O pins.

SS VSS — P Ground reference for logic and I/O pins.

V Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

/VPP RB3 TTL — Input port. Can be software programmed for internal weak

MCLR ST — Master Clear (Reset). When configured as MCLR, thi s pin is

VPP — — Programming voltage input.

OSC2 — XTAL Oscillator cr ystal output. C onnection s to cr ystal or resonato r in

CLKOUT — CMOS In EXTRC and INTRC modes, the pin output can be

OSC1 XTAL — Crystal input. CLKIN ST — External clock source input.

T0CKI ST — Clock input to TMR0.

ST = Schmitt Trigger input

Input

Type

Output

Type

Description

weak pull-up and wake-up from Sleep on pin change.

pull-up and wake-up from Sleep on pin change.

an active-low Reset to the device . V ol tage on MCLR not exceed V will enter Programming mode. Weak pull-up always on if configured as MCLR.

weak pull-up and wake-up from Sleep on pin change.

Crystal Oscillator mode (XT, HS and LP modes only).

configured for CLKOUT, which has 1/4 the frequenc y of OSC1 and denotes the instruction cycle rate.

DD during normal device operation or the device

/VPP must

PIC12F508/509/16F505

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internal ly divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is s hown in Figure3-3 and Example 3-1.

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

3.2 Instruction Flow/Pipelining

An instruction cy cle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g ., GOTO), t hen two c yc le s are required to complete the ins tructi on (Exampl e 3-1).

A fetch cycle begins with the PC incrementing in Q1. In the execution cy cle, the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

PC + 1 PC + 2

Q2 Q3 Q4

Internal phase clock

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTB, BIT1

All instructions are si ngle cycle, except for any program bra nches. These tak e two cycles, since th e fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then ex ecuted.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC12F508/509/16F505

4.0 MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized into program memory and data memory. For devices with more than 512 byte s of program me mory , a p aging scheme is used. Program memory pages are accessed using one Status register bit. For the PIC12F509 and PIC16F505, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Orga nization for the PIC12F508/509

The PIC12F508 device has a 10-bit Program Counter (PC) and PIC12F509 has a 11-bit Program Counter (PC) capable of add ressing a 2K x 12 program me mory space.

Only the first 512 x 12 (0000h-01FFh) for the PIC12F508, and 1K x 12 (0000h-03FFh) for the PIC12F509 are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12F508) or 1K x 12 space (PIC12F509). The effective Reset vector is a 000 0h (see Figure 4-1). L ocation 01FFh (PIC12F508) and location 03FFh (PIC12F509) contain the internal clock oscillator calibration value. This value shou ld never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F508/509

PC<11:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

On-chip Program

Memory

512 Word

Space

User Memory

On-chip Program

Memory

1024 Word

(1)

0000h

01FFh 0200h

03FFh 0400h

7FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location 01FFh, 03FFh (PIC12F508, PIC12F509) contains the MOVLW XX internal oscillator calibration value.

PIC12F508/509/16F505

4.2 Program Memory Organization For The PIC16F505

The PIC16F505 device has a 11-bit Program Counter (PC) capable of add ressing a 2K x 12 program me mory space.

The 1K x 12 (0000h-03FFh) for the PIC16F505 are physically implemented. Refer to Figure 4-2. Accessing a location above this boundary will cause a wraparound within the first 1K x 12 space. The effective Reset vector is at 0000h (see Figure 4-2). Location 03FFh contains th e in tern al osc il la tor c ali bration value. This value should never be overwritten.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16F505

PC<11:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

Space

User Memory

On-chip Program

Memory

(1)

0000h

01FFh 0200h

4.3 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, da ta memory for a device is speci f ie d by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Regi st ers in cl ude the TMR0 register, the Program Counter (PCL), the STAT US register , the I/O registers (ports) and the File Select Register (FSR). In addition, Special Func tion Registers are use d to control the I/O port configuration and prescaler options.

The General Purpose Registers are used for data and control informatio n u nd er com ma nd of the instructions.

For the PIC12F508/509, the register file is composed of 7 Special Function Registers, 9 General Purpose Registers and 16 or 32 General Purpose Registers accessed by banking (see Figure 4-3 and Figure 4-4).

For the PIC16F505, the register file is composed of 8 Special Function Registers, 8 General Purpose Registers and 64 General Pu rpose Registers accesse d by banking (Figure4-5).

4.3.1 GENERAL PURPOSE REGISTER FILE

The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

1024 Words

Note 1: Address 0000h becomes the

effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value.

03FFh 0400h

7FFh

PIC12F508/509/16F505

FIGURE 4-3: PIC12F508 REGISTER

FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

FIGURE 4-4: PIC12F509 REGISTER

FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General Purpose Registers

Bank 0 Bank 1

20h

Addresses map back to addresses in Bank 0.

2Fh

30h

General Purpose Registers

3Fh

FIGURE 4-5: PIC16F505 REGISTER FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h 08h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB PORTC

General Purpose Registers

Bank 0

20h

2Fh

30h

General Purpose Registers

3Fh

Bank 1

40h

Addresses map back to addresses in Bank 0.

4Fh

50h

General Purpose Registers

5Fh

Bank 2

60h

6Fh 70h

General Purpose Registers

7Fh

Bank 3

PIC12F508/509/16F505

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and per ipheral functio ns to con trol the operation of the device (Table 4-1).

The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33

(1)

02h 03h STATUS GPWU

04h FSR Indirect Data Memory Address Pointer 111x xxxx 26 04h 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24 06h GPIO N/A TRISGPIO — — I/O Control Register --11 1111 29 N/A OPTION GPWU

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter”

PCL Low-order 8 bits of PC 1111 1111 25

—PA0

(4)

FSR Indirect Data Memory Address Pointer 110x xxxx 26

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 29

GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 22

for an explanation of how to access these bits.

2: Other (non Power-up) Resets include externa l Reset th rough MCLR

change Reset.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 4: PIC12F509 only. 5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

(5)

TO PD ZDCC0-01 1xxx

, Watchdog Timer and wake-up on pin

Power-On

(2)

Reset

xxxx xxxx 26

(3)

Page #

PIC12F508/509/16F505

TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33

(1)

02h 03h STATUS RBWUF 04h FSR Indirect Data Memory Address Pointer 110x xxxx 26 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24

06h PORTB 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 29 N/A TRISB — — I/O Control Register --11 1111 29 N/A TRISC N/A OPTION RBWU

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

PCL Low-order 8 bits of PC 1111 1111 25

—PA0TO PD ZDCC0-01 1xxx 20

— — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 29

— — I/O Control Register --11 1111 29

RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 23

2: Other (non Power-up) Resets include external reset through MCLR

change Reset.

, Watchdog Timer and wake-up on pin

Power-On

Reset

xxxx xxxx 26

(2)

Page #

PIC12F508/509/16F505

4.4 STATUS Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO

and PD bits are not

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. The se in structions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect S tatus bits, see Section 8.0 “Instruction Set Summary”.

writable. Therefore, the result of an instruction with the STATUS regis ter as destina tion may be differ ent than intended.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF

bit 7 bit 0

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for prog ram page preselect is not recommended, since this may affect upward compatibility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instructi on

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

ADDWF

: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

—PA0TO PD ZDCC

(1)

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508.

PIC12F508/509/16F505

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

RBWUF

bit 7 bit 0

bit 7 RBWUF: PORTB Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the P A 0 bit as a gene ral purpos e read/wri te bit in de vices whi ch do not u se it for program page presele ct is not recommen ded, since this may affect upward compatib ility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

—PA0TO PD ZDCC

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.5 OPTION Register

The OPTION re gister is a 8-bit wid e, write-only register , which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executin g the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit 7 bit 0

GPPU T0CS T0SE PSA PS2 PS1 PS0

Note: If TRIS bit is set to ‘0’, the wake-up on

Note: If the T0CS bit is set to ‘1’, it will override

change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU GPWU

/RBWU).

the TRIS function on the T0CKI pin.

/RBPU and

bit 7 GPWU

bit 6 GPPU

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescale r Rate Select bits

: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU

bit 7 bit 0

RBPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 RBWU

bit 6 RBPU

bit 5 T0CS: Timer0 clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assign ment bit

bit 2-0 PS<2:0>: Prescale r Rate Select bits

: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.6 OSCCAL Register

The Oscillator Calibrati on (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bit s for cal ibra tio n

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogramm ed correctly later.

After you move in the calibration constant, do not change the value. See Section 7.2.5 “Internal 4 MHz

RC Oscillator”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

bit 7 bit 0

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 =Maximum frequency

•

0000001 0000000 =Center frequency

1111111

•

• 1000000 =Minimum frequency

bit 0 Unimplemented: Read as ‘0’

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.7 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure4-6).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruct ion word, but is alway s cleared (Figure 4-6).

Instructions wh ere the PCL is th e destinatio n, or modif y PCL instructions, incl ude MOVWF PC, ADDWF PC and

BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program me mory page (512 words long).

FIGURE 4-6: LOADING OF PC

BRANCH INSTRUCTIONS

GOTO Instruction

7 0

87 0

910

PCL

Instruction Wor d

PA0

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code.

The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is pre-selected.

Therefore, upon a Reset, a GOTO instruction will automatically c ause the program t o jump to page0 until the value of the page bits is altered.

4.8 Stack

The PIC12F508/509/16F505 devices have a 2-deep, 12-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of Stack 1 into S t a ck 2 an d t he n PUS H th e c ur ren t PC v a lu e, in cre mented by one, into Stack Level 1. If more than two sequential CALLs are executed, o nly the mo st recen t two return addresses a re s tor ed .

A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into S t ack Level 1. If more tha n two sequentia l RETLWs are execute d, the stack will be fi lled with the address previously stored in Stack Level 2. Note that the W register will be loaded with the literal value specified in the i nstruction. Th is is particu larly useful f or the implementation of data look-up tables within the program memory.

Note 1: There are no Status bits to indicate stack

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the e xecution of the CALL and RETLW instructions.

Status

CALL or Modify PCL Instruction

87 0

910

Reset to ‘0’

PA0

7 0

Status

PCL

Instruction Word

PIC12F508/509/16F505

4.9 Indirect Data Addressing: INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

4.9.1 INDIREC T ADDRES SING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF

;register INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue :

The FSR is a 5-bit wide register. It is used in conjunctio n with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC12F508 – Does not use banking. FSR <7:5> are unimplemented and read as ‘1’s.

PIC12F509 – Uses FSR<5>. Select s between ba nk 0 and bank 1. FSR<7:6> is unimp lemented , read as ‘1’.

PIC16F505 – Uses FSR<6:5>. S elects fro m bank 0 to bank 3. FSR<7> is unimplemented, read as ‘1’.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509)

Direct Addressing

(FSR)

Bank Select

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

2: PIC12F509.

Location Select

Data Memory

(opcode) 04

00 01

00h

Addresses map back to addresses in Bank 0.

0Fh

(1)

10h

1Fh 3Fh

Bank 0 Bank 1

(2)

Indirect Addressing

Bank

(FSR)

Location Select

PIC12F508/509/16F505

FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505)

Direct Addressing

(FSR)

6 5 4 (opcode) 0

Bank Select Location Select

00h

Data Memory

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

0Fh

(1)

10h

00 01 10 11

Addresses map back to addresses in Bank 0.

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Indirect Addressing

6 5 4 (FSR) 0

Bank

Location Select

PIC12F508/509/16F505

NOTES:

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