MICROCHIP PIC12F508, PIC12F509, PIC16F505 DATA SHEET

PIC12F508/509/16F505

Data Sheet

8/14-Pin, 8-Bit Flash Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MP SIM, PICkit , PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC12F508/509/16F505

8/14-Pin, 8-Bit Flash Microcontroller

Devices Included In This Data Sheet:

•PIC12F508

•PIC12F509

•PIC16F505

High-Performance RISC CPU:

• Only 33 single-word instructions to learn

• All single-cycle instructions except for program

branches, which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 8 Special Function Hardware registers

• Operating speed:

- DC – 20 MHz clock input (PIC16F505 only)

- DC – 200 ns instruction cycle (PIC16F505 only)

- DC – 4 MHz clock input

- DC – 1000 ns instruction cycle

Special Microcontroller Features:

• 4 MHz precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR)

• Device Reset Tim er (DRT)

• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR

• Internal weak pull-ups on I/O pins

• Power-saving Sleep mode

• Wake-up from Sleep on pin change

• Selectable oscillator options:

- INTRC: 4 MHz precision Internal oscillator

- EXTRC: Ext ernal low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

input pin

(PIC16F505 only)

- LP: Power-saving, low-frequency crystal

- EC: High-speed external clock input (PIC16F505 only)

Low-Power Features/CMOS Technology:

• Operating Current:

- < 350 μA @ 2V, 4 MHz

• Standby Current:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

- 100,000 Flash endurance

- > 40 year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features (PIC12F508/509):

• 6 I/O pins:

- 5 I/O pins with individual direction control

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

Peripheral Features (PIC16F505):

• 12 I/O pins:

- 11 I/O pins w ith ind iv idu al dire ct ion contro l

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

PIC12F508/509/16F505

Pin Diagrams

PDIP, SOIC, TSSOP

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR

/VPP

RC5/T0CKI

RC4 RC3

1 2 3 4

5 6 7

14 13 12 11

PIC16F505

9 8

VSS RB0/ICSPDAT RB1/ICSPCLK

RB2 RC0

RC1 RC2

PDIP, SOIC, MSOP

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR

/VPP

1 2 3 4

8 7 6 5

PIC12F508/509

VSS GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI

Device

Program Memory Data Memory

I/O

Timers

Flash (words) SRAM (bytes)

PIC12F508 512 25 6 1 PIC12F509 1024 41 6 1 PIC16F505 1024 72 12 1

8-bit

PIC12F508/509/16F505

Table of Contents

1.0 General Description............................................................................ ....... .... .. .... .. .... ................................................................... 5

2.0 PIC12F508/509/16F505 Device Varieties ......................................................................... .. .... .... ................................................ 7

3.0 Architectural Overview................................................................................................................................................................. 9

4.0 Memory Organization.................................................................................................................................................................15

5.0 I/O Port................................ ............. ............. ............ ............. ............ ............. ...........................................................................29

6.0 Timer0 Module and TMR0 Register........................................................................................................................................... 33

7.0 Special Feature s Of The CPU.......... ......................... ............. ............ .......................... .............................................................. 39

8.0 Instruction Set Summary............................................................................................................................................................ 55

9.0 Development Support................................................................................................................................................................. 63

10.0 Electrical Characteristics............................................................................................................................................................67

11.0 DC and AC Characteristics Graphs and Charts................................................................... .... .... .............................................. 79

12.0 Packaging Information. ............. ......................... ............ ............. ............. ............ .......................................................................81

Index .................................................................................................................................................................................................... 91

The Microchip Web Site........................... ............ ............. ............. ............ ............. ............ ... .............................................................. 93

Customer Change Notification Service ................................................................................................................................................ 93

Customer Support................................................................................................................................................................................ 93

Reader Response. ............................................................................................................................................................................... 94

Product Identification System.............................................................................................................................................................. 95

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Customer Notification System

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

1.0 GENERAL DESCRIPTION

The PIC12F508/509/16F505 devices from Microchip T ec hnology are lo w-cost, hig h-performance , 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (200 μs) except for program branches, which take two cycles. The PIC12F508/509/16F505 devices deliver performanc e an order of magnit ude high er than their competitors in t he same price c ategory. Th e 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly.

The PIC12F508/509/16F505 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset T imer (DR T) elimina te the need for external Reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F 50 5), inclu din g INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC12F508/509/16F505 devices are available in the cost-e ffective Fl ash progr ammable ver sion, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility.

The PIC12F508/509/16F505 products are supported by a full-featured mac ro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM compatible machines.

PC and

1.1 Applications

The PIC12F508/509/16F505 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footpri nt p ackag es, for t hrough h ole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low cost, low power , high pe rformance, ea se of use and I/O fl exibilit y make the PIC12F508/509/16F505 devices very versatile even in areas where no microcontroller use has been considered b efore (e.g., tim er functions, lo gic and PLDs in larger system s and co processor applications ).

T ABLE 1-1: PIC12F508/509/16F505 DEVICES

PIC12F508 PIC12F509 PIC16F505

Clock Maximum Frequency of Operation (MHz) 4 4 20 Memory Flash Program Memory 512 1024 1024

Data Memory (bytes) 25 41 72

Peripherals Timer Module(s) TMR0 TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes Yes

Features I/O Pins 5 5 11

Input Pins 1 1 1 Internal Pull-ups Yes Yes Yes In-Circuit Serial Programming Yes Yes Yes Number of Instructions 33 33 33 Packages 8-pin PDIP, SOIC,

MSOP

The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F508/509/16F505 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.

8-pin PDIP, SOIC,

MSOP

14-pin PDIP, SOIC,

TSSOP

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

2.0 PIC12F508/509/1 6F5 05 DEVIC E VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in th is section. Wh en placing orde rs, please use the PIC12F508/509/16F505 Product Identification System at the back of this data sheet to specify the correct part number.

2.1 Quick Turn Programming (QTP) Devices

Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your loc al Microchi p Technology sales off ice for more details.

2.2 Serialized Quick Turn Programming

Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.

(SQTPSM) Devices

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

3.0 ARCHITECTURAL OVERVIEW

The high perfor ma nce of t he P IC 12F 508/ 509 /1 6F 505 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F508/509/16F505 devices use a Harvard ar chit ectur e in whi ch progr am and da ta are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separati ng pro gr am an d data mem or y fur ther allows instructions to be sized differently than the 8-bit wide data w ord. Instr uction opcode s are 12 b its wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycl e (200 ns @ 20 MHz, 1 μs @ 4 MHz) except for program branches.

T abl e 3-1 below list s program m emory (Flash) a nd data memory (RAM) for the PIC12F508/509/16F505 devices.

TABLE 3-1: PIC12F508/509/16F505

MEMORY

The PIC12F508/509/16F505 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions be tween dat a in the work ing regist er and any register file.

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typica lly t he W (working) register. T he oth er operand is either a file register or an immediate constant. In sing le ope ran d inst ruction s, the operan d is either the W register or a file register.

The W register is an 8-bit workin g register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the ST ATUS register . The C and DC bit s operate as a borrow tively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure3-2, with the corresponding device pins described in Table 3-3.

and digit borrow out bit, respec-

Device

Program Data

PIC12F508 512 x 12 25 x 8 PIC12F509 1024 x 12 41 x 8 PIC16F505 1024 x 12 72 x 8

The PIC12F508/509/16F505 devices can directly or indirectly address its reg ister file s and dat a mem ory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F508/509/ 16F505 devices have a highly orthogonal (symmetrical) instruc tion set that makes it possible to carry ou t any operat ion, on any regis ter, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC12F508/509/16F505 devices simple, yet efficient. In addition, the learning curve is reduced significantly.

Memory

PIC12F508/509/16F505

FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM

OSC1/CLKIN

OSC2

Program

Bus

Flash

512 x 12 or

1024 x 12

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

Internal RC

OSC

Program Counter

Stack 1 Stack 2

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VDD, VSS

RAM Addr

Data Bus

Addr MUX

RAM

25 x 8 or

File

Registers

5-7

FSR Reg

Status Reg

MUX

ALU

W Reg

Timer0

Indirect

Addr

GPIO

GP0/ISCPDAT GP1/ISCPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN

PIC12F508/509/16F505

TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION

Name Function

GP0/ICSPDA T GP0 TTL CMOS Bidirectional I/O pin. Can b e software prog rammed for inte rnal

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

GP1\ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be so ftware program med for internal

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak

MCLR

PP HV — Programming voltage input.

GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin.

OSC2 — XTAL Oscillator cr ystal output. C onnection s to cr ystal or resonato r in

GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Oscillator crystal input. CLKIN ST — External clock source input.

DD VDD — P Positive supply for logic and I/O pins.

SS VSS — P Ground reference for logic and I/O pins.

V Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input

Input

Type

Output

Type

weak pull-up and wake-up from Sleep on pin change.

pull-up and wake-up from Sleep on pin change.

ST — Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device . V ol tage on MCLR not exceed V will enter Programming mode. Weak pull-up always on if configured as MCLR

Crystal Oscill ator mode (XT and LP m odes only, GPIO in other modes).

DD during normal device operation or the device

Description

/VPP must

PIC12F508/509/16F505

FIGURE 3-2: PIC16F505 BLOCK DIAGRAM

Program

OSC1/CLKIN OSC2/CLKOUT

Bus

Instruction Reg

Instruction

Decode &

Generation

Flash

1K x 12

Program

Memory

Control

Timing

Program Counter

Stack 1 Stack 2

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Internal RC

OSC

RAM Addr

Data Bus

Addr MUX

RAM

File

Registers

5-7

FSR Reg

Status Reg

MUX

ALU

W Reg

Timer0

Indirect

Addr

PORTB

RB0/ICSPCLK RB1/ICSPDAT RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN

PORTC

RC0 RC1 RC2 RC3 RC4 RC5/T0CKI

MCLR

VDD, VSS

PIC12F508/509/16F505

TABLE 3-3: PIC16F505 PINOUT DESCRIPTION

Name Function

RB0/ICSPDA T RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for i nternal

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

RB1/ICSPCLK RB1 TTL CMOS Bid irectional I/O pin. Can be so ftware program med for internal

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin. RB2 RB2 TTL CMOS Bidirectional I/O pin. RB3/MCLR

RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can b e software prog rammed for inte rnal

RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin.

RC0 RC0 TTL CMOS Bidirectional I/O pin. RC1 RC1 TTL CMOS Bidirectional I/O pin. RC2 RC2 TTL CMOS Bidirectional I/O pin. RC3 RC3 TTL CMOS Bidirectional I/O pin. RC4 RC4 TTL CMOS Bidirectional I/O pin. RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin.

DD VDD — P Positive supply for logic and I/O pins.

SS VSS — P Ground reference for logic and I/O pins.

V Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

/VPP RB3 TTL — Input port. Can be software programmed for internal weak

MCLR ST — Master Clear (Reset). When configured as MCLR, thi s pin is

VPP — — Programming voltage input.

OSC2 — XTAL Oscillator cr ystal output. C onnection s to cr ystal or resonato r in

CLKOUT — CMOS In EXTRC and INTRC modes, the pin output can be

OSC1 XTAL — Crystal input. CLKIN ST — External clock source input.

T0CKI ST — Clock input to TMR0.

ST = Schmitt Trigger input

Input

Type

Output

Type

Description

weak pull-up and wake-up from Sleep on pin change.

pull-up and wake-up from Sleep on pin change.

an active-low Reset to the device . V ol tage on MCLR not exceed V will enter Programming mode. Weak pull-up always on if configured as MCLR.

weak pull-up and wake-up from Sleep on pin change.

Crystal Oscillator mode (XT, HS and LP modes only).

configured for CLKOUT, which has 1/4 the frequenc y of OSC1 and denotes the instruction cycle rate.

DD during normal device operation or the device

/VPP must

PIC12F508/509/16F505

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internal ly divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is s hown in Figure3-3 and Example 3-1.

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

3.2 Instruction Flow/Pipelining

An instruction cy cle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g ., GOTO), t hen two c yc le s are required to complete the ins tructi on (Exampl e 3-1).

A fetch cycle begins with the PC incrementing in Q1. In the execution cy cle, the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

PC + 1 PC + 2

Q2 Q3 Q4

Internal phase clock

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTB, BIT1

All instructions are si ngle cycle, except for any program bra nches. These tak e two cycles, since th e fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then ex ecuted.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC12F508/509/16F505

4.0 MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized into program memory and data memory. For devices with more than 512 byte s of program me mory , a p aging scheme is used. Program memory pages are accessed using one Status register bit. For the PIC12F509 and PIC16F505, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Orga nization for the PIC12F508/509

The PIC12F508 device has a 10-bit Program Counter (PC) and PIC12F509 has a 11-bit Program Counter (PC) capable of add ressing a 2K x 12 program me mory space.

Only the first 512 x 12 (0000h-01FFh) for the PIC12F508, and 1K x 12 (0000h-03FFh) for the PIC12F509 are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12F508) or 1K x 12 space (PIC12F509). The effective Reset vector is a 000 0h (see Figure 4-1). L ocation 01FFh (PIC12F508) and location 03FFh (PIC12F509) contain the internal clock oscillator calibration value. This value shou ld never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC12F508/509

PC<11:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

On-chip Program

Memory

512 Word

Space

User Memory

On-chip Program

Memory

1024 Word

(1)

0000h

01FFh 0200h

03FFh 0400h

7FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location 01FFh, 03FFh (PIC12F508, PIC12F509) contains the MOVLW XX internal oscillator calibration value.

PIC12F508/509/16F505

4.2 Program Memory Organization For The PIC16F505

The PIC16F505 device has a 11-bit Program Counter (PC) capable of add ressing a 2K x 12 program me mory space.

The 1K x 12 (0000h-03FFh) for the PIC16F505 are physically implemented. Refer to Figure 4-2. Accessing a location above this boundary will cause a wraparound within the first 1K x 12 space. The effective Reset vector is at 0000h (see Figure 4-2). Location 03FFh contains th e in tern al osc il la tor c ali bration value. This value should never be overwritten.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16F505

PC<11:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

Space

User Memory

On-chip Program

Memory

(1)

0000h

01FFh 0200h

4.3 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, da ta memory for a device is speci f ie d by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Regi st ers in cl ude the TMR0 register, the Program Counter (PCL), the STAT US register , the I/O registers (ports) and the File Select Register (FSR). In addition, Special Func tion Registers are use d to control the I/O port configuration and prescaler options.

The General Purpose Registers are used for data and control informatio n u nd er com ma nd of the instructions.

For the PIC12F508/509, the register file is composed of 7 Special Function Registers, 9 General Purpose Registers and 16 or 32 General Purpose Registers accessed by banking (see Figure 4-3 and Figure 4-4).

For the PIC16F505, the register file is composed of 8 Special Function Registers, 8 General Purpose Registers and 64 General Pu rpose Registers accesse d by banking (Figure4-5).

4.3.1 GENERAL PURPOSE REGISTER FILE

The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

1024 Words

Note 1: Address 0000h becomes the

effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value.

03FFh 0400h

7FFh

PIC12F508/509/16F505

FIGURE 4-3: PIC12F508 REGISTER

FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

FIGURE 4-4: PIC12F509 REGISTER

FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General Purpose Registers

Bank 0 Bank 1

20h

Addresses map back to addresses in Bank 0.

2Fh

30h

General Purpose Registers

3Fh

FIGURE 4-5: PIC16F505 REGISTER FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h 08h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB PORTC

General Purpose Registers

Bank 0

20h

2Fh

30h

General Purpose Registers

3Fh

Bank 1

40h

Addresses map back to addresses in Bank 0.

4Fh

50h

General Purpose Registers

5Fh

Bank 2

60h

6Fh 70h

General Purpose Registers

7Fh

Bank 3

PIC12F508/509/16F505

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and per ipheral functio ns to con trol the operation of the device (Table 4-1).

The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33

(1)

02h 03h STATUS GPWU

04h FSR Indirect Data Memory Address Pointer 111x xxxx 26 04h 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24 06h GPIO N/A TRISGPIO — — I/O Control Register --11 1111 29 N/A OPTION GPWU

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter”

PCL Low-order 8 bits of PC 1111 1111 25

—PA0

(4)

FSR Indirect Data Memory Address Pointer 110x xxxx 26

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 29

GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 22

for an explanation of how to access these bits.

2: Other (non Power-up) Resets include externa l Reset th rough MCLR

change Reset.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 4: PIC12F509 only. 5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

(5)

TO PD ZDCC0-01 1xxx

, Watchdog Timer and wake-up on pin

Power-On

(2)

Reset

xxxx xxxx 26

(3)

Page #

PIC12F508/509/16F505

TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33

(1)

02h 03h STATUS RBWUF 04h FSR Indirect Data Memory Address Pointer 110x xxxx 26 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24

06h PORTB 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 29 N/A TRISB — — I/O Control Register --11 1111 29 N/A TRISC N/A OPTION RBWU

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

PCL Low-order 8 bits of PC 1111 1111 25

—PA0TO PD ZDCC0-01 1xxx 20

— — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 29

— — I/O Control Register --11 1111 29

RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 23

2: Other (non Power-up) Resets include external reset through MCLR

change Reset.

, Watchdog Timer and wake-up on pin

Power-On

Reset

xxxx xxxx 26

(2)

Page #

PIC12F508/509/16F505

4.4 STATUS Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO

and PD bits are not

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. The se in structions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect S tatus bits, see Section 8.0 “Instruction Set Summary”.

writable. Therefore, the result of an instruction with the STATUS regis ter as destina tion may be differ ent than intended.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF

bit 7 bit 0

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for prog ram page preselect is not recommended, since this may affect upward compatibility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instructi on

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

ADDWF

: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

—PA0TO PD ZDCC

(1)

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508.

PIC12F508/509/16F505

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

RBWUF

bit 7 bit 0

bit 7 RBWUF: PORTB Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh)

Each page is 512 bytes. Using the P A 0 bit as a gene ral purpos e read/wri te bit in de vices whi ch do not u se it for program page presele ct is not recommen ded, since this may affect upward compatib ility with future products.

bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit carry/borrow

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

—PA0TO PD ZDCC

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.5 OPTION Register

The OPTION re gister is a 8-bit wid e, write-only register , which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executin g the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit 7 bit 0

GPPU T0CS T0SE PSA PS2 PS1 PS0

Note: If TRIS bit is set to ‘0’, the wake-up on

Note: If the T0CS bit is set to ‘1’, it will override

change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU GPWU

/RBWU).

the TRIS function on the T0CKI pin.

/RBPU and

bit 7 GPWU

bit 6 GPPU

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescale r Rate Select bits

: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU

bit 7 bit 0

RBPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 RBWU

bit 6 RBPU

bit 5 T0CS: Timer0 clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assign ment bit

bit 2-0 PS<2:0>: Prescale r Rate Select bits

: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.6 OSCCAL Register

The Oscillator Calibrati on (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bit s for cal ibra tio n

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogramm ed correctly later.

After you move in the calibration constant, do not change the value. See Section 7.2.5 “Internal 4 MHz

RC Oscillator”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

bit 7 bit 0

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 =Maximum frequency

•

0000001 0000000 =Center frequency

1111111

•

• 1000000 =Minimum frequency

bit 0 Unimplemented: Read as ‘0’

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

4.7 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure4-6).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruct ion word, but is alway s cleared (Figure 4-6).

Instructions wh ere the PCL is th e destinatio n, or modif y PCL instructions, incl ude MOVWF PC, ADDWF PC and

BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program me mory page (512 words long).

FIGURE 4-6: LOADING OF PC

BRANCH INSTRUCTIONS

GOTO Instruction

7 0

87 0

910

PCL

Instruction Wor d

PA0

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code.

The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is pre-selected.

Therefore, upon a Reset, a GOTO instruction will automatically c ause the program t o jump to page0 until the value of the page bits is altered.

4.8 Stack

The PIC12F508/509/16F505 devices have a 2-deep, 12-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of Stack 1 into S t a ck 2 an d t he n PUS H th e c ur ren t PC v a lu e, in cre mented by one, into Stack Level 1. If more than two sequential CALLs are executed, o nly the mo st recen t two return addresses a re s tor ed .

A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into S t ack Level 1. If more tha n two sequentia l RETLWs are execute d, the stack will be fi lled with the address previously stored in Stack Level 2. Note that the W register will be loaded with the literal value specified in the i nstruction. Th is is particu larly useful f or the implementation of data look-up tables within the program memory.

Note 1: There are no Status bits to indicate stack

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the e xecution of the CALL and RETLW instructions.

Status

CALL or Modify PCL Instruction

87 0

910

Reset to ‘0’

PA0

7 0

Status

PCL

Instruction Word

PIC12F508/509/16F505

4.9 Indirect Data Addressing: INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

4.9.1 INDIREC T ADDRES SING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF

;register INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue :

The FSR is a 5-bit wide register. It is used in conjunctio n with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC12F508 – Does not use banking. FSR <7:5> are unimplemented and read as ‘1’s.

PIC12F509 – Uses FSR<5>. Select s between ba nk 0 and bank 1. FSR<7:6> is unimp lemented , read as ‘1’.

PIC16F505 – Uses FSR<6:5>. S elects fro m bank 0 to bank 3. FSR<7> is unimplemented, read as ‘1’.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509)

Direct Addressing

(FSR)

Bank Select

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

2: PIC12F509.

Location Select

Data Memory

(opcode) 04

00 01

00h

Addresses map back to addresses in Bank 0.

0Fh

(1)

10h

1Fh 3Fh

Bank 0 Bank 1

(2)

Indirect Addressing

Bank

(FSR)

Location Select

PIC12F508/509/16F505

FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505)

Direct Addressing

(FSR)

6 5 4 (opcode) 0

Bank Select Location Select

00h

Data Memory

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

0Fh

(1)

10h

00 01 10 11

Addresses map back to addresses in Bank 0.

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Indirect Addressing

6 5 4 (FSR) 0

Bank

Location Select

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

5.0 I/O PORT

As with any other register, the I/O register(s) can be written and read under pro gram contro l. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set.

Note: On the PIC12F508/509, I/O PORTB i s ref-

erenced as GPIO. On the PIC16F505, I/O PORTB is referenced as PORTB.

5.1 PORTB/GPIO

PORTB/GPIO is an 8-bit I/O register. Only the loworder 6 bits a re used ( RB/GP<5: 0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Please note that RB3/ GP3 is an input only pin. The Configuration Word can set several I/O ’ s t o a lte rnate fu nc tio ns. When acting as alternate function s, the pins wil l read as ‘0’ during a port read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4 can be configured with weak pull-ups and also for wake-up on change . The wake-up on chan ge and weak pull-up functions are not pin selectable. If RB3/GP3/

is configured as MCLR, weak pull-up is always

MCLR on and wake-up on change for this pin is not enabled.

5.2 PORTC (PIC16F505 Only)

PORTC is an 8-bit I/O register . Only the lo w-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-2. All port pins, except RB3/GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding directio n contro l bit in TR IS must be c leared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3/GP3) can be programmed individually as input or output.

FIGURE 5-1: PIC12F508/509/16F505

EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Data Latch

TRIS Latch

Reset

VDD

VSS

(1)

I/O pin

5.3 TRIS Registers

The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bi t puts the corre-

Note 1: See Table 3-3 for buffer type.

sponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RB3/GP3, which is input only and the T0CKI pin, which may be controlled by the OPTION register. See Register 4-3 and R egister 4-4.

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enab led and driv en high, but the external system is holding it low, a read of the port will indicate that the pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon Reset.

RD Port

PIC12F508/509/16F505

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Power-On

Reset

Value on

(1)

N/A TRISGPIO N/A TRISB N/A TRISC N/A OPTION N/A OPTION 03h STATUS 03h STATUS 06h GPIO 06h PORTB 07h PORTC

(2) (2)

(1) (2) (1) (2)

(1)

(2)

— — I/O Control Register --11 1111 --11 1111 — — I/O Control Register --11 1111 --11 1111

— — I/O Control Register --11 1111 --11 1111 GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

GPWUF — PAO TO PD Z DC C 0-01 1xxx q00q quuu RBWUF — PAO TO PD Z DC C 0-01 1xxx q00q quuu

— — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

— — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu

— — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

Legend: Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown, u = unchanged,

q = depends on condition.

Note 1: PIC12F508/509 only.

2: PIC16F505 only. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

Value on All Other

Resets

(3) (3)

PIC12F508/509/16F505

5.5 I/O Programming Considerations

5.5.1 BID IREC TION AL I/O PORTS

Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire po rt into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/ outputs. For example, a BSF operation on bit 5 of PORTB/ GPIO wil l cause all eight bit s of PORTB/GPIO to be read into the CPU, bit 5 to be set a nd th e P ORTB /G P IO val u e to be written to the output latches. If another bit of PORTB/ GPIO is used as a bid irecti onal I /O pi n (say b it 0) an d it is defined as an input at this time, the input signal present on the pin itself wo uld be read into the CPU and rewritten to the data latch o f this p articular pin , overwriting the previous c ontent. As l ong as the p in stay s in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch m ay now be unknown.

Example 5-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired OR”, “wired AND”). The resulting high out put current s may damag e the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT(e.g. PIC16F505)

;Initial PORTB Settings ;PORTB<5:3> Inputs ;PORTB<2:0> Outputs ; ; PORTB latch PORTB pins ; ---------- ----------

BCF PORTB, 5 ;--01 -ppp --11 pppp BCF PORTB, 4 ;--10 -ppp --11 pppp MOVLW 007h; TRIS PORTB ;--10 -ppp --11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCF caused RB5 to be latched as the pin value (High).

5.5.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cy cle, whe rea s for readin g, th e data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that f ile to b e read int o th e CPU . Oth erwis e, t he previous st ate of that pin may be read into the CPU ra ther than the new state. When in doubt, it is better to separate these instructio ns with a NOP or another instruction not accessing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetched

RB<5:0>

Instruction

Executed

PC PC + 1 PC + 2

MOVWF PORTB NOP

Port pin written here

MOVWF PORTB

(Write to PORTB)

Port pin sampled here

(Read PORTB)

PC + 3

NOPMOVF PORTB, W

NOPMOVF PORTB,W

This example shows a write to PORTB followed by a read from PORTB.

Data setup time = (0.25 T where: T

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

CY – TPD)

CY = instruction cycle.

PD = propagation delay

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

6.0 TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0 module.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the Timer0 module will increment every ins tru cti on cy cl e (w i tho ut p r es ca ler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

(GP2/RC5)/T0CKI

T0SE

FOSC/4

T0CS

(1)

Programmable

Prescaler

PS2, PS1, PS0

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit ( OPTION<4>) dete rmines the so urce edge. Clearing the T0SE bit selects the rising edge. Restrictions on the externa l c loc k in put are dis c us sed in de t ai l in Section 6.1 “Using Timer0 with an External Clock”.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit, PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to T imer0. Th e presca ler is n ot readable or writabl e. When the prescaler is assi gned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 “Prescaler” details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

Data Bus

OUT

(2)

PSA

(1)

Sync with

Internal

Clocks

(2 TCY delay)

TMR0 Reg

PSOUT

Sync

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC (Program Counter)

Instruction

Fetch

Timer0 Instruction

Executed

Q1 Q2 Q3 Q4

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0 + 1 T0 + 2 NT0

Write TMR0 executed

Read TMR0 reads NT0

PC + 5

NT0 + 1

Read TMR0 reads NT0 + 1

NT0 + 2

Read TMR0 reads NT0 + 2

PIC12F508/509/16F505

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC (Program Counter)

Instruction Fetch

Timer0 Instruction

Executed

Q1 Q2 Q3 Q4

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0 + 1 NT0

Write TMR0 executed

Read TMR0 reads NT0

PC + 5

Read TMR0 reads NT0 + 1

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx N/A OPTION N/A OPTION

N/A TRISGPIO N/A TRISC

(1)

(2)

(2), (3)

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111

(1), (3)

— — I/O Control Register --11 1111 — — RC5 RC4 RC3 RC2 RC1 RC0 --11 1111

Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged. Note 1: PIC12F508/509 only.

2: PIC16F505 only. 3: The TRIS of the T0CKI pin is overridden when T0CS = 1.

Value on

Power-On

Reset

NT0 + 1

Read TMR0 reads NT0 + 2

Value on All Other

Resets

uuuu uuuu

1111 1111

--11 1111

PIC12F508/509/16F505

6.1 Using Timer0 with an External Clock

When an external clock input i s used for T i mer0, it must meet certain requ ir e me nts. The ex t er na l cl oc k req u ir ement is due to internal phas e clock (TOSC) synchroniza- tion. Also, there is a dela y in the ac tual inc remen ting of Timer0 after synchronization.

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that t he presc aler out put is symmetric al. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessa ry for T0CKI to have a p eriod of at least 4 T by the prescaler value. The on ly requirem ent on T0CKI high and low time is that they do not violate the

6.1.1 EXTERNAL CLOCK

SYNCHRONIZATION

When no pr escal er is us ed, t he ex ternal clock inpu t is the same as the prescaler outp ut. Th e synchronization of T0CKI with the internal phase clocks is accomplished by sampli ng the prescale r output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2 T for at least 2 T Refer to the electrical specification of the desired

OSC (and a small RC delay of 2 Tt0H) and low

OSC (and a small RC delay of 2 Tt0H).

minimum pulse width requirement of Tt0H. Refer to parameters 40 , 41 a nd 42 in the electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.

device.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or

Prescaler Output

External Clock/Prescaler

Output After Sampling

(2)

(1)

(3)

OSC (and a small RC delay of 4 Tt0H) div ided

Small pulse misses sampling

Increment Timer0 (Q4)

Timer0

Note 1: Delay from clock input change to Timer0 increment is 3 T

in measuring the interval between two edges on Timer0 input = ±4 T

2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

T0 T0 + 1 T0 + 2

OSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

OSC max.

PIC12F508/509/16F505

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 7.6 “Watch- dog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet.

Note: The prescaler may be used by either the

Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TM R0 registe r (e.g., CLRF 1, MOVWF 1, BSF 1, x, etc.) will clear the presca ler . When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescal er conta ins all ‘0’s.

6.2.1 SWITCHING PRESCA LER ASSIGNMENT

The prescaler assignment is fully under software control (i. e., it can b e changed “ on-the- fly” dur ing program execution). To avoid an unintended de vice Rese t, the following instruction sequence (Example6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0 → WDT)

CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 & Prescaler MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7) OPTION ;are required only if

;desired CLRWDT ;PS<2:0> are 000 or 001 MOVLW ‘00xx1xxx’b ;Set Postscaler to OPTION ;desired WDT rate

To change the prescaler from the WDT to the Timer0 module, use the se quence show n in Examp le 6-2. This sequence must be us ed ev en if th e WDT is disab led. A CLRWDT instruction should be executed before switching the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and ;clock source

OPTION

PIC12F508/509/16F505

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY (= FOSC/4)

M U

PSA

M U

T0CS

8-bit Prescaler

8-to-1 MUX

MUX

M U

PSA

Sync

Cycles

PS<2:0>

(GP2/RC5)/T0CKI

T0SE

Watchdog

Timer

WDT Enable bit

(1), (2)

Data Bus

TMR0 Reg

WDT

Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

2: T0CKI is shared with pin RC5 on the PIC16F505 and pin G P 2 on the PIC12F508/509.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

7.0 SPECIAL FEATURES OF THE CPU

What sets a mic rocontroller apart from other processors are special circuits that deal with the n eeds of rea ltime applications. The PIC12F508/509/16F505 microcontrollers have a host of such features intended to maximize syst em reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are:

• Oscillator Selection

• Reset:

- Power-on Reset (P OR)

- Device Reset Timer (DR T)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming ™

•Clock Out

The PIC12F508/509 /16F505 device s have a W atchdog Timer, which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability . If using HS (PIC16F505), XT or LP sele ctable oscillator o ptions, the re is always an 18 ms (no minal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. If using INTRC or EXTRC, there is an 18 ms delay only on V

DD power-up . With this timer

on-chip, most applications need no external Reset circuitry.

The Sleep mode is designed to of fer a ve ry lo w current Power-down mode. The user can wake-up from Sleep through a change on in put pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

7.1 Configuration Bits

The PIC12F508/509/16F505 Configuration Words consist of 12 bits. Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type; (two bits on the PIC12F508/509), one bit is the Watchdog T imer enable bit, one bit is the MCLR bit and one bit is for code protection (Register 7-1, Register 7-2).

enable

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0

bit 11 bit 0

bit 11-5 Unimplemented: Read as ‘0’ bit 4

bit 3 CP: Code Protection bit

bit 2 WDTE: Watchdog Timer Enable bit

bit 1-0 FOSC<1:0>: Oscillator Selection bits

MCLRE: GP3/MCLR Pin Function Select bit

1 = GP3/MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD

1 = Code protection off 0 = Code protection on

1 = WDT enabled 0 = WDT disabled

11 = EXTRC = external selection bits 10 = INTRC = internal RC oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to access

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

pin function is MCLR

the Configuration Word. The Configuration Word is not user addressable during device operation.

(1)

PIC12F508/509/16F505

— — — — — — MCLRE CP WDTE FOSC2 FOSC1 FOSC0

bit 11 bit 0

bit 11-6 Unimplemented: Read as ‘0’ bit 5 MCLRE: RB3/MCLR

1 = RB3/MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 4 CP: Code Protection bit

1 = Code protection off 0 = Code protection on

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabl ed 0 = WDT disabled

bit 2-0 FOSC<1:0>: Oscillator Selection bits

111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator

Pin Function Select bit

pin function is MCLR

(1)

Note 1: Refer to the “PIC16F505 Memory Programming S pec ifi ca tio ns” (D S4 122 6) to d ete rmi ne ho w to

access the Configuration Word. The Configuration Word is not user addressable during device operation.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

PIC12F508/509/16F505

7.2 Oscillator Configurations

7.2.1 OSCILLATOR TYPES

The PIC12F508/509/16F505 devices can be operated in up to six different oscillator modes. The user can program up to three configuration bits (FOSC<1:0> [PIC12F508/509], FOSC<2:0> [P IC16F505 ]). To select one of these modes:

• LP: Low-Power Crystal

• XT: Crystal/Resonator

• HS: High-Speed Crystal/Resonator

(PIC16F505 only)

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

• EC: External High-Speed Clock Input

(PIC16F505 only)

7.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In HS (PIC16F505), XT or LP modes, a crystal or ceramic resonator is connected to the (GP5/RB5)/ OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins to establish oscillation (Figure 7-1). The PIC12F508/ 509/16F505 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS (PIC16F505), XT or LP modes, the dev ice can have an external clock sour ce drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).

FIGURE 7-1: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

(1)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF approx. value = 10 MΩ.

XTAL

(2)

OSC1

OSC2

(3)

PIC12F508/509

PIC16F505

Sleep

To internal

logic

FIGURE 7-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

Clock from ext. system

Open

OSC1

PIC12F508/509

PIC16F505

OSC2

Note 1: This device has been designed to per-

form to th e paramet ers of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have differ ent perfor mance cha racteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.

2: The user should verify that the device

oscillator starts and performs as expected. Adjustin g the loading capa citor values and/or the Oscillator mode may be required.

T ABLE 7-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS – PIC12F508/509/16F505

Osc

Type

XT 4.0 MHz 30 pF 30 pF

Note 1: These values are for design guidance

Resonator

Cap. RangeC1Cap. Range

Freq.

(2)

16 MHz 10-47 pF 10-47 pF

only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

2: PIC16F505 only.

(1)

PIC12F508/509/16F505

TABLE 7-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR – PIC12F508/509/16F505

Osc

Type

LP 32 kHz

XT 200 kHz

Note 1: For V

Resonator

Freq.

(1)

Cap. Range

15 pF 15 pF

47-68 pF

(3)

1 MHz 4 MHz

20 MHz 15-47 pF 15-47 pF

DD > 4.5V, C1 = C2 ≈ 30 pF is

15 pF 15 pF

recommended.

2: These values are for design guidance

only. Rs may be required to avoid overdriving crystal s with lo w drive le vel spe cification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

3: PIC16F505 only.

(2)

Cap. Range

47-68 pF

15 pF 15 pF

7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed cry stal oscillat or will provid e good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

Figure 7-3 shows implement ation of a parallel resona nt oscillator circuit. The circuit is designed to use the fundamental freq uency of th e crystal. The 74AS04 in verter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 7-3: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

+5V

10k

4.7k

74AS04

10k

XTAL

10k

20 pF

Figure 7-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330Ω resistors provide the negative feedback to bias the inverters in their linear region.

74AS04

To Other Devices

CLKIN

PIC16F505 PIC12F508 PIC12F509

FIGURE 7-4: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other

74AS04

Devices

CLKIN

PIC16F505 PIC12F508 PIC12F509

330

74AS04

330

74AS04

0.1 mF XTAL

7.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device option offers additi ona l cos t savings. The RC oscillator frequency is a function of the supply voltage, the resis-

EXT) and capacitor (CEXT ) v alues, a nd the opera t-

tor (R ing temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process paramete r variatio n. Further more, the d ifference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low

EXT values. The user also needs to take into account

C variation due to tolerance of external R and C components used.

Figure 7-5 shows how the R/C combination is connected to the PIC12F508/509/16F505 devices. For

EXT values below 3.0 kΩ, the oscillator operat ion may

R become unstable, or stop completely. For very high REXT values (e.g., 1 MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0 kΩ and 100 kΩ.

PIC12F508/509/16F505

Although the oscillator will operate with no external capacitor (C

EXT = 0 pF), we recommend using values

above 20 pF for noise a nd st a bi lity re as ons . With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

Section 10.0 “Ele ctr ical Ch arac te rist ics” shows RC frequency variation from part-to-part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect RC frequency more for large R) and for smal ler values of C (since variation of input capacitance will affect RC frequency more).

Also, see the Electrical Specifications section for variation of oscillator frequency due to V R

EXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and V

DD for given

values.

FIGURE 7-5: EXTERNAL RC

OSCILLATOR MODE

VDD

REXT

CEXT VSS

FOSC/4

OSC1

OSC2/CLKOUT

Internal clock

PIC16F505 PIC12F508 PIC12F509

In addition, a ca librati on in structi on is progra mmed into the last address of me mory, which contains the calib ration value for the internal RC oscillator. This location is always uncode protected, regardless of the code-protect settings. This valu e is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the Re set v ector. This will load the W reg ister with the calibration value upon Reset and the PC will then roll over to the users program at address 0x000. The user then has the op tion of writing the value to the OSCCAL Register (05h) or ignoring it.

OSCCAL, when writte n to with the cali bration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency.

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogramm ed correctly later.

For the PIC12F508/509/16F505 devices, only bits <7:1> of OSCCAL are implemented. Bits CAL6-CAL0 are used for calibration. Adjusting CAL6-CAL0 from ‘0000000’ to ‘1111111’ changes the cl ock spee d. See Register 4-5 for more information.

Note: The 0 bit of OSCCAL is unimplemented

and should be written as ‘0’ when modifying OSCCAL for compatibility with future devices.

7.2.5 INTERNAL 4 MHz RC OSCILLATOR

The internal RC osci llator provides a fixed 4 MHz (nominal) system clock at V Section 10.0 “Electrical Characteristics” for information on v ariation over volt age and temperature ).

DD = 5V and 25°C, (see

PIC12F508/509/16F505

7.3 Reset

The device differentiates between various kinds of Reset:

• Power-on Reset (POR)

•MCLR

• WDT time-out Reset during normal operation

• WDT time-out Reset during Sleep

• Wake-up from Sleep on pin change Some registers are not reset in any way, they are

unknown on P OR an d uncha nged i n any other R eset. Most other registers are reset to “Reset state” on Power-on Reset (POR), MCLR pin change Reset during normal operation. They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as resumption of norm al op erati on . The ex ce pti ons to this are TO, PD and RBWUF/GPWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 7-4 for a full description of Reset states of all registers.

Reset during normal operation Reset during Sleep

, WDT or Wake-up on

7.3.1 EXTERNAL CLOCK IN

For applications where a clock is already available elsewhere, users may directly drive the PIC12F508/ 509/16F505 devices provided that this external clock source meets the AC/DC timing requirements listed in Section 7.6 “Watchdog Timer (WDT)”. Figure 7-6 below shows how an external clock circuit should be configured.

FIGURE 7-6: EXTERNAL CLOCK INPUT

OPERATION

PIC16F505: EC, HS, XT, LP

Clock From ext. system

OSC2/CLKOUT/RB4

PIC12F508/509: XT, LP

Clock From ext. system

OSC2

Note 1: RB4 is available in EC mode only.

RB5/OSC1/CLKIN PIC16F505 OSC2/CLKOUT/RB4

GP5/OSC1/CLKIN PIC12F508

PIC12F509 GP4/OSC2

(1)

TABLE 7-3: RESET CONDITIONS FOR REGISTERS – PIC12F508/509

Reset, WDT Time-out,

W—qqqq qqqu

(1)

INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu

(4)

FSR FSR

(5)

04h 110x xxxx 11uu uuuu

04h 111x xxxx 111u uuuu OSCCAL 05h 1111 111- uuuu uuu- GPIO 06h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of mem-

ory.

2: See Table7-8 for Reset value for specific conditions. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 4: PIC12F509 only. 5: PIC12F508 only.

MCLR

Wake-up On Pin Change

qqqq qqqu

(1)

(2), (3)

PIC12F508/509/16F505

TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505

W—qqqq qqqu INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111

memory.

2: See Table7-8 for Reset value for specific conditions. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

(1)

MCLR Reset, WDT Time-out,

Wake-up On Pin Change

qqqq qqqu

(1)

(2), (3)

TABLE 7-5: RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h PCL Addr: 02h

Power-on Reset 0001 1xxx 1111 1111

Reset during normal operation 000u uuuu 1111 1111

MCLR

Reset during Sleep 0001 0uuu 1111 1111

MCLR WDT Reset during Sleep 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from Sleep on pin change 1001 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.

PIC12F508/509/16F505

7.3.2 MCLR ENABLE

This configuration bit, when unprogrammed (left in the ‘1’ state), en ables the external M CLR programmed, the MCLR V

DD and the pin is assigned to be a I/O. See Figure 7-7.

function is tied to the internal

function. When

FIGURE 7-7: MCLR SELECT

GPWU/RBWU

(GP3/RB3)/MCLR/VPP

MCLRE

Internal MCLR

7.4 Power-on Reset (POR)

The PIC12F508/509/16F505 devices incorporate an on-chip Power-on Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations.

The on-chip POR circuit holds the chip in Reset until

DD has reached a high enough level for proper oper-

V ation. To take advantage of the internal POR, program the (GP3/RB3)/MCLR/VPP pin as MCLR and tie through a resistor to V RB3). An internal weak pull-up resistor is implemented using a transistor (refer to Table 10-2 for the pull-up resistor ranges). T his will elimi nate external RC co mponents usually needed to create a Power-on Reset. A maximum rise time for V Section 10.0 “Electrical Charac teristics” for details.

When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be m et to en su re operation. If these conditions are not met, the devices must be held in Reset until the operating parameters are met.

A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 7-8.

DD, or program the pin as (GP3/

DD is specified. See

The Power-on Reset circuit and the Device Reset Timer (see Section 7.5 “Device Reset Timer (DRT)”) circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR

to be high. After the time-out period, w hich is typ ically 18 ms, it will reset the Reset latch and thus end the on-chip Reset signal.

A power-up example where MCLR in Figure 7-9. V bringing MCLR Reset T

DD is allowed to rise and stabil ize before

high. The chip will actually come out of

DRT msec after MCLR goes high.

is held low is sho wn

In Figure 7-10, the on-chip Power-on Reset feature is being used (MCLR is programmed to be (GP3/RB3). The V

and VDD are tied together or the pin

DD is stable

before the start-up timer ti mes out and there is no problem in getting a proper Reset. However, Figure 7-11 depicts a proble m situ ation whe re V The time between when t he DRT senses that MCLR high and when MCLR

and VDD actually reach their full

DD rises too slowly.

value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the ch ip ma y n ot function correctly. For such situations, we recommend that external RC circuits be used to achieve longer PO R delay ti mes (Fig ure 7-10).

Note: When the devices start normal operation

(exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

For additional information, refer to Application Notes AN522 “Power-Up Considerations” (DS00522) and AN607 “Power-up Trouble Shooting” (DS00607).

PIC12F508/509/16F505

FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

(GP3/RB3)/MCLR/VPP

POR (Power-on Reset)

Reset

MCLR

MCLRE

WDT Time-out

Pin Change

Sleep

WDT Reset

Wake-up on pin Change Reset

FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIME

Start-up Timer

(10 μs or 18 ms)

CHIP Reset

PULLED LOW)

TDRT

TIED TO VDD): FAST VDD RISE

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

TDRT

PIC12F508/509/16F505

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ V

TDRT

DD min.

PIC12F508/509/16F505

7.5 Device Reset Timer (DRT)

On the PIC12F508/509/16 F50 5 devices, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 7-6).

The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the D RT is active. The DRT delay allow s V for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keep s the devices in a Reset condition for approximately 18 ms after MCLR has reached a logic high (VIH MCLR) level. Programming (GP3/RB3)/MCLR using an external RC network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/or space res tricted applications , as well as allowing the use of the (GP3/RB3)/MCLR/VPP pin as a general purpose input.

The Device Reset Time delays will vary from chip-tochip due to V See AC parameters for details.

The DRT will also be tri ggered upon a Watchdog Timer time-out from Sleep. This is particularly important for applications using the WDT to wake from Sleep mode automatically.

Reset sources are POR, MCLR wake-up on pin change. See Section 7.9.2 “Wake-up from Sleep”, Notes 1, 2 and 3.

DD, temperature and process variation.

DD to rise above VDD min. and

/VPP as MCLR and

, WDT time-out and

7.6 Watchdog Timer (WDT)

TABLE 7-6: DRT (DEVICE RESET TIMER

PERIOD)

Oscillator

Configuration

INTOSC, EXTRC 18 ms (typical) 10 μs (typical)

(1)

, XT, LP 1 8 ms (typical) 18 m s (typical)

(1)

Note 1: PIC16F505 only.

POR Reset

18 ms (typical) 10 μs (typical)

Subsequent

Resets

7.6.1 WDT PERIOD

The WDT has a nomin al time-out p eriod of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V cess variations (see DC specs).

Under worst case condi tions ( VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs .

DD and part-to-part pro-

7.6.2 WDT PROGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the postscaler , if as signed to the WDT, and prevents it from timing out and generating a device Reset.

The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset.

The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the (GP5/RB5)/OSC1/CLKIN pin and the internal 4 MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset.

The TO Watchdog Timer Reset.

The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see Section 7.1 “Configuration Bits”). Refer to the PIC12F508/509/ 16F505 Programming Speci fic ati ons to determine how to access the Configuration Word.

bit (STATUS<4>) will be cleared upon a

PIC12F508/509/16F505

FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-5)

Watchdog

Time

U X

Postscaler

8-to-1 MUX

WDT Enable

Configuration

Bit

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

PSA

MUX

WDT Time-out

PS<2:0>

To Timer0

PSA

(Figure 6-4)

TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(1)

N/A OPTION N/A OPTION

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

(2)

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged. Note 1: PIC12F508/509 only.

2: PIC16F505 only.

Power-On

Reset

Value on

All Other

Resets

PIC12F508/509/16F505

7.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO

The TO, PD and (GPWUF/RBWUF) bi ts in th e ST ATUS register can be tested to determine if a Reset condition has been caused by a Power-up condition, a MCLR or Watchdog Timer (WDT) Reset.

TABLE 7-8: TO/PD/(GPWUF/RBWUF)

GPWUF/

RBWUF

000WDT wake-up from Sleep 00uWDT time-out (not from

010MCLR 011Power-up

0uuMCLR 110Wake-up from Sleep on pin

Legend: u = unchanged Note 1: The TO

maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not change the TO GPWUF/RBWUF Status bits.

, PD, GPWUF/RBWUF)

STATUS AFTER RESET

PD Reset Caused By

Sleep)

wake-up from Sleep

not during Sleep

change

, PD and GPWUF/RBWUF bits

, PD and

7.8 Reset on Brown-out

A brown-out is a condition where device power (VDD) dips below its minimum value, but no t to zero, and the n recovers. The device should be reset in the event of a brown-out.

To reset PIC12F508/509/16F505 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14.

FIGURE 7-14: BROWN-OUT

PROTECTION CIRCUIT 2

VDD

MCLR

Note 1: This brown-out circuit is less expensive,

although less accurate. Transistor Q1 turns off when V that:

2: Pin must be confirmed as MCLR

DD is below a certain level such

DD •

40k

R1 + R2

(1)

= 0.7V

PIC16F505 PIC12F508

(2)

PIC12F509

FIGURE 7-15: BROWN-OUT

PROTECTION CIRCUIT 3

VDD

MCP809

VSS

RST

Note: This brown-out protection c ircuit employs

Bypass

Capacitor

VDD

Microchip Technology’s MCP809 microcontroller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems.

VDD

MCLR

PIC16F505 PIC12F508 PIC12F509

FIGURE 7-13: BROWN-OUT

PROTECTION CIRCUIT 1

VDD

33k

40k

MCLR

(1)

10k

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be confirmed as MCLR

PIC16F505 PIC12F508 PIC12F509

(2)

PIC12F508/509/16F505

7.9 Power-down Mode (Sleep)

A device may be powered down (Sleep) and later powered up (wake-up from Sleep).

7.9.1 SLEEP

The Power-Down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance).

Note: A Reset generated by a WDT time-out

does not drive the MCLR

For lowest current consumption while powered down, the T0CKI input should be at V (GP3/RB3)/MCLR level if MCLR

is enabled.

7.9.2 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the following events:

1. An external Reset input on (GP3/RB3)/MCLR/

PP pin, when configured as MCLR.

2. A Watchdog Timer time-out Reset (if WDT was enabled).

3. A change on input pin GP0/RB0, GP1/RB1, GP3/RB3 or RB4 when wake-up on change is enabled.

These events cause a device Reset. The TO GPWUF/RBWUF bits can be used to determine the cause of devi ce Rese t . T he TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD which is set on power-up, is cleared when SLEEP is invoked. The GPWUF/RBWUF bit indicates a change in state while in Sleep at pins GP0/RB0, GP1/RB1, GP3/RB3 or RB4 (since the last file or bit operation on GP/RB port).

Note: Caution: Right before entering Sleep,

read the input pins. When in Sleep, wakeup occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read befo re reentering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode.

The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source.

bit (STATUS<4>) is set, the PD

pin low.

DD or VSS and the

/VPP pin must be at a logic high

, PD and

bit,

7.10 Program Veri fication/Code Protection

If the code protecti on bit has not been p rogrammed, the on-chip program memory can be read out for verification purposes.

The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting.

The last memory loca tion can be read reg ardless of the code protection bit setting on the PIC12F508/509/ 16F505 devices.

7.11 ID Locations

Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Progr am/ Verify.

Use only the lower 4 bit s of the ID locati ons and alw ays program the upper 8 bits as ‘0’s.

7.12 In-Circuit Serial Programming™

The PIC12F508/509/16F505 microcontrollers can be serially programme d while in the en d application circ uit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom fi rmware, to be programmed.

The devices are pl aced into a Program/Verify mode by holding the GP1/RB1 an d GP0/RB0 pins low whil e raising the MCLR ming specification). GP1/RB1 becomes the programming clock and GP0/RB0 becomes the programming data. Both GP1/RB1 and GP0/RB0 are Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the device. Depending on the command , 14 b its of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the PIC12F508/509/16F505 Programming Specifications.

A typical In-Circuit Serial Programming connection is shown in Figure 7-16.

(VPP) pin from VIL to VIHH (see program-

FIGURE 7-16: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING CONNECTION

To Normal

External Connector Signals

+5V

Connections

PIC16F505 PIC12F508 PIC12F509

V VSS MCLR/VPP

PIC12F508/509/16F505

CLK

Data I/O

To Normal Connections

GP1/RB1

GP0/RB0

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

8.0 INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is comprised of three basic categories.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 8-1, while the various opcode fields are summarized in Table 8-1.

For byte-oriented instructions , ‘f’ represent s a file reg- ister designator and ‘ d’ represents a destination designator. The file regi ster designator s pecifies which fi le register is to be used by the instruction.

The destination des ignator specifies w here the result of the operation is to be placed. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in the file register specified in the instruction.

For bit-oriented instru ctions, ‘b’ represents a bit field designator which selects the number of the bit affected by the operation, while ‘f’ represents the number of the file in which the bit is located.

For literal and control operations, ‘k’ represents an 8 or 9-bit constant or literal value.

All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction exec ution time is 1 μs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs.

Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number:

0xhhh

where ‘h’ signifies a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file regi s ter operations

11 6 5 4 0

OPCODE d f (FILE #)

d = 0 for destination W d = 1 for destination f f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of us e for compat ibility with all Microchip software tools.

d Destination select;

d = 0 (store result in W) d = 1 (store result in file register ‘f’) Default is d = 1

label Label name

TOS Top-of-Stack

PC Program Counter

WDT Watchdog Timer counter

Time-out bit

Power-down bit

dest Des ti n a ti o n, either the W re gi ster or the speci fied

[ ] Options ( ) Contents

< > Register bit fi eld

italics User defined term (font is courier)

→ Assigned to

∈ In th e se t of

b = 3-bit bit address f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations – GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

PIC12F508/509/16F505

TABLE 8-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BCF BSF BTFSC BTFSS

ANDL W CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW

Note 1: The 9th bit of the pro gra m c oun ter wil l be fo rce d to a ‘0’ by any instruc tio n tha t writes to th e PC except for

f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d

f, b f, b f, b f, b

k k — k k k — k — f k

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value present on the pins t hemse lves . For examp le, if the dat a la tch is ‘1’ for a pi n conf igured a s inpu t and is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

AND literal with W Call Subroutine Clear Watchdo g Timer Unconditional branch Inclusive OR literal with W Move literal to W Load OPTION register Return, place literal in W Go into Standby mode Load TRIS register Exclusive OR literal to W

Description Cycles

1 1 1 1 1 1

(2)

1 1 1 1 1 1 1 1 1

BIT-ORIENTED FILE REGISTER OPERATIONS

1 1

(2)

LITERAL AND CONTROL OPERATIONS

1 2 1 2 1 1 1 2 1 1 1

12-Bit Opcode

MSb LSb

0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001

0100 0101 0110 0111

1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111

11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df

bbbf bbbf bbbf bbbf

kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk

ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk

Status

Affected

C, DC, Z

Z Z Z Z Z

None

Z None None

C, DC, Z

None

None None None None

Z None

, PD

None

Z None None None

, PD

None

Notes

1, 2, 4

2, 4

2, 4 2, 4 2, 4 2, 4 2, 4 2, 4 1, 4

2, 4 2, 4

1, 2, 4

2, 4 2, 4

PIC12F508/509/16F505

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Description: Add the contents of the W register

and register ‘f’. If ‘d’ is’0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

ANDLW AND literal with W

Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W).AND. (k) → (W)

Status Affected: Z

Description: The contents of the W register are

AND’ed with the eight-bit literal ‘k’. The result is placed in the W register.

BCF Bit Clear f

Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None

Description: Bit ‘b’ in register ‘f’ is set.

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Description: The contents of the W register are

AND’ed with register ‘f’. If ‘d ’ is ‘0’,

the result is stored in the W register .

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Description: If bit ‘b’ in regis ter ‘f’ is ‘ 0’, then the

next instruction is skipped.

If bit ‘b’ is ‘0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOP is executed instead,

making this a two-cy cle i nstruc tion.

PIC12F508/509/16F505

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 31

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, the n the nex t ins tru c-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed instead,

making this a two-cycle instruction.

CALL Subroutine Call

Syntax: [ label ] CALL k Operands: 0 ≤ k ≤ 255 Operation: (PC) + 1→ Top-of-Stack;

k → PC<7:0>;

(STATUS<6:5>) → PC<10:9>;

0 → PC<8> Status Affected: None Description: Subroutine call. First, return

address (PC + 1) is PUSHed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

ST ATUS<6:5>, PC<8> is cleared.

CALL is a two-cycle instruction.

CLRW Clear W

Syntax: [ label ] CLRW Operands: None Operation: 00h → (W);

1 → Z Status Affected: Z Description: The W register is cleared. Zero bit

(Z) is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD Status Affected: TO, PD Description: The CLRWDT instruction resets the

WDT . It a lso reset s the prescaler , if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

CLRF Clear f

Syntax: [ label ] CLRF f Operands: 0 ≤ f ≤ 31 Operation: 00h → (f);

1 → Z Status Affected: Z Description: The contents of register ‘f’ are

cleared and the Z bit is set.

COMF Complement f

Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f Status Affected: Z Descriptio n: The co ntents of register ‘f’ are

) → (dest)

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stor ed back in

PIC12F508/509/16F505

DECF Decrement f

Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → (dest) Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOP is executed

instead making it a two-cycle

instruction.

INCF Increment f

Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Descriptio n: The co ntents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Descriptio n: The co ntents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOP is

executed instead making it a

two-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k Operands: 0 ≤ k ≤ 511 Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9> Status Affected: None Description: GOTO is an unconditional branch.

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTO is a two-

cycle instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (k) → (W) Status Affected: Z Description: The contents of the W regis ter are

OR’ed with the eight-bit literal ‘k’. The result is placed in the W register .

PIC12F508/509/16F505

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W).OR. (f) → (dest) Status Affected: Z Description: I nclusive OR the W register with

placed in the W regis ter. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

MOVF Move f

Syntax: [ label ] MOVF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Description: The contents of register ‘f’ are

moved to destina tion ‘d’. If ‘d’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file

test of a file register, since status

flag Z is affected.

MOVWF Move W to f

Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 31 Operation: (W) → (f) Status Affected: None Description: Move data from the W register to

NOP No Operation

Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Description: No operation.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Description: The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

cares” will assembled as ‘0’s.

OPTION Load OPTION Register

Syntax: [ label ] OPTION Operands: None Operation: (W) → OPTION Status Affected: None Description: The content of the W register is

loaded into the OPTION register.

PIC12F508/509/16F505

RETLW Return with Literal in W

Syntax: [ label ] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Description: The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instructi on.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is stored back in

SLEEP Enter SLEEP Mode

Syntax: Operands: None

Operation: 00h → WDT;

Status Affected: TO, PD, RBWUF Description: Time-out S t atus bit (TO

SUBWF Subtract W from f

Syntax: Operands: 0 ≤ f ≤ 31

Operation: (f) – (W) → (dest) Stat us Affected: C, DC, Z Description: Subtract (2’s comp lemen t method )

[label ]

0 → WDT prescaler; 1 → TO 0 → PD

Power-down St atu s bit (PD cleared.

RBWUF is unaffected. The WDT and its prescaler are

cleared. The processor is put in to Sleep

mode with the oscillato r st op ped . See Section 7.9 “Po wer-down Mode (Sleep)” on Sleep for more details.

[label ] SUBWF f,d

d ∈ [0,1]

the W register from register ‘ f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.

SLEEP

;

) is set. The

) is

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>) Status Affected: None Description: The upper and lower nibbles of

‘0’, the result is placed in W

placed in register ‘f’.

PIC12F508/509/16F505

TRIS Load TRIS Register

Syntax: [ label ] TRIS f Operands: f = Operation: (W) → TRIS register f Status Affected: None Description: TRIS register ‘f’ (f = 6 or 7) is

XORLW Exclusive OR literal with W

Syntax: Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are

loaded with the contents of the W register

[label ]XORLW k

XOR’ed with the eight- bit lite ral ‘k ’. The result is placed in the W register.

XORWF Exclusive OR W wit h f

Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

PIC12F508/509/16F505

9.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a full range of ha rdware a nd softwa re develo pment to ols:

• Integrated Development Environment

- MPLAB

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK MPLIB

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Programmers

- PICSTART

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration and Development Boards and Evaluation Kits

IDE Software

Object Linker/

Object Librarian

Plus Development Programmer

9.1 MPLAB Integrated Development Environment Software

The MPLAB IDE so ftware brin gs an ease of sof tware development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows operating system-bas ed application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Deb ugger (sol d separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR C Compilers

The MPLAB IDE allows you to:

• Edit your s ource files (either assembly or C)

• One touch assemble (or compile) and download

to PICmicro MCU emulator and simulator tools (automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.

PIC12F508/509/16F505

9.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs.

The MPASM Assembler generates relocatable object files for the MPLINK Ob ject Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline assembly code

• Conditional assembly for multi-purpose source files

• Directives that allow complete control over the assembly process

standard HEX

9.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 family of microcontrollers and dsPIC30F family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers.

For easy source level debuggi ng, the compil ers provide symbol information that is opt imized to the MPLAB IDE debugger.

9.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script.

The MPLIB Object Librar ian manag es the cre ation an d modification of library files of precompiled code. When a routine from a library is called from a source file , only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many smaller files

• Enhanced code maintainability by grouping related modules together

• Flexible creation of libraries with easy module listing, replacement, deletion and extraction

9.5 MPLAB ASM30 Assembler, Linker and Librarian

MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linke d with other relocat able object fi les and archives t o cr eat e an e xec utabl e fi le. Notab le f eat ures of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

9.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code developmen t in a PC-hosted env ironment by simu lating the PICmicro MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program ex ecution, actions on I/O, as well as intern al registers.

The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.

PIC12F508/509/16F505

9.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.

The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interc hangeabl e proces sor modul es allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PICmicro microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft chosen to best make these features available in a simple, unified application.

Windows® 32-bit operating system were

9.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PICmicro MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emula tor features inc lude comple x triggering and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.

9.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial Programming offers cost-effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debu g source code b y setting bre akpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.

(ICSPTM) protocol,

9.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus an d error m essag es and a m odular, detachable socket assembly to support various package type s. The ICSP™ cable as sembly is incl uded as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can rea d, verify an d program PICmicro devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-spe ed comm unicatio ns and optimized algorithms for quick programming of large memory devices and in corporates an SD/MMC card f or file storage and secure data applications.

PIC12F508/509/16F505

9.1 1 PICSTART Plus Development Programmer

The PICSTART Plus Develo pment Program mer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Devel opmen t Envi ronme nt sof tware makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be sup ported with a n adapter socke t. The PICSTART Plus Development Programmer is CE compliant.

9.12 Demonstration, Development and Evaluation Boards

A wide variety of demonstration, development and evaluation boards for various PICmicro MCUs and dsPIC DSCs allows qui ck applicatio n development o n fully functional syst ems. Most boards inc lude prototy ping areas for adding custom circuitry and provide application firmware and source code for examination and modification.

The boards suppo rt a variety of fea tures, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory.

The demonstration and development boards can be used in teaching environ ments, for prototyping custom circuits and for learning about various microcontroller applications.

In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, K

, PowerSmart® battery management, SEEVAL

IrDA evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more.

Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits.

EELOQ

security ICs, CAN,

10.0 ELECTRICAL CHARACTERISTICS

PIC12F508/509/16F505

Absolute Maximum Ratings

(†)

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature............................................................................................................................-65°C to +150°C

Voltage on V Voltage on MCLR Voltage on all other pins with respect to V Total power dissipation Max. current out of V Max. current into V Input clamp current, I Output clamp current, I

DD with respect to VSS ...............................................................................................................0 to +6.5V

with respect to VSS..........................................................................................................0 to +13.5V

SS ...............................................................................-0.3V to (VDD + 0.3V)

(1)

..................................................................................................................................800 mW

SS pin.................................................................................................... ..... ...... ...... ...........200 mA

DD pin...................................................................................................................................150 mA

IK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

OK (VO < 0 or VO > VDD)...........................................................................................................±20 mA

Max. output current sunk by any I/O pin..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissipation is calculated as fol lows: P

†

NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

DIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi c at e d in t he o pe rat i o n l is tin g s o f t his s pec if i ca t io n is not i mp li e d. Ex po su r e to m ax im um r at i ng c ond it i on s for extended periods may affect device reliability.

PIC12F508/509/16F505

FIGURE 10-1: PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

6.0

5.5

5.0

4.5

(Volts)

4.0

3.5

3.0

2.5

2.0 0

410

Frequency (MHz)

FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE

LP XT

INTOSC

XTRC

Oscillator Mode

200 kHz

4 MHz 20 MHz

Frequency (MHz)

PIC12F508/509/16F505

10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)

DC CHARACTERISTICS

Param

No.

D001 V

Sym Characteristic Min Ty p

DD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Voltage D003 V

POR VDD Start Voltage to ensure

Power-on Reset

D004 S

VDD VDD Rise Rate to ensure

Power-on Reset

D010 I

DD Supply Current

(3)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ T

(1)

Max Units Conditions

(2)

— 1.5* — V Device in Sleep mode

A ≤ +85°C (industrial)

—VSS —VSee Section 7.4 "DC Characteris-

tics" for details

0.05*— — V/ms See Section 7.4 "DC Characteris- tics" for details

—

170 — — —

0.4

1.7 15

TBD TBD TBD TBD

μA

FOSC = 4 MHz, VDD = 2.0V FOSC = 10 MHz, VDD = 3.0V

μA

OSC = 20 MHz, VDD = 5.0V OSC = 32 kHz, VDD = 2.0V, WDT

(4)

disabled

D020 I

PD Power-down Current

D022 ΔIWDT WDT Current

(5)

—0.1TBDμAVDD = 2.0V —1.0TBDμAVDD = 2.0V

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which V

DD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscilla tor ty pe , bu s rat e, in tern al c od e ex ec uti on pattern and temperature also have an imp a ct o n the current consumption.

a) The test conditions for all I

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

= VDD; WDT enabled/disabled as specified.

MCLR

DD measurements in active operation mode are:

SS, T0CKI = VDD,

b) For standby current measurements, the conditions are the same, except that the device is in Sleep

mode.

4: Does not include current through R

EXT (in EXTRC mode only). The current through the resistor can be

estimated by the formula: I = VDD/2REXT (mA) with REXT in kΩ.

5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V

DD or VSS.

PIC12F508/509/16F505

10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)

DC CHARACTERISTICS

Param

No.

D001 V

Sym Characteristic Min Typ

DD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Volt age D003 V

POR VDD Start Voltage to ensure

Power-on Reset

D004 S

VDD VDD Rise Rate to ensure

Power-on Reset

D010 I

DD Supply Current

(3)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ T

(1)

Max Units Conditions

(2)

— 1.5* — V Device in Sleep mode

A ≤ +125°C (Extended)

—VSS —VSee Section 7.4 "DC Character-

istics" for details

0.05* — — V/ms See Section 7.4 "DC Character- istics" for details

—

170 — — —

0.4

1.7 15

TBD TBD TBD TBD

μA

FOSC = 4 MHz, VDD = 2.0V FOSC = 10 MHz, VDD = 3.0V

μA

OSC = 20 MHz, VDD = 5.0V OSC = 32 kHz, VDD = 2.0V, WDT

(4)

disabled

D020 I

PD Power-down Current

D022 ΔIWDT WDT Current

(5)

—0.1TBDμAVDD = 2.0V —1.0TBDμAVDD = 2.0V

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which V

DD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillato r type, bus rate, internal code execution p a ttern an d te mp era t ure als o hav e a n i mpact on the current consumption.

a) The test conditions for all I

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

= VDD;

MCLR

DD measurements in active operation mode are:

SS, T0CKI = VDD,

WDT enabled/disabled as specified.

a) For standby current measurements, the conditions are the same, except that the device is in Sleep

mode.

4: Does not include current through R

EXT (in EXTRC mode only). The current through the resistor can be

estimated by the formula: I = VDD/2REXT (mA) with REXT in kΩ.

5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V

DD or VSS.

PIC12F508/509/16F505

TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial , Extended)

Standard Operating Conditions (unless otherwise specified)

DC CHARACTERISTICS

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

IL Input Low Voltage

Operating temperature -40°C ≤ T Operating voltage V

DD range as described in DC specification

I/O ports: D030 with TTL buffer Vss — 0.8V V For all 4.5 ≤ V D030A Vss — 0.15 V D031 with Schmitt Trigger buffer Vss — 0.15 V D032 MCLR

, T0CKI Vss — 0.15 VDD V D033 OSC1 (in EXTRC) Vss — 0.15 V D033 OSC1 (in HS) Vss — 0.3 V D033 OSC1 (in XT and LP) Vss — 0.3 V (Note1)

IH Input High Voltage

I/O ports: — D040 with TTL buffer 2.0 — V D040A 0.25 V

—VDD V Otherwise

+ 0.8 VDD D041 with Schmitt Trigger buffer 0.85 V D042 M CLR, T0CKI 0.85 V D043 OSC1 (in EXTRC) 0.85 V D043 OSC1 (in HS) 0.7 V

DD —VDD V For entire VDD range DD —VDD V DD —VDD V (Note1)

DD —VDD V (Note1)

D043 OSC1 (in XT and LP) 1.6 — V D070 I

PUR GPIO weak pull-up current

IIL Input Le akage Current

(2), (3)

(4)

TBD 250 TBD μAVDD = 5V, VPIN = VSS

D060 I/O ports — — ± 1 μAVss ≤ VPIN ≤ VDD, Pin at high-impedance D061 GP3/RB3/MCLR D061A GP3/RB3/MCLRI

(5)

(6)

——± 30μAVss ≤ VPIN ≤ VDD ——± 5μAVss ≤ VPIN ≤ VDD

D063 OSC1 — — ± 5 μAVss ≤ VPIN ≤ VDD, XT, HS and LP oscillator

Output Low Voltage

D080 I/O ports/CLKOUT — — 0.6 V I D080A — — 0.6 V I D083 OSC2 — — 0.6 V I D083A — — 0.6 V I

Output High Voltage

D090 I/O ports/CLKOUT D090A V D092 OSC2 V D092A V

(3)

VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C

DD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C DD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C DD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C

Capacitive Loading Specs on Output Pins

D100 OSC2 pin — — 15 pF In XT , HS and LP modes when external clock is

D101 All I/O pins and OSC2 — — 50 pF Legend: TBD = To Be Determined.

† Data in “Ty p” colum n is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/

16F505 be driven with external clock in RC mode.

2: The leaka ge cu rren t on th e MCLR

pin is strongly dependent on the applied voltage level. The specified levels represent normal operating

conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin. 4: Does not include GP3/ RB3. For GP3/RB3 see par ameters D061 and D061A. 5: This specification applies to GP3/RB3/MCLR

enabled.

6: This specification applies when GP3/RB3/MCLR

configured as external MCLR and GP3/RB3/MCLR configured as input with internal pull-up

is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

A ≤ +85°C (industrial ) A ≤ +125°C (extended)

-40°C ≤ T

DD ≤ 5.5V DD V Otherwise DD V

DD V (Note1)

DD V4.5 ≤ VDD ≤ 5.5V

DD V

configuration

OL = 8.5 mA, VDD = 4.5V, -40°C to +85°C OL = 7.0 mA, VDD = 4.5V, -40°C to +125°C OL = 1.6 mA, VDD = 4.5V, -40°C to +85°C OL = 1.2 mA, VDD = 4.5V, -40°C to +125°C

used to drive OSC1.

PIC12F508/509/16F505

TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505

VDD (Volts) Temperature (°C) Min Typ Max Units

RB0/RB1/RB4

2.0 -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

5.5 -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

RB3

2.0 -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

5.5 -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

Legend: TBD = To Be determined.

* These parameters are characterized but not tested.

PIC12F508/509/16F505

10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR ck CLKOUT osc Oscillator cy Cycle time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings:

FFall PPeriod HHigh RRise I Invalid (high-impedance) V Valid L Low Z High-impedance

FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505

Legend:

VSS

L = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock is used to drive OSC1

FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505

OSC1

Q1 Q2

133

Q3 Q4 Q1

PIC12F508/509/16F505

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505

Standard Opera ting Conditi ons (unle ss otherw is e speci fied)

A ≤ +85°C (industrial), A ≤ +125°C (extended)

only)

AC CHARACTERISTICS

Param

No.

1A F

Sym Characteristic Min Typ

OSC External CLKIN Frequency

Oscillator Frequency

OSC External CLKIN Period

Oscillator Period

(2)

Operating Temperature -40°C ≤ T

-40°C ≤ T

Operating Voltage V

DD range is described in Section 10.1 "DC

Characteristics"

(1)

Max Units Conditions

(2)

DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode (PIC16F505

DC — 200 kHz LP Oscillator mode

— — 4 MHz EXTRC Oscillator mode

0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS Oscillator mode (PIC16F505

— — 200 kHz LP Oscillator mode

250 — — ns XT Oscillator mode

50 — — ns HS Oscillat or mode (PIC16 F505

5——μs LP Oscillator mode

250 — — ns EXTRC Oscillator mode 250 — 10,000 ns XT Oscillator mode

50 — 250 ns HS Oscillator mode (PIC16F505

only)

5——μs LP Oscillator mode

2T 3 TosL,

CY Instruction Cycle Time 200 4/FOSC —ns

TosH

Clock in (OSC1) Low or High Time

50* — — ns XT Oscillator

2* — — μs LP Oscillator

10* — — ns HS Oscillator (PIC16F505 only)

4TosR,

TosF

Clock in (OSC1) Rise or Fall Time

— — 25* ns XT Oscillator — — 50* ns LP Oscillator — — 15* ns HS Oscillator (PIC16 F505 only)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC12F508/509/16F505

TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ T

AC CHARACTERISTICS

Operating Voltage V

Section 10.1 "DC Characteristics"

Param

No.

Sym Characteristic

F10 FOSC Internal Calibrated

INTOSC Frequency

(1)

Freq

Tolerance

± 1% 7.92 4.00 8.08 MHz VDD and Temperature

± 2% 7.84 4.00 8.16 MHz 2.5V ≤ V

± 5% 7.60 4.00 8.40 MHz 2.0V ≤ V

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: To ensure these oscil lat or f r equ ency to lerances, V

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

-40°C ≤ T

DD range is described in

Min Typ† Max Units Conditions

DD and VSS must be capacitively decoupled as close to

A ≤ +85°C (industrial),

A ≤ +125°C (extended)

TBD

A ≤ +85°C

0°C ≤ T

-40°C ≤ T

DD ≤ 5.5V

A ≤ +85°C (Ind.) A ≤ +125°C (Ext.)

FIGURE 10-5: I/O TIMING – PIC12F508/509/16F505

OSC1

I/O Pin

(input)

I/O Pin

(output)

Old Value

20, 21

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

Q2 Q3

New Value

PIC12F508/509/16F505

TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS

Param

No.

17 T

Sym Characteristic Min Typ

OSH2IOVOSC1↑ (Q1 cycle) to Port Out Valid

18 TOSH2IOIOSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hol d ti me) 19 T

20 T 21 T

IOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) TBD — — ns IOR Port Output Rise Time IOF Port Output Fall Time

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested. ** These parameters are design targets and are not tested.

Note 1: Data in the Typical (“Typ”) col umn is a t 5V, 25°C unless otherwis e st ated. Th ese p aramete rs ar e for de sign

guidance only and are not tested.

2: Measurements are taken in EXTRC mode. 3: See Figure 10-3 for loading conditions.

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage V

-40°C ≤ T

DD range is described in Section 10.1 "DC Characteristics"

(3)

A ≤ +125°C (extended)

(2), (3)

(1)

Max Units

— — 100* ns

(2)

TBD — — ns

—1025**ns —1025**ns

FIGURE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC12F508/509/16F505

VDD

MCLR

Internal

POR

DRT

Timeout

Internal

Reset

Watchdog

Timer

Reset

I/O pin

(2)

(1)

Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

2: Runs in MCLR

or WDT Reset only in XT, LP and HS (PIC16F505) modes.

PIC12F508/509/16F505

T ABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505

Standard Operat ing Cond ition s (unle ss oth erwise s peci fied)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

AC CHARACTERISTICS

Param

No.

Sym Characteristic Min Typ

Operating Temperature -40°C ≤ T

-40°C ≤ T

Operating Voltage V

DD range is described in

Section 10.1 "DC Characteristics "

(1)

Max Units Conditions

30 T 31 T

32 TDRT Device Reset Timer Period

34 T

MCLMCLR Pulse Width (low) 2000* — — ns VDD = 5.0V WDT Watchdog Timer T ime-out Period

(no prescaler)

(2)

IOZ I/O High-impedance from MCLR

9* 9*

18* 18*

30* 40*

msmsVDD = 5.0V (Industrial)

— — 2000* ns

DD = 5.0V (Extended)

low

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

PIC12F508/509/16F505

FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505

T0CKI

40 41

TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ T

AC CHARACTERISTICS

Operating Voltage V

Section 10.1 "DC Characterist ics"

Param

40 Tt0H T0CKI High Pulse

41 Tt0L T0CKI Low Pulse

42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater.

Note 1: Data in the T y pica l (“Typ”) column is at 5V , 25°C unl ess oth erwise s tate d. These para meters are for desi gn

Sym Characteristic Min Typ

No.

No Prescaler 0.5 T

Width

* These parameters are characterized but not tested.

guidance only and are not tested.

With Prescaler 10* — — ns No Prescaler 0.5 T With Prescaler 10* — — ns

-40°C ≤ T

DD range is described in

CY + 20* — — ns

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

N = Prescale Value (1, 2, 4,..., 256)

11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

Graphs and charts are not available at this time.

PIC12F508/509/16F505

NOTES:

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

PIC12F508/509/16F505

8-Lead PDIP

XXXXXXXX

XXXXXNNN

YYWW

8-Lead SOIC (.150”)

XXXXXXXX

XXXXYYWW

NNN

8-Lead MSOP

XXXXXX

YWWNNN

Example

12F508-I /P017

0410

Example

12F509-I

/SN0410

017

Example

12F509

0431017

Legend: XX...X Customer-specific info rm atio n

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip p art numb er canno t be mark ed on one line, it wil l

be carried over to the next line thus limiting the number of available characters for customer specific information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

PIC12F508/509/16F505

12.1 Package Marking Information (Cont’d)

14-Lead PDIP (300 mil)

XXXXXXXXXXXXXX XXXXXXXXXXXXXX

YYWWNNN

14-Lead SOIC (150 mil)

XXXXXXXXXXX XXXXXXXXXXX

YYWWNNN

14-Lead TSSOP (150 mil)

XXXXXXXX

YYWW

NNN

Example

PIC16F505-I/PG

0215

0410017

Example

PIC16F505-E /SLG0125

0431017

Example

16F505-I

0431

017

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

PIC12F508/509/16F505

Number of Pins Pitch Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

Units INCHES* MILLIMETERS

n p

α β

.008 .012 .015 0.20 0.29 0.38

.100 2.54

51015 51015 51015 51015

PIC12F508/509/16F505

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Number of Pins Pitch

Foot Angle Lead Thickness

Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057

45°

n p

048048

MILLIMETERSINCHES*Units

1.27.050

MAXNOMMINMAXNOMMINDimension Limits

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2Molded Packag e Thickness

0.250.180.10.010.007.004A1Standoff §

6.206.025.79.244.237.228EOverall Width

3.993.913.71.157.154.146E1Molded Package Width

5.004.904.80.197.193.189DOverall Length

0.510.380.25.020.015.010hChamfer Distance

0.760.620.48.030.025.019LFoot Length

0.250.230.20.010.009.008

0.510.420.33.020.017.013BLead Width 1512015120 1512015120

PIC12F508/509/16F505

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

n 1

(F)

Units

Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length

Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom

*Controlling Parameter Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-187

Drawing No. C04-111

MIN

n p

D L

α β

.026 BSC

.030 .000

.193 TYP. .118 BSC .118 BSC

.016 .024

.037 REFFFootprint (Reference)

0° - 8° .003 .009

5°

5° -

INCHES

NOM

.033

.006 .012

MAX NOM

.043 .037 .006

.031

.009 .016

15° 15°

MIN

0.75

0.00

0.40

0.08

0.22

MILLIMETERS*

MAX

0.65 BSC

0.85

4.90 BSC

3.00 BSC

0.60

0.95 REF

0°

1.10

0.95

0.15

0.80

8°

0.23

0.40 15°5° 15°5° -

PIC12F508/509/16F505

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Number of Pins Pitch Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width Overall Length D .740 .75 0 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-001 Drawing No. C04-005

Dimension Limits M IN NOM MAX MIN NOM MAX

Units INCHES* MILLIMETERS

n p

.240 .250 .260 6.10 6.35 6.60

.008 .012 .015 0.20 0.29 0.38

5 10 15 5 10 15 5 10 15 5 10 15Mold Draft Angle Bottom

14 14

.100 2.54

PIC12F508/509/16F505

14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)

45°

Number of Pins Pitch

Foot Angle Lead Thickne ss

Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065

n p

α β

048048

MILLIMETERSINCHES*Units

1.27.050

MAXNOMMINMAXNOMMINDimension Limits

1414

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2Molded Packag e Thickness

0.250.180.10.010.007.004A1Standoff §

6.205.995.79.244.236.228EOverall Width

3.993.903.81.157.154.150E1Molded Package Width

8.818.698.56.347.342.337DOverall Length

0.510.380.25.020.015.010hChamfer Distance

1.270.840.41.050.033.016LFoot Length

0.250.230.20.010.009.008

0.510.420.36.020.017.014BLead Width 1512015120 1512015120

PIC12F508/509/16F505

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

Number of Pins Pitch

Foot Angle Lead Thickne ss

Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087

n p

MILLIMETERS*INCHESUnits

0.65.026

A2A1

MAXNOMMINMAXNOMMINDimension Limits

1414

1.10.043AOverall Height

0.950.900.85.037.035.033A2Molded Package Thickness

0.150.100.05.006.004.002A1Standoff §

6.506.386.25.256.251.246EOverall Width

4.504.404.30.177.173.169E1Mold ed Packag e Width

5.105.004.90.201.197.193DMolded Package Length

0.700.600.50.028.024.020LFoot Length 840840

0.200.150.09.008.006.004

0.300.250.19.012.010.007BLead Width

10501050 10501050

APPENDIX A: REVISION HISTORY

Revision A (April 2004)

Original data sheet for PIC12F508/509/16F505 devices

Revision B (June 2005)

Update packages

PIC12F508/509/16F505

NOTES:

INDEX

PIC12F508/509/16F505

ALU....................................................................................... 9

Assembler

MPASM Assembler.....................................................64

Block Diagram

On-Chip Reset Circuit........................ .........................47

Timer0......................................................................... 33

TMR0/WDT Prescaler.................................................37

Watchdog Timer..........................................................50

Brown-Out Protection Circuit ..............................................51

C Compilers

MPLAB C18...................... ......................... .................64

MPLAB C30...................... ......................... .................64

Carry..................................................................................... 9

Clocking Scheme................................................................14

Code Protection ............................................................39, 52

Configuration Bits................................................................39

Configuration Word.............................................................40

Customer Change Notification Service ...............................93

Customer Notification Ser vice.................. ...........................93

Customer Support...............................................................93

DC and AC Characteristics.................................................79

Development Support .........................................................63

Digit Carry.............................................................................9

Errata....................................................................................3

Family of Devices

PIC12F508/509/PIC16F505..........................................5

FSR .....................................................................................26

I/O Interfacing.....................................................................29

I/O Ports..................... .........................................................29

I/O Programming Considerations................. .......................31

ID Locations..................................................................39, 52

INDF....................................................................................26

Indirect Data Addressing..................................................... 26

Instruction Cycle ................................................................. 14

Instruction Flow/Pipelining.................................................. 14

Instruction Set Summary.....................................................56

Internet Address.............................. .......................... ..........93

Loading of PC ............................................................. .. .. .. ..25

Memory Organization..........................................................15

Data Memory ....................................... .......................16

Program Memory (PIC12F508/509)............................ 15

Program Memory (PIC16F505)................................... 16

Microchip Internet Web Site................................................93

MPLAB ASM30 Assembler, Linker, Librarian .....................64

MPLAB ICD 2 In-Circuit Debugger .....................................65

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator ...................................................... 65

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator...................................................... 65

MPLAB Integrated Development Environment Software.... 63

MPLAB PM3 Device Programmer...................................... 65

MPLINK Obje ct Linker/MPLIB Object Li b ra r i an .................. 64

Option Register................................................................... 22

OSC selection..................................................................... 39

OSCCAL Register....................................................... ........ 24

Oscillator Configurations.............. ....................................... 41

Oscillator Types

HS............................................................................... 41

LP............................................................................... 41

RC .............................................................................. 41

XT...............................................................................41

PIC12F508/509/16F505 Device Varieties ............................ 7

PICSTART Plus Development Programmer.......................66

POR

Device Reset Timer (DR T) .................... .. ............ . 39 , 4 9

............................................................................... 51

Power-on Reset (POR)............................................... 39

............................................................................... 51

PORTB............................................................................... 29

Power-down Mode.............................................................. 52

Prescaler ............................................................................ 36

Program Counter................................................................ 25

Q cycles........... ............................................................. ...... 14

RC Oscillator....................................................................... 42

Reader Response............................................................... 94

Read-Modify-Write.............................................................. 31

PIC12F508 .................................................................17

PIC12F509 .................................................................17

PIC16F505 .................................................................17

Registers

Special Function......................................................... 18

Reset.................................................................................. 39

Reset on Brown-Out............... .......................... .................. 51

Sleep ............................................................................ 39, 52

Software Simulator ( MP L AB SIM ).................... .................. 64

Special Features of the CPU.............................................. 39

Special Function Registers................................................. 18

Stack................................................................................... 25

Status Register...............................................................9, 20

Timer0

Timer0 ........................................................................ 33

Timer0 (TMR0) Module .............................................. 33

TMR0 with External Clock.......................................... 35

Timing Diagrams and Specifications .................................. 73

Timing Parameter Symbology and Load Conditions .......... 73

TRIS Registers.................................... ......................... ...... 29

PIC12F508/509/16F505

Wake-up from Sleep ...........................................................52

Watchdog Timer (WDT) ................................................39, 49

Period..........................................................................49

Programming Considerat io n s.....................................49

WWW Address....................................................................93

WWW, On-Line Support........................................................3

Zero bit............. ......................... ......................... ...................9

PIC12F508/509/16F505

THE MICROCHIP WEB SITE

Microchip provides onlin e support v ia our W WW site at

www.m ic roc hi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

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• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing

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PIC12F508/509/16F505

READER RESPONSE

It is our intentio n to pro vi de you with the best documentation po ss ib le to e ns ure suc c es sfu l u se of y ou r Mic r oc hip pro duct. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter, and ways in which our d ocument ation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: RE: Reader Response From:

Application (optional): Would you like a reply? Y N

Device: Literature Number: Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

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Technical Publications Manager

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Total Pages Sent ________

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DS41236BPIC12F508/509/16F505

4. What additions to the document do you think would enhance the structure and subject?

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PIC12F508/509/16F505

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX XXX

Device

Range

Device: PIC16F505

Temperature Range:

PIC12F508 PIC12F509 PIC16F505T (Tape & Reel) PIC12F508T (Tape & Reel) PIC12F509T (Tape & Reel)

I= -40°C to +85°C (Industrial) E= -40°C to +125°C (Extended)

PatternPackageTemperatu re

Examples:

a) PIC16F505-I/P = Industrial temp., PDIP

package (Pb-free)

b) PIC16F505T-I/SL = Industrial temp., SOIC

package (Pb-free), Tape and Reel

c) PIC16F505T-I/SL = Industrial temp., SOIC

package (Pb-free), Tape and Reel

d) PIC12F508T-I/SN = Industrial temp., 150 mil

SOIC package (Pb-free), Tape and Reel

e) PIC12F508T-E/MS = Extended temp., MSOP

package (Pb-free), Tape and Reel

f) PIC12F509-E/P = Extended temp., PDIP

package (Pb-free)

g) PIC12F509-I/SM = Industrial temp., 208 mil

SOIC package (Pb-free)

Package: P = 300 mil PDIP (Pb-free)

Pattern: Special Requirements

Note: Tape and Reel availabl e for only the fo llowing packages : SOI C, MSOP

SL = 150 mil SOIC, 14-LD (Pb-free) SN = 150 mil SOIC, 8-LD (Pb-free) MS = MSOP (Pb-free) ST = TSSOP (Pb-free)

and TSSOP.

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Tel: 34-91-352-30-52 Fax: 34-91-352-11-47

UK - Wokingham

Tel: 44-118-921-5869 Fax: 44-118-921-5820

07/01/05

MICROCHIP PIC12F508, PIC12F509, PIC16F505 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

8/14-Pin, 8-Bit Flash Microcontroller

1.0 GENERAL DESCRIPTION

2.0 PIC12F508/509/1 6F5 05 DEVIC E VARIETIES

3.0 ARCHITECTURAL OVERVIEW

4.0 MEMORY ORGANIZATION

5.0 I/O PORT

6.0 TIMER0 MODULE AND TMR0 REGISTER

7.0 SPECIAL FEATURES OF THE CPU

8.0 INSTRUCTION SET SUMMARY

9.0 DEVELOPMENT SUPPORT

9.1 MPLAB Integrated Development Environment Software

9.2 MPASM Assembler

9.5 MPLAB ASM30 Assembler, Linker and Librarian

9.6 MPLAB SIM Software Simulator

9.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator

9.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator

9.9 MPLAB ICD 2 In-Circuit Debugger

9.10 MPLAB PM3 Device Programmer

9.1 1 PICSTART Plus Development Programmer

9.12 Demonstration, Development and Evaluation Boards

10.0 ELECTRICAL CHARACTERISTICS

11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

12.0 PACKAGING INFORMATION

THE MICROCHIP WEB SITE

CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

READER RESPONSE

PRODUCT IDENTIFICATION SYSTEM

WORLDWIDE SALES AND SERVICE