Microchip PIC12C508, PIC12C508A, PIC12CE518, PIC12C509, PIC12C509A Data Sheet

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PIC12C5XX

8-Pin, 8-Bit CMOS Microcontrollers

Devices included in this Data Sheet:

• PIC12C508 • PIC12C508A • PIC12CE518

• PIC12C509 • PIC12C509A • PIC12CE519

• PIC12CR509A Note: Throughout this data sheet PIC12C5XX

refers to the PIC12C508, PIC12C509, PIC12C508A, PI C1 2C 50 9A , PIC12CR509A, PIC12CE518 and PIC12CE519. PIC12CE5XX refers to PIC12CE518 and PIC12CE519.

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (1 µs) except for program branches which are two-cycle

• Operating speed: DC - 4 MHz clock input

Device

PIC12C508 512 x 12 25 PIC12C508A 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C509A 1024 x 12 41 PIC12CE518 512 x 12 25 16 PIC12CE519 1024 x 12 41 16 PIC12CR509A 1024 x 12 41

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for data and instructions

• Internal 4 MHz RC oscillator with programmable calibration

• In-circuit serial programming

DC - 1 µs instruction cycle

Memory

EPROM

Program

ROM

Program

RAM Data

EEPROM

Data

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

• Power-On Reset (POR)

•Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• 1,000,000 erase/write cycle EEPROM data memory

• EEPROM data retention > 40 years

• Power saving SLEEP mode

• Wake-up from SLEEP on pin change

• Internal weak pull-ups on I/O pins

• Internal pull-up on MCLR

• Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low power, high speed CMOS EPROM/ROM technology

• Fully static design

• Wide operating voltage range

• Wide temperature range:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 KHz

- < 1 µA typical standby current

 1999 Microchip Technology Inc. DS40139E-page 1

PIC12C5XX

Pin Diagram - PIC12C508/509

PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed

PIC12C508

GP5/OSC1/CLKIN

GP3/MCLR

VDD

GP4/OSC2

/VPP

PIC12C509

1 2 3 4

8 7 6 5

Pin Diagram - PIC12C508A/509A, PIC12CE518/519

PDIP, 150 & 208 mil SOIC, Windowed CERDIP

PIC12C509A

PIC12CE518

PIC12CE519

GP5/OSC1/CLKIN

GP3/MCLR

VDD

GP4/OSC2

/VPP

PIC12C508A

1 2 3 4

8 7 6 5

Pin Diagram - PIC12CR509A

PDIP, 150 & 208 mil SOIC

VDD

GP5/OSC1/CLKIN

GP4/OSC2

/VPP

GP3/MCLR

PIC12CR509A

1 2 3 4

8 7 6 5

Device Differences

Device

PIC12C508A 3.0-5.5 See Note 1 6 0.7 PIC12LC508A 2.5-5.5 See Note 1 6 0.7 PIC12C508 2.5-5.5 See Note 1 4 0.9 PIC12C509A 3.0-5.5 See Note 1 6 0.7 PIC12LC509A 2.5-5.5 See Note 1 6 0.7 PIC12C509 2.5-5.5 See Note 1 4 0.9 PIC12CR509A 2.5-5.5 See Note 1 6 0.7 PIC12CE518 3.0-5.5 - 6 0.7 PIC12LCE518 2.5-5.5 - 6 0.7 PIC12CE519 3.0-5.5 - 6 0.7 PIC12LCE519 2.5-5.5 - 6 0.7

Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify

oscillator characteristics in your application.

Note 2: See Section 7.2.5 for OSCCAL implementation differences.

Voltage

Range

VSS GP0 GP1 GP2/T0CKI

Oscillator

Calibration

(Bits)

Process

Technology

(Microns)

DS40139E-page 2  1999 Microchip Technology Inc.

PIC12C5XX

TABLE OF CONTENTS

1.0 General Description............................................................................................................................................... 4

2.0 PIC12C5XX Device Varieties................................................................................................................................ 7

3.0 Architectural Overview........................................................................................................................................... 9

4.0 Memory Organizatio n ......................................... .............. ............. .............. ............. ........................... ................ 13

5.0 I/O Port ................................................................................................................................................................21

6.0 Timer0 Module and TMR0 Register .................................................................................................................... 25

7.0 EEPROM Peripheral Operation........................................................................................................................... 29

8.0 Special Features of the CPU...............................................................................................................................35

9.0 Instruction Set Summary..................................................................................................................................... 47

10.0 Development Support.............. ........................... .............. ............. .............. ............. .............. ............. ................ 59

11.0 Electrical Characteristics - PIC12C508/PIC12C509............................................................................................ 65

12.0 DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75

13.0 Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/ PIC12CE518/PIC12CE519/

PIC12LCE518/PIC12LCE519/PIC12LCR509A ...................................................................................................79

14.0 DC and AC Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/

PIC12LCE518/PIC12LCE519/ PIC12LCR509A ..................................................................................................93

15.0 Packaging Information......................................................................................................................................... 99

Index ........................................................................................................................................................................... 105

PIC12C5XX Product Identification System ................................................................................................................ 109

Sales and Support: ..................................................................................................................................................... 109

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet

(include literature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please:

• Fill out and mail in the reader response form in the back of this data sheet.

• E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.

 1999 Microchip Technology Inc. DS40139E-page 3

PIC12C5XX

1.0 GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technolog y is a f amily of low-cost, high performance, 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 µs) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.

The PIC12C5XX products are equipped with speci al features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability.

The PIC12C5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility.

The PIC12C5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM PC and compatible machines.

1.1 Applications

The PIC12C5XX series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient, while the EEPROM data memory technology allows for the changing of calibration factors and security codes. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC12C5XX series very versatile even in areas where no microcon troller use has been considered before (e.g., timer functions, replacement of “glue” logic and PLD’s in larger systems, coprocessor applications).



DS40139E-page 4  1999 Microchip Technology Inc.

TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674

4444410101010

512 x 12 1024 x 12 1024 x 12

25 41 41 25 41 128 128 128 128

———1616——1616

TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0

—————4444

Yes Yes Yes Yes Yes Yes Yes Yes Yes

——— 4444

Yes Yes Yes Yes Yes Yes Yes Yes Yes

Yes Yes — Yes Yes Yes Yes Yes Yes

33 33 33 33 33 35 35 35 35

JW, SOIC

8-pin DIP, JW, SOIC

(ROM)

8-pin DIP, SOIC

512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14

8-pin DIP, JW, SOIC

Clock

Memory

Peripherals

Features

Maximum Frequency of Operation (MHz)

EPROM Program Memory

RAM Data Memory (bytes)

EEPROM Data Memory (bytes)

Timer Module(s)

A/D Converter (8-bit) Channels

Wake-up from SLEEP on pin change

Interrupt Sources

I/O Pins 5 5 5 5 5 5 5 5 5 Input Pins111111111 Internal

Pull-ups In-Circuit

Serial Programming

Number of Instructions

Packages 8 -pin DIP,

PIC12C5XX

8-pin DIP, JW, SOIC

8-pin DIP, JW8-pin DIP,

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

 1999 Microchip Technology Inc. DS40139E-page 5

PIC12C5XX

NOTES:

DS40139E-page 6  1999 Microchip Technology Inc.

PIC12C5XX

2.0 PIC12C5XX DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12C5XX Product Identification System at the back of this data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the configuration modes.

Note: Please note that erasing the device will

also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.

Microchip’s PICSTART grammers all support programming of the PIC12C5XX. Third party programmers also are available; refer to the

Microchip Third Party Guide

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications.

The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.



PLUS and PRO MATE pro-

for a list of sources.

2.3 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Pl ease contact your local Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

2.5 Read Only Memory (ROM) Device

Microchip offers masked ROM to give the customer a low cost option for high volume, mature products.

 1999 Microchip Technology Inc. DS40139E-page 7

PIC12C5XX

NOTES:

DS40139E-page 8  1999 Microchip Technology Inc.

PIC12C5XX

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Har vard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently , all instructions (33) exe cut e in a si n gle cycl e (1 µs @ 4MHz) except f or program branches.

The table below lists program memory (EPROM), data memory (RAM), ROM memory, and non-volatile (EEPROM) for each device.

Memory

Device

PIC12C508 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C508A 512 x 12 25 PIC12C509A 1024 x 12 41 PIC12CR509A 1024 x 12 41 PIC12CE518 512 x 12 25 x 8 16 x 8 PIC12CE519 1024 x 12 41 x 8 16 x 8

The PIC12C5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12C5XX has a highly orthogonal (symmetr ical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make programming with the PIC12C5XX simple yet efficient. In addition, the learning curve is reduced significantly.

EPROM

Program

ROM

Program

RAM Data

EEPROM

Data

The PIC12C5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit wor king register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow

and digit borrow out bit, respectively , in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

 1999 Microchip Technology Inc. DS40139E-page 9

PIC12C5XX

FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM

OSC1/CLKIN

OSC2

Program

Bus

ROM/EPROM

512 x 12 or

1024 x 12

Program Memory

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Internal RC

OSC

Program Counter

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

MCLR

STACK1 STACK2

VDD, VSS

RAM Addr

Data Bus

RAM

25 x 8 or

File

Registers

Addr MUX

5-7

FSR reg

STATUS reg

ALU

W reg

Timer0

MUX

Indirect

Addr

GPIO

SCL

16 X 8

EEPROM

Data

Memory

PIC12CE5XX

Only

GP0 GP1 GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN

SDA

DS40139E-page 1 0  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION

DIP

Name

GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can

GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can

GP2/T0CKI 5 5 I/O ST Bi-directional I/O por t. Can be configured as T0CKI. GP3/MCLR

GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con-

GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external

DD 11P— Positive supply for logic and I/O pins

SS 8 8 P — Ground reference for logic and I/O pins

/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming volt-

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input

Pin #

SOIC Pin #

I/O/P Type

Buffer

Type

be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt T rigger input when used in serial programming mode.

age input. When configured as MCLR active low reset to the device. Voltage on MCLR must not exceed V or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR mode.

nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes).

clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode.

Description

DD during normal device operation

. ST when in MCLR

, this pin is an

/VPP

 1999 Microchip Technology Inc. DS40139E-page 11

PIC12C5XX

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

PC PC+1 PC+2

Fetch IN ST ( PC)

Execute INST (PC-1) Fetch INST (PC+1)

3.2 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cyc le while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Execute INST (PC+1)

Internal phase clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

4. BSF GPIO, BIT1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40139E-page 12  1999 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC12C5XX

4.0 MEMORY ORGANIZATION

PIC12C5XX memory is organized into program memory and data memor y. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A, PICCR509A and PIC12CE519 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization

The PIC12C5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space.

Only the first 512 x 12 (0000h-01FFh) for the PIC12C508, PIC12C508A and PIC12CE518 and 1K x 12 (0000h-03FFh) for the PIC12C509, PIC12C509A, PIC12CR509A, and PIC12CE519 are physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12C508, PIC12C508A and PIC12CE518) or 1K x 12 space (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519). The effective reset vector is at 000h, (see Figure 4-1). Location 01FFh (PIC12C508, PIC12C508A and PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519) contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

CALL, RETLW

Space

User Memory

PC<11:0>

Stack Level 1 Stack Level 2

Reset Vector (note 1)

On-chip Program

Memory

512 Word

On-chip Program

Memory

1024 Word

Note 1: Address 0000h becomes the

effective reset vector. Location 01FFh (PIC12C508, PIC12C508A, PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519) contains the MOVLW XX INTERNAL RC oscillator calibration value.

0000h

01FFh 0200h

03FFh 0400h

7FFh

 1999 Microchip Technology Inc. DS40139E-page 13

PIC12C5XX

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers.

The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special pur pose registers are used to control the I/O port configuration and prescaler options.

The general purpose registers ar e used for data and control information under command of the instructions.

FIGURE 4-2: PIC12C508, PIC12C508A AND

PIC12CE518 REGISTER FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

For the PIC12C508, PIC12C508A and PIC12CE518, the register file is composed of 7 special function registers and 25 general pur pose registers (Figure 4-

2). For the PIC12C509, PIC12C509A, PIC12CR509A,

General Purpose

Registers

and PIC12CE519 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Fig ure 4-3).

4.2.1 GENERAL PURPOSE REGISTER FILE

1Fh

Note 1: Not a physical register. See Section4.8

The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8).

FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.8

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General Purpose Registers

Bank 0 Bank 1

20h

Addresses map back to addresses in Bank 0.

2Fh

30h

General Purpose Registers

3Fh

DS40139E-page 1 4  1999 Microchip Technology Inc.

PIC12C5XX

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the operation of the device (Table 4-1).

The special registers can be classified into two sets. The special function registers associated with the

“core” functions are described in this section. Tho se related to the operation of the per ipheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS — —

N/A OPTION 00h INDF Uses contents of FSR to address data memory (not a physical register) 01h TMR0 8-bit real-time clock/counter

(1)

02h 03h STATUS GPWUF —PA0TO PD ZDCC

04h

05h

06h

PCL Low order 8 bits of PC

FSR (PIC12C508/ PIC12C508A/ PIC12C518)

FSR (PIC12C509/ PIC12C509A/ PIC12CR509A/ PIC12CE519)

OSCCAL (PIC12C508/ PIC12C509) CAL3 CAL2 CAL1 CAL0

OSCCAL (PIC12C508A/ PIC12C509A/ PIC12CE518/ PIC12CE519/ PIC12CR509A) CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)

GPIO (PIC12CE518/ PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0

Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as ’0’ (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6

for an explanation of how to access these bits. 2: Other (non power-up) resets include external reset through MCLR 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.

Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-up on chan ge, an d wea k pul l-u ps

Indirect data memory address pointer

— — — —

— —

— — GP5 GP4 GP3 GP2 GP1 GP0

, watchdog timer and wake-up on pin change reset.

Value on

Power-On

Reset

Value on All Other

Resets

(2)

--11 1111 --11 1111

1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0001 1xxx q00q quuu

111x xxxx 111u uuuu

110x xxxx 11uu uuuu

0111 ---- uuuu ----

1000 00-- uuuu uu--

--xx xxxx --uu uuuu

11xx xxxx 11uu uuuu

(3)

 1999 Microchip Technology Inc. DS40139E-page 15

PIC12C5XX

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furtherm ore, the TO

and PD bits are

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.

not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF

bit7 6 5 4 3 2 1 bit0 bit 7: GPWUF: GPIO reset bit

bit 6: Unimplemented bit 5: PA0: Program page preselect bits

bit 4: TO

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow

bit 0: C: Carry/borrow

—

1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset

1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12C5XX Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products.

: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

PA0 TO PD Z DC C R = Readable bit

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

W = Writable bit

- n = Value at POR reset

DS40139E-page 1 6  1999 Microchip Technology Inc.

PIC12C5XX

4.4 OPTION Register

The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of GPPU

Note: If the T0CS bit is set to ‘1’, GP2 is forced to

be an input even if TRIS GP2 = ‘0’.

FIGURE 4-5: OPTION REGISTER

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit7 6 5 4 3 2 1 bit0

bit 7: GPWU

bit 6: GPPU

bit 5: T0CS: Timer0 clock source select bit

bit 4: T0SE: Timer0 source edge select bit

bit 3: PSA: Prescaler assignment bit

bit 2-0: PS2:PS0: Prescaler rate select bits

GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

: Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled

: Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4

1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Tim er0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

and GPWU.

U = Unimplemented bit

- n = Value at POR reset Reference Table4-1 for other resets.

 1999 Microchip Technology Inc. DS40139E-page 17

PIC12C5XX

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration. Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator.

FIGURE 4-6: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0

CAL3 CAL2 CAL1 CAL0

bit7 bit0

bit 7-4: CAL<3:0>: Calibration bit 3-0: Unimplemented: Read as ’0’

— — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/

12CE519

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

bit7 bit0

bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented: Read as ’0’

— — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS40139E-page 1 8  1999 Microchip Technology Inc.

PIC12C5XX

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instructi on, bits 8:0 of th e PC ar e provided by the GOTO instruction word. The PC Latch ( PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC ( Figure 4-

8). For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC ag ain are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-8).

Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

FIGURE 4-8: LOADING OF PC

BRANCH INSTRUCTIONS PIC12C5XX

GOTO Instruction

CALL or Modify PCL Instruction

87 0

910

PA0

STATUS

87 0

910

PCL

Instruction Word

PCL

4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

means that the PC addresses the l ast location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code.

The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected.

Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.

4.7 Stack

PIC12C5XX devices have a 12-bit wide L.I.F.O. hardware push/pop stack.

A CALL instruction will 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only

the most recent two return addresses are stored. A RETLW instruction will

1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled wi th the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0.

Note 1: There are no STATUS bits to indicate

stack overflows or stack underflow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are a ctions that occur from the execution of the CALL and RETLW instructions.

push

the current value of stack

pop

the contents of stack level

Instruction Word

Reset to ‘0’

PA0

STATUS

 1999 Microchip Technology Inc. DS40139E-page 19

PIC12C5XX

4.8 Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will retur n the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the IN DF register i ndirectly resul ts in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

FIGURE 4-9: DIRECT/INDIRECT ADDRESSING

Direct Addressing

(FSR) 6

(opcode) 04

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x10 ;initialize pointer

NEXT clrf INDF ;clear IN D F regi ster

CONTINUE

The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to selec t data memory addresses 00h to 1Fh.

PIC12C508/PIC12C508A/PIC12CE518: Does not use banking. FSR<7:5> are unimplemented and read as '1's.

PIC12C509/PIC12C509A/PIC12CR509A/ PIC12CE519: Uses FSR<5>. Selects between bank 0

and bank 1. FSR<7:6> is unimplemented, read as '1’ .

movwf FSR ; to RAM

incf FSR,F ;inc pointer btfsc FSR,4 ;all done? goto NEXT ;NO, clear next

: ;YES, continue

Indirect Addressing

(FSR)

bank select

location select

Data Memory

bank

00 01

00h

0Fh

(1)

10h

1Fh 3Fh

Bank 0 Bank 1

Addresses map back to addresses in Bank 0.

(2)

location select

Note 1: For register map detail see Section 4.2. Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12 CE519.

DS40139E-page 2 0  1999 Microchip Technology Inc.

PIC12C5XX

5.0 I/O PORT

As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O

pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. See Section 7.0 for SCL and SDA description for PIC12CE5XX.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The configuration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ du ring port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR up is always on and wake-up on change for this pin is not enabled.

5.2 TRIS Register

The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4-

5. Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indica te that th e pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

, weak pull-

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, ma y be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Note 1: I/O pins have protection diodes to VDD

Note 2: See Table 3-1 for buffer type. Note 3: See Section 7.0 for SCL and SDA

Data Latch

TRIS Latch

Reset

(2)

RD Port

and VSS.

description for PIC12CE5XX

VDD

I/O

(1,3)

 1999 Microchip Technology Inc. DS40139E-page 21

PIC12C5XX

TABLE 5-1: SUMMARY OF PORT REGISTERS

Value on

Power-On

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS — — --11 1111 --11 1111 N/A 03H

06h

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

OPTION GPWU STATUS GPIO

(PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)

GPIO (PIC12CE518/ PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0

q = see tables in Section 8.7 for possible values.

GPWUF

GPPU T0CS T0SE PSA PS2 PS1 PS0

— PAO TO PD Z DC C 0001 1xxx q00q quuu

— — GP5 GP4 GP3 GP2 GP1 GP0

Reset

1111 1111 1111 1111

--xx xxxx --uu uuuu

11xx xxxx 11uu uuuu

Value on

All Other Resets

(1)

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate inter nally as read followed

by write operations. The BCF and BSF instr uc tion s, for example, read the entire port into t he CPU, execute the bit operation and re-write the result. Caution must be used when these ins tructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritte n to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ---------- --------- BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).

5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port ha ppens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cyc le (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

DS40139E-page 22  1999 Microchip Technology Inc.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PIC12C5XX

Instruction

fetched

GP5:GP0

Instruction

executed

Q1 Q2

PC PC + 1 PC + 2

MOVWF GPIO

Q1 Q2

MOVF GPIO,W

MOVWF GPIO

Port pin written here

(Write to

GPIO)

Q1 Q2

NOP

Port pin sampled here

MOVF GPIO,W

(Read

GPIO)

Q1 Q2

PC + 3

NOP

This example shows a write to GPIO followed by a read from GPIO.

Data setup time = (0.25 T

where: T

CY = instruction cycle.

PD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

CY – TPD)

 1999 Microchip Technology Inc. DS40139E-page 23

PIC12C5XX

NOTES:

DS40139E-page 24  1999 Microchip Technology Inc.

PIC12C5XX

6.0 TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0 module.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module wi ll increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can wor k around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

GP2/T0CKI

T0SE

FOSC/4

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS

(1)

Programmable

Prescaler

PS2, PS1, PS0

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clo ck input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled i n software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

Data bus

PSout

(2)

(1)

PSA

Sync with

Internal

Clocks

(2 T

(1)

CY delay)

PSout

Sync

TMR0 reg

 1999 Microchip Technology Inc. DS40139E-page 25

PIC12C5XX

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Executed

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

T0+1 T0+2 NT0 NT0+1 NT0+2

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Execute

Q1 Q2 Q3 Q4

T0 NT0+1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0+1

Write TMR0 executed

Read TMR0 reads NT0

NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0

Power-On

Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION N/A TRIS

Legend: Shaded cells not used by Timer0,

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

—

—GP5GP4 GP3 GP2 GP1 GP0

- = unimplemented, x = unknown, u = unchanged,

--11 1111 --11 1111

Value on All Other

Resets

DS40139E-page 26  1999 Microchip Technology Inc.

PIC12C5XX

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler out put on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2T and low for at least 2T

OSC (and a small RC delay of 20 ns)

OSC (and a small RC delay of

20 ns). Refer to the electrical specification of the desired device.

OSC)

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4T 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time i s that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. F igure 6-4 shows the delay from the external clock edge to the timer incrementing.

6.1.3 OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMER0 from the pin,

the port is forced to an input regardless of the TRIS register setting.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

External Clock Input or Prescaler Output (2)

External Clock/Prescal er Output After Sampling

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(3)

(1)

OSC (and a small RC delay of

Small pulse misses sampling

Increment Timer0 (Q4)

Timer0

Note 1:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

 1999 Microchip Technology Inc. DS40139E-page 27

T0 T0 + 1 T0 + 2

PIC12C5XX

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.6). For simplicity,

this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.

EXAMPLE 6-1: CHANGING PRESCALER

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;T h e s e 3 lines ( 5 , 6 , 7 )

4.OPTION ; are required only if

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the se quen ce s hown in Examp le 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switchin g t he pr es cal e r.

EXAMPLE 6-2: CHANGING PRESCALER

CLRWDT ;Clear WDT and

MOVLW 'xxxx0xxx' ;Select TMR0, new

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

OPTION

(i.e., it can be changed “on the fly” during program execution). To avoid an unintended d evice RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

GP2/T0CKI

M U

Sync

Cycles

(TIMER0→WDT)

; desired

(WDT→TIMER0)

;prescaler

;prescale value and ;clock source

Data Bus

TMR0 reg

T0SE

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40139E-page 2 8  1999 Microchip Technology Inc.

PSA

T0CS

8-bit Prescaler

U X

8 - to - 1MUX

Time-Out

MUX

WDT

PSA

PS2:PS0

PSA

PIC12C5XX

7.0 EEPROM PERIPHERAL OPERATION

This section applies to PIC12CE518 and PIC12CE519 only.

The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 tha t are connected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to th e following functions:

; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our website www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASH5IX.ASM.

It is very important to check the return codes when using these calls, and retry the operation if unsuccessful. Unsuccessful return codes occur when the EE data memory is busy with the previous write, which can take up to 4 mS.

7.0.1 SERIAL DATA

SDA is a bi-directional pin used to transfer addresses and data into and data out of the device.

For normal data transfer SDA is allo wed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

The EEPROM interface is a 2-wire bus protocol consisting of data (SDA) and a clock (SCL). Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the internal EEPROM peripheral. SDA and SCL op eration is also slightly different than GPO-GP5 as listed below.

Namely, to avoid code overhead in modifying the TRIS register, both SDA and SCL are always outputs. To read data from the EEPROM peripheral requires out-

putting a ‘1’ on SDA placing it in high-Z state, where only the internal 100K pull-up is active on the SDA line.

SDA:

Built-in 100K (typical) pull-up to VDD Open-drain (pull-down only) Always an output Outputs a ‘1’ on reset

SCL:

Full CMOS output Always an output Outputs a ‘1’ on reset

The following example requires:

• Code Space: 77 words

• RAM Space: 5 bytes (4 are overlayable)

• Stack Levels:1 (The call to the function itself. The functions do not call any lower level functions.)

• Timing:

- WRITE_BYTE takes 328 cycles

- READ_CURRENT takes 212 cycles

- READ_RANDOM takes 416 cycles.

• IO Pins: 0 (No external IO pins are used)

This code must reside in the lower half of a page. The code achieves it’s small size without additional calls through the use of a sequencing table. The table is a list of procedures that must be called in order. The table uses an ADDWF PCL,F instruction, effectively a computed goto, to sequence to the next procedure. However the ADDWF PCL,F instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page.

 1999 Microchip Technology Inc. DS40139E-page 29

PIC12C5XX

Figure 7-1: Block diagram of GPIO6 (SDA line)

reset

write

Read GPIO

GPIO

databus

Figure 7-2: Block diagram of GPIO7 (SCL line)

ck Q

Output Latch

Input Latch

Schmitt Trigger

ltchpin

VDD

To 24L00 SDA Pad

databus

Read GPIO

write GPIO

ck Q

ltchpin

Schmitt Trigger

VDD

To 24LC00 SCL Pad

DS40139E-page 3 0  1999 Microchip Technology Inc.

PIC12C5XX

7.0.2 SERIAL CLOCK This SCL input is used to synchronize the data transfer

from and to the device.

7.1 BUS CHARACTERISTICS

The following bus protocol is to be used with the EEPROM data memory.

• Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 7-3).

7.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

7.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a ST ART condition. All commands must be preceded by a START condi tion.

7.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

7.1.4 DATA VALID (D) The state of the data line represents valid data when,

after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The numbe r of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.

7.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stabl e LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 7-4).

 1999 Microchip Technology Inc. DS40139E-page 31

PIC12C5XX

FIGURE 7-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

START

CONDITION

(C)

ADDRESS OR

ACKNOWLEDGE

VALID

(B)

FIGURE 7-4: ACKNOWLEDGE TIMING

SCL

SDA

Data from transmitter

Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.

7.2 Device Addressing

After generating a START condition, th e bus master transmits a control byte consisting of a slave address and a Read/Write tion is to be performed. The slave address consists of a 4-bit device code (1010) followed by three don’t care bits.

The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 7-5). The bus is monitored for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.

bit that indicates what type of opera-

(D)

DAT A

ALLOWED

TO CHANGE

Acknowledge

Bit

987654321123

Data from transmitter

Receiver must release the SDA line at this point so the Transmitter can continue sending data.

FIGURE 7-5: CONTROL BYTE FORMAT

Read/Write

Device Select

Bits

1010XXXSACKR/W

Slave Address

Start Bit

Don’t Care

Bits

Acknowledge Bit

STOP

CONDITION

Bit

(A)(C)

DS40139E-page 32  1999 Microchip Technology Inc.

PIC12C5XX

7.3 WRITE OPERATIONS

7.3.1 BYTE WRITE

Following the start signal fr om the master, the device code (4 bits), the don’t care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be wri tten into the address pointer. Only the lower four address bits are used by the device, and the upper four bits are

don’t cares. The address byte is acknowledgeable and the master device will then transmit the data word to be written into the addressed memory location. The memory acknowledges again and the master generates a stop condition. This initiates the inter nal write cycle, and during this time will not generate acknowledge signals (Figure 7-7). After a byte write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command w ill abort and no data will be written. If more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abor t and no data will be written. The EEPROM memory employs a V circuit which disables the internal erase/write logic if the V

CC is below minimum VDD.

Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both SDA and SCL are held high.

CC threshold detector

7.4 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop co ndition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This inv olves the master sending a start condition followed by the control byte for a write command (R/W

= 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the star t bit and c ontrol byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-6 for flow diagram.

FIGURE 7-6: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Operation

FIGURE 7-7: BYTE WRITE

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

 1999 Microchip Technology Inc. DS40139E-page 33

T A R T

CONTROL

BYTE

10 X10 XXX

A C K

XXX

WORD

ADDRESS

DATA

A C K

S T O P

A C K

PIC12C5XX

7.5 READ OPERATIONS

Read operations are initiated in the same way as write operations with the exception that the R/W

bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.

7.5.1 CURRENT ADDRESS READ It contains an address counter that maintains the

address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W

bit set to one, the device issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 7-8).

7.5.2 RANDOM READ Random read operations allow the master to access

any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the

FIGURE 7-8: CURRENT ADDRESS READ

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

T A R T

FIGURE 7-9: RANDOM READ

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

CONTROL

BYTE

R T

S1 100XXX0 S1100XXX1

WORD

ADDRESS (n)

XXXX

A C K

FIGURE 7-10: SEQUENTIAL READ

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

A C K

device as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 7-9). After this command, the internal address counter will point to the addr ess location following the one that was just read.

7.5.3 SEQUENTIAL READ Sequential reads are initiated in the same way as a ran-

dom read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the device to transmit the next sequentially addressed 8-bit word (Figure 7-10).

To provide sequential reads, it contains an internal address pointer which is increment ed by one at the completion of each read operation. This address pointer allows the entire memory contents to be serially read during one operation.

CONTROL

BYTE

1100XXX1

S T A R T

A C K

bit set to a one. It will then issue an

S T O P

A C K

CONTROL

BYTE

DATA

N O

A C K

A C

DATA (n)

A C K

S T O P

N O

A C K

S T O P

N O

A C K

DS40139E-page 3 4  1999 Microchip Technology Inc.

PIC12C5XX

8.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits to deal with the nee ds of real-time applications. The PIC12C5XX family of microcontrollers has a host of suc h features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

• Oscillator selection

• Reset

- Power-On Reset (POR)

-Device Reset Timer (DRT)

- Wake-up from SLEEP on pin change

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit Serial Programming

The PIC12C5XX has a Watchdog Timer which can be shut off only through configuration bit WD TE. It runs off of its own RC oscillator for added reliability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal os cillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on V

DD power-up.

With this timer on-chip, most applications need no external reset circuitry.

The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an inter nal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

8.1 Configuration Bits

The PIC12C5XX configuration word consists of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR

enable bit.

FIGURE 8-1: CONFIGURATION WORD FOR PIC12C5XX

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0 Register: CONFIG

bit1110987654321bit0 bit 11-5: Unimplemented bit 4: MCLRE: MCLR

1 = MCLR 0 = MCLR

bit 3: CP: Code protection bit.

1 = Code protection off 0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = EXTRC - external RC oscillator 10 = INTRC - internal RC oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the

configuration word. This register is not user addressable during device operation.

 1999 Microchip Technology Inc. DS40139E-page 35

enable bit. pin enabled tied to VDD, (Internally)

Address

(1)

:FFFh

PIC12C5XX

8.2 Oscillator Configurations

8.2.1 OSCILLATOR TYPES The PIC12C5XX can be operated in four different

oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes:

•LP: Low Power Crystal

• XT: Crystal/Resonator

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

8.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN a nd GP4/OSC2 pins to establish oscillation (Figure 8-2). The PIC12C5XX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal ma y giv e a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device can have an external clock source drive the GP5/ OSC1/CLKIN pin (Figure 8-3).

FIGURE 8-2: CRYSTAL OPERATION (OR

CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION)

(1)

OSC1

PIC12C5XX

TABLE 8-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12C5XX

Osc

Resonator

Type

XT 4.0 MHz 30 pF 30 pF

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

Freq

Cap. RangeC1Cap. Range

TABLE 8-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR PIC12C5XX

Osc

Resonator

Type

LP 32 kHz

XT 200 kHz

Note 1: For V

These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Freq

1 MHz 4 MHz

DD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

(1)

Cap.Range

15 pF 15 pF

47-68 pF

15 pF 15 pF

Cap. Range

47-68 pF

15 pF 15 pF

XTAL

OSC2

(2)

(1)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF approximate value = 10 MΩ.

SLEEP

(3)

To internal

logic

FIGURE 8-3: EXTERNAL CLOCK INPUT

OPERATION (XT OR LP OSC CONFIGURATION)

Clock from ext. system

Open

DS40139E-page 3 6  1999 Microchip Technology Inc.

OSC1

PIC12C5XX

OSC2

PIC12C5XX

8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stabi lity. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

Figure 8-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 8-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

+5V

10k

4.7k

74AS04

XTAL

10k

20 pF

Figure 8-5 shows a series resonant oscillator circu it. This circuit is also designed to use the fundamental frequency of the cry stal. The inverter pe rforms a 180degree phase shift in a series resonant oscillator circuit. The 330 Ω resistors provide the negative feedback to bias the inverters in their linear region.

74AS04

10k

To Other Devices

PIC12C5XX

CLKIN

FIGURE 8-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other

74AS04

Devices

PIC12C5XX

CLKIN

330

74AS04

330

74AS04

0.1 µF XTAL

8.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used.

Figure 8-6 shows how the R/C combination is connected to the PIC12C5XX. For Rext values below

2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MΩ) the o scillator becomes sensi tive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

Also, see the Electrical Specifications sections for variation of oscillator frequency due to V

DD for given

Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and V

DD values.

FIGURE 8-6: EXTERNAL RC OSCILLATOR

MODE

VDD

Rext

Cext

OSC1

Internal clock

PIC12C5XX

 1999 Microchip Technology Inc. DS40139E-page 37

PIC12C5XX

8.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, see “Electri-

cal Specifications” section for information on variation over voltage and temperature.

In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This location is never code protected regardless of the code protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it.

OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. .

Note: Please note that erasing the device will

also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be reprogrammed correctly later.

For the PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, and PIC12CR509A, bits <7:2>, CA L5CAL0 are used for calibration. Adjusting CAL5-0 from 000000 to 111111 yields a higher clock speed. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices.

For the PIC12C508 and PIC12C509, the upper 4 bits of the register are used. Writing a larger value in this location yields a higher clock speed.

8.3 RESET

The device differentiates between various kinds of reset:

a) Power on reset (POR) b) MCLR c) MCLR d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change

reset during normal operation reset during SLEEP

Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to “reset state” on poweron reset (POR), MCLR change reset during normal operation. T hey a re not affected by a WDT reset during SLEEP or MCLR during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO

, PD, and GPWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the n ature of r eset. See Table 8-3 for a full description of reset states of all registers.

, WDT or wake-up on pin

reset

DS40139E-page 3 8  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 8-3: RESET CONDITIONS FOR REGISTERS

Reset

MCLR

W (PIC12C508/509)

W (PIC12C508A/509A/ PIC12CE518/519/ PIC12CE509A)

INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx

FSR (PIC12C508/ PIC12C508A/ PIC12CE518)

FSR (PIC12C509/ PIC12C509A/ PIC12CE519/ PIC12CR509A)

OSCCAL (PIC12C508/509)

OSCCAL (PIC12C508A/509A/ PIC12CE518/512/ PIC12CR509A)

GPIO (PIC12C508/PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)

GPIO (PIC12CE518/ PIC12CE519)

OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table 8-7 for reset value for specific conditions Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.

— —

04h 111x xxxx 111u uuuu

04h 110x xxxx 11uu uuuu

05h 0111 ---- uuuu ----

05h 1000 00-- uuuu uu--

06h --xx xxxx --uu uuuu

06h

qqqq xxxx qqqq qqxx

11xx xxxx 11uu uuuu

(1)

WDT time-out

Wake-up on Pin Change

qqqq uuuu qqqq qquu

q00q quuu

(1)

(2,3)

TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h PCL Addr: 02h

Power on reset 0001 1xxx 1111 1111

reset during normal operation 000u uuuu 1111 1111

MCLR

reset during SLEEP 0001 0uuu 1111 1111

MCLR WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.

 1999 Microchip Technology Inc. DS40139E-page 39

PIC12C5XX

8.3.1 MCLR EN ABLE This configuration bit when unprogrammed (left in the

‘1’ state) enables the external MCLR programmed, the MCLR V

DD, and the pin is assigned to be a GPIO. See

function is tied to the internal

Figure 8-7. When pin GP3/MCLR MCLR

, the internal pull-up is always on.

function. When

/VPP is configured as

FIGURE 8-7: MCLR SELECT

MCLRE

WEAK PULL-UP

GP3/MCLR/VPP

8.4 P

ower-On Reset (POR)

The PIC12C5XX family incorporates on-chip PowerOn Reset (POR) circuitry which provides an inter nal chip reset for most power-up situations.

The on-chip POR circuit holds the chip in reset until V

DD has reached a high enough level for proper opera-

tion. To take a dvantage of the internal POR, program the GP3/MCLR resistor to V

/VPP pin as MCLR and tie through a

DD or program the pin as GP3. An internal

weak pull-up resistor is implemented using a transistor. Refer to Table 11-1 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for V

DD is specified. See Electrical Specifications for

details. When the device starts normal operation (exits the

reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met.

A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 8-8.

INTERNAL MCLR

The Power-On Reset circuit and the Device Reset Timer (Section 8.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the onchip reset signal.

A power-up example where MCLR shown in Figure 8-9. V

DD is allowed to rise and

stabilize before bringing MCLR actually come out of reset T

is held low is

high. The chip will

DRT msec after MCLR

goes high. In Figure 8-10, the on-chip Power-On Reset feature is

being used (MCLR pin is programmed to be GP3.). The V

and VDD are tied together or the

DD is stable

before the start-up timer times out and there is no problem in getting a proper reset. However, Figure811 depicts a problem situation where V

DD rises too

slowly. The time between when the DRT senses that MCLR

is high and when MCLR (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, V V

DD (min) value and the chip is, therefore, not

DD has not reached the

guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 8-10).

Note: When the device starts normal operation

(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

For additional information refer to Application Notes “

Power-Up Considerations”

Trouble Shooting

” - AN607.

- AN522 and “

Power-up

DS40139E-page 4 0  1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up

VDD

GP3/MCLR/VPP

Detect

POR (Power-On Reset)

Pin Change

SLEEP

Wake-up on pin change

MCLRE

On-Chip

DRT OSC

WDT Time-out

8-bit Asynch

Ripple Counter

(Start-Up Timer)

FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TDRT

RESET

CHIP RESET

PULLED LOW)

TDRT

TIED TO VDD): FAST VDD RISE TIME

DRT TIME-OUT

INTERNAL RESET

 1999 Microchip Technology Inc. DS40139E-page 41

PIC12C5XX

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

TDRT

8.5 Device Reset Timer (DRT)

In the PIC12C5XX, DRT runs from RESET and varies based on oscillator selection (see Table8-5.)

The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows V min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR level. Thus, programming GP3/MCLR and using an external RC network connecte d to the MCLR

input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the G P3/ MCLR

/VPP pin as a general purpose input. The Device Reset ti me d elay will vary from chip to chip

due to V AC parameters for details.

The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automatically.

has reached a logic high (VIHMCLR)

DD, temperature, and process variation. See

DD to rise above VDD

/VPP as MCLR

8.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscillator of the GP5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET.

The TO

bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset. The WDT can be permanently disabled by

programming the configuration bit WDTE as a ’0’ (Section 8.1). Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word.

TABLE 8-5: DRT (DEVICE RESET TIMER

PERIOD)

Oscillator

Configuration

IntRC & ExtRC

XT & LP 18 ms (typical) 18 ms (typical)

POR Reset

18 ms (typical) 300 µs (typical)

Subsequent

Resets

DS40139E-page 4 2  1999 Microchip Technology Inc.

PIC12C5XX

8.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V

DD and part-to-

part process variations (see DC specs). Under worst case conditions (V

DD = Min., Temperature

= Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.

FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source (Figure 8-5)

Watchdog

Timer

WDT Enable

Configur at i o n B i t

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

U X

PSA

8.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.

Postscaler

8 - to - 1 MUX

MUX

WDT

Time-out

PS2:PS0

To Timer0 (Figure 8-4)

PSA

TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A OPTION Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged

 1999 Microchip Technology Inc. DS40139E-page 43

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Powe r -On

Reset

Value on All Other

Resets

PIC12C5XX

8.7 Time-Out Sequence, Power Down,

and Wake-up from SLEEP Status Bits (TO/PD/GPWUF)

The TO, PD, and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR

Watchdog Timer (WDT) reset.

TABLE 8-7: TO

/PD/GPWUF STATUS

AFTER RESET

GPWUF TO PD RESET caused by

0 0 0 W DT wake-up from

SLEEP

0 0 u W DT time-out (not from

SLEEP)

010MCLR

wake-up from

SLEEP 011Power-up 0uuMCLR

not during SLEEP

1 1 0 Wake-up from SLEEP on

pin change

Legend: u = unchanged Note 1: The TO

, PD, and GPWUF bits maintain their status (u) until a reset occurs. A lowpulse on the MCLR the TO

, PD, and GPWUF status bits.

input does not change

8.8 Reset on Brown-Out

A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out.

To reset PIC12C5XX devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 8-13 , Figure 8-14 and Figure8-15

FIGURE 8-13: BROWN-OUT PROTECTION

CIRCUIT 1

VDD

40k*

VDD

MCLR

PIC12C5XX

33k

10k

FIGURE 8-14: BROWN-OUT PROTECTION

CIRCUIT 2

VDD

40k*

VDD

MCLR

PIC12C5XX

This brown-out circuit is less expensive, although less accurate. Transistor Q1 tur ns off when V is below a certain level such that:

VDD •

R1 + R2

= 0.7V

*Refer to Figure 8-7 and Table 11-1 for internal weak pull-up on MCLR.

FIGURE 8-15: BROWN-OUT PROTECTION

CIRCUIT 3

VDD

MCP809

Vss

RST

capacitor

VDD

bypass

This brown-out protection circuit employs

Microchip Te chnology’s MCP809 mic rocontroller supervisor. The MCP8XX and MCP1XX family of supervisors provide push-pull and open collector outputs with both high and low active reset pins. There are 7 different trip point selections to accomodate 5V and 3V systems.

VDD

MCLR

PIC12C5XX

This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage).

*Refer to Figure 8-7 and Table 11-1 for internal weak pull-up on MCLR.

DS40139E-page 4 4  1999 Microchip Technology Inc.

PIC12C5XX

8.9 Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).

8.9.1 SLEEP The Power-Down mode is entered by executing a

SLEEP instruction. If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<3>) is cleared and the oscillator dri ver is turned off. The I/O por ts maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT time-out does not drive the MCLR

For lowest current consumption while powered down, the T0CKI input should be at V MCLR

/VPP pin must be at a logic high level (VIHMC) if

MCLR

is enabled.

8.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

the following events:

1. An external reset input on GP3/MCLR when configured as MCLR

2. A Watchdog Timer time-out reset (if WDT was enabled).

3. A change on input pin GP0, GP1, or GP3/ MCLR

/VPP when wake-up on change is

enabled.

These events cause a device reset. The TO GPWUF bits can be used to deter mine the cause of device reset . The TO occurred (and caused wake-up). The PD set on power-up, is cleared when SLEEP is i nvoked. The GPWUF bit indicates a change in state while in SLEEP at pins GP0, GP1, or GP3 (since the last time there was a file or bit operation on GP port).

Caution: Right before entering SLEEP, read the

The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.

input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode.

bit (STATUS<4>) is set, the PD

pin low.

DD or VSS and the GP3/

/VPP pin,

, PD, and

bit is cleared if a WDT time-out

bit, which is

8.10 Program Verification/Code Protection

If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes.

The first 64 locations can be read by the PIC12C5 XX regardless of the code protection bit setting.

The last memory locatio n cannot be read if code protection is enabled on the PIC12C508/509.

The last memory location can be read regardless of the code protection bit setting on the PIC12C508A/509A/ CR509A/CE518/CE519.

8.11 ID Locations

Four memory locations are designated as I D locatio ns where the user can store checksum or other codeidentification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify.

Use only the lower 4 bits of the ID locations and always program the upper 8 bits as ’0’s.

 1999 Microchip Technology Inc. DS40139E-page 45

PIC12C5XX

8.12 In-Circuit Serial Programming

The PIC12C5XX microcontrollers with EPROM program memory can be serially programmed while in the end application circuit. This is s imply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming specification). GP1 becomes the programming clock and GP0 becomes the programming data. Both GP1 and GP0 are Schmitt Trigger inputs in this mode.

After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12C5XX Programming Specifications.

A typical in-circuit serial programming connection is shown in Figure 8-16.

FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

To Nor mal

External Connector Signals

+5V

CLK

Data I/O

Connections

To Normal Connections

PIC12C5XX

VSS MCLR/VPP

GP1

GP0

DS40139E-page 4 6  1999 Microchip Technology Inc.

PIC12C5XX

9.0 INSTRUCTION SET SUMMARY

Each PIC12C5XX instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which fur ther specify the operation of the instruction. The PIC12C5XX instruction set summary in Table 9-2 groups the instructions into byte-oriented, bit-or iented, and literal and control operations. Table 9-1 shows the opcode field descriptions.

For byte-oriented instructions, ’f’ represents a file register designator and ’d’ represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be us ed by the instruction.

The destination designator specifies where the result of the operation is to be placed. If ’d’ is ’0’, the r esult is placed in the W register. If ’d’ is ’1’, the result is placed in the file register specified in the instruction.

For bit-oriented instructi ons, ’b’ represents a bit field designator which selects the number of the bit affected by the operation, while ’f’ represents the number of the file in which the bit is located.

For literal and control operations, ’k ’ represents an 8 or 9-bit constant or literal value.

TABL E 9-1: OPCODE FIELD

Field Description

f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label

label Label name

TOS Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

TO PD

dest

[ ]

( )

→

< >

∈

talics

DESCRIPTIONS

Don’t care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

Destination select;

d = 0 (store result in W) d = 1 (store result in file register ’f’)

Default is d = 1

Time-Out bit Power-Down bit Destination, either the W register or the specified

All instructions are executed within a single instr uction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a c onditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Figure 9-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number:

0xhhh

where ’h’ signifies a hexadecimal digit.

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

11 6 5 4 0

OPCODE d f (FILE #)

d = 0 for destination W d = 1 for destination f f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

 1999 Microchip Technology Inc. DS40139E-page 47

PIC12C5XX

TABLE 9-2: INSTRUCTION SET SUMMARY

1 1 1 1 1 1

1 1

1 1 1 1 1 1 1 1

1 1

1 2 1 2 1 1 1 2 1 1 1

12-Bit Opcode

11df

0001

01df

0001

011f

0000

0100

0000

01df

0010

11df

0000

11df

0010

10df

0010

11df

0011

00df

0001

00df

0010

001f

0000

01df

0011

00df

0011

10df

0000

10df

0011

10df

0001

0100

bbbf

0101

bbbf

0110

bbbf

0111

bbbf

kkkk

1110

kkkk

1001

0000

kkkk

101k

kkkk

1101

kkkk

1100

0000

kkkk

1000

0000

kkkk

1111

ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk

Status

Affected NotesMSb LSb

C,DC,Z

Z Z Z Z Z

None

Z None None

C C

C,DC,Z

None

None None None None

None

, PD

None

Z None None None

, PD

None

1,2,4

Mnemonic,

Operands Description Cycles

Add W and f

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

LITERAL AND CONTROL OPERATIONS ANDLW

CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW

Note 1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO.

f,d

AND W with f

f,d

Clear f

Clear W

–

Complement f

f, d

Decrement f

f, d

Decrement f, Skip if 0

f, d

Increment f

f, d

Increment f, Skip if 0

f, d

Inclusive OR W with f

f, d

Move f

f, d

Move W to f

No Operation

–

Rotate left f through Carry

f, d

Rotate right f through Carry

f, d

Subtract W from f

f, d

Swap f

f, d

Exclusive OR W with f

f, d

Bit Clear f

f, b

Bit Set f

f, b

Bit Test f, Skip if Clear

f, b

Bit Test f, Skip if Set

f, b

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

–

Return, place Literal in W

Go into standby mode

–

Load TRIS register

Exclusive OR Literal to W

(Section 4.6)

2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is ’1’ f or a pin configured as input and is driven low by an external device, the data will be written back with a ’0’.

3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of

GPIO. A ’1’ for ces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

1(2) 1(2)

1 (2) 1 (2)

2,4

2,4 2,4 2,4 2,4 2,4 2,4 1,4

2,4 2,4

DS40139E-page 4 8  1999 Microchip Technology Inc.

PIC12C5XX

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding: Description:

0001 11df ffff

Add the contents of the W register and

in the W register. If ’d’ is ’1’ the result is

stored back in register ’f’

Words: 1 Cycles: 1 Example:

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW And literal with W

Syntax: [

label

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W).AND. (k) → (W) Status Affected: Z Encoding: Description:

1110 kkkk kkkk

The contents of the W register are

AND’ed with the eight-bit literal 'k'. The result is placed in the W register

Words: 1 Cycles: 1 Example:

ANDLW 0x5F

Before Instruction

W= 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding: Description:

0001 01df ffff

The contents of th e W re gi s te r ar e

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'

. Words: 1 Cycles: 1 Example:

ANDWF FSR, 1

Before Instruction

W = 0 x1 7 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

Description: Words: 1

0100 bbbf ffff

Bit 'b' in register 'f' is cleared.

Cycles: 1 Example:

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

 1999 Microchip Technology Inc. DS40139E-page 49

PIC12C5XX

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding: Description:

0101 bbbf ffff

Bit ’b’ in register ’f’ is set.

Words: 1 Cycles: 1 Example:

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110 Description:

If bit ’b’ in register ’f’ is 0 then the next

instruction is skipped.

If bit ’b’ is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

bbbf ffff

Words: 1 Cycles: 1(2)

HERE

Example:

FALSE

TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

•

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1>=0, PC = address (TRUE); if FLAG<1>=1, PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Description:

0111 bbbf ffff

If bit ’b’ in register ’f’ is ’1’ then the next

instruction is skipped.

If bit ’b’ is ’1’, then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example:

HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0, PC = address (FALSE); if FLAG<1>=1, PC = address (TRUE)

DS40139E-page 50  1999 Microchip Technology Inc.

PIC12C5XX

CALL Subroutine Call

Syntax: [

label

] CALL k Operands: 0 ≤ k ≤ 255 Operation: (PC) + 1→ Top of Stack;

k → PC<7:0>; (STATUS<6:5>) → PC<10:9>;

0 → PC<8> Status Affected: None Encoding: Description:

1001 kkkk kkkk

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared . CALL is

a two cycle instruction.

Words: 1 Cycles: 2 Example:

HERE CALL THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE) TOS = address (HERE + 1)

CLRF Clear f

Syntax: [

label

] CLRF f Operands: 0 ≤ f ≤ 31 Operation: 00h → (f);

1 → Z Status Affected: Z Encoding: Description:

0000 011f ffff

The contents of register ’f’ are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example:

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z=1

CLRW Clear W

Syntax: [

label

] CLRW Operands: None Operation: 00h → (W);

1 → Z Status Affected: Z Encoding: Description:

0000 0100 0000

The W register is cleared. Zero bit (Z)

is set.

Words: 1 Cycles: 1 Example:

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z=1

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT Operands: None Operation: 00h → WDT;

0 → WDT prescaler (if assigned); 1 → TO;

1 → PD Status Affected: TO, PD Encoding: Description:

0000 0000 0100

The CLRWDT instruction resets the

WDT. It also resets the prescaler, if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO

set.

Words: 1 Cycles: 1 Example:

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescale = 0 TO PD

=1 =1

and PD are

 1999 Microchip Technology Inc. DS40139E-page 51

PIC12C5XX

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f

) → (dest) Status Affected: Z Encoding: Description:

0010 01df ffff

The contents of register ’f’ are complemented. If ’d’ is 0 the result is stored in the W register. If ’d’ is 1 the result is stored back in register ’f’.

Words: 1 Cycles: 1 Example:

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W=0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – 1 → (dest)

Status Affected: Z Encoding: Description:

0000 11df ffff

Decrement register ’f’. If ’d’ is 0 the result is s tor ed i n th e W re gis ter. If ’d’ is 1 the result is stored back in register ’f’.

Words: 1 Cycles: 1 Example:

DECF CNT,

Before Instruction

CNT = 0x01 Z=0

After Instruction

CNT = 0x00 Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Status Affected: None Encoding: Description:

0010 11df ffff

The contents of register ’f’ are decre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words: 1 Cycles: 1(2) Example:

HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT - 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE+1)

GOTO Unconditional Branch

Syntax: [

label

] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9> Status Affected: None Encoding: Description:

101k kkkk kkkk

GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTO is a

two cycle instruction.

Words: 1 Cycles: 2 Example:

GOTO THERE

After Instruction

PC = address (THERE)

DS40139E-page 52  1999 Microchip Technology Inc.

PIC12C5XX

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding: Description:

0010 10df ffff

The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Words: 1 Cycles: 1 Example:

INCF CNT,

Before Instruction

CNT = 0xFF Z=0

After Instruction

CNT = 0x00 Z=1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding: Description:

0011 11df ffff

The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

Words: 1 Cycles: 1(2) Example:

HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE +1)

IORLW Inclusive OR literal with W

Syntax: [

label

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (k) → (W) Status Affected: Z Encoding: Description:

1101 kkkk kkkk

The contents of the W register are

OR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example:

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W= 0xBF Z=0

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W).OR. (f) → (dest) Status Affected: Z Encoding: Description:

0001 00df ffff

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example:

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z=0

 1999 Microchip Technology Inc. DS40139E-page 53

PIC12C5XX

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: Description:

0010 00df ffff

The contents of register ’f’ is moved to

destination ’d’. If ’d’ is 0, destination is

the W register. If ’d’ is 1, the destination

is file register ’f’. ’d’ is 1 is useful to test

a file register since status flag Z is

affected.

Words: 1 Cycles: 1 Example:

MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding: Description:

1100 kkkk kkkk

The eight bi t l i t eral ’k’ is load ed i nt o t he

W register. The don’t cares will assemble as 0s.

Words: 1 Cycles: 1 Example:

MOVLW 0x5A

After Instruction

W= 0x5A

MOVWF Move W to f

Syntax: [

label

] MOVWF f Operands: 0 ≤ f ≤ 31 Operation: (W) → (f) Status Affected: None Encoding: Description:

0000 001f ffff

Move data from the W register to register 'f'

. Words: 1 Cycles: 1 Example:

MOVWF TEMP_REG

Before Instruction

TEMP_REG = 0xFF W = 0x4F

After Instruction

TEMP_REG = 0x4F W = 0x4F

NOP No Operation

Syntax: [

label

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

0000 0000 0000

Description: No operation. Words: 1 Cycles: 1 Example:

NOP

DS40139E-page 54  1999 Microchip Technology Inc.

PIC12C5XX

OPTION Load OPTION Register

label

Syntax: [

] OPTION Operands: None Operation: (W) → OPTION Status Affected: None Encoding: Description:

0000 0000 0010

The content of the W register is loaded into the OPTION register.

Words: 1 Cycles: 1 Example

OPTION

Before Instruction

W=0x07

After Instruction

OPTION = 0x07

RETLW Return with Literal in W

Syntax: [

label

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding: Description:

1000 kkkk kkkk

The W register is loaded with the eight

bit literal ’k’. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W= 0x07

After Instruction

W= value of k8

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

0011 01df ffff

The contents of register ’f’ are rotated

one bit to the left through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register. If ’d’ is 1 the result is stored

back in register ’f’.

Words: 1 Cycles: 1 Example:

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C=0

After Instruction

REG1 = 1110 0110 W=1100 1100 C=1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

0011 00df ffff

The contents of register ’f’ are rotated

one bit to the right through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register. If ’d’ is 1 th e r e su l t i s p l ac ed

back in register ’f’.

Words: 1 Cycles: 1 Example:

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C=0

After Instruction

REG1 = 1110 0110 W=0111 0011 C=0

 1999 Microchip Technology Inc. DS40139E-page 55

PIC12C5XX

SLEEP Enter SLEEP Mode

Syntax:

[

label

]

SLEEP Operands: None Operation: 00h → WDT;

0 → WDT prescaler; 1 → TO

;

0 → PD Status Affected: TO, PD, GPWUF Encoding: Description:

0000 0000 0011

Time-out status bit (TO) is set. The

power down status bit (PD

GPWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

Words: 1 Cycles: 1 Example: SLEEP

) is cleared.

SUBWF Subtract W from f

Syntax:

[

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – (W) → (dest)

Status Affected: C, DC, Z Encoding: Description:

0000 10df ffff

Subtract (2’s complement method) the W registe r f r om r eg i st e r 'f ' . If ' d' is 0 the result is s tor ed i n th e W re gis ter. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example 1

SUBWF REG1, 1

Before Instruction

REG1 = 3 W=2 C=?

After Instruction

REG1 = 1 W=2 C = 1 ; result is positive

Example 2:

Before Instruction

REG1 = 2 W=2 C=?

After Instruction

REG1 = 0 W=2 C = 1 ; result is zero

Example 3:

Before Instruction

REG1 = 1 W=2 C=?

After Instruction

REG1 = FF W=2 C = 0 ; result is negative

DS40139E-page 56  1999 Microchip Technology Inc.

PIC12C5XX

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding: Description:

0011 10df ffff

The upper and lower nibbles of register

’f’ are exchanged. If ’d’ is 0 the result is

placed in W register. If ’d’ is 1 the result

is placed in register ’f’.

Words: 1 Cycles: 1 Example

SWAPF

REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0X5A

TRIS Load TRIS Re gister

label

Syntax: [ Operands: f =

] TRIS f

Operation: (W) → TRIS register f Status Affected: None Encoding: Description:

0000 0000 0fff

TRIS regis ter ’ f’ (f = 6) is loaded w it h the

contents of the W register

Words: 1 Cycles: 1 Example

TRIS GPIO

Before Instruction

W=0XA5

After Instruction

TRIS = 0XA5

Note: f = 6 for PIC12C5XX only.

XORLW Exclusive OR literal with W

Syntax:

[

label

]XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: Description:

1111 kkkk kkkk

The contents of the W register are

XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W= 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: Description:

0001 10df ffff

Exclusive OR the contents of the W

result is s tor ed i n th e W re gis ter. If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example XORWF

REG,1

Before Instruction

REG = 0xAF W=0xB5

After Instruction

REG = 0x1A W=0xB5

 1999 Microchip Technology Inc. DS40139E-page 57

PIC12C5XX

NOTES:

DS40139E-page 58  1999 Microchip Technology Inc.

PIC12C5XX

10.0 DEVELOPMENT SUPPORT

10.1 Development Tools

The PICmicro microcontrollers are suppor ted with a full range of hardware and software development tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

•PRO MATE

• PICSTART Programmer

• SIMICE

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

•MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic De velopment System (

fuzzy

•K

EELOQ

10.2 MPLAB-ICE: High Performance

The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro supplied with the MPLAB Integrated Development

Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Micr ochip microcontrollers.

The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows Windows 95 environment were chosen to best make these features available to you, the end user.

MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed range of the PICmicro MCU.



II Universal Programmer



Plus Entry-Level Prototype

TECH−MP)

Evaluation Kits and Programmer

Universal In-Circuit Emulator with MPLAB IDE



microcontrollers (MCUs). MPLAB-ICE is



3.x or

10.3 ICEPIC: Low-Cost PICmicro



In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentium based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.

10.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant.

The PRO MATE II has programmable V supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II c an read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.

DD and VPP

10.5 PICSTART P lus Entry Level Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) por ts. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICST ART Plus is not recommended for production programming.

PICST AR T Pl us supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an ad apter socket. PICSTART Plus is CE compliant.



 1999 Microchip Technology Inc. DS40139E-page 59

PIC12C5XX

10.6 SIMICE Entry-Level Hardware Simulator

SIMICE is an entry-level hardware development system designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE pro vides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro trollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development.



8-bit microcon-

10.7 PICDEM-1 Low-Cost PICmicro Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic d emo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download t h e firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

10.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program th e samp le mi croc ontr olle rs pr ovide d with the PICDEM-2 board, on a PRO MATE II programmer or PICSTAR T-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Seria l EEPROM to demonstrate usage of the I tion to an LCD module and a keypad.

C bus and separate headers for connec-

10.9 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontroll ers wi th a LCD Modu le . Al l th e nece ssary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programme r o r PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test fir mware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller sock et(s). S ome of t he f eatur es inc lude an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a ther mistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

DS40139E-page 6 0  1999 Microchip Technology Inc.

PIC12C5XX

10.10 MPLAB Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

-editor

-emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro project information)

• Debug using:

- source files

- absolute listing file

The ability to use MPLAB with Mi crochip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.



tools (automatically updates all

10.11 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third par ty programmers.

MPASM allows full symbolic debugging from MPLABICE, Microchip’s Universal Emulator System.

MPASM has the following features to assist in developing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a r ich directive language to support programming of the PICmicro in making the development of your assemble source code shorter and more maintainable.



. Directives are helpful

10.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging us ing MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.



series microcontrollers

10.13 MPLAB-C17 Compiler

The MPLAB-C17 Code Development System is a complete ANSI ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compati ble wi th the MPLAB IDE memory display.

10.14 Fuzzy Logic Development System (

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, menting more complex systems.

Both versions include Microchip’s stration board for hands-on experience with fuzzy logic systems implementation.

fuzzy

TECH-MP, Edition for imple-

fuzzy

LAB demon-

10.15 SEEVAL Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Seri als and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.

 1999 Microchip Technology Inc. DS40139E-page 61

PIC12C5XX

10.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

DS40139E-page 6 2  1999 Microchip Technology Inc.

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX

HCS200

24CXX

HCS300

25CXX

HCS301

93CXX

ICEPIC Low-Cost

In-Circuit Emulator

MPLAB

Integrated

Development

Environment

Emulator Products

MPLAB C17*

-MP



TECH

Explorer/Edition

Fuzzy Logic

Compiler

Dev. Tool

fuzzy

Software Tools

Plus



Universal

Low-Cost

Total Endurance

Software Model

PICSTART

Programmer

Universal Dev. Kit

PRO MATE

KEELOQProgrammer

SEEVALDesigners KitáSIMICE

Programmers

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX

MPLAB™-ICE

 1999 Microchip Technology Inc. DS40139E-page 63

PICDEM-14AáPICDEM-1

PICDEM-2

PICDEM-3áKEELOQ®Evaluation KitáKEELOQ

Transponder Kit

Demo Boards

PIC12C5XX

NOTES:

DS40139E-page 6 4  1999 Microchip Technology Inc.

PIC12C5XX

11.0 ELECTRICAL CHARACTERISTICS - PIC 12C508/PIC12C509

Absolute Maximum Ratings†

Ambient Temperature under bias........................................................................................................... –40°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on V Voltage on MCLR Voltage on all other pins with respect to V Total Power Dissipation Max. Current out of V Max. Current into V Input Clamp Current, I Output Clamp Current, I

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................25 mA

Max. Output Current sourced by I/O port (GPIO) .................................................................................................100 mA

Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA

Note 1: Power Dissipation is calculated as follows: P

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permane nt damage to the device. This is a stress rating only and f unctional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DD with respect to VSS .................................................................................................................0 to +7.5 V

with respect to VSS...............................................................................................................0 to +14 V

(1)

....................................................................................................................................700 mW

SS pin ..................................................................................................................................200 mA

DD pin.....................................................................................................................................150 mA

IK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

OK (VO < 0 or VO > VDD).............................................................................................................±20 mA

SS ............................................................................... –0.6 V to (VDD + 0.6 V)

DIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

 1999 Microchip Technology Inc. DS40139E-page 65

PIC12C5XX

11.1 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended)

DC Characteristics Power Supply Pins

Parm

No.

Characteristic Sym Min

D001 Supply Voltage V

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

DD 2.5

–40°C ≤ T –40°C ≤ T

(1)

Max Units Conditions

Typ

5.5

A ≤ +85°C (industrial) A ≤ +125°C (extended)

FOSC = DC to 4 MHz (Commercial/ Industrial)

Standard Operating Conditions (unless otherwise specified)

D002 RAM Data Retention

(2)

Voltage

D003 V

DD Start Voltage to

3.0

VDR 1.5* V Device in SLEEP mode

VPOR VSS V See section on Power-on Reset for details

5.5VV

OSC = DC to 4 MHz (Extended)

ensure Power-on Reset

D004 V

D010

DD Rise Rate to ensure

Power-on Reset Supply Current

(3)

SVDD 0.05

IDD —

.78

V/ms See section on Power-on Reset for details

2.4

XT and EXTRC options

(4)

FOSC = 4 MHz, VDD = 5.5V

D010C D010A

Power-Down Current

D020

(5)

D021 D021B

D022 ∆I

— —

IPD —

— —

WDT —

— —

1.1 10

14 14

0.25

0.25 2

3.75

2.4 27

35 35

INTRC Option F

OSC = 4 MHz, VDD = 5.5V

µA

LP O

PTION, Commercial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Industrial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Extended Te mperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

8 9

VDD = 3.0V, Commercial WDT disabled

µA

DD = 3.0V, Industrial WDT disabled

µA

DD = 3.0V, Extended WDT disabled

µA

VDD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

* These parameters are characterized but not tested. Note 1: Data in the T y pical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.

a) The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power do wn current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V V

SS.

DD or

DS40139E-page 6 6  1999 Microchip Technology Inc.

PIC12C5XX

11.2 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ T

DC CHARACTERISTICS

Operating voltage V

–40°C ≤ T –40°C ≤ T

DD range as described in DC spec Section 11.1 and

Section 11.2.

Param

Characteristic Sym Min Typ† Max Units Conditions

No.

Input Low Voltage

I/O ports V

D030 with TTL buffer V

IL -

SS -0.8VV4.5 < VDD ≤ 5.5V

-0.15V D031 with Schmitt Trigger buffer V D032 MCLR D033

, GP2/T0CKI (in EXTRC mode) VSS -0.15VDD V

OSC1 (EXTRC)

(1)

SS -0.15VDD V

VSS -0.15VDD

D033 OSC1 (in XT and LP) VSS -0.3VDD VNote1

Input High Voltage

I/O ports V D040 with TTL buffer V D040A 0.25V

IH -

SS 2.0V - VDD V4.5 ≤ VDD ≤ 5.5V

DD +

-VDD Votherwise

0.8V D041 with Schmitt Trigger buffer 0.85V D042 MCLR

/GP2/T0CKI 0.85VDD -VDD V D042A OSC1 (XT and LP) 0.7V D043 OSC1 (in EXTRC mode) 0.85V D070 GPIO weak pull-up current I

Input Leakage Current

(2, 3)

D060 I/O ports I

D061 MCLR

, GP2/T0CKI 20 130

PUR 50 250 400 µAVDD = 5V, VPIN = VSS

IL -1 0.5 +1 µA Vss ≤ VPIN ≤ VDD,

DD -VDD V For entire VDD range

DD -VDD VNote1

DD -VDD V

0.5

D063 OSC1 -3 0.5 +3 µA Vss ≤ VPIN ≤ VDD,

Output Low Voltage

D080 I/O ports/CLKOUT V

OL --0.6VIOL = 8.7 mA, VDD = 4.5V

Output High Voltage

D090

I/O ports/CLKOUT

(3)

VOH VDD - 0.7--VIOH = -5.4 mA, VDD = 4.5V

Capacitive Loading Specs on Output Pins

D100 OSC2 pin C

D101 All I/O pins C

OSC2 - - 15 pF In XT and LP modes when

IO - - 50 pF

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C5XX be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of th e pin.

A ≤ +70°C (commercial) A ≤ +85°C (industrial) A ≤ +125°C (extended)

DD Votherwise

For VDD ≤5.5V

Pin at hi-impedance

250+5µA

PIN = VSS + 0.25V

µA

VPIN = VDD

XT and LP options

external clock is used to drive OSC1.

(2)

 1999 Microchip Technology Inc. DS40139E-page 67

PIC12C5XX

TABL E 11-1: PULL-UP RESISTOR RANGES - PIC12C508/C509

VDD (Volts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 38K 42K 63K Ω

25 42K 48K 63K Ω 85 42K 49K 63K Ω

125 50K 55K 63K Ω

5.5 –40 15K 17K 20K Ω 25 18K 20K 23K Ω 85 19K 22K 25K Ω

125 22K 24K 28K Ω

GP3

2.5 –40 285K 346K 417K Ω 25 343K 414K 532K Ω 85 368K 457K 532K Ω

125 431K 504K 593K Ω

5.5 –40 247K 292K 360K Ω 25 288K 341K 437K Ω 85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

DS40139E-page 6 8  1999 Microchip Technology Inc.

PIC12C5XX

11.3 Timing Parameter Symbology and Load Conditions - PIC12C508/C509

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase subscripts (pp) and their meanings:

2to mcMCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings:

F Fall P Period HHigh RRise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedanc e

FIGURE 11-1: LOAD CONDITIONS - PIC12C508/C509

VSS

 1999 Microchip Technology Inc. DS40139E-page 69

L = 50 pF for all pins except OSC2

15 pF for OSC2 in XT or LP

modes when external clock is used to drive OSC1

PIC12C5XX

11.4 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509

OSC1

Q1 Q2

133

Q3 Q4 Q1

TABL E 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Parameter

No.

2Tcy 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

* These paramet ers are charact er ized but not tested .

Sym Characteristic Min

FOSC

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (T

Operating Temperature 0°C ≤ T

Operating Voltage V

External CLKIN Frequency

Oscillator Frequency

OSC

External CLKIN Period

Oscillator Period

Instruction Cycle Time

(2)

CY) equals four times the input oscillator time base period.

–40°C ≤ T –40°C ≤ T

DD range is described in Section 11.1

(2)

(3)

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Max Units Conditions

Typ

DC — 4 MHz XT osc mode DC — 200 kHz LP osc mode

0.1 — 4 MHz XT osc mode

DC — 200 kHz LP osc mode 250 — — ns EXTRC osc mode 250 — — ns XT osc mode

5 — — ms LP osc mode 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode

5 — — ms LP osc mode

—4/FOSC ——

2* — — ms LP oscillator

— — 50* ns LP oscillator

DS40139E-page 7 0  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

Operating Voltage V

Parameter

No.

* These parameters are characterized but not tested.

Sym Characteristic Min*

Internal Calibrated RC Frequency 3.58 4.00 4.32 MHz VDD = 5.0V

Internal Calibrated RC Frequency

–40°C ≤ T –40°C ≤ T

DD range is described in Section 10.1

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Max* Units Conditions

Typ

3.50 —4.26MHzV

DD = 2.5V

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

FIGURE 11-3: I/O TIMING - PIC12C508/C509

OSC1

I/O Pin

(input)

I/O Pin

(output)

Old Value

Q2 Q3

New Value

20, 21

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

 1999 Microchip Technology Inc. DS40139E-page 71

PIC12C5XX

TABL E 11-4: TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Te mperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

DD range is described in Section 11.1

Parameter

No. Sym Characteristic Min Typ

17 18

TosH2io V

OSC1↑ (Q1 cycle) to Port out valid

TosH2io I OSC1↑ (Q2 cycle) to Port input invalid

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(3)

— — 100* ns

TBD — — ns

(1)

Max Units

(I/O in hold time)

TioV2osH Port input valid to OSC1↑

TBD — — ns

(I/O in setup time)

20 21

TioR TioF

Port output rise time Port output fall time

(2, 3)

—1025**ns —1025**ns

* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Dat a in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 11-1 for loading conditions.

FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509

VDD

MCLR

Internal

POR

DRT

Timeout (Note 2)

Internal

RESET

Watchdog

Timer

RESET

I/O pin (Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes.

DS40139E-page 7 2  1999 Microchip Technology Inc.

PIC12C5XX

TABL E 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

DD range is described in Section 11.1

Parameter

No. Sym Characteristic Min Typ

TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V

Twdt Watchdog Timer Time-out Period

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

9* 18* 30* ms VDD = 5 V (Commercial)

(No Prescaler)

TDRT Device Reset Timer Period

TioZ I/O Hi-impedance from MCLR Low — — 2000* ns

(2)

9* 18* 30* ms VDD = 5 V (Commercial)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 2: See Table 11-6.

TABL E 11-6: DRT (DEVICE RESET TIMER PERIOD - PIC12C508/C509)

Oscillator Configuration POR Reset Subsequent Resets

IntRC & ExtRC 18 ms (typical) 300 µs (typical) XT & LP 18 ms (typical) 18 ms (typical)

 1999 Microchip Technology Inc. DS40139E-page 73

PIC12C5XX

FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509

T0CKI

40 41

TABL E 11-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

Parameter

No.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

Sym Characteristic Min Typ

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 T

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or T

and are not tested.

DD range is described in Section 11.1.

CY + 20* — — ns

CY + 40*

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

— — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

DS40139E-page 7 4  1999 Microchip Technology Inc.

PIC12C5XX

12.0 DC AND AC CHARACTERISTICS - PIC12C50 8/PIC12C509

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified V only and devices will operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical ” represents the me an of the dis tribution while “max” or “min” represents ( mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation.

DD range). This is for information

FIGURE 12-1: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS. TEMPERATURE (V

4.50

4.40

4.30

4.20

4.10

4.00

Frequency (MHz)

3.90

3.80

3.70

3.60

3.50

-40 25 85 125 Temperature (Deg.C)

DD = 2.5V)

Max.

Min.

FIGURE 12-2: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS . TEMPERATURE (V

4.50

4.40

4.30

4.20

4.10

4.00

Frequency (MHz)

3.90

3.80

3.70

3.60

3.50

-40 25 85 125 Temperature (Deg.C)

DD = 5.0V)

Max.

Min.

 1999 Microchip Technology Inc. DS40139E-page 75

PIC12C5XX

TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator Frequency VDD = 2.5V VDD = 5.5V

External RC 4 MHz 250 µA* 780 µA* Internal RC 4 MHz 420 µA 1.1 mA XT 4 MHz 251 µA 780 µA LP 32 KHz 15 µA 37 µA *Does not include current through external R&C.

FIGURE 12-3: WDT TIMER TIME-OUT

PERIOD VS. V

WDT period (mS)

234567

Max +125°C

Max +85°C

Ty p + 25°C

MIn –40°C

DD (Volts)

FIGURE 12-4: SHORT DRT PERIOD VS. VDD

1000

900

800

700

600

500

WDT period (µs)

400

300

200

100

234567

DD (Volts)

Max +125°C

Max +85°C

Ty p + 2 5°C

MIn –40°C

DS40139E-page 76  1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V

-1

-2

-3

IOH (mA)

-4

-5

-6

-7

500m 1.0 1.5

FIGURE 12-6: I

–

VOH (Volts)

OH vs. VOH, VDD = 5.5 V

2.0 2.5

FIGURE 12-7: IOL vs. VOL, VDD = 2.5 V

Max –40°C

Ty p + 2 5°C

IOL (mA)

Min +85°C

FIGURE 12-8: I

250.0m 500.0m 1.0

OL (Volts)

OL vs. VOL, VDD = 5.5 V

Min +125°C

-5

Max –40°C

-10

-15

Typ +25°C

IOH (mA)

-20

-25

-30

3.5 4.0 4.5

–

5.0 5.5

VOH (Volts)

 1999 Microchip Technology Inc. DS40139E-page 77

IOL (mA)

250.0m

Min +85°C

Min +125°C

500.0m 750.0m 1.0

OL (Volts)

PIC12C5XX

NOTES:

DS40139E-page 78  1999 Microchip Technology Inc.

PIC12C5XX

13.0 ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/ PIC12LCE518/PIC12LCE519/PIC12LCR509A

Absolute Maximum Ratings†

Ambient Temperature under bias........................................................................................................... –40°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on V Voltage on MCLR Voltage on all other pins with respect to V Total Power Dissipation Max. Current out of V Max. Current into V Input Clamp Current, I Output Clamp Current, I

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................25 mA

Max. Output Current sourced by I/O port (GPIO) .................................................................................................100 mA

Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA

Note 1: Power Dissipation is calculated as follows: P

†

DD with respect to VSS .................................................................................................................0 to +7.0 V

with respect to VSS...............................................................................................................0 to +14 V

(1)

....................................................................................................................................700 mW

SS pin ..................................................................................................................................200 mA

DD pin.....................................................................................................................................150 mA

IK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

OK (VO < 0 or VO > VDD).............................................................................................................±20 mA

SS ............................................................................... –0.3 V to (VDD + 0.3 V)

DIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

 1999 Microchip Technology Inc. DS40139E-page 79

PIC12C5XX

13.1 DC CHARACTERISTICS: PIC12C508A/509A (Commercial, Industrial, Extended) PIC12CE518/519 (Commercial, Industrial, Extended) PIC12CR509A (Commercial, Industrial, Extended)

DC Characteristics Power Supply Pins

Parm

No.

Characteristic Sym Min

D001 Supply Voltage V

D002 RAM Data Retention

(2)

Voltage

D003 V

DD Start Voltage to ensure

Power-on Reset

D004 V

DD Rise Rate to ensure

Power-on Reset

D010

Supply Current

(3)

D010C D010A

D020

Power-Down Current

D021

(5)

D021B D022

Power-Down Current

Supply Current

(3)

During read/write to EEPROM peripheral

* These parameters are characterized but not tested. Note 1: Dat a in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-

ance only and is not tested. 2: This is the limit to which V 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the

current consumption.

a) The test conditions for all I

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

Standard Operating Conditions (unless otherwise specif ied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ T –40°C ≤ T

(1)

Typ

DD 3.0 5.5 V FOSC = DC to 4 MHz (Commercial/

Max Units Conditions

A ≤ +85°C (industrial) A ≤ +125°C (extended)

Industrial, Extended)

VDR 1.5* V Device in SLEEP mode

VPOR VSS V See section on Power-on Reset for details

SVDD 0.05* V/ms See section on Power-on Reset for details

IDD —

— — — —

IPD —

— —

∆I

WDT —

— —

∆I

EE — 0.1 0.2 mA FOSC = 4 MHz, Vdd = 5.5V,

0.8

0.8 19 19

0.25

0.25 2

2.2

2.2 4

1.4

1.4 27 35

OSC = 4 MHz, VDD = 5.5V

INTRC Option F

OSC = 4 MHz, VDD = 5.5V

µA

LP O

PTION, Commercial Tem perature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Industrial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Extended Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

5 6

VDD = 3.0V, Commercial WDT disabled

µA

DD = 3.0V, Industr ial WDT disabled

µA

DD = 3.0V, Extended WDT disabled

µA

VDD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

XT and EXTRC options (Note 4)

SCL = 400kHz

DD can be lowered in SLEEP mode without losing RAM data.

DD measurements in active operation mode are:

DD or VSS.

DS40139E-page 8 0  1999 Microchip Technology Inc.

PIC12C5XX

13.2 DC CHARACTERISTICS: PIC12LC508A/509A (Commercial, Industrial) PIC12LCE518/519 (Commercial, Industrial) PIC12LCR509A (Commercial, Industrial)

DC Characteristics Power Supply Pins

Parm

No.

Characteristic Sym Min

D001 Supply Voltage V

D002 RAM Data Retention

(2)

Voltage

D003 V

DD Start Voltage to ensure

Power-on Reset

D004 V

DD Rise Rate to ensure

Power-on Reset

D010

Supply Current

(3)

D010C

D010A

D020

Power-Down Current

D021

(5)

D021B

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested. 2: This is the limit to which V 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an

impact on the current consumption.

a) The test conditions for all I

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

SS.

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

–40°C ≤ T

(1)

Max Units Conditions

Typ

DD 2.5 5.5 V FOSC = DC to 4 MHz (Commercial/

A ≤ +70°C (commercial) A ≤ +85°C (industrial)

Industrial)

VDR 1.5* V Device in SLEEP mode

VPOR VSS V See section on Power-on Reset for details

SVDD 0.05* V/ms See section on Power-on Reset for details

IDD —

0.4

0.8

XT and EXTRC options (Note 4) F

—

0.4

0.8

—

OSC = 4 MHz, VDD = 2.5V

INTRC Option F

OSC = 4 MHz, VDD = 2.5V

µA

LP O

PTION, Commercial Temperature

OSC = 32 kHz, VDD = 2.5V, WDT disabled

µA

LP O

PTION, Industrial Temperature

OSC = 32 kHz, VDD = 2.5V, WDT disabled

IPD

——0.2

0.234µAµA

∆I

WDT —2.0

2.045mAmA

DD can be lowered in SLEEP mode without losing RAM data.

DD measurements in active operation mode are:

VDD = 2.5V, Commercial V

DD = 2.5V, Industrial

VDD = 2.5V, Commercial V

DD = 2.5V, Industrial

DD or

 1999 Microchip Technology Inc. DS40139E-page 81

PIC12C5XX

13.3 DC CHARACTERISTICS: PIC12C508A/509A (Commercial, Industrial, Extended) PIC12C518/519 (Commercial, Industrial, Extended) PIC12CR509A (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ T

DC CHARACTERISTICS

Operating voltage V

–40°C ≤ T –40°C ≤ T

DD range as described in DC spec Section 13.1 and

Section 13.2.

Param

Characteristic Sym Min Typ† Max Units Conditions

No.

Input Low Voltage

I/O ports V

D030 with TTL buffer VSS - 0.8V V For 4.5V ≤ VDD ≤

SS - 0.15VDD V otherwise

D031 with Schmitt Trigger buffer V D032 MCLR

, GP2/T0CKI (in EXTRC mode) VSS -0.2VDD V D033 OSC1 (in EXTRC mode) V D033 OSC1 (in XT and LP) V

SS -0.2VDD V

SS -0.2VDD Note 1 SS -0.3VDD V Note 1

Input High Voltage

I/O ports V

D040 with TTL buffer 0.25V

IH -

DD +

-VDD V4.5V ≤ VDD ≤ 5.5V

0.8V D040A 2.0V - V D041 with Schmitt Trigger buffer 0.8V D042 MCLR

, GP2/T0CKI 0.8VDD -VDD V D042A OSC1 (XT and LP) 0.7V D043 OSC1 (in EXTRC mode) 0.9V D070 GPIO weak pull-up current (Note 4) I

PUR 30 250 400

DD -VDD V For entire VDD range

DD -VDD V Note 1 DD -VDD V

MCLR pull-up current - - - 30 Input Leakage Current (Notes 2, 3)

D060 I/O ports I

IL --+1

D061 T0CKI - - + D063 OSC1 - - +5

Output Low Voltage

D080 I/O ports V

OL --0.6VIOL = 8.5 mA, VDD = 4.5V,

D080A - - 0.6 V I

Output High Voltage

D090 I/O ports (Note 3) V

D090A V

OH VDD - 0.7--VIOH = -3.0 mA, VDD = 4.5V,

DD - 0.7--VIOH = -2.5 mA, VDD = 4.5V,

Capacitive Loading Specs on Output Pins

D100 OSC2 pin COSC2 - - 15 pF In XT and LP modes when exter-

D101 All I/O pins C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC12C5XX be driven with external clock in RC mode.

2: The leakage current on the MCLR

normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: This spec. applies when GP3/MCLR

standard I/O logic.

pin is strongly dependent on the applied voltage level. The specified levels represent

IO - - 50 pF

is configured as MCLR. The leakage current of the MCLR circuit is higher than the

A ≤ +70°C (commercial) A ≤ +85°C (industrial) A ≤ +125°C (extended)

DD V otherwise

AVDD = 5V, VPIN = VSS

A Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

A Vss ≤ VPIN ≤ VDD

A Vss ≤ VPIN ≤ VDD, XT and LP osc

configuration

–40°C to +85°C

OL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

–40°C to +85°C

–40°C to +125°C

nal clock is used to drive OSC1.

5.5V

DS40139E-page 8 2  1999 Microchip Technology Inc.

PIC12C5XX

13.4 DC CHARACTERISTICS: PIC12LC508A/509A (Commercial, Industrial) PIC12LC518/519 (Commercial, Industrial) PIC12LCR509A (Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

DC CHARACTERISTICS

Operating voltage V

–40°C ≤ T

DD range as described in DC spec Section 13.1 and

Section 13.2.

Operating temperature 0°C ≤ T

Param

Characteristic Sym Min Typ† Max Units Conditions

No.

Input Low Voltage

I/O ports V

D030 with TTL buffer VSS - 0.8V V For 4.5V ≤ VDD ≤

SS -0.15VDD V otherwise

D031 with Schmitt Trigger buffer V D032 MCLR

, GP2/T0CKI (in EXTRC mode) VSS -0.2VDD V D033 OSC1 (in EXTRC mode) V D033 OSC1 (in XT and LP) V

SS -0.2VDD V

SS -0.2VDD V Note 1 SS -0.3VDD V Note 1

Input High Voltage

I/O ports V

D040 with TTL buffer 0.25V

IH -

DD +

-VDD V4.5V ≤ VDD ≤ 5.5V

0.8V D040A 2.0V - V D041 with Schmitt Trigger buffer 0.8V D042 MCLR

, GP2/T0CKI 0.8VDD -VDD V D042A OSC1 (XT and LP) 0.7V D043 OSC1 (in EXTRC mode) 0.9V D070 GPIO weak pull-up current (Note 4) I

PUR 30 250 400

DD -VDD V For entire VDD range

DD -VDD V Note 1 DD -VDD V

MCLR pull-up current - - - 30 Input Leakage Current (Notes 2, 3)

D060 I/O ports I

IL --+1

D061 T0CKI - - + D063 OSC1 - - +5

Output Low Voltage

D080 I/O ports V

OL --0.6VIOL = 8.5 mA, VDD = 4.5V,

D080A - - 0.6 V I

Output High Voltage

D090 I/O ports (Note 3) V

D090A V

OH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

DD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

Capacitive Loading Specs on Output Pins

D100 OSC2 pin COSC2- - 15 pF In XT and LP modes when exter-

D101 All I/O pins C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC12C5XX be driven with external clock in RC mode.

2: The leakage current on the MCLR

normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: This spec. applies when GP3/MCLR

standard I/O logic.

pin is strongly dependent on the applied voltage level. The specified levels represent

IO - - 50 pF

is configured as MCLR. The leakage current of the MCLR circuit is higher than the

+70°C (commercial)

≤

+85°C (industrial)

≤

DD V otherwise

AVDD = 5V, VPIN = VSS

A Vss ≤ VPIN ≤ VDD, Pin at hi-imped-

ance

A Vss ≤ VPIN ≤ VDD

A Vss ≤ VPIN ≤ VDD, XT and LP osc

configuration

–40°C to +85°C

OL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

–40°C to +85°C

–40°C to +125°C

nal clock is used to drive OSC1.

5.5V

 1999 Microchip Technology Inc. DS40139E-page 83

PIC12C5XX

TABLE 13-1: PULL-UP RESISTOR RANGES* - PIC12C508A, PIC12C509A, PIC12CR509A,

PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

VDD (Volts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 38K 42K 63K Ω

25 42K 48K 63K Ω 85 42K 49K 63K Ω

125 50K 55K 63K Ω

5.5 –40 15K 17K 20K Ω 25 18K 20K 23K Ω 85 19K 22K 25K Ω

125 22K 24K 28K Ω

GP3

2.5 –40 285K 346K 417K Ω 25 343K 414K 532K Ω 85 368K 457K 532K Ω

125 431K 504K 593K Ω

5.5 –40 247K 292K 360K Ω 25 288K 341K 437K Ω 85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

DS40139E-page 8 4  1999 Microchip Technology Inc.

PIC12C5XX

13.5 Timing Parameter Symbology and Load Conditions - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase subscripts (pp) and their meanings:

2to mcMCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings:

F Fall P Period HHigh RRise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedanc e

FIGURE 13-1: LOAD CONDITIONS - PIC12C508A/C509A, PIC12CE518/519, PIC12LC508A/509A,

PIC12LCE518/519, PIC12LCR509A

VSS

 1999 Microchip Technology Inc. DS40139E-page 85

L = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock is used to drive OSC1

PIC12C5XX

13.6 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC12C508A, PIC12C509A, PIC12CR509A,

PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

OSC1

Q1 Q2

133

Q3 Q4 Q1

TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508A, PIC12C509A,

PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Parameter

No.

2Tcy 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

* These paramet ers are charact er ized but not tested .

Sym Characteristic Min

FOSC

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

3: Instruction cycle period (T

Operating Temperature 0°C ≤ T

Operating Voltage V

External CLKIN Frequency

Oscillator Frequency

OSC

External CLKIN Period

Oscillator Period

Instruction Cycle Time

(2)

CY) equals four times the input oscillator time base period.

–40°C ≤ T –40°C ≤ T

DD range is described in Section 13.1

(2)

(3)

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Max Units Conditions

Typ

DC — 4 MHz XT osc mode DC — 200 kHz LP osc mode DC — 4 MHz EXTRC osc mode

0.1 — 4 MHz XT osc mode

DC — 200 kHz LP osc mode

250 — — ns XT osc mode

5 — — ms LP osc mode 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode

5 — — ms LP osc mode

—4/FOSC ——

2* — — ms LP oscillator

— — 5 0* ns LP oscillator

DS40139E-page 8 6  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 13-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508A, PIC12C509A,

PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Parameter

No.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

Sym Characteristic Min*

guidance only and are not tested.

Operating Temperature 0°C ≤ T

Operating Voltage V

Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.0V

Internal Calibrated RC Frequency

–40°C ≤ T –40°C ≤ T

DD range is described in Section 10.1

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Max* Units Conditions

Typ

3.55 —4.31MHzV

DD = 2.5V

 1999 Microchip Technology Inc. DS40139E-page 87

PIC12C5XX

FIGURE 13-3: I/O TIMING - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,

PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

OSC1

I/O Pin

(input)

I/O Pin

(output)

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

Old Value

20, 21

Q2 Q3

New Value

TABLE 13-4: TIMING REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519,

PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Parameter

No. Sym Characteristic Min Typ

17 18

20 21

TosH2io V TosH2io I OSC1↑ (Q2 cycle) to Port input invalid

TioV2osH Port input valid to OSC1↑

TioR TioF

* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Dat a in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 13-1 for loading conditions.

Operating Te mperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

OSC1↑ (Q1 cycle) to Port out valid

DD range is described in Section 13.1

(3)

(I/O in hold time)

(I/O in setup time) Port output rise time Port output fall time

(2, 3)

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

— — 100* ns

TBD — — ns

—1025**ns —1025**ns

(1)

Max Units

DS40139E-page 8 8  1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -

PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

VDD

MCLR

Internal

POR

DRT

Timeout (Note 2)

Internal

RESET

Watchdog

Timer

RESET

I/O pin (Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes.

TABLE 13-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508A,

PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

DD range is described in Section 13.1

Parameter

No. Sym Characteristic Min Typ

TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V

Twdt Watchdog Timer Time-out Period

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

9* 18* 30* ms VDD = 5 V (Commercial)

(No Prescaler)

TDRT Device Reset Timer Period

TioZ I/O Hi-impedance from MCLR Low — — 2000* ns

(2)

9* 18* 30* ms VDD = 5 V (Commercial)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 2: See Table 13-6.

 1999 Microchip Technology Inc. DS40139E-page 89

PIC12C5XX

TABLE 13-6: DRT (DEVICE RESET TIMER PERIOD) - PIC12C508A, PIC12C509A, PIC12CE518,

PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

Oscillator Configuration POR Reset Subsequent Resets

IntRC & ExtRC

XT & LP

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

18 ms (typical)

(1) (1)

300 µs (typical)

18 ms (typical)

(1)

FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519,

PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

T0CKI

40 41

TABLE 13-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518,

PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Parameter

No.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

Sym Characteristic Min Typ

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 T

42 Tt0P T0CKI Period 20 or T

and are not tested.

Operating Temperature 0°C ≤ T

Operating Voltage V

- With Prescaler 10* — — ns

–40°C ≤ T –40°C ≤ T

DD range is described in Section 13.1.

CY + 20* — — ns

CY + 40*

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

— — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

DS40139E-page 9 0  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 13-8: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX ONLY.

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ T

Operating Voltage V

DD range is described in Section 13.1

–40°C ≤ T –40°C ≤ T

A ≤ +70°C, Vcc = 3.0V to 5.5V (commercial)

A ≤ +85°C, Vcc = 3.0V to 5.5V (industrial) A ≤ +125°C, Vcc = 4.5V to 5.5V (extended)

Parameter Symbol Min Max Units Conditions

Clock frequency F

Clock high time T

Clock low time T

SDA and SCL rise time (Note 1)

SDA and SCL fall time T START condition hold time T

START condition setup time T

Data input hold time T Data input setup time T

STOP condition setup time T

HD:STA 4000

SU:STA 4700

HD:DAT 0 — ns (Note 2) SU:DAT 250

SU:STO 4000

Output valid from clock (Note 2)

Bus free time: Time the bus must

T be free before a new transmission can start

Output fall time from V

minimum to VIL maximum Input filter spike suppression

CLK —

HIGH 4000

4000

600

LOW 4700

4700 1300

R —

F — 300 ns (Note 1)

4000

600

4700

600

250 100

4000

600

AA —

BUF 4700

4700 1300

OF 20+0.1

SP — 50 ns (Notes 1, 3)

100 — —

1000

—

1000

—

3500

—

3500

—

kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 100 400

— — —

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

300

— — —

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

900

— — —

4.5V ≤ Vcc ≤ 5.5V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

3.0V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

250 ns (Note 1), CB ≤ 100 pF

(SDA and SCL pins) Write cycle time T Endurance 1M — cycles 25°C, V

WC —4ms

CC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on Microchip’s website.

 1999 Microchip Technology Inc. DS40139E-page 91

PIC12C5XX

NOTES:

DS40139E-page 9 2  1999 Microchip Technology Inc.

PIC12C5XX

14.0 DC AND AC CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A, PIC12CE518/PIC12CE519/PIC12CR509A/ PIC12LCE518/PIC12LCE519/ PIC12LCR509A

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical ” represents the me an of the dis tribution while “max” or “min” represents ( mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation.

DD range). This is for information

FIGURE 14-1: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS. TEMPERATURE (V

DD = 5.0V)

(INTERNAL RC IS

CALIBRATED TO 25°C, 5.0V)

4.50

4.40

4.30

4.20

4.10

4.00

3.90

Frequency (MHz)

3.80

3.70

3.60

3.50

-40 2 5 85 125

Temperature (Deg.C)

Max.

Min.

FIGURE 14-2: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS . TEMPERATURE (V

DD = 2.5V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

4.50

4.40

4.30

4.20

4.10

4.00

3.90

Frequency (MHz)

3.80

3.70

3.60

3.50

-40 25 85 125

Temperature (Deg.C)

Max.

Min

 1999 Microchip Technology Inc. DS40139E-page 93

PIC12C5XX

TABLE 14-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator Frequency VDD =3.0V VDD = 5.5V

External RC 4 MHz 240 µA* 800 µA* Internal RC 4 MHz 320 µA 800 µA XT 4 MHz 300 µA 800 µA LP 32 KHz 19 µA 50 µA *Does not include current through external R&C.

FIGURE 14-3: TYPICAL IDD VS. VDD

(WDT DIS, 25°C, FREQUENCY

= 4MH

600

550

500

450

400

350

)

µA

300

(

250

200

150

100

3.0

2.5 4.5 5.0 5.5

VDD (V o lts )

FIGURE 14-4: TYPICAL IDD VS. FREQ UENCY

(WDT DIS, 25°C, V

600

550

500

450

400

350

)

µA

300

(

250

200

150

100

1.0

0 2.0 3.5 4.0

Frequency (MHz)

DD = 5.5V)

3.02.51.5.5

DS40139E-page 9 4  1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 14-5: WDT TIMER TIME-OUT

DD (Volts)

Max +125°C

Max +85°C

Ty p + 2 5°C

MIn –40°C

PERIOD vs. V

WDT period (µS)

0 2.5 3.5 4.5 5.5 6.5

FIGURE 14-6: SHORT DRT PERIOD VS. VDD

950

FIGURE 14-7: IOH vs. VOH, VDD = 2.5 V

-0

-1

-2

-3

-4

Min +125°C

-5

IOH (mA)

-6

-7

-8

-9

-10

FIGURE 14-8: I

Min +85°C

Typ +25°C

Max -40°C

.5 1.0 1.5 2.0 2.5

VOH (Volts)

OH vs. VOH, VDD = 3.5 V

2.251.751.25.75

850

-5

750

650

550

450

WDT period (µs)

350

Max +125°C

Max +85°C

Ty p + 25°C

250

MIn –40°C

150

0 2.5 3.5 4.5 5.5 6.5

DD (Volts)

 1999 Microchip Technology Inc. DS40139E-page 95

Min +125°C

-10

IOH (mA)

Min +85°C

-15

-20

-25

Typ +25°C

Max -40°C

1.5 2.0 2.5

VOH (Volts)

3.0

3.5

PIC12C5XX

FIGURE 14-9: IOL vs. VOL, VDD = 2.5 V

Max -40°C

IOL (mA)

FIGURE 14-10: I

0.25

0.5 0.75 1.0

VOL (Volts)

OL vs. VOL, VDD = 3.5 V

Ty p + 2 5°C

Min +85°C

Min +125°C

Max -40°C

FIGURE 14-11: IOH vs. VOH, VDD = 5.5 V

-5

-10

-15

-20

IOH (mA)

-25

-30

-35

-40

3.5 4.0 4.5

FIGURE 14-12: I

–

VOH (Volts)

OL vs. VOL, VDD = 5.5 V

5.0 5.5

Max -40°C

Ty p + 2 5°C

IOL (mA)

Min +85°C

Min +125°C

0.25

0.5 0.75 1.0

VOL (Volts)

Ty p + 25°C

IOL (mA)

Min +85°C

Min +125°C

0.25

0.5 0.75 1.0

VOL (Volts)

DS40139E-page 9 6  1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 14-13: TYPICAL IPD VS. VDD,

WATCHDOG DISABL ED (25°C)

260

250

240

230

Ipd (nA)

220

210

200

2.5 3.0 3.5 4.5 5.0 5.5 V

DD (Volts)

FIGURE 14-14: VTH (INPUT THRESHOLD

VOLTAGE) OF GPIO PINS

VS. V

1.8

1.6

1.4

VTH (Volts)

1.2

1.0

0.8

0.6

2.5 3.5 4.5 5.5 V

DD (Volts)

Max (-40 to 125)

Ty p ( 2 5

)

Min (-40 to 125)

 1999 Microchip Technology Inc. DS40139E-page 97

PIC12C5XX

FIGURE 14-15: VIL, VIH OF NMCLR, AND T0CKI VS. VDD

3.5

3.0

2.5

2.0

VIL, VIH (Volts)

1.5

1.0

0.5

2.5 3.5 4.5 5.5 V

DD (Volts)

Vih Max (-40 to 125)

VIH Typ (25

)

VIH Min (-40 to 125)

VIL Max (-40 to 125)

VIL Typ ( 25

)

VIL Min (-40 to 125)

DS40139E-page 9 8  1999 Microchip Technology Inc.

15.0 PACKAGING INFORMATION

15.1 Package Marking Information

8-Lead PDIP (300 mil)

XXXXXXXX XXXXXCDE

AABB

PIC12C5XX

Example

12C508A 04I/PSAZ

9825

8-Lead SOIC (150 mil)

XXXXXXX

AABB

8-Lead SOIC (208 mil)

XXXXXXX XXXXXXX AABBCDE

8-Lead Windowed Ceramic Side Brazed (300 mil)

XXX

XXXXXX

Legend: MM...M Microchip part number information

XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

O = Outside Vendor C = 5” Line S = 6” Line

H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters for customer specific information.

* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

Example

C508A

9825

Example

12C508A 04I/SM

9824SAZ

Example

12C508A

 1999 Microchip Technology Inc. DS40139E-page 99

PIC12C5XX

Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil

Units Dimension Limits

PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

n p B

†

B1 R c A A1 A2

‡

E E1 eB

α β

MIN

0.014

0.055

0.000

0.006

0.140

0.060

0.005

0.120

0.355

0.245

0.267

0.310

INCHES*

5 5

0.300

0.100

0.018

0.060

0.005

0.012

0.150

0.080

0.020

0.130

0.370

0.250

0.280

MILLIMETERS

MAX

0.022

0.065

0.010

0.015

0.160

0.100

0.035

0.140

0.385

0.260

0.292

0.3800.342 10 10

MINNOM

0.36

1.40

0.00

0.20

3.56

1.52

0.13

3.05

9.02

6.22

6.78

15 15

5 5

NOM MAX

7.62 8

2.54

0.46

1.52

0.13

0.29

3.81

2.03

0.51

3.30

9.40

6.35

7.10

10 10

0.56

1.65

0.25

0.38

4.06

2.54

0.89

3.56

9.78

6.60

7.42

9.658.677.87 15 15

DS40139E-page 100  1999 Microchip Technology Inc.

Microchip PIC12C508, PIC12C508A, PIC12CE518, PIC12C509, PIC12C509A Data Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 GENERAL DESCRIPTION

1.1 Applications

2.0 PIC12C5XX DEVICE VARIETIES

2.1 UV Erasable Devices

2.3 Quick-Turnaround-Production (QTP) Devices

2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices

2.5 Read Only Memory (ROM) Device

3.0 ARCHITECTURAL OVERVIEW

3.1 Clocking Scheme/Instruction Cycle

3.2 Instruction Flow/Pipelining

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

4.2 Data Memory Organization

4.2.1 GENERAL PURPOSE REGISTER FILE

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers

4.3 STATUS Register

4.4 OPTION Register

4.5 OSCCAL Register

4.6 Program Counter

4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

4.7 Stack

4.8 Indirect Data Addressing; INDF and FSR Registers

5.0 I/O PORT

5.1 GPIO

5.2 TRIS Register

5.3 I/O Interfacing

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate inter nally as read followed

5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS

6.0 TIMER0 MODULE AND TMR0 REGISTER

6.1 Using Timer0 with an External Clock

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

6.1.3 OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMER0 from the pin,

6.2 Prescaler

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

7.0 EEPROM PERIPHERAL OPERATION

7.0.1 SERIAL DATA

7.0.2 SERIAL CLOCK This SCL input is used to synchronize the data transfer

7.1 BUS CHARACTERISTICS

7.1.1 BUS NOT BUSY (A)

7.1.2 START DATA TRANSFER (B)

7.1.3 STOP DATA TRANSFER (C)

7.1.4 DATA VALID (D) The state of the data line represents valid data when,

7.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to

7.2 Device Addressing

7.3 WRITE OPERATIONS

7.3.1 BYTE WRITE

7.4 ACKNOWLEDGE POLLING

7.5 READ OPERATIONS

7.5.1 CURRENT ADDRESS READ It contains an address counter that maintains the

7.5.2 RANDOM READ Random read operations allow the master to access

7.5.3 SEQUENTIAL READ Sequential reads are initiated in the same way as a ran-

8.0 SPECIAL FEATURES OF THE CPU

8.1 Configuration Bits

8.2 Oscillator Configurations

8.2.1 OSCILLATOR TYPES The PIC12C5XX can be operated in four different

8.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

8.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device

8.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nom-

8.3 RESET

8.3.1 MCLR EN ABLE This configuration bit when unprogrammed (left in the

8.5 Device Reset Timer (DRT)

8.6 Watchdog Timer (WDT)

8.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms,

8.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the

8.8 Reset on Brown-Out

8.9 Power-Down Mode (SLEEP)

SLEEP instruction. If enabled, the Watchdog Timer will be cleared but

8.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

8.10 Program Verification/Code Protection

8.11 ID Locations

8.12 In-Circuit Serial Programming

9.0 INSTRUCTION SET SUMMARY

10.0 DEVELOPMENT SUPPORT