Microchip PIC12C508, PIC12C508A, PIC12CE518, PIC12C509, PIC12C509A Data Sheet

...

PIC12C5XX

8-Pin, 8-Bit CMOS Microcontrollers

Devices included in this Data Sheet:

• PIC12C508 • PIC12C508A • PIC12CE518

• PIC12C509 • PIC12C509A • PIC12CE519

• PIC12CR509A Note: Throughout this data sheet PIC12C5XX

refers to the PIC12C508, PIC12C509, PIC12C508A, PI C1 2C 50 9A , PIC12CR509A, PIC12CE518 and PIC12CE519. PIC12CE5XX refers to PIC12CE518 and PIC12CE519.

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (1 µs) except for program branches which are two-cycle

• Operating speed: DC - 4 MHz clock input

Device

PIC12C508 512 x 12 25 PIC12C508A 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C509A 1024 x 12 41 PIC12CE518 512 x 12 25 16 PIC12CE519 1024 x 12 41 16 PIC12CR509A 1024 x 12 41

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for data and instructions

• Internal 4 MHz RC oscillator with programmable calibration

• In-circuit serial programming

DC - 1 µs instruction cycle

Memory

EPROM

Program

ROM

Program

RAM Data

EEPROM

Data

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

• Power-On Reset (POR)

•Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• 1,000,000 erase/write cycle EEPROM data memory

• EEPROM data retention > 40 years

• Power saving SLEEP mode

• Wake-up from SLEEP on pin change

• Internal weak pull-ups on I/O pins

• Internal pull-up on MCLR

• Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low power, high speed CMOS EPROM/ROM technology

• Fully static design

• Wide operating voltage range

• Wide temperature range:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 KHz

- < 1 µA typical standby current

 1999 Microchip Technology Inc. DS40139E-page 1

PIC12C5XX

Pin Diagram - PIC12C508/509

PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed

PIC12C508

GP5/OSC1/CLKIN

GP3/MCLR

VDD

GP4/OSC2

/VPP

PIC12C509

1 2 3 4

8 7 6 5

Pin Diagram - PIC12C508A/509A, PIC12CE518/519

PDIP, 150 & 208 mil SOIC, Windowed CERDIP

PIC12C509A

PIC12CE518

PIC12CE519

GP5/OSC1/CLKIN

GP3/MCLR

VDD

GP4/OSC2

/VPP

PIC12C508A

1 2 3 4

8 7 6 5

Pin Diagram - PIC12CR509A

PDIP, 150 & 208 mil SOIC

VDD

GP5/OSC1/CLKIN

GP4/OSC2

/VPP

GP3/MCLR

PIC12CR509A

1 2 3 4

8 7 6 5

Device Differences

Device

PIC12C508A 3.0-5.5 See Note 1 6 0.7 PIC12LC508A 2.5-5.5 See Note 1 6 0.7 PIC12C508 2.5-5.5 See Note 1 4 0.9 PIC12C509A 3.0-5.5 See Note 1 6 0.7 PIC12LC509A 2.5-5.5 See Note 1 6 0.7 PIC12C509 2.5-5.5 See Note 1 4 0.9 PIC12CR509A 2.5-5.5 See Note 1 6 0.7 PIC12CE518 3.0-5.5 - 6 0.7 PIC12LCE518 2.5-5.5 - 6 0.7 PIC12CE519 3.0-5.5 - 6 0.7 PIC12LCE519 2.5-5.5 - 6 0.7

Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify

oscillator characteristics in your application.

Note 2: See Section 7.2.5 for OSCCAL implementation differences.

Voltage

Range

VSS GP0 GP1 GP2/T0CKI

Oscillator

Calibration

(Bits)

Process

Technology

(Microns)

DS40139E-page 2  1999 Microchip Technology Inc.

PIC12C5XX

TABLE OF CONTENTS

1.0 General Description............................................................................................................................................... 4

2.0 PIC12C5XX Device Varieties................................................................................................................................ 7

3.0 Architectural Overview........................................................................................................................................... 9

4.0 Memory Organizatio n ......................................... .............. ............. .............. ............. ........................... ................ 13

5.0 I/O Port ................................................................................................................................................................21

6.0 Timer0 Module and TMR0 Register .................................................................................................................... 25

7.0 EEPROM Peripheral Operation........................................................................................................................... 29

8.0 Special Features of the CPU...............................................................................................................................35

9.0 Instruction Set Summary..................................................................................................................................... 47

10.0 Development Support.............. ........................... .............. ............. .............. ............. .............. ............. ................ 59

11.0 Electrical Characteristics - PIC12C508/PIC12C509............................................................................................ 65

12.0 DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75

13.0 Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/ PIC12CE518/PIC12CE519/

PIC12LCE518/PIC12LCE519/PIC12LCR509A ...................................................................................................79

14.0 DC and AC Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/

PIC12LCE518/PIC12LCE519/ PIC12LCR509A ..................................................................................................93

15.0 Packaging Information......................................................................................................................................... 99

Index ........................................................................................................................................................................... 105

PIC12C5XX Product Identification System ................................................................................................................ 109

Sales and Support: ..................................................................................................................................................... 109

To Our Valued Customers

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet

(include literature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please:

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 1999 Microchip Technology Inc. DS40139E-page 3

PIC12C5XX

1.0 GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technolog y is a f amily of low-cost, high performance, 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 µs) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.

The PIC12C5XX products are equipped with speci al features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability.

The PIC12C5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility.

The PIC12C5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM PC and compatible machines.

1.1 Applications

The PIC12C5XX series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient, while the EEPROM data memory technology allows for the changing of calibration factors and security codes. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC12C5XX series very versatile even in areas where no microcon troller use has been considered before (e.g., timer functions, replacement of “glue” logic and PLD’s in larger systems, coprocessor applications).



DS40139E-page 4  1999 Microchip Technology Inc.

TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674

4444410101010

512 x 12 1024 x 12 1024 x 12

25 41 41 25 41 128 128 128 128

———1616——1616

TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0

—————4444

Yes Yes Yes Yes Yes Yes Yes Yes Yes

——— 4444

Yes Yes Yes Yes Yes Yes Yes Yes Yes

Yes Yes — Yes Yes Yes Yes Yes Yes

33 33 33 33 33 35 35 35 35

JW, SOIC

8-pin DIP, JW, SOIC

(ROM)

8-pin DIP, SOIC

512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14

8-pin DIP, JW, SOIC

Clock

Memory

Peripherals

Features

Maximum Frequency of Operation (MHz)

EPROM Program Memory

RAM Data Memory (bytes)

EEPROM Data Memory (bytes)

Timer Module(s)

A/D Converter (8-bit) Channels

Wake-up from SLEEP on pin change

Interrupt Sources

I/O Pins 5 5 5 5 5 5 5 5 5 Input Pins111111111 Internal

Pull-ups In-Circuit

Serial Programming

Number of Instructions

Packages 8 -pin DIP,

PIC12C5XX

8-pin DIP, JW, SOIC

8-pin DIP, JW8-pin DIP,

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

 1999 Microchip Technology Inc. DS40139E-page 5

PIC12C5XX

NOTES:

DS40139E-page 6  1999 Microchip Technology Inc.

PIC12C5XX

2.0 PIC12C5XX DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12C5XX Product Identification System at the back of this data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the configuration modes.

Note: Please note that erasing the device will

also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.

Microchip’s PICSTART grammers all support programming of the PIC12C5XX. Third party programmers also are available; refer to the

Microchip Third Party Guide

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications.

The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.



PLUS and PRO MATE pro-

for a list of sources.

2.3 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Pl ease contact your local Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

2.5 Read Only Memory (ROM) Device

Microchip offers masked ROM to give the customer a low cost option for high volume, mature products.

 1999 Microchip Technology Inc. DS40139E-page 7

PIC12C5XX

NOTES:

DS40139E-page 8  1999 Microchip Technology Inc.

PIC12C5XX

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Har vard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently , all instructions (33) exe cut e in a si n gle cycl e (1 µs @ 4MHz) except f or program branches.

The table below lists program memory (EPROM), data memory (RAM), ROM memory, and non-volatile (EEPROM) for each device.

Memory

Device

PIC12C508 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C508A 512 x 12 25 PIC12C509A 1024 x 12 41 PIC12CR509A 1024 x 12 41 PIC12CE518 512 x 12 25 x 8 16 x 8 PIC12CE519 1024 x 12 41 x 8 16 x 8

The PIC12C5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12C5XX has a highly orthogonal (symmetr ical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make programming with the PIC12C5XX simple yet efficient. In addition, the learning curve is reduced significantly.

EPROM

Program

ROM

Program

RAM Data

EEPROM

Data

The PIC12C5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit wor king register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow

and digit borrow out bit, respectively , in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

 1999 Microchip Technology Inc. DS40139E-page 9

PIC12C5XX

FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM

OSC1/CLKIN

OSC2

Program

Bus

ROM/EPROM

512 x 12 or

1024 x 12

Program Memory

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Internal RC

OSC

Program Counter

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

MCLR

STACK1 STACK2

VDD, VSS

RAM Addr

Data Bus

RAM

25 x 8 or

File

Registers

Addr MUX

5-7

FSR reg

STATUS reg

ALU

W reg

Timer0

MUX

Indirect

Addr

GPIO

SCL

16 X 8

EEPROM

Data

Memory

PIC12CE5XX

Only

GP0 GP1 GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN

SDA

DS40139E-page 1 0  1999 Microchip Technology Inc.

PIC12C5XX

TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION

DIP

Name

GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can

GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can

GP2/T0CKI 5 5 I/O ST Bi-directional I/O por t. Can be configured as T0CKI. GP3/MCLR

GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con-

GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external

DD 11P— Positive supply for logic and I/O pins

SS 8 8 P — Ground reference for logic and I/O pins

/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming volt-

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input

Pin #

SOIC Pin #

I/O/P Type

Buffer

Type

be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt T rigger input when used in serial programming mode.

age input. When configured as MCLR active low reset to the device. Voltage on MCLR must not exceed V or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR mode.

nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes).

clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode.

Description

DD during normal device operation

. ST when in MCLR

, this pin is an

/VPP

 1999 Microchip Technology Inc. DS40139E-page 11

PIC12C5XX

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

PC PC+1 PC+2

Fetch IN ST ( PC)

Execute INST (PC-1) Fetch INST (PC+1)

3.2 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cyc le while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Execute INST (PC+1)

Internal phase clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

4. BSF GPIO, BIT1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40139E-page 12  1999 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC12C5XX

4.0 MEMORY ORGANIZATION

PIC12C5XX memory is organized into program memory and data memor y. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A, PICCR509A and PIC12CE519 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization

The PIC12C5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space.

Only the first 512 x 12 (0000h-01FFh) for the PIC12C508, PIC12C508A and PIC12CE518 and 1K x 12 (0000h-03FFh) for the PIC12C509, PIC12C509A, PIC12CR509A, and PIC12CE519 are physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12C508, PIC12C508A and PIC12CE518) or 1K x 12 space (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519). The effective reset vector is at 000h, (see Figure 4-1). Location 01FFh (PIC12C508, PIC12C508A and PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519) contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

CALL, RETLW

Space

User Memory

PC<11:0>

Stack Level 1 Stack Level 2

Reset Vector (note 1)

On-chip Program

Memory

512 Word

On-chip Program

Memory

1024 Word

Note 1: Address 0000h becomes the

effective reset vector. Location 01FFh (PIC12C508, PIC12C508A, PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519) contains the MOVLW XX INTERNAL RC oscillator calibration value.

0000h

01FFh 0200h

03FFh 0400h

7FFh

 1999 Microchip Technology Inc. DS40139E-page 13

PIC12C5XX

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers.

The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special pur pose registers are used to control the I/O port configuration and prescaler options.

The general purpose registers ar e used for data and control information under command of the instructions.

FIGURE 4-2: PIC12C508, PIC12C508A AND

PIC12CE518 REGISTER FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

For the PIC12C508, PIC12C508A and PIC12CE518, the register file is composed of 7 special function registers and 25 general pur pose registers (Figure 4-

2). For the PIC12C509, PIC12C509A, PIC12CR509A,

General Purpose

Registers

and PIC12CE519 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Fig ure 4-3).

4.2.1 GENERAL PURPOSE REGISTER FILE

1Fh

Note 1: Not a physical register. See Section4.8

The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8).

FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.8

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General Purpose Registers

Bank 0 Bank 1

20h

Addresses map back to addresses in Bank 0.

2Fh

30h

General Purpose Registers

3Fh

DS40139E-page 1 4  1999 Microchip Technology Inc.

PIC12C5XX

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the operation of the device (Table 4-1).

The special registers can be classified into two sets. The special function registers associated with the

“core” functions are described in this section. Tho se related to the operation of the per ipheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS — —

N/A OPTION 00h INDF Uses contents of FSR to address data memory (not a physical register) 01h TMR0 8-bit real-time clock/counter

(1)

02h 03h STATUS GPWUF —PA0TO PD ZDCC

04h

05h

06h

PCL Low order 8 bits of PC

FSR (PIC12C508/ PIC12C508A/ PIC12C518)

FSR (PIC12C509/ PIC12C509A/ PIC12CR509A/ PIC12CE519)

OSCCAL (PIC12C508/ PIC12C509) CAL3 CAL2 CAL1 CAL0

OSCCAL (PIC12C508A/ PIC12C509A/ PIC12CE518/ PIC12CE519/ PIC12CR509A) CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)

GPIO (PIC12CE518/ PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0

Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as ’0’ (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6

for an explanation of how to access these bits. 2: Other (non power-up) resets include external reset through MCLR 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.

Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-up on chan ge, an d wea k pul l-u ps

Indirect data memory address pointer

— — — —

— —

— — GP5 GP4 GP3 GP2 GP1 GP0

, watchdog timer and wake-up on pin change reset.

Value on

Power-On

Reset

Value on All Other

Resets

(2)

--11 1111 --11 1111

1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0001 1xxx q00q quuu

111x xxxx 111u uuuu

110x xxxx 11uu uuuu

0111 ---- uuuu ----

1000 00-- uuuu uu--

--xx xxxx --uu uuuu

11xx xxxx 11uu uuuu

(3)

 1999 Microchip Technology Inc. DS40139E-page 15

PIC12C5XX

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furtherm ore, the TO

and PD bits are

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.

not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF

bit7 6 5 4 3 2 1 bit0 bit 7: GPWUF: GPIO reset bit

bit 6: Unimplemented bit 5: PA0: Program page preselect bits

bit 4: TO

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow

bit 0: C: Carry/borrow

—

1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset

1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12C5XX Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products.

: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

PA0 TO PD Z DC C R = Readable bit

bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

W = Writable bit

- n = Value at POR reset

DS40139E-page 1 6  1999 Microchip Technology Inc.

PIC12C5XX

4.4 OPTION Register

The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of GPPU

Note: If the T0CS bit is set to ‘1’, GP2 is forced to

be an input even if TRIS GP2 = ‘0’.

FIGURE 4-5: OPTION REGISTER

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit7 6 5 4 3 2 1 bit0

bit 7: GPWU

bit 6: GPPU

bit 5: T0CS: Timer0 clock source select bit

bit 4: T0SE: Timer0 source edge select bit

bit 3: PSA: Prescaler assignment bit

bit 2-0: PS2:PS0: Prescaler rate select bits

GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

: Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled

: Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4

1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Tim er0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

and GPWU.

U = Unimplemented bit

- n = Value at POR reset Reference Table4-1 for other resets.

 1999 Microchip Technology Inc. DS40139E-page 17

PIC12C5XX

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration. Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator.

FIGURE 4-6: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0

CAL3 CAL2 CAL1 CAL0

bit7 bit0

bit 7-4: CAL<3:0>: Calibration bit 3-0: Unimplemented: Read as ’0’

— — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/

12CE519

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

bit7 bit0

bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented: Read as ’0’

— — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

DS40139E-page 1 8  1999 Microchip Technology Inc.

PIC12C5XX

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instructi on, bits 8:0 of th e PC ar e provided by the GOTO instruction word. The PC Latch ( PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC ( Figure 4-

8). For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC ag ain are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-8).

Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

FIGURE 4-8: LOADING OF PC

BRANCH INSTRUCTIONS PIC12C5XX

GOTO Instruction

CALL or Modify PCL Instruction

87 0

910

PA0

STATUS

87 0

910

PCL

Instruction Word

PCL

4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

means that the PC addresses the l ast location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code.

The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected.

Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.

4.7 Stack

PIC12C5XX devices have a 12-bit wide L.I.F.O. hardware push/pop stack.

A CALL instruction will 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only

the most recent two return addresses are stored. A RETLW instruction will

1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled wi th the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0.

Note 1: There are no STATUS bits to indicate

stack overflows or stack underflow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are a ctions that occur from the execution of the CALL and RETLW instructions.

push

the current value of stack

pop

the contents of stack level

Instruction Word

Reset to ‘0’

PA0

STATUS

 1999 Microchip Technology Inc. DS40139E-page 19

PIC12C5XX

4.8 Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will retur n the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the IN DF register i ndirectly resul ts in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

FIGURE 4-9: DIRECT/INDIRECT ADDRESSING

Direct Addressing

(FSR) 6

(opcode) 04

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x10 ;initialize pointer

NEXT clrf INDF ;clear IN D F regi ster

CONTINUE

The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to selec t data memory addresses 00h to 1Fh.

PIC12C508/PIC12C508A/PIC12CE518: Does not use banking. FSR<7:5> are unimplemented and read as '1's.

PIC12C509/PIC12C509A/PIC12CR509A/ PIC12CE519: Uses FSR<5>. Selects between bank 0

and bank 1. FSR<7:6> is unimplemented, read as '1’ .

movwf FSR ; to RAM

incf FSR,F ;inc pointer btfsc FSR,4 ;all done? goto NEXT ;NO, clear next

: ;YES, continue

Indirect Addressing

(FSR)

bank select

location select

Data Memory

bank

00 01

00h

0Fh

(1)

10h

1Fh 3Fh

Bank 0 Bank 1

Addresses map back to addresses in Bank 0.

(2)

location select

Note 1: For register map detail see Section 4.2. Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12 CE519.

DS40139E-page 2 0  1999 Microchip Technology Inc.

PIC12C5XX

5.0 I/O PORT

As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O

pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. See Section 7.0 for SCL and SDA description for PIC12CE5XX.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The configuration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ du ring port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR up is always on and wake-up on change for this pin is not enabled.

5.2 TRIS Register

The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4-

5. Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indica te that th e pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

, weak pull-

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, ma y be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Note 1: I/O pins have protection diodes to VDD

Note 2: See Table 3-1 for buffer type. Note 3: See Section 7.0 for SCL and SDA

Data Latch

TRIS Latch

Reset

(2)

RD Port

and VSS.

description for PIC12CE5XX

VDD

I/O

(1,3)

 1999 Microchip Technology Inc. DS40139E-page 21

PIC12C5XX

TABLE 5-1: SUMMARY OF PORT REGISTERS

Value on

Power-On

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRIS — — --11 1111 --11 1111 N/A 03H

06h

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

OPTION GPWU STATUS GPIO

(PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A)

GPIO (PIC12CE518/ PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0

q = see tables in Section 8.7 for possible values.

GPWUF

GPPU T0CS T0SE PSA PS2 PS1 PS0

— PAO TO PD Z DC C 0001 1xxx q00q quuu

— — GP5 GP4 GP3 GP2 GP1 GP0

Reset

1111 1111 1111 1111

--xx xxxx --uu uuuu

11xx xxxx 11uu uuuu

Value on

All Other Resets

(1)

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate inter nally as read followed

by write operations. The BCF and BSF instr uc tion s, for example, read the entire port into t he CPU, execute the bit operation and re-write the result. Caution must be used when these ins tructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritte n to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ---------- --------- BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).

5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port ha ppens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cyc le (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

DS40139E-page 22  1999 Microchip Technology Inc.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PIC12C5XX

Instruction

fetched

GP5:GP0

Instruction

executed

Q1 Q2

PC PC + 1 PC + 2

MOVWF GPIO

Q1 Q2

MOVF GPIO,W

MOVWF GPIO

Port pin written here

(Write to

GPIO)

Q1 Q2

NOP

Port pin sampled here

MOVF GPIO,W

(Read

GPIO)

Q1 Q2

PC + 3

NOP

This example shows a write to GPIO followed by a read from GPIO.

Data setup time = (0.25 T

where: T

CY = instruction cycle.

PD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

CY – TPD)

 1999 Microchip Technology Inc. DS40139E-page 23

PIC12C5XX

NOTES:

DS40139E-page 24  1999 Microchip Technology Inc.

PIC12C5XX

6.0 TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0 module.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module wi ll increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can wor k around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

GP2/T0CKI

T0SE

FOSC/4

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS

(1)

Programmable

Prescaler

PS2, PS1, PS0

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clo ck input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled i n software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

Data bus

PSout

(2)

(1)

PSA

Sync with

Internal

Clocks

(2 T

(1)

CY delay)

PSout

Sync

TMR0 reg

 1999 Microchip Technology Inc. DS40139E-page 25

PIC12C5XX

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Executed

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

T0+1 T0+2 NT0 NT0+1 NT0+2

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Execute

Q1 Q2 Q3 Q4

T0 NT0+1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0+1

Write TMR0 executed

Read TMR0 reads NT0

NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0

Power-On

Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION N/A TRIS

Legend: Shaded cells not used by Timer0,

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

—

—GP5GP4 GP3 GP2 GP1 GP0

- = unimplemented, x = unknown, u = unchanged,

--11 1111 --11 1111

Value on All Other

Resets

DS40139E-page 26  1999 Microchip Technology Inc.

PIC12C5XX

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler out put on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2T and low for at least 2T

OSC (and a small RC delay of 20 ns)

OSC (and a small RC delay of

20 ns). Refer to the electrical specification of the desired device.

OSC)

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4T 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time i s that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. F igure 6-4 shows the delay from the external clock edge to the timer incrementing.

6.1.3 OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMER0 from the pin,

the port is forced to an input regardless of the TRIS register setting.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

External Clock Input or Prescaler Output (2)

External Clock/Prescal er Output After Sampling

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(3)

(1)

OSC (and a small RC delay of

Small pulse misses sampling

Increment Timer0 (Q4)

Timer0

Note 1:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

 1999 Microchip Technology Inc. DS40139E-page 27

T0 T0 + 1 T0 + 2

PIC12C5XX

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.6). For simplicity,

this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.

EXAMPLE 6-1: CHANGING PRESCALER

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;T h e s e 3 lines ( 5 , 6 , 7 )

4.OPTION ; are required only if

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the se quen ce s hown in Examp le 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switchin g t he pr es cal e r.

EXAMPLE 6-2: CHANGING PRESCALER

CLRWDT ;Clear WDT and

MOVLW 'xxxx0xxx' ;Select TMR0, new

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

OPTION

(i.e., it can be changed “on the fly” during program execution). To avoid an unintended d evice RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

GP2/T0CKI

M U

Sync

Cycles

(TIMER0→WDT)

; desired

(WDT→TIMER0)

;prescaler

;prescale value and ;clock source

Data Bus

TMR0 reg

T0SE

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40139E-page 2 8  1999 Microchip Technology Inc.

PSA

T0CS

8-bit Prescaler

U X

8 - to - 1MUX

Time-Out

MUX

WDT

PSA

PS2:PS0

PSA

PIC12C5XX

7.0 EEPROM PERIPHERAL OPERATION

This section applies to PIC12CE518 and PIC12CE519 only.

The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 tha t are connected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to th e following functions:

; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our website www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASH5IX.ASM.

It is very important to check the return codes when using these calls, and retry the operation if unsuccessful. Unsuccessful return codes occur when the EE data memory is busy with the previous write, which can take up to 4 mS.

7.0.1 SERIAL DATA

SDA is a bi-directional pin used to transfer addresses and data into and data out of the device.

For normal data transfer SDA is allo wed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

The EEPROM interface is a 2-wire bus protocol consisting of data (SDA) and a clock (SCL). Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the internal EEPROM peripheral. SDA and SCL op eration is also slightly different than GPO-GP5 as listed below.

Namely, to avoid code overhead in modifying the TRIS register, both SDA and SCL are always outputs. To read data from the EEPROM peripheral requires out-

putting a ‘1’ on SDA placing it in high-Z state, where only the internal 100K pull-up is active on the SDA line.

SDA:

Built-in 100K (typical) pull-up to VDD Open-drain (pull-down only) Always an output Outputs a ‘1’ on reset

SCL:

Full CMOS output Always an output Outputs a ‘1’ on reset

The following example requires:

• Code Space: 77 words

• RAM Space: 5 bytes (4 are overlayable)

• Stack Levels:1 (The call to the function itself. The functions do not call any lower level functions.)

• Timing:

- WRITE_BYTE takes 328 cycles

- READ_CURRENT takes 212 cycles

- READ_RANDOM takes 416 cycles.

• IO Pins: 0 (No external IO pins are used)

This code must reside in the lower half of a page. The code achieves it’s small size without additional calls through the use of a sequencing table. The table is a list of procedures that must be called in order. The table uses an ADDWF PCL,F instruction, effectively a computed goto, to sequence to the next procedure. However the ADDWF PCL,F instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page.

 1999 Microchip Technology Inc. DS40139E-page 29

PIC12C5XX

Figure 7-1: Block diagram of GPIO6 (SDA line)

reset

write

Read GPIO

GPIO

databus

Figure 7-2: Block diagram of GPIO7 (SCL line)

ck Q

Output Latch

Input Latch

Schmitt Trigger

ltchpin

VDD

To 24L00 SDA Pad

databus

Read GPIO

write GPIO

ck Q

ltchpin

Schmitt Trigger

VDD

To 24LC00 SCL Pad

DS40139E-page 3 0  1999 Microchip Technology Inc.

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