MICROCHIP PIC10F220, PIC10F222 DATA SHEET

PIC10F220/222

Data Sheet

6-Pin, 8-Bit Flash Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICD EM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC10F220/222

6-Pin, 8-Bit Flash Microcontrollers

Device Included In This Data Sheet

•PIC10F220

•PIC10F222

High-Performance RISC CPU

• Only 33 single-word instructions to learn

• All single-cycle instructions except for program

branches which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 8 special function hardware registers

• Operating speed:

- 500 ns instruction cycle with 8 MHz internal clock

-1μs instruction cycle with 4 MHz internal clock

Special Microcontroller Features

• 4 or 8 MHz precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™) programming capability

• In-Circuit Debugging (ICD) support

• Power-on Reset (PO R)

• Short Device Reset Timer (DRT) – 1.125 ms typical

• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR

• Internal weak pull-ups on I/O pins

• Power-saving Sleep mode

• Wake-up from Sleep on pin change

input pin

Low Power Features/CMOS Technology

• Operating Current:

- < 350 μA @ 2V, 4 MHz

• Standby Current:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

- 100,000 Flash endurance

- > 40 year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features

• 4 I/O pins:

- 3 I/O pins with individual direction control

- 1 input only pin

- High-current sink/source for direct LED drive

- Wake-up on change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

• Analog-to-Digital (A/D) Converter

- 8-bit resolution

- 2 external input channels

- 1 internal input channel dedicated to

conversion of the 0.6V absolute voltage reference

Device

PIC10F220 256 16 4 1 2 PIC10F222 512 23 4 1 2

Program Memory Data Memory

I/O

Flash (words) SRAM (bytes)

Timers

8-bit

8-Bit A/D (ch)

PIC10F220/222

Pin Diagrams

6-Lead SOT -23

8-Lead PDIP

GP0/AN0/ICSPDAT

GP1/AN1/ICSPCLK

N/C

VDD

GP2/T0CKI/F

GP1/AN1/ICSPCLK

OSC4

PIC10F220/222

6 5

8 7 6 5

GP3/MCLR

VDD GP2/T0CKI/FOSC4

GP3/MCLR/VPP VSS

N/C

GP0/AN0/ICSPDAT

/VPP

1 2

1 2 3 4

PIC10F220/222

Table of Contents

1.0 General Description............................................................................ ....... .... .. .... .. .... ...................................................................7

2.0 Device Varieties .......................................................................................................................................................................... 9

3.0 Architectural Overview ...............................................................................................................................................................11

4.0 Memory Organization................................................................................................................................................................. 15

5.0 I/O Port......................................... ..................... ..................... ..................... ............................................................................... 23

6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 27

7.0 Analog-to-Digital (A/D) converter ............................................................................................................................................... 31

8.0 Special Feature s Of The CPU.......... .......................................... ..................... ..................... ...................................................... 35

9.0 Instruction Set Summary............................................................................................................................................................ 45

10.0 Electrical Characteristics............................................................................................................................................................ 53

11.0 Development Support.................................................................................................................................................................63

12.0 DC and AC Characteristics Graphs and Charts.........................................................................................................................67

13.0 Packaging Information. ..................... ..................... ..................... ..................... ........................................................................... 69

Index .................................................................................................................................................................................................... 73

The Microchip Web Site................................... ............................................................. ....................................................................... 75

Customer Change Notification Service ................................................................................................................................................ 75

Customer Support................................................................................................................................................................................ 75

Reader Response................................................................................................................................................................................76

Product Identification System .............................................................................................................................................................. 77

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC10F220/222

NOTES:

PIC10F220/222

1.0 GENERAL DESCRIPTION

The PIC10F220/222 devices, from Microchip Technology, are low-cost, high-performan ce, 8-b it, fully static, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word, single-cycle instructions. All instructions are singlecycle (1 μs @ 4 MHz) except for prog ram branches, which take two cycles. The PIC10F220/222 devices deliver performance in an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typ ical 2:1 co de compre ssion over o ther 8-bi t microcontrollers in i ts class . The easy-to-us e and easyto-remember instr ucti on se t reduc es de velop ment time significantly.

The PIC10F220/222 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Ti mer (DR T) e limin ates the ne ed fo r the externa l Reset circuitry. Internal Oscillator (INTOSC) mode is provided, thereby, preserving the li mi ted num be r of I/O pins available. Power-saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC10F220/222 devices are available in costeffective Flash, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers while benefiting from the Flash programmable flexibility.

The PIC10F220/222 products are supported by a fullfeatured macro assembler, a software simulator, an in-circuit debugger, a C compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM compatible machines.

PC and

1.1 Applications

The PIC10F220/222 devices fit in applications ranging from personal care app li anc es an d s ecu rity s yst ems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make th ese micr ocontroll ers wel l suited for applications with space limitations. Low-cost, lowpower , high-perform ance, ease of use and I/O fl exibility make the PIC10F220/222 devices very versatile, even in areas where no m icrocontroller us e has been con sidered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications).

T ABLE 1-1: PIC10F220/222 DEVICES

Clock Maximum Frequency of Operation (MHz) 8 8 Memory Flash Program Memory 256 512

Data Memory (bytes) 16 23

Peripherals Timer Module(s) TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes Analog Inputs 2 2

Features I/O Pins 3 3

Input Only Pins 1 1 Internal Pull-ups Yes Yes In-Circuit Serial Programming™ Yes Yes Number of Instructions 33 33 Packages 6-pin SOT-23,

Note 1: The PIC10F220/222 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O

current capability and precision internal oscillator.

2: The PIC10F220/222 devices use serial programming with data pin GP0 and clock pin GP1.

(1, 2)

PIC10F220 PIC10F222

8-pin PDIP

6-pin SOT-23,

8-pin PDIP

PIC10F220/222

NOTES:

2.0 DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in th is section. Wh en placing orde rs, please use the PIC10F220/222 Product Identification System at the back of this data s heet to s pecify the correct p art number.

2.1 Quick Turn Programming (QTP) Devices

Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your loc al Microchi p Technology sales office for more details.

PIC10F220/222

2.2 Serialized Quick Turn Programming

Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.

(SQTPSM) Devices

PIC10F220/222

NOTES:

PIC10F220/222

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC10F220/222 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC10F220/222 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetch ed on the sa me bu s. Separating program and data memor y further allow s instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bit s wide, making it p ossible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1 μs @ 4 MHz or 500 ns @ 8 MHz) except for program branches.

The table belo w lists p rogram me mory (Flash) and data memory (RAM) for the PIC10F220/222 devices.

Memory

Device

Program Data

PIC10F220 256 x 12 16 x 8 PIC10F222 512 x 12 23 x 8

The PIC10F220/222 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It perfor ms arithmetic a nd Boolean fun ctions between data in the working register and any register file.

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typically the W (Working) register. The other operand is either a file register or an immediate constant. In sing le ope ran d inst ruction s, the operan d is either the W register or a file register.

The W register is an 8-bit workin g register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the ST ATUS register . The C and DC bits operate as B tively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1 with the corresponding device pins described in Table 3-1.

orrow and Digit borrow out bits, respec-

The PIC10F220/222 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the Program Counter (PC), are mapped in the data memory. The PIC10F220/222 devices have a highly orthogonal (symmetrica l) instruct ion set that m akes it possib le to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situ ations” make programm ing with the PIC10F220/222 devices simple yet efficient. In addition, the learning curve is reduced significantly.

PIC10F220/222

FIGURE 3-1: BLOCK DIAGRAM

9-10

Program Counter

STACK1 STACK2

Direct Addr

Program

Bus

Flash

512 x 12 or 256 x 12

Program

Memory

Instruction reg

RAM Addr

Data Bus

RAM

23 or 16

bytes

File

Registers

Addr MUX

5-7

FSR reg

Indirect

Addr

GPIO

GP0/AN0/ICSPDAT GP1/AN1/ICSPCLK GP2/T0CKI/FOSC4 GP3/MCLR/VPP

STATUS reg

ALU

W reg

Timer0

MUX

ADC

Absolute Voltage Reference

AN0

AN1

Instruction

Decode and

Control

Timing

Generation

MCLR

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Internal RC

Clock

VDD, VSS

TABLE 3-1: PINOUT DESCRIPTION

Name Function

Input

Type

GP0/AN0/ICSPDAT GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak

AN0 AN — Analog Input.

ICSPDAT ST CMOS In-Circuit Programming data.

GP1/AN1/ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak

AN1 AN — Analog Input.

ICSPCLK ST CMOS In-Circuit Programming clock.

GP2/T0CKI/FOSC4 GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

OSC4 — CMOS Oscillator/4 output.

GP3/MCLR

/VPP GP3 TTL — Input pin. Can be software programmed for internal weak pull-up and

MCLR

PP HV — Programming voltage input.

DD VDD P — Positive supply for logic and I/O pins.

V V

SS VSS P — Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, AN = Analog Input

Output

Type

Description

pull-up and wake-up from Sleep on pin change.

wake-up from Sleep on pin change.

ST — Master Clear (Reset). When configured as MC LR, this pin is an

active-low Reset to the device. Voltage on MCLR exceed V

DD during normal device operation or the device will enter

/VPP must not

Programming mode. Weak pull-up is always on if configured as MCLR

PIC10F220/222

3.1 Clocking Scheme/Instruction Cycle

The clock is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1, and the instruction is fetched from program memory and latched into the Instru ction Regis ter (IR) in Q4. It is decoded and executed during Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

3.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g ., GOTO), t hen two c yc le s are required to complete the ins tructi on (Exampl e 3-1).

A fetch cycle begins with the PC incrementing in Q1. In the execution cy cle, the fetch ed instruction i s latched

into the Instr uction Regist er in cycle Q1. Th is instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

PC + 1 PC + 2

Q2 Q3 Q4

Internal Phase Clock

Fetch INST (PC)

Execute INST (PC - 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

4. BSF GPIO, BIT1

All instructions are si ngle cycle, except for any program bra nches. These tak e two cycles, since th e fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC10F220/222

NOTES:

PIC10F220/222

4.0 MEMORY ORGANIZATION

The PIC10F220/222 memories are organized into program memory and data memory. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization for the PIC10F220

The PIC10F220 devices hav e a 9-bit Prog ram Coun ter (PC) capable of addressing a 512 x 12 program memory space.

Only the first 256 x 12 (0000h-00FFh) for the PIC10F220 are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wraparound within the first 256 x 12 space (PIC10F220). The effective Reset vector is at 0000h, (see Figure 4-1). Location 00FF h (PIC10F220) contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC10F220

PC<7:0>

CALL, RETLW

Stack Level 1 Stack Level 2

<8:0>

4.2 Program Memory Organization for the PIC10F222

The PIC10F222 devices have a 10-bit Program Counter (PC) capable of addressing a 1024 x 12 program memory space.

Only the first 512 x 12 (0000h-01FFh) for the MemHigh are physically implemented (see Figure 4-2). Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC10F222). The effective Reset vector is at 0000h (see Figure 4-2). Location 01FFh (PIC10F222) contains the internal clock oscillator calibration value. This value should never be overwritt en.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC10F222

<9:0>

0000h

CALL, RETLW

PC<8:0>

Stack Level 1 Stack Level 2

Reset Vector

On-Chip Program

Memory

(1)

Reset Vector

On-chip Program

Memory

Space

User Memory

256 Word

Note 1: Address 0000h becomes the

effective Reset vector. Location 00FFh contains the MOVLW xx internal oscillator calibration value.

(1)

0000h

00FFh 0100h

01FFh

Space

User Memory

512 Words

Note 1: Address 0000h becomes the effective

Reset vector. Location 01FFh contains the MOVLW xx internal oscillator calibration value.

01FFh 0200h

02FFh

PIC10F220/222

4.3 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, d ata memory for a device is sp ec ifie d by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Reg ist ers incl ude the TM R0 register, the Program Counter (PC), the STATUS register, the I/O register (GPIO) and the File Select Register (FSR). In addition, Speci al Function Registe rs are used to control the I/O port configuration and prescaler options.

The General Purpose Registers are used for data and control information under com mand of the instructions .

For the PIC10F220, the register file is composed of 9 Special Function Registers and 16 General Purpose Registers (Figure 4-3, Figure 4-4).

For the PIC10F222, the register file is composed of 9 Special Function Registers and 23 General Purpose Registers (Figure 4-4).

4.3.1 GENERAL PURPOSE REGISTER FILE

The General Purpos e Registe r file i s accessed , eithe r directly o r indirectly, through the F ile Select Regist er (FSR). See Section 4.9 “Indirect Data Addressing;

INDF and FSR Registers”.

FIGURE 4-4: PIC10F222 REGISTER

FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing; INDF and FSR Registers”.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

ADCON0

ADRES

General Purpose Registers

FIGURE 4-3: PIC10F220 REGIST E R

FILE MAP

File Address

(1)

00h 01h 02h 03h 04h 05h 06h 07h

08h 09h

0Fh 10h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing; INDF and FSR Registers”.

2: Unimplemented, read as 00h.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

ADCON0

ADRES

Unimplemented

General Purpose Registers

(2)

PIC10F220/222

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and per ipheral functio ns to con trol the operation of the device (Table 4-1).

The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 27 02h PCL

03h STATUS GPWUF 04h FSR Indirect Data Memory Address Pointer 111x xxxx 22 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 20 06h GPIO

07h ADCON0 ANS1 ANS0 08h ADRES Result of Analog-to-Digital Conversion xxxx xxxx 32 N/A TRISGPIO

N/A OPTION GPWU

Legend: — = unimplemented, read as ‘0’, x = unknown, u = unchanged. Note 1: The upper byte of the Program Counter is not directly accessible. See S ecti on 4.7 “Program Counter” for an

(1)

Low-Order 8 bits of PC 1111 1111 21

— —TOPD ZDCC0--1 1xxx

— — — — GP3 GP2 GP1 GP0 ---- xxxx 23

— — CHS1 CHS0 GO/DONE ADON 11-- 1100 32

— — — — I/O Control Register ---- 1111 23

GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19

explanation of how to access these bits.

2: Other (non power-up) Resets include external Reset through MCLR

Reset.

3: See Table8-1 for other Reset specific values.

, Watchdog Timer and wake-up on pin change

Value on

Power-on

(2)

Reset

Page #

(3)

PIC10F220/222

4.4 STATUS Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as the destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. The se in structions do not affect the Z, DC or C bits from the ST A TUS reg ister . For other instructio ns, which do affect STATUS bits, see Section 9.0 “Instruction

Set Summary”.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF

bit 7 bit 0

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6-5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products. bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Bo

bit 0 C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry to the 4th low-order bit of the result occurred 0 = A carry to the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

ADDWF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

: SUBWF: RRF or RLF:

— —TO PD ZDCC

rrow bit (for ADDWF and SUBWF instructions)

bit (for ADDWF, SUBWF and RRF, RLF instructions)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

4.5 OPTION Register

The OPTION re gister is a 8-bit wid e, write-only register , which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

The OPTION register is not memory mapped and is therefore only addressable by executing the OPTION instruction. The cont ent s of the W re gister w ill be tran sferred to the OPTION register. A Reset sets the OPTION<7:0> bits.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit 7 bit 0

GPPU T0CS T0SE PSA PS2 PS1 PS0

PIC10F220/222

Note 1: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU GPWU)

2: If the T0CS bit is set to ‘1’, it w i ll ov er r ide

the TRIS function on the T0CKI pin.

and

bit 7 GPWU

bit 6 GPPU

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, F

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

OSC/4

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC10F220/222

4.6 OSCCAL Register

The Oscillator Calibrati on (OSCCAL) register is used to calibrate the internal precision 4/8 MHz oscillator. It contains seven bit s for cal ibra tio n

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.

After you move in the calibration constant, do not change the value. See Section 8.2.2 “Internal 4/8 MHz

Oscillator”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

bit 7 bit 0

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 =Maximum frequency

•

0000001 0000000 =Center frequency

1111111

•

• 1000000 =Minimum frequency

bit 0 FOSC4: INTOSC/4 Output Enab le bit

1 = INTOSC/4 output onto GP2 0 = GP2/T0CKI/COUT applied to GP2

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4

(1)

Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC10F220/222

4.7 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO inst ruction word . The PC Latch (P CL) is mapped to PC<7:0>.

For a CALL instruction, or any instruction where the PCL is the destinatio n, bits 7:0 of the PC ag ain are pr ovided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-5).

Instructions wh ere the PCL is th e destinatio n, or modif y PCL instructi ons, incl ude MOVWF PC, ADDWF PC and BSF PC, 5.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instructi on, all subroutine calls or computed jumps are limited to the first 256 locations of any program me mory page ( 512 words long).

FIGURE 4-5: LOADING OF PC

BRANCH INSTRUCTIONS

GOTO Instruction

87 0

Instruction Word

PCL

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in program memory (i.e., the oscillator calibration instruction). After executing MOVLW xx, the PC will roll over to location 0000h and begin executing user code.

4.8 Stack

The PIC10F220 device has a 2-deep, 8-bit wide hardware PUSH/POP stack.

The PIC10F222 device has a 2-deep, 9-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of stack 1 into stack 2 and then PUSH the current PC value, incremented by one, into stack level 1. If more than two sequential CALLs are exec uted, onl y the most recent two return addresses are stored.

A RETLW instruction will POP the contents of stack level 1 into the PC an d then copy st ack l evel 2 cont ent s into level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in level 2.

Note 1: The W register will be loaded with the lit-

eral value spec ified in the ins truction. This is particularly useful for the implementation of data look-up tables within the program memory.

2: There are no Status bits to indicate stack

overflows or stack underflow conditions.

3: There are no instructions mnemonics

called PUSH or POP. These are actions that occur from the e xecution of the CALL and RETLW instructions.

CALL or Modify PCL Instruction

87 0

Reset to ‘0’

PCL

Instruction Word

PIC10F220/222

4.9 Indirect Data Addressing; INDF

and FSR Registers

The INDF register is not a physi cal register. Addressing INDF actually address es the reg ister whos e addres s is contained in the FSR regis ter (FSR is a pointer). This is Indirect A ddressing mode.

4.9.1 INDIRECT ADDRESSING

• Register file 09 contains the value 10h.

• Register file 0A contains the value 0Ah.

• Load the value 09 into the FSR register.

• A read of the INDF register will return the value

of 10h.

• Increment the value of the FSR register by one

(FSR = 0A).

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using Indirect Addressing is shown in Example 4-1.

FIGURE 4-6: DIRECT/INDIRECT ADDRESSING

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF

;register INCF FSR, F ;inc pointer BTFSC FSR, 4 ;all done? GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue :

The FSR is a 5-bit wide register. It is used in conjunction with the INDF regis ter to indirectly a ddress the dat a memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

Note: The 10F220 and 10F222 do not use

banking. FSR<7:5> are unimplemented and read as ‘1’s.

Direct Addressing

(opcode) 04

Location Select

00h

Data Memory

Note 1: For register map detail, see Section 4.3 “D ata Memory Organization”.

0Fh

(1)

10h

1Fh

Bank 0

Indirect Addressing

(FSR)

Location Select

PIC10F220/222

5.0 I/O PORT

As with any other register, the I/O register(s) can be written and read under pro gram contro l. However, read instructions (e.g., MOVF GPIO, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low-order 4 bits are used (GP<3:0>). Bits 7 through 4 are unimplemented and read as ‘0’s. Please note that GP3 is an input only pin. Pins GP0, GP1 and GP3 can be configured with weak pull-ups and also for wake-up on change. The wake-up on change and weak pull-up functions are not individu al ly pin sele ct able. If GP3/MCLR be enabled via the Configuration Word. Configuring GP3 as MCLR function for this pin.

5.2 TRIS Registers

The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bi t puts the corresponding output driver in a high-impe dance mod e. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the outp ut buffer. The exceptions are GP3, which is input only, and the GP2/T0CKI/FOSC4 pin, which may be controlled by various registers. See Table5-1.

Note: A read of the ports reads the pins, not the

is configured as MCLR, a weak pull-up can

disables the wake-up on change

output data latches. That is, if an output driver on a pin is enab led and driv en high, but the external system is holding it low, a read of the port will indicate that the pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon Re se t.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-5. All port pins, except GP3, which is input only , ma y be used for both in put and out put operati ons. For input operations , the se ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged unt il t he outp ut latc h is rewri tten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Note 1: See Table 3-1 for buffer type.

Data Latch

TRIS Latch

Reset

VDD

RD Port

(1)

I/O pin

VSS

TABLE 5-1: ORDER OF PRECEDENCE FOR PIN FUNCTIONS

Priority GP0 GP1 GP2 GP3

1 AN0 AN1 FOSC4 I/MCLR 2 TRIS GPIO TRIS GPIO T0CKI — 3

— — TRIS GPIO —

TABLE 5-2: REQUIREMENTS TO MAKE PINS AVAILABLE IN DIGITAL MODE

FOSC4 T0CS ANS1 ANS0 MCLR E

Register OSCCAL OPTION ADCON0 ADCON0 CONFIG GP0 GP1 GP2 00 GP3 Legend: — = Condition of bit will have no effect on the setting of the pin to digital mode.

— — — 0 — — — 0 — —

— — —

— — — — 0

PIC10F220/222

)

FIGURE 5-2: BLOCK DIAGRAM OF GP0

AND GP1

GPPU

Data Bus

WR Port

W Reg

TRIS ‘f’

Data Latch

TRIS Latch

Reset

Analog Enable

I/O Pin

FIGURE 5-3: BLOCK DIAGRAM OF GP2

Data Bus

WR Port

W Reg

TRIS ‘f’

Note 1: I/O pins have protection diodes to VDD and

Data Latch

TRIS Latch

Reset

SS.

T0CS

RD Port

FOSC4

OSC Fuse

T0CKI

I/O Pin

(1)

RD Port

Mismatch

ADC

Note 1: I/O pins have protection diodes to VDD and

SS.

FIGURE 5-4: BLOCK DIAGRAM OF GP3

GPPU

MCLRE

Reset

I/O Pin

Data Bus

RD Port

Mismatch

Note 1: GP3/MCLR pin has a protection diode to VSS

only.

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