MICROCHIP PIC10F200 DATA SHEET

查询PIC10F206-E/MC供应商

PIC10F200/202/204/206

Data Sheet

6-Pin, 8-bit Flash Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC® DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

code hopping devices, Serial

PIC10F200/202/204/206

6-Pin, 8-Bit Flash Microcontrollers

Devices Included In This Data Sheet:

• PIC10F200 • PIC10F204

• PIC10F202 • PIC10F206

High-Performance RISC CPU:

• Only 33 single-word instructions to learn

• All single-cycle instructions except for program

branches, which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 8 Special Function Hardware registers

• Operating speed:

- 4 MHz internal clock

-1μs instruction cycle

Special Microcontroller Features:

• 4 MHz precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with dedicated on-chip

RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR

• Internal weak pull-ups on I/O pins

• Power-Saving Sleep mode

• Wake-up from Sleep on pin change

input pin

Low-Power Features/CMOS Technology:

• Operating Current:

- < 175 μA @ 2V, 4 MHz, typical

• Standby Current:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

- 100,000 Flash endurance

- > 40 year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features (PIC10F200/202):

• 4 I/O pins:

- 3 I/O pins with individual direction control

- 1 input-only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

Peripheral Features (PIC10F204/206):

• 4 I/O pins:

- 3 I/O pins with individual direction control

- 1 input-only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

• 1 Comparator:

- Internal absolute voltage reference

- Both comparator inputs visible externally

- Comparator output visible externally

TABLE 1-1: PIC10F20X MEMORY AND FEATURES

Device

PIC10F200 256 16 4 1 0

PIC10F202 512 24 4 1 0

PIC10F204 256 16 4 1 1

PIC10F206 512 24 4 1 1

Program Memory Data Memory

I/O

Flash (words) SRAM (bytes)

Timers

8-bit

Comparator

PIC10F200/202/204/206

SOT-23 Pin Diagrams

8-Pin PDIP Pin Diagrams

GP2/T0CKI/FOSC4

GP2/T0CKI/COUT/FOSC4

GP1/ICSPCLK/CIN-

GP0/ICSPDAT

GP1/ICSPCLK

GP0/ICSPDAT/CIN+

GP1/ICSPCLK/CIN-

N/C

VDD

GP1/ICSPCLK

N/C

VDD

PIC10F200/202

PIC10F204/206

PIC10F200/202

PIC10F204/206

GP3/MCLR

VDD

GP2/T0CKI/FOSC4

GP3/MCLR

VDD

GP2/T0CKI/COUT/FOSC4

/VPP

GP3/MCLR/VPP

VSS

N/C

GP0/ICSPDAT

GP3/MCLR/VPP

VSS

N/C

GP0/ICSPDAT/CIN+

8-Pin DFN Pin Diagrams

GP2/T0CKI/FOSC4

GP2/T0CKI/COUT/FOSC4

GP1/ICSPCLK/CIN-

N/C

VDD

GP1/ICSPCLK

N/C

VDD

PIC10F200/202

PIC10F204/206

GP3/MCLR/VPP

VSS

N/C

GP0/ICSPDAT

GP3/MCLR/VPP

VSS

N/C

GP0/ICSPDAT/CIN+

PIC10F200/202/204/206

Table of Contents

1.0 General Description...................................................................................................................................................................... 5

2.0 PIC10F200/202/204/206 Device Varieties .................................................................................................................................. 7

3.0 Architectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization ................................................................................................................................................................. 15

5.0 I/O Port....................................................................................................................................................................................... 25

6.0 Timer0 Module and TMR0 Register (PIC10F200/202)............................................................................................................... 29

7.0 Timer0 Module and TMR0 Register (PIC10F204/206)............................................................................................................... 33

8.0 Comparator Module.................................................................................................................................................................... 37

9.0 Special Features of the CPU...................................................................................................................................................... 41

10.0 Instruction Set Summary............................................................................................................................................................ 51

11.0 Development Support................................................................................................................................................................. 59

12.0 Electrical Characteristics............................................................................................................................................................ 63

13.0 DC and AC Characteristics Graphs and Tables......................................................................................................................... 73

14.0 Packaging Information................................................................................................................................................................ 81

Index .................................................................................................................................................................................................... 89

The Microchip Web Site....................................................................................................................................................................... 91

Customer Change Notification Service ................................................................................................................................................ 91

Customer Support ................................................................................................................................................................................ 91

Reader Response ................................................................................................................................................................................ 92

Product Identification System .............................................................................................................................................................. 93

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Most Current Data Sheet

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Customer Notification System

PIC10F200/202/204/206

NOTES:

PIC10F200/202/204/206

1.0 GENERAL DESCRIPTION

The PIC10F200/202/204/206 devices from Microchip Technology are low-cost, high-performance, 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (1 μs) except for program branches, which take two cycles. The PIC10F200/202/204/206 devices deliver performance in an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly.

The PIC10F200/202/204/206 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. INTRC Internal Oscillator mode is provided, thereby preserving the limited number of I/O available. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC10F200/202/204/206 devices are available in cost-effective Flash, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility.

The PIC10F200/202/204/206 products are supported by a full-featured macro assembler, a software simulator, an in-circuit debugger, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM compatible machines.

PC and

1.1 Applications

The PIC10F200/202/204/206 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make these microcontrollers well suited for applications with space limitations. Low cost, low power, high performance, ease-of-use and I/O flexibility make the PIC10F200/202/204/206 devices very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications).

TABLE 1-1: PIC10F200/202/204/206 DEVICES

PIC10F200 PIC10F202 PIC10F204 PIC10F206

Clock Maximum Frequency of Operation (MHz) 4 4 4 4

Memory Flash Program Memory 256 512 256 512

Data Memory (bytes) 16 24 16 24

Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes Yes Yes

Comparators 0 0 1 1

Features I/O Pins 3 3 3 3

Input-Only Pins 1 1 1 1

Internal Pull-ups Yes Yes Yes Yes

In-Circuit Serial Programming™ Yes Yes Yes Yes

Number of Instructions 33 33 33 33

Packages 6-pin SOT-23

8-pin PDIP, DFN

The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC10F200/202/204/206 device uses serial programming with data pin GP0 and clock pin GP1.

6-pin SOT-23

8-pin PDIP, DFN

6-pin SOT-23

8-pin PDIP, DFN

6-pin SOT-23

8-pin PDIP, DFN

PIC10F200/202/204/206

NOTES:

PIC10F200/202/204/206

2.0 PIC10F200/202/204/206 DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC10F200/202/204/206 Product Identification System at the back of this data sheet to specify the correct part number.

2.1 Quick Turn Programming (QTP) Devices

Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.

2.2 Serialized Quick Turn Programming

Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.

(SQTPSM) Devices

PIC10F200/202/204/206

NOTES:

PIC10F200/202/204/206

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC10F200/202/204/206 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC10F200/202/204/206 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1 μs @ 4 MHz) except for program branches.

The table below lists program memory (Flash) and data memory (RAM) for the PIC10F200/202/204/206 devices.

TABLE 3-1: PIC10F2XX MEMORY

Memory

Device

Program Data

PIC10F200 256 x 12 16 x 8

PIC10F202 512 x 12 24 x 8

PIC10F204 256 x 12 16 x 8

PIC10F206 512 x 12 24 x 8

The PIC10F200/202/204/206 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow tively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1 and Figure 3-2, with the corresponding device pins described in Table 3-2.

and digit borrow out bit, respec-

The PIC10F200/202/204/206 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC10F200/202/ 204/206 devices have a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC10F200/202/204/206 devices simple, yet efficient. In addition, the learning curve is reduced significantly.

PIC10F200/202/204/206

FIGURE 3-1: PIC10F200/202 BLOCK DIAGRAM

Program

Bus

Flash

512 x12 or

256 x12

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

9-10

Program Counter

Direct Addr

Device Reset

Power-on

Watchdog

Internal RC

MCLR

Stack 1

Stack 2

Timer

Reset

Timer

Clock

VDD, VSS

RAM Addr

Data Bus

RAM

24 or 16

bytes

File

Registers

Addr MUX

ALU

W Reg

Indirect

5-7

Addr

FSR Reg

STATUS Reg

MUX

Timer0

GPIO

GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI/FOSC4 GP3/MCLR/VPP

PIC10F200/202/204/206

FIGURE 3-2: PIC10F204/206 BLOCK DIAGRAM

Program

Bus

Flash

512 x12 or

256 x12

Program

Memory

Instruction Reg

Instruction

Decode &

Control

Timing

Generation

9-10

Program Counter

Direct Addr

Device Reset

Power-on

Watchdog

Internal RC

MCLR

Stack 1

Stack 2

Timer

Reset

Timer

Clock

VDD, VSS

RAM Addr

Data Bus

RAM

24 or 16

bytes

File

Registers

Addr MUX

ALU

W Reg

Indirect

5-7

Addr

FSR Reg

STATUS Reg

MUX

Timer0

GPIO

Comparator

GP0/ICSPDAT/CIN+ GP1/ICSPCLK/CINGP2/T0CKI/COUT/FOSC4 GP3/MCLR/VPP

CIN+

CIN-

COUT

PIC10F200/202/204/206

TABLE 3-2: PIC10F200/202/204/206 PINOUT DESCRIPTION

Name Function

GP0/ICSPDAT/CIN+ GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal

ICSPDAT ST CMOS In-Circuit Serial Programming

CIN+ AN — Comparator input (PIC10F204/206 only).

GP1/ICSPCLK/CIN- GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

CIN- AN — Comparator input (PIC10F204/206 only).

GP2/T0CKI/COUT/ FOSC4

GP3/MCLR

VDD VDD P — Positive supply for logic and I/O pins.

SS VSS P — Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

/VPP GP3 TTL — Input pin. Can be software programmed for internal weak

ST = Schmitt Trigger input, AN = Analog input

GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

COUT — CMOS Comparator output (PIC10F204/206 only).

FOSC4 — CMOS Oscillator/4 output.

MCLR

VPP HV — Programming voltage input.

Input

Type

Output

Typ e

weak pull-up and wake-up from Sleep on pin change.

pull-up and wake-up from Sleep on pin change.

ST — Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on GP3/MCLR must not exceed V device will enter Programming mode. Weak pull-up always on if configured as MCLR.

Description

™

data pin.

/VPP

DD during normal device operation or the

PIC10F200/202/204/206

3.1 Clocking Scheme/Instruction Cycle

The clock is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3 and Example 3-1.

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

PC PC PC + 1 PC + 2

3.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Internal

phase clock

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

4. BSF GPIO, BIT1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC10F200/202/204/206

NOTES:

PIC10F200/202/204/206

4.0 MEMORY ORGANIZATION

The PIC10F200/202/204/206 memories are organized into program memory and data memory. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization for the PIC10F200/204

The PIC10F200/204 devices have a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space.

Only the first 256 x 12 (0000h-00FFh) for the PIC10F200/204 are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wraparound within the first 256 x 12 space (PIC10F200/204). The effective Reset vector is at 0000h (see Figure 4-1). Location 00FFh (PIC10F200/204) contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC10F200/204

PC<7:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

On-chip Program

Memory

Space

User Memory

256 Word

(1)

0000h

00FFh 0100h

Note 1: Address 0000h becomes the

effective Reset vector. Location 00FFh contains the MOVLW XX internal oscillator calibration value.

01FFh

PIC10F200/202/204/206

4.2 Program Memory Organization for the PIC10F202/206

The PIC10F202/206 devices have a 10-bit Program Counter (PC) capable of addressing a 1024 x 12 program memory space.

Only the first 512 x 12 (0000h-01FFh) for the PIC10F202/206 are physically implemented (see Figure 4-2). Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC10F202/206). The effective Reset vector is at 0000h (see Figure 4-2). Location 01FFh (PIC10F202/206) contains the internal clock oscillator calibration value. This value should never be overwritten.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC10F202/206

PC<8:0>

CALL, RETLW

Stack Level 1 Stack Level 2

Reset Vector

On-chip Program

Memory

(1)

0000h

4.3 Data Memory Organization

Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).

The Special Function Registers include the TMR0 register, the Program Counter (PCL), the STATUS register, the I/O register (GPIO) and the File Select Register (FSR). In addition, Special Function Registers are used to control the I/O port configuration and prescaler options.

The General Purpose registers are used for data and control information under command of the instructions.

For the PIC10F200/204, the register file is composed of 7 Special Function registers and 16 General Purpose registers (see Figure 4-3 and Figure 4-4).

For the PIC10F202/206, the register file is composed of 8 Special Function registers and 24 General Purpose registers (see Figure 4-4).

4.3.1 GENERAL PURPOSE REGISTER FILE

The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

Space

User Memory

512 Words

Note 1: Address 0000h becomes the

effective Reset vector. Location 01FFh contains the MOVLW XX internal oscillator calibration value.

01FFh 0200h

02FFh

PIC10F200/202/204/206

FIGURE 4-3: PIC10F200/204 REGISTER

FILE MAP

File Address

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

2: PIC10F204 only. Unimplemented on the

PIC10F200 and reads as 00h.

3: Unimplemented, read as 00h.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General Purpose

(2)

CMCON0

Unimplemented

Registers

(3)

FIGURE 4-4: PIC10F202/206 REGISTER

FILE MAP

File Address

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR Registers”.

2: PIC10F206 only. Unimplemented on the

PIC10F202 and reads as 00h.

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

CMCON0

General

Purpose

Registers

(2)

PIC10F200/202/204/206

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1).

The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 23

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 29, 33

(1)

02h

03h STATUS GPWUF CWUF

04h FSR Indirect Data Memory Address Pointer 111x xxxx 23

05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 21

06h GPIO

07h

N/A TRISGPIO

N/A OPTION GPWU

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an

PCL Low-order 8 bits of PC 1111 1111 22

(5)

—TOPD ZDCC00-1 1xxx

— — — — GP3 GP2 GP1 GP0 ---- xxxx 25

(4)

CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 34

— — — — I/O Control Register ---- 1111 37

GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20

explanation of how to access these bits.

2: Other (non Power-up) Resets include external Reset through MCLR

Reset.

3: See Table 9-1 for other Reset specific values. 4: PIC10F204/206 only. 5: PIC10F204/206 only. On all other devices, this bit is reserved and should not be used.

, Watchdog Timer and wake-up on pin change

Value on

Power-On

(2)

Reset

(3)

Page #

PIC10F200/202/204/206

4.4 STATUS Register

This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 10.0 “Instruction

Set Summary”.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF CWUF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset

bit 6 CWUF: Comparator Wake-up on Change Flag bit

1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset conditions.

bit 5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products.

bit 4 TO

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow

ADDWF

1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred

bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred

(1)

: Time-out bit

: SUBWF: RRF or RLF:

—TOPD ZDCC

(1)

bit (for ADDWF and SUBWF instructions)

Note 1: This bit is used on the PIC10F204/206. For code compatibility do not use this bit on the PIC10F200/202.

PIC10F200/202/204/206

4.5 OPTION Register

The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

GPPU T0CS T0SE PSA PS2 PS1 PS0

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU

Note: If the T0CS bit is set to ‘1’, it will override

the TRIS function on the T0CKI pin.

and GPWU).

bit 7 GPWU

bit 6 GPPU

bit 5 T0CS: Timer0 Clock Source Select bit

bit 4 T0SE: Timer0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, F

1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

OSC/4

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

PIC10F200/202/204/206

4.6 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bits for calibration

Note: Erasing the device will also erase the pre-

programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.

After you move in the calibration constant, do not change the value. See Section 9.2.2 “Internal 4 MHz

Oscillator”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 = Maximum frequency

•

0000001 0000000 = Center frequency 1111111

•

• 1000000 =Minimum frequency

(1)

bit 0 FOSC4: INTOSC/4 Output Enable bit

1 = INTOSC/4 output onto GP2 0 = GP2/T0CKI/COUT applied to GP2

Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.

PIC10F200/202/204/206

4.7 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter Low (PCL) is mapped to PC<7:0>.

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-5).

Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PC, ADDWF PC and

BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

FIGURE 4-5: LOADING OF PC

BRANCH INSTRUCTIONS

GOTO Instruction

87 0

PCL

Instruction Word

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC addresses the last location in program memory (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 0000h and begin executing user code.

4.8 Stack

The PIC10F200/204 devices have a 2-deep, 8-bit wide hardware PUSH/POP stack.

The PIC10F202/206 devices have a 2-deep, 9-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored.

A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2.

Note 1: The W register will be loaded with the lit-

eral value specified in the instruction. This is particularly useful for the implementation of the data look-up tables within the program memory.

2: There are no Status bits to indicate stack

overflows or stack underflow conditions.

3: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions.

CALL or Modify PCL Instruction

87 0

Reset to ‘0’

PCL

Instruction Word

PIC10F200/202/204/206

4.9 Indirect Data Addressing: INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

4.10 Indirect Addressing

• Register file 09 contains the value 10h

• Register file 0A contains the value 0Ah

• Load the value 09 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 0A)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF

;register INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue :

The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

Note: PIC10F200/202/204/206 – Do not use

banking. FSR <7:5> are unimplemented and read as ‘1’s.

FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206)

Direct Addressing

(opcode) 04

Location Select

00h

Data Memory

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

0Fh

(1)

10h

1Fh

Bank 0

Indirect Addressing

(FSR)

Location Select

PIC10F200/202/204/206

NOTES:

PIC10F200/202/204/206

5.0 I/O PORT

As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF GPIO, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low-order 4 bits are used (GP<3:0>). Bits 7 through 4 are unimplemented and read as ‘0’s. Please note that GP3 is an input-only pin. Pins GP0, GP1 and GP3 can be configured with weak pull-ups and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If GP3/MCLR ured as MCLR

, weak pull-up is always on and wake-up

on change for this pin is not enabled.

5.2 TRIS Registers

The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3, which is input-only and the GP2/T0CKI/ COUT/FOSC4 pin, which may be controlled by various registers. See Table 5-1.

is config-

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is inputonly, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.

FIGURE 5-1: PIC10F200/202/204/206

EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Data Latch

TRIS Latch

VDD

VSS

I/O pin

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon Reset.

TABLE 5-1: ORDER OF PRECEDENCE

FOR PIN FUNCTIONS

Priority GP0 GP1 GP2 GP3

1 CIN+ CIN- FOSC4 I/MCLR

2 TRIS GPIO TRIS GPIO COUT —

— —T0CKI—

— —TRIS GPIO—

Reset

Note 1: See Table 3-2 for buffer type.

(1)

RD Port

PIC10F200/202/204/206

TABLE 5-2: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRISGPIO

N/A OPTION GPWU

03h STATUS GPWUF CWUF

06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu

Legend: Shaded cells are not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u =

unchanged, q = depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

2: If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.

— — — — I/O Control Register

GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111

— TO PD Z DC C 00-1 1xxx

Value on

Power-On

Reset

---- 1111

Value on

All Other Resets

---- 1111

1111 1111

qq-q quuu

(1), (2)

5.4 I/O Programming Considerations

5.4.1 BIDIRECTIONAL I/O PORTS

Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and rewrite the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 2 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit 2 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit 0), and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired OR”, “wired AND”). The resulting high output currents may damage the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial GPIO Settings ;GPIO<3:2> Inputs ;GPIO<1:0> Outputs ; ; GPIO latch GPIO pins ; ---------- ----------

BCF GPIO, 1 ;---- pp01 ---- pp11 BCF GPIO, 0 ;---- pp10 ---- pp11 MOVLW 007h; TRIS GPIO ;---- pp10 ---- pp11

;

Note 1: The user may have expected the pin val-

ues to be

GP1 to be latched as the pin value (High).

---- pp00. The 2nd BCF caused

5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

PIC10F200/202/204/206

FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetched

GP<2:0>

Instruction

Executed

PC PC + 1 PC + 2

MOVWF GPIO NOP

Port pin written here

MOVWF GPIO

(Write to GPIO)

Port pin sampled here

(Read GPIO)

PC + 3

NOPMOVF GPIO, W

NOPMOVF GPIO,W

This example shows a write to GPIO followed by a read from GPIO.

Data setup time = (0.25 T

where: T

CY = instruction cycle

PD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

CY – TPD)

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