MICROCHIP MCP6V06, MCP6V07, MCP6V08 Technical data

MCP6V06/7/8

VIN+

V

IN

–

V

SS

V

DD

V

OUT

1
2
3

4

8
7
6

5

NC

NCNC

V

INA

+

V

INA

–

V

SS

1
2
3
4

8
7
6
5

V

OUTA

V

DD

V

OUTB

V

INB

–

V

INB

+

MCP6V06

SOIC

MCP6V07

SOIC

VIN+

V

IN

–

V

SS

V

DD

V

OUT

1
2
3

4

8
7
6

5

NC

CS

NC

MCP6V08

SOIC

V

INA

+

V

INA

–

V

SS

1
2
3
4

8
7
6
5

V

OUTA

V

DD

V

OUTB

V

INB

–

V

INB

+

MCP6V07

4×4 DFN

Offset Voltage Correction for Power Driver

MCP6V06

C

2

R

2

R

1

R

3

MCP6XXX

VDD/2

3kΩ

V

IN

V

OUT

R

2

300 µA, Auto-Zeroed Op Amps

Features

• High DC Precision:

-VOS Drift: ±50 nV/°C (maximum)
: ±3 µV (maximum)

-V

OS

: 125 dB (minimum)

-A

OL

- PSRR: 125 dB (minimum)

- CMRR: 120 dB (minimum)

-E

: 1.7 µV

ni

(typical), f = 0.1 Hz to 10 Hz

P-P

-Eni: 0.54 µVp-p (typical), f = 0.01 Hz to 1 Hz

• Low Power and Supply Voltages:
: 300 µA/amplifier (typical)

-I

Q

- Wide Supply Voltage Range: 1.8V to 5.5V

• Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 1.3 MHz (typical)

- Unity Gain Stable

- Available in Single and Dual

- Single with Chip Select (CS

): MCP6V08

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Description

The Microchip Technology Inc. MCP6V06/7/8 family of
operational amplifiers has input offset voltage
correction for very low offset and offset drift. These
devices have a wide gain bandwidth product (1.3 MHz,
typical) and strongly reject switching noise. They are
unity gain stable, have no 1/f noise, and have good
PSRR and CMRR. These products operate with a
single supply voltage as low as 1.8V, while drawing
300 µA/amplifier (typical) of quiescent current.

The Microchip Technology Inc. MCP6V06/7/8 op amps
are offered in single (MCP6V06), single with Chip
Select (CS

) (MCP6V08), and dual (MCP6V07). They

are designed in an advanced CMOS process.

Package Types

Design Aids

• SPICE Macro Models

• FilterLab® Software

• Mindi™ Circuit Designer & Simulator

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Related Parts

• MCP6V01/2/3: Spread clock, lower offset

© 2008 Microchip Technology Inc. DS22093A-page 1

Typical Application Circuit

MCP6V06/7/8

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD–VSS .......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (V

All other Inputs and Outputs ............ V

Difference Input voltage ...................................... |V

+ and VIN–) †† ... VSS– 1.0V to VDD+1.0V

IN

– 0.3V to VDD+0.3V

SS

DD–VSS

Output Short Circuit Current .................................Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ....................................-65°C to +150°C

|

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

†† See Section 4.2.1 “Rail-to-Rail Inputs”.

Max. Junction Temperature ........................................+150°C

ESD protection on all pins (HBM, MM) ................≥ 4 kV, 300V

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

V

OUT=VDD

Input Offset

Input Offset Voltage V
Input Offset Voltage Drift with Temperature

(linear Temp. Co.)

Input Offset Voltage Quadratic Temp. Co. TC
Power Supply Rejection PSRR 125 142 — dB (Note 1)

Input Bias Current and Impedance

Input Bias Current I
Input Bias Current across Temperature I

Input Offset Current I
Input Offset Current across Temperature I

Common Mode Input Impedance Z
Differential Input Impedance Z

Common Mode

Common-Mode Input Voltage Range V
Common-Mode Rejection CMRR 120 136 — dB V

Open-Loop Gain

DC Open-Loop Gain (large signal) A

Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these

/2, VL=VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

OS

TC

1

2

B

B

I

B

OS

OS

I

OS

CM

DIFF

CMRVSS

CMRR 130 147 — dB V

OL

A

OL

parts can only be screened in production (except TC

2: Figure 2-18 shows how V

changed across temperature for the first three production lots.

CMR

-3 — +3 µV TA = +25°C (Note 1)

-50 — +50 nV/°C TA = -40 to +125°C

(Note 1)

— ±0.15 — nV/°C2TA = -40 to +125°C

—+6—pA
—+140— pAT

= +85°C

A

— +1500 +5000 pA TA = +125°C
—-85— pA
—-85— pAT

= +85°C

A

-1000 -190 1000 pA TA = +125°C
—1013||6 — Ω||pF
—1013||6 — Ω||pF

− 0.20 — VDD+0.20 V (Note 2)

DD

V

CM

(Note 1, Note 2)

DD

V

CM

(Note 1, Note 2)

125 147 — dB VDD=1.8V,

V

OUT

135 158 — dB VDD=5.5V,

V

OUT

; see Appendix B: “Offset Related Test Screens”).

1

= 1.8V,

= -0.2V to 2.0V

= 5.5V,

= -0.2V to 5.7V

= 0.2V to 1.6V (Note 1)

= 0.2V to 5.3V (Note 1)

DS22093A-page 2 © 2008 Microchip Technology Inc.

MCP6V06/7/8

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

V

OUT=VDD

Output

Maximum Output Voltage Swing V
Output Short Circuit Current I

Power Supply

Supply Voltage V
Quiescent Current per amplifier I
POR Trip Voltage V

Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

V

OUT=VDD

Amplifier AC Response

Gain Bandwidth Product GBWP — 1.3 — MHz
Slew Rate SR — 0.5 — V/µs
Phase Margin PM — 65 — ° G = +1

Amplifier Noise Response

Input Noise Voltage E

Input Noise Voltage Density e

Input Noise Current Density i

Amplifier Distortion (Note 1)

Intermodulation Distortion (Not DC) IMD — 32 — µV

Amplifier Step Response

Start Up Time t
Offset Correction Settling Time t

Output Overdrive Recovery Time t

Note 1: These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD

/2, VL=VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

, V

OL

OHVSS

SC

I

SC

DD

Q

POR

parts can only be screened in production (except TC

2: Figure 2-18 shows how V

changed across temperature for the first three production lots.

CMR

/2, VL=VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).

+15 — VDD− 15 mV G = +2, 0.5V input overdrive
—±7—mAVDD=1.8V
—±22— mAVDD=5.5V

1.8 — 5.5 V

200 300 400 µA IO = 0

1.15 — 1.65 V

; see Appendix B: “Offset Related Test Screens”).

1

Parameters Sym Min Typ Max Units Conditions

—0.54— µV

ni

—1.7—µV

E

ni

—82 —nV/√Hz f < 2.5 kHz

ni

—52 —nV/√Hz f = 100 kHz

e

ni

—0.6—fA/√Hz

ni

IMD — 25 — µV

—500— µs VOS within 50 µV of its final value

STR

— 300 — µs G = +1, VIN step of 2V,

STL

— 100 — µs G = -100, ±0.5V input overdrive to VDD/2,

ODR

tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry.

2: t

includes some uncertainty due to clock edge timing.

ODR

f = 0.01 Hz to 1 Hz

P-P

f = 0.1 Hz to 10 Hz

P-P

PKVCM

PKVCM

tone = 50 mV
tone = 50 mV

V

within 50 µV of its final value

OS

V

50% point to V

IN

at 1 kHz, GN = 1, VDD = 5.5V

PK

at 1 kHz, GN = 1, VDD = 5.5V

PK

90% point (Note 2)

OUT

© 2008 Microchip Technology Inc. DS22093A-page 3

MCP6V06/7/8

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

V

OUT=VDD

CS Pull-Down Resistor (MCP6V08)

Pull-Down Resistor R

CS

Low Specifications (MCP6V08)

CS

Logic Threshold, Low V

CS

CS Input Current, Low I

CS High Specifications (MCP6V08)

Logic Threshold, High V

CS

CS Input Current, High I

CS Input High, GND Current per
amplifier

Amplifier Output Leakage, CS

CS Dynamic Specifications (MCP6V08)

Low to Amplifier Output On

CS
Turn-on Time

CS

High to Amplifier Output High-Z t

Internal Hysteresis V

/2, VL=VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

35—MΩ

V

SS

—0.3VDDV

—5—pA

0.7V

DD

—VDD/R

—VDDV

—pA

PD

—-0.7—µA

—-2.3—µA

—20—pA

— 11 100 µs

—10—µs

—0.25—V

CS

= V

SS

CS

= V

DD

CS

= VDD, VDD = 1.8V

CS

= VDD, VDD = 5.5V

CS

= V

DD

CS

Low = VSS+0.3 V, G = +1 V/V,

= 0.9 VDD/2

V

OUT

CS

High = VDD– 0.3 V, G = +1 V/V,

= 0.1 VDD/2

V

OUT

High I

PD

IL

CSL

IH

CSH

I

SS

I

SS

O_LEAK

t

ON

OFF

HYST

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

-40 — +125 °C

A

-40 — +125 °C (Note 1)

A

-65 — +150 °C

A

Thermal Package Resistances

Thermal Resistance, 8L-4×4 DFN θ
Thermal Resistance, 8L-SOIC θ

Note 1: Operation must not cause T

J

JA

JA

to exceed Maximum Junction Temperature specification (150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

—44—°C/W(Note 2)

— 150 — °C/W

DD

= +1.8V to +5.5V, VSS = GND.

DS22093A-page 4 © 2008 Microchip Technology Inc.

MCP6V06/7/8

V

DD

V

OS

VOS+50µV

V

OS

–50µV

t

STR

0V

1.8V to 5.5V

1.8V

V

IN

V

OS

VOS+50µV

VOS+50µV

t

STL

V

IN

V

OUT

V

DD

V

SS

t

ODR

t

ODR

VDD/2

V

IL

High-Z

t

ON

V

IH

CS

t

OFF

V

OUT

-2 µA

High-Z

I

SS

-2 µA

300 µA

1µA

I

DD

1µA

300 µA

VDD/5 MΩ

I

CS

VDD/5 MΩ

5pA

(typical)

(typical)

(typical) (typical)

(typical) (typical)

(typical)

(typical)

(typical)

V

DD

MCP6V0X

R

G

R

F

R

N

V

OUT

V

IN

VDD/3

1µF

C

L

R

L

V

L

100 nF

R

ISO

V

DD

MCP6V0X

R

G

R

F

R

N

V

OUT

VDD/3

V

IN

1µF

C

L

R

L

V

L

100 nF

R

ISO

V

DD

MCP6V0X

V

OUT

1µF

C

L

R

L

V

L

100 nF

R

ISO

20.0 kΩ

24.9 Ω

20.0 kΩ 50Ω

V

IN

V

REF

0.1%

0.1% 25 turn

20.0 kΩ

20.0 kΩ

0.1%

0.1%

2.49 kΩ 2.49 kΩ

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start Up.

FIGURE 1-2: Offset Correction Settling

Time.

1.4 Test Circuits

The circuits used for the DC and AC tests are shown in

Figure 1-5 and Figure 1-6. Lay the bypass capacitors

out as discussed in Section 4.3.7 “Supply Bypassing
and Filtering”. R

and RG to minimize bias current effects.

of R

F

FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.

is equal to the parallel combination

N

FIGURE 1-3: Output Overdrive Recovery.

FIGURE 1-4: Chip Select (MCP6V08).

© 2008 Microchip Technology Inc. DS22093A-page 5

FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions.

The circuit in Figure 1-7 tests the op amp input’s
dynamic behavior (i.e., IMD, t
potentiometer balances the resistor network (V
should equal V

at DC). The op amp’s common

REF

STR

, t

STL

and t

ODR

). The

OUT

mode input voltage is VCM=VIN/2. The error at the
input (V

) appears at V

ERR

with a noise gain of

OUT

10 V/V.

FIGURE 1-7: Test Circuit for Dynamic Input Behavior.

MCP6V06/7/8

0%

2%

4%

6%

8%

10%

12%

14%

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

Input Offset Voltage (µV)

Percentage of Occurrences

80 Samples
T

A

= +25°C

V

DD

= 1.8V and 5.5V

Soldered on PCB

0%

5%

10%

15%

20%

25%

-50

-40

-30

-20

-10

0

10

20

30

40

50

Input Offset Voltage Drift; TC1 (nV/°C)

Percentage of Occurrences

80 Samples
V

DD

= 1.8V and 5.5V

Soldered on PCB

0%

5%

10%

15%

20%

25%

30%

-0.4

-0.2

0.0

0.2

0.4

Input Offset Voltage's Quadratic Temp Co;

TC

2

(nV/°C2)

Percentage of Occurrences

80 Samples
V

DD

= 1.8V and 5.5V

Soldered on PCB

-4

-3

-2

-1

0

1

2

3

4

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5
Power Supply Voltage (V)

Input Offset Voltage (µV)

+125°C
+85°C
+25°C

-40°C

VCM = V

CMR_L

Representative Part

-4

-3

-2

-1

0

1

2

3

4

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5
Power Supply Voltage (V)

Input Offset Voltage (µV)

+125°C
+85°C
+25°C

-40°C

VCM = V

CMR_H

Representative Part

-4

-3

-2

-1

0

1

2

3

4

0.00.51.01.52.02.53.03.54.04.55.05.5

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V

VDD = 5.5V

Representative Part

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V
V

L=VDD

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.1 DC Input Precision

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-4: Input Offset Voltage vs.

Power Supply Voltage with V

OUT=VDD

/2,

CM=VCMR_L

.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage

Quadratic Temp Co.

DS22093A-page 6 © 2008 Microchip Technology Inc.

FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with V

CM=VCMR_H

.

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

MCP6V06/7/8

-4

-3

-2

-1

0

1

2

3

4

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V
Representative Part

-40°C
+25°C
+85°C

+125°C

-4

-3

-2

-1

0

1

2

3

4

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 5.5V
Representative Part

0%

5%

10%

15%

20%

25%

30%

35%

-0.4

-0.3

-0.2

-0.2

-0.1

0.0

0.1

0.2

0.2

0.3

0.4

1/CMRR (µV/V)

Percentage of Occurrences

39 Samples
T

A

= +25°C

Soldered on PCB

VDD = 1.8V

VDD = 5.5V

0%

2%

4%

6%

8%

10%

12%

14%

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

1/PSRR (µV/V)

Percentage of Occurrences

40 Samples
T

A

= +25°C

Soldered on PCB

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

1/AOL (µV/V)

Percentage of Occurrences

40 Samples
T

A

= +25°C

Soldered on PCB

VDD = 1.8V

VDD = 5.5V

120

125

130

135

140

145

150

155

160

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

CMRR, PSRR (dB)

PSRR

CMRR

VDD = 5.5V
V

DD

= 1.8V

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V
V

L=VDD

FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with V

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

=1.8V.

DD

+125°C

+85°C
+25°C

-40°C

FIGURE 2-10: PSRR.

OUT=VDD

/2,

FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with V

FIGURE 2-9: CMRR.

© 2008 Microchip Technology Inc. DS22093A-page 7

FIGURE 2-11: DC Open-Loop Gain.

=5.5V.

DD

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

MCP6V06/7/8

120

125

130

135

140

145

150

155

160

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

DC Open-Loop Gain (dB)

VDD = 5.5V
V

DD

= 1.8V

-150

-100

-50

0

50

100

150

200

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

I

B

TA = +85°C

DD

= 5.5V

I

OS

-400

-200

0

200

400

600

800

1000

1200

1400

1600

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

I

B

TA = +125°C
V

DD

= 5.5V

I

OS

1

10

100

1,000

10,000

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

VDD = 5.5V

-I

OS

I

B

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C
+25°C

10m

1m

100µ

10µ

1µ

100n

10n

1n

100p

10p

1p

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

V

L=VDD

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

V

FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
V

= +5.5V.

DD

OUT=VDD

/2,

FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

=+85°C.

A

FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T

= +125°C.

A

DS22093A-page 8 © 2008 Microchip Technology Inc.

-40°C

FIGURE 2-17: Input Bias Current vs. Input
Voltage (below V

SS

).

MCP6V06/7/8

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

Input Common Mode Voltage

Headroom (V)

Lower (V

CMR

– VSS)

Upper ( VDD – V

CMR

)

3 Lots

10

100

1000

0.1 1 10
Output Current Magnitude (mA)

Output Voltage Headroom

(mV)

VDD – V

V

DD

VOL – V

V

DD

V

0

1

2

3

4

5

6

7

8

9

10

11

12

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

Output Headroom (mV)

VDD – V

V

DD

VOL – V

SS

V

DD

RL = 20 k

-40

-30

-20

-10

0

10

20

30

40

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Output Short Circuit Current

(mA)

-40°C
+25°C
+85°C

+125°C

+125°C

+85°C
+25°C

-40°C

0

50

100

150

200

250

300

350

400

450

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Supply Current (µA)

-40°C

0%

5%

10%

15%

20%

25%

30%

1.1

1.2

1.3

1.4

1.5

1.6

1.7

POR Trip Voltage (V)

Percentage of Occurrences

93 Samples
3 Lots
T

A

= +25°C

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V
V

L=VDD

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.2 Other DC Voltages and Currents

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

= 5.5V

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

OUT=VDD

/2,

OH

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

Ω

= 5.5V

= 1.8V

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

© 2008 Microchip Technology Inc. DS22093A-page 9

= 1.8

+125°C

+85°C
+25°C

SS

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

OH

FIGURE 2-23: Power On Reset Trip Voltage.

MCP6V06/7/8

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

POR Trip Voltage (V)

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

V

L=VDD

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature.

OUT=VDD

/2,

DS22093A-page 10 © 2008 Microchip Technology Inc.

MCP6V06/7/8

0

10

20

30

40

50

60

70

80

90

100

110

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

CMRR, PSRR (dB)

CMRR

PSRR+
PSRR-

10 100k1k 1M10k100

-30

-20

-10

0

10

20

30

40

50

60

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Open-Loop Gain (dB)

-270

-240

-210

-180

-150

-120

-90

-60

-30

0

Open-Loop Phase (°)

| AOL |

∠

A

OL

1k 10k 100k 1M 10M

VDD = 1.8V
C

L

= 60 pF

-30

-20

-10

0

10

20

30

40

50

60

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Open-Loop Gain (dB)

-270

-240

-210

-180

-150

-120

-90

-60

-30

0

Open-Loop Phase (°)

| AOL |

∠

A

OL

1k 10k 100k 1M 10M

VDD = 5.5V
C

L

= 60 pF

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

(MHz)

40

50

60

70

80

90

100

110

120

130

Phase Margin (°)

V

DD

PM

GBWP

DD

= 1.8V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

40

50

60

70

80

90

100

110

120

130

Phase Margin (°)

V

DD

V

DD

GBWP

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Gain Bandwidth Product

(MHz)

40

50

60

70

80

90

100

110

120

130

Phase Margin (°)

V

DD

V

PM

V

DD

GBWP

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V
V

L=VDD

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.3 Frequency Response

V

= 1.8V

FIGURE 2-25: CMRR and PSRR vs. Frequency.

Gain Bandwidth Product

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

OUT=VDD

= 5.5V

= 5.5V

/2,

FIGURE 2-26: Open-Loop Gain vs.
Frequency with V

FIGURE 2-27: Open-Loop Gain vs.
Frequency with V

© 2008 Microchip Technology Inc. DS22093A-page 11

=1.8V.

DD

=5.5V.

DD

PM

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

= 1.8V

= 5.5

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

MCP6V06/7/8

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

VDD = 1.8V

100k 1M 10M 100M

1

10

100

1k

10k

G = 1 V/V
G = 10 V/V
G = 100 V/V

Open-Loop Output Impedance ( Ω )

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

VDD = 5.5V

100k 1M 10M 100M

1

10

100

1k

10k

G = 1 V/V
G = 10 V/V
G = 100 V/V

Open-Loop Output Impedance ( Ω )

0

10

20

30

40

50

60

70

80

90

100

1.E+05 1.E+06 1.E+07

Frequency (Hz)

Channel-to-Channel

Separation (dB)

V

DD

V

DD

100k 1M 10M

0.1

1

10

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

Maximum Output Voltage

Swing (V

P-P

)

V

DD

V

DD

1k 10k 100k 1M

Note: Unless otherwise indicated, TA= +25°C, VDD= +1.8V to 5.5V, VSS= GND, VCM=VDD/3, V

V

L=VDD

FIGURE 2-31: Closed-Loop Output
Impedance vs. Frequency with V

/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

=1.8V.

DD

= 1.8V

FIGURE 2-33: Channel-to-Channel Separation vs. Frequency.

= 1.8V

OUT=VDD

= 5.5V

= 5.5V

/2,

RTI

FIGURE 2-32: Closed-Loop Output
Impedance vs. Frequency with V

DS22093A-page 12 © 2008 Microchip Technology Inc.

DD

=5.5V.

FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency.