MICROCHIP MCP6S21, MCP6S22, MCP6S26, MCP6S28 Technical data

M

Single-Ended, Rail-to-Rail I/O, Low Gain PGA

MCP6S21/2/6/8

Features

• Multiplexed Inputs: 1, 2, 6 or 8 channels

• 8 Gain Selections:

- +1, +2, +4, +5, +8, +10, +16 or +32 V/V

• Serial Peripheral Interface (SPI™)

• Rail-to-Rail Input and Output

• Low Gain Error: ±1% (max)

• Low Offset: ±275 µV (max)

• High Bandwidth: 2 to 12 MHz (typ)

• Low Noise: 10 nV/√Hz @ 10 kHz (typ)

• Low Supply Current: 1.0 mA (typ)

• Single Supply: 2.5V to 5.5V

Typical Applications

• A/D Converter Driver

• Multiplexed Analog Applications

• Data Acquisition

• Industrial Instrumentation

• Test Equipment

• Medical Instrumentation

Package Types

MCP6S21

PDIP, SOIC, MSOP

V

1

OUT

CH0

2

V

3

REF

V

4

SS

V

8

DD

SCK

7

SI

6

5

CS

MCP6S22

PDIP, SOIC, MSOP

V

1

OUT

CH0

2

3

CH1

V

4

SS

Description

The Microchip Technology Inc. MCP6S21/2/6/8 are
analog Programmable Gain Amplifiers (PGA). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to eight chan­nels through an SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single
supply applications needing flexible performance or
multiple inputs.

The one channel MCP6S21 and the two channel
MCP6S22 are available in 8-pin PDIP, SOIC and
MSOP packages. The six channel MCP6S26 is avail­able in 14-pin PDIP, SOIC and TSSOP packages. The
eight channel MCP6S28 is available in 16-pin PDIP
and SOIC packages. All parts are fully specified from

-40°C to +85°C.

Block Diagram

V

DD

CH0
CH1
CH2
CH3
CH4

V

8

DD

SCK

7

SI

6

5

CS

CH5
CH6

CH7

CS

SO

SCK

MUX

SI

SPI™

Logic

+

-

Gain

Switches

V

OUT

Resistor Ladder (R

R

8

F

R

G

LAD

)

MCP6S26

PDIP, SOIC, TSSOP

V

1

OUT

CH0

2

CH1

3

CH2

4

5

CH3

CH4

6

7

CH5

 2003 Microchip Technology Inc. DS21117A-page 1

14

13

12

11

10

V

DD

SCK

SO

SI

CS

V

9

SS

V

8

REF

V

OUT

CH0

CH1

CH2

CH3

CH4

CH5

CH6

MCP6S28

PDIP, SOIC

1

2

3

4

5

6

7

8

16

15

14

13 SI

12

11

10

9

V

DD

SCK

SO

CS

V

SS

V

REF

CH7

POR

V

SS

V

REF

MCP6S21/2/6/8

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

VDD - VSS.........................................................................7.0V

All inputs and outputs....................... V

Difference Input voltage ........................................ |V

Output Short Circuit Current...................................continuous

Current at Input Pin .............................................................±2mA

Current at Output and Supply Pins ................................ ±30 mA

Storage temperature .....................................-65°C to +150°C

Junction temperature .................................................. +150°C

ESD protection on all pins (HBM;MM).................. ≥ 2 kV; 200V

- 0.3V to VDD +0.3V

SS

DD

- VSS|

PIN FUNCTION TABLE

Name Function

V

OUT

CH0-CH7 Analog Inputs

V

SS

V

DD

SCK SPI Clock Input

SI SPI Serial Data Input

SO SPI Serial Data Output

CS

V

REF

Analog Output

Negative Power Supply

Positive Power Supply

SPI Chip Select

External Reference Pin

† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA=+25°C, VDD= +2.5V to +5.5V, VSS= GND, V

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

=10kΩ to VDD/2, SI and SCK are tied low and CS is tied high.

L

Parameters Sym Min Typ Max Units Conditions

Amplifier Input

Input Offset Voltage V
Input Offset Voltage Drift ∆V

OS

OS

/∆T

-275 — +275 µV G = +1, VDD = 4.0V

—±4 —µV/°CT

A

= -40 to +85°C

A

Power Supply Rejection Ratio PSRR 70 85 — dB G = +1 (Note 1)

Input Bias Current I

Input Bias Current over
Temperature

Input Impedance Z

Input Voltage Range V

B

I

B

IN

IVR

— ±1 — pA CHx = VDD/2

— — 250 pA TA = -40 to +85°C,

CHx = V

—1013||15 — Ω||pF

VSS−0.3 — VDD+0.3 V

Amplifier Gain

Nominal Gains G — 1 to 32 — V/V +1, +2, +4, +5, +8, +10, +16 or +32

DC Gain Error G = +1 g

G ≥ +2 g

E

E

DC Gain Drift G = +1 ∆G/∆T

G ≥ +2 ∆G/∆T

Internal Resistance R

Internal Resistance over

∆R

LAD

LAD

Temperature

-0.1 — +0.1 % V

-1.0 — +1.0 % V

— ±0.0002 — %/°C TA = -40 to +85°C

A

— ±0.0004 — %/°C TA = -40 to +85°C

A

3.4 4.9 6.4 kΩ (Note 1)

/∆T

—+0.028 — %/°C(Note 1)

A

≈ 0.3V to V

OUT

≈ 0.3V to V

OUT

T

= -40 to +85°C

A

Amplifier Output

DC Output Non-linearity G = +1 V

G ≥ +2 V

Maximum Output Voltage Swing V

Short-Circuit Current I

Note 1: R

(RF + RG in Figure 4-1) connects V

LAD

V

tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We

REF

recommend the MCP6S22’s V

2: I

includes current in R

Q

3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.

ONL

ONL

, VOLVSS+20 — VDD-100 mV G ≥ +2; 0.5V output overdrive

OH

O(SC)

SS

(typically 60 µA at V

LAD

— ±0.003 — % of FSR V

— ±0.001 — % of FSR V

+60 — VDD-60 G ≥ +2; 0.5V output overdrive,

V

SS

—±30 — mA

, V

REF

and the inverting input of the internal amplifier. The MCP6S22 has

OUT

pin be tied directly to ground to avoid noise problems.

= 0.3V). Both IQ and I

OUT

Q_SHDN

= 0.3V to V

OUT

= 0.3V to V

OUT

V

= VDD/2

REF

exclude digital switching currents.

= VSS, G = +1 V/V,

REF

/2

DD

DD

DD

DD

DD

− 0.3V

− 0.3V

− 0.3V, V

− 0.3V, V

DD

DD

= 5.0V

= 5.0V

DS21117A-page 2  2003 Microchip Technology Inc.

DC CHARACTERISTICS (CONTINUED)

MCP6S21/2/6/8

Electrical Specifications: Unless otherwise indicated, TA=+25°C, VDD= +2.5V to +5.5V, VSS= GND, V

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

=10kΩ to VDD/2, SI and SCK are tied low and CS is tied high.

L

Parameters Sym Min Typ Max Units Conditions

Power Supply

Supply Voltage V

Quiescent Current I

Quiescent Current, Shutdown

I

Q_SHDN

DD

Q

2.5 — 5.5 V

0.5 1.0 1.35 mA IO = 0 (Note 2)

—0.51.0 µAI

= 0 (Note 2)

O

mode

Power-On Reset

POR Trip Voltage V
POR Trip Voltage Drift ∆V

Note 1: R

2: I
3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.

(RF + RG in Figure 4-1) connects V

LAD

V

tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We

REF

recommend the MCP6S22’s V

includes current in R

Q

POR

POR

(typically 60 µA at V

LAD

1.2 1.7 2.2 V (Note 3)

/∆T— -3.0 — mV/°CTA = -40°C to+85°C

, V

REF

pin be tied directly to ground to avoid noise problems.

SS

and the inverting input of the internal amplifier. The MCP6S22 has

OUT

= 0.3V). Both IQ and I

OUT

exclude digital switching currents.

Q_SHDN

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA=+25°C, VDD= +2.5V to +5.5V, VSS= GND, V

Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, R

Parameters Sym Min Typ Max Units Conditions

Frequency Response

-3 dB Bandwidth BW — 2 to 12 — MHz All gains; V

Gain Peaking GPK — 0 — dB All gains; V

Total Harmonic Distortion plus Noise

f = 1 kHz, G = +1 V/V THD+N — 0.0015 — %

f = 1 kHz, G = +4 V/V THD+N — 0.0058 — %

f = 1 kHz, G = +16 V/V THD+N — 0.023 — %

f = 20 kHz, G = +1 V/V THD+N — 0.0035 — %

f = 20 kHz, G = +4 V/V THD+N — 0.0093 — %

f = 20 kHz, G = +16 V/V THD+N — 0.036 — %

Step Response

Slew Rate SR — 4.0 — V/µs G = 1, 2

Noise

Input Noise Voltage E

Input Noise Voltage Density e

Input Noise Current Density i

Note 1: See Table 4-1 for a list of typical numbers.

and eni include ladder resistance noise. See Figure 2-33 for eni vs. G data.

2: E

ni

=10kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.

L

= 1.5V ± 1.0VPK, VDD = 5.0V,

V

OUT

BW = 22 kHz

V

= 1.5V ± 1.0VPK, VDD = 5.0V,

OUT

BW = 22 kHz

V

= 1.5V ± 1.0VPK, VDD = 5.0V,

OUT

BW = 22 kHz

V

= 1.5V ± 1.0VPK, VDD = 5.0V,

OUT

BW = 80 kHz

V

= 1.5V ± 1.0VPK, VDD = 5.0V,

OUT

BW = 80 kHz

V

= 1.5V ± 1.0VPK, VDD = 5.0V,

OUT

BW = 80 kHz

— 11 — V/µs G = 4, 5, 8, 10

—22—V/µsG = 16, 32

ni

—3.2—µV

f = 0.1 Hz to 10 kHz (Note 2)

P-P

— 26 — f = 0.1 Hz to 200 kHz (Note 2)

ni

ni

—10—nV/√Hz f = 10 kHz (Note 2)
—4—fA/√Hz f = 10 kHz

= VSS, G = +1 V/V,

REF

= VSS, G = +1 V/V,

REF

< 100 mV

OUT

< 100 mV

OUT

(Note 1)

P-P

P-P

 2003 Microchip Technology Inc. DS21117A-page 3

MCP6S21/2/6/8

DIGITAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA=+25°C, VDD= +2.5V to +5.5V, VSS= GND, V

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

Parameters Sym Min Typ Max Units Conditions

=10kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.

L

= VSS, G = +1 V/V,

REF

SPI Inputs (CS

Logic Threshold, Low V

Input Leakage Current I

Logic Threshold, High V

, SI, SCK)

IL

IL

IH

0 — 0.3V

-1.0 — +1.0 µA

0.7V

—VDDV

DD

DD

V

Amplifier Output Leakage Current — -1.0 — +1.0 µA In Shutdown mode

SPI Output (SO, for MCP6S26 and MCP6S28)

Logic Threshold, Low V

Logic Threshold, High V

OL

OH

V

SS

VDD-0.5 — V

—VSS+0.4 V IOL = 2.1 mA, VDD = 5V

DD

VIOH = -400 µA

SPI Timing

Pin Capacitance C

Input Rise/Fall Times (CS

, SI, SCK)

Output Rise/Fall Times (SO) t

high time

CS

SCK edge to CS

CS

fall to first SCK edge setup time

fall setup time

SCK Frequency f

SCK high time t

SCK low time t

SCK last edge to CS

CS

rise to SCK edge setup time

rise setup time

SI set-up time t

SI hold time t

SCK to SO valid propagation delay t

rise to SO forced to zero

CS

PIN

t

RFI

RFO

t

CSH

t

CS0

t

CSSC

SCK

LO

t

SCCS

t

CS1

SU

HD

DO

t

SOZ

HI

— 10 — pF All digital I/O pins

——2µsNote 1

— 5 — ns MCP6S26 and MCP 6S28

40 — — ns

10 — — ns

SCK edge when CS is high

40 — — ns

——10MHzVDD = 5V (Note 2)

40 — — ns

40 — — ns

30 — — ns

100 — — ns

SCK edge when CS is high

40 — — ns

10 — — ns

— — 80 ns MCP6S26 and MCP 6S28

— — 80 ns MCP6S26 and MCP 6S28

Channel and Gain Select Timing

Channel Select Time t

Gain Select Time t

CH

G

— 1.5 — µs CHx = 0.6V, CHy =0.3V, G = 1,

CHx to CHy select
C

S = 0.7VDD to V

OUT

— 1 — µs CHx = 0.3V, G = 5 to G = 1 select,

C

S = 0.7VDD to V

OUT

Shutdown Mode Timing

Out of Shutdown mode (CS

goes

high) to Amplifier Output Turn-on

t

ON

—3.510µs

CS

= 0.7VDD to V

OUT

90% point

Time

Into Shutdown mode (CS

goes high)

to Amplifier Output High-Z Turn-off

t

OFF

—1.5—µs

CS

= 0.7VDD to V

OUT

90% point

Time

POR Timing

Power-On Reset power-up time t

Power-On Reset power-down time t

RPU

RPD

—30—µsVDD = V

50% V

—10—µsVDD = V

50% V

POR

to 90% V

DD

POR

to 90% V

DD

- 0.1V to V

OUT

+ 0.1V to V

OUT

Note 1: Not tested in production. Set by design and characterization.

2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of

propagation delay time (t
fall times of 5 ns. Maximum f

≤ 80 ns), data input setup time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns), and SCK rise and

DO

is, therefore, ≈ 5.8 MHz.

SCK

90% point

90% point

+ 0.1V,

POR

point

- 0.1V,

POR

point

DS21117A-page 4  2003 Microchip Technology Inc.

TEMPERATURE CHARACTERISTICS

MCP6S21/2/6/8

Electrical Specifications: Unless otherwise indicated, V

= +2.5V to +5.5V, VSS= GND.

DD

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

A

A

A

-40 — +85 °C

-40 — +125 °C (Note Note:)

-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 8L-PDIP θ
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 8L-MSOP θ
Thermal Resistance, 14L-PDIP θ
Thermal Resistance, 14L-SOIC θ
Thermal Resistance, 14L-TSSOP θ
Thermal Resistance, 16L-PDIP θ
Thermal Resistance, 16L-SOIC θ

JA

JA

JA

JA

JA

JA

JA

JA

—85—°C/W

—163—°C/W

—206—°C/W

—70—°C/W

—120—°C/W

—100—°C/W

—70—°C/W

—90—°C/W

Note 1: The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced

performance. Operation in this range must not cause T

to exceed the Maximum Junction Temperature

J

(150°C).

CS

CS

t

CH

V

OUT

0.6V

0.3V

FIGURE 1-1: Channel Select Timing Diagram.

CS

t

OFF

V

OUT

I

SS

t

ON

Hi-Z Hi-Z

0.3V

1.0 mA (typ)

500 nA (typ)

FIGURE 1-2: PGA Shutdown timing
diagram (must enter correct commands before
CS

goes high).

t

G

V

OUT

1.5V

0.3V

FIGURE 1-3: Gain Select Timing Diagram.

V

+ 0.1V

t

RPU

POR

0.3V

1.0 mA (typ)

t

RPD

POR

- 0.1V

V

V

OUT

DD

V

- 0.1V V

POR

Hi-Z Hi-Z

I

SS

500 nA (typ)

FIGURE 1-4: POR power-up and power­down timing diagram.

 2003 Microchip Technology Inc. DS21117A-page 5

MCP6S21/2/6/8

CS

t

CSH

t

CSSC

tLOt

HI

SCK

1/f

t

t

HD

SU

SCK

SI

t

DO

SO

(first 16 bits out are always zeros)

FIGURE 1-5: Detailed SPI Serial Interface Timing, SPI 0,0 mode.

CS

t

CSSC

tHIt

LO

SCK

t

SCCS

t

SCCS

t

CS1

t

SOZ

t

CS1

t

CSH

t

CS0

t

CS0

1/f

tSUt

HD

SCK

SI

t

DO

SO

(first 16 bits out are always zeros)

FIGURE 1-6: Detailed SPI Serial Interface Timing, SPI 1,1 mode.

t

SOZ

DS21117A-page 6  2003 Microchip Technology Inc.

1.1 DC Output Voltage Specs / Model

1.1.1 IDEAL MODEL

MCP6S21/2/6/8

V

(V)

OUT

The ideal PGA output voltage (V

OUT

) is:

EQUATION

V

O_ideal

where: G is the nominal gain

(see Figure 1-7). This equation holds when there are
no gain or offset errors and when the V
a low impedance source (<< 0.1Ω) at ground potential
(V

= 0V).

SS

GV

= V

IN

REFVSS

pin is tied to

REF

0V==

1.1.2 LINEAR MODEL

The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line V

O_linear

, shown

in Figure 1-7.

EQUATION

V

O_linear

V

The endpoints of this line are at V
V

-0.3V. The gain and offset specifications referred to

DD

in the electrical specifications are related to Figure 1-7,
as follows:

G1 g

REFVSS

+()V

E

0V==

IN

0.3 V V

+–()0.3V+=

O_ideal

OS

=0.3V and

EQUATION

V

DD

V

DD

2

V

1

V

(V)

IN

V

-0.3

DD

T

U

O

r

V

O

V

l

a

a

e

e

n

d

i

i

l

_

_

O

V

0.3

0

0.3 V

0

- 0.3 V

DD

GGG

FIGURE 1-7: Output Voltage Model with
the standard condition V

= VSS = 0V.

REF

1.1.3 OUTPUT NON-LINEARITY

Figure 1-8 shows the Integral Non-Linearity (INL) of the
output voltage.

EQUATION

INL V

The output non-linearity specification in the electrical
specifications is related to Figure 1-8 by:

–=

OUTVO_linear

gE100%

V

OS

∆⁄∆

GT

A

---------- ------------- --

=

G1 g

g

∆

----------

=

T

∆

V

2V1

----------- ------------- --------------=

GV

DD

V

1

+()

E

E

A

–

0.6V–()

G+1=

EQUATION

max V4V3,{}

ONL

---------- ------------- ----------

=

V

DD

0.6 V–

V

INL (V)

V

4

0

0.3 V

0

DD

V

3

(V)

V

- 0.3 V

IN

DD

GGG

FIGURE 1-8: Output Voltage INL with the
standard condition V

= VSS = 0V.

REF

 2003 Microchip Technology Inc. DS21117A-page 7

MCP6S21/2/6/8

1.1.4 DIFFERENT V

CONDITIONS

REF

Some of the plots in Section 2.0, “Typical Performance
Curves”, have the conditions V
V

REF=VDD

. The equations and figures above are eas-

REF=VDD

ily modified for these conditions. The ideal V

/2 or

OUT

becomes:

EQUATION

V

O_idealVREF

V

DDVREFVSS

The complete linear model is:

GVINV

> 0V=≥

–()+=

REF

EQUATION

V

O_linear

where the new VIN endpoints are:

G1 g

+()V

E

INVIN_LVOS

+–()0.3 V+=

EQUATION

0.3V V

–

GV

+

REF

0.3V– V

GV

+

REF

REF

–

REF

V

V

=

IN_L

V

---------- ------------- ------------- -----------

=

IN_R

---------- ------------- -------

DD

The equations for extracting the specifications do not
change.

DS21117A-page 8  2003 Microchip Technology Inc.

MCP6S21/2/6/8

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

22%

420 Samp les

20%

G = +1

18%
16%
14%
12%
10%

8%
6%
4%
2%

Percentage of Occurrences

0%

-0.040

-0.036

-0.032

-0.028

-0.024

-0.020

= +25°C, V

A

-0.016

-0.012

-0.008

L

-0.004

DC Gain Error (%)

FIGURE 2-1: DC Gain Error, G = +1.

18%

420 Samples

16%

G t +2

14%

12%

10%

8%

6%

4%

2%

Percentage of Occurrences

0%

0.0

0.1

0.2

-0.5

-0.4

-0.3

-0.2

-0.1

DC Gain Error (%)

0.3

= +5.0V, V

DD

= GND, V

SS

REF =VSS

=10kΩ to VDD/2, and CL = 60 pF.

18%

420 Samp les

16%

G = +1

14%

T

= -40 to +125°C

A

12%

10%

8%

6%

4%

2%

0%

Percentage of Occurrences

0.000

0.004

-0.0006

FIGURE 2-4: DC Gain Drift, G = +1.

24%

420 Samples

22%

G t +2

20%

= -40 to +125°C

T

A

18%
16%
14%
12%
10%

8%
6%
4%
2%

Percentage of Occurrences

0%

0.4

0.5

-0.0020

, G= +1 V/V,

-0.0005

-0.0004

-0.0003

DC Gain Drift (%/°C)

-0.0016

-0.0012

DC Gain Drift (%/°C)

-0.0002

-0.0008

-0.0001

-0.0004

0.0000

0.0000

0.0001

0.0004

0.0002

0.0008

0.0003

0.0012

0.0004

0.0005

0.0016

0.0006

0.0020

FIGURE 2-2: DC Gain Error, G ≥+2.

22%

420 Samp les

20%

T

= -40 to +125°C

A

18%
16%

14%
12%
10%

8%
6%
4%

2%

Percentage of Occurrences

0%

0.023

0.024

0.025

0.026

0.027

0.028

0.029

0.030

Ladder Resistance Drift (%/°C)

FIGURE 2-3: Ladder Resistance Drift.

0.031

FIGURE 2-5: DC Gain Drift, G ≥+2.

20%

360 Samples

18%

VDD = 4.0 V

16%

G = +1

14%

12%

10%

8%

6%

4%

2%

Percentage of Occurrences

0%

-240

-200

-160

-120

-80

-40

0

40

80

120

160

Input Offset Voltage (µV)

FIGURE 2-6: Input Offset Voltage,

= 4.0V.

V

DD

200

240

 2003 Microchip Technology Inc. DS21117A-page 9

MCP6S21/2/6/8

Note: Unless otherwise indicated, T

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

200

G = +1

150

100

50

0

-50

-100

-150

Input Offset Voltage (µV)

-200

0.00.51.01.52.02.53.03.54.04.55.05.5

VDD = +2.5

VDD = +5.5

V

Voltage (V)

REF

= +25°C, V

A

L

FIGURE 2-7: Input Offset Voltage vs.
V

Voltage.

REF

0.01

0.001

0.0001

DC Output Non-Linearity,

Input Referred (% of FSR)

0.00001

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

V

V

V

/G, G = +1

ONL

/G, G = +2

ONL

/G, G t +4

ONL

V

= 0.3V to VDD -0.3V

OUT

= +5.0V, V

DD

= GND, V

SS

REF =VSS

=10kΩ to VDD/2, and CL = 60 pF.

22%

420 Samples

20%

TA = -40 to +125°C

18%

G = +1

16%

14%

12%

10%

8%

6%

4%

2%

Percentage of Occurrences

0%

-16

-14

FIGURE 2-10: Input Offset Voltage Drift.

0.0100%

0.0010%

Input Referred (%)

DC Output Non-Linearity,

0.0001%

VDD = +5.5 V

110

, G= +1 V/V,

-8-6-4

-12

-10

Input Offset Voltage Drift (µV/° C)

Output Voltage Swing (V

02468

-2

V

V

ONL

ONL

/G, G = +1

/G, G t +2

P-P

101214

)

16

FIGURE 2-8: DC Output Non-Linearity vs. Supply Voltage.

1000

100

Hz)



(nV/

10

Input Noise Voltage Density

1

0.1 1 10 100 1000 10000 100000

1k 10k 100k1 10 1000.1

Frequency (Hz)

FIGURE 2-9: Input Noise Voltage Density vs. Frequency.

FIGURE 2-11: DC Output Non-Linearity vs. Output Swing.

12

f = 10 kHz

11

10

9

8

7

Hz)



6

5

(nV/

4

3

2

1

Input Noise Voltage Density

0

12458101632

Gain (V/V)

FIGURE 2-12: Input Noise Voltage Density vs. Gain.

DS21117A-page 10  2003 Microchip Technology Inc.

MCP6S21/2/6/8

Note: Unless otherwise indicated, T

=+25°C, V

A

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

120

110

100

(dB)

90

80

Power Supply Rejection Ratio

70

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

FIGURE 2-13: PSRR vs. Ambient Temperature.

1,000

CH0 = V

DD

VDD = 5.5 V

100

10

Input Bias Current (pA)

1

55 65 75 85 95 105 11 5 125

Ambient Temperature (°C)

= +5.0V, V

DD

=10kΩ to VDD/2, and CL = 60 pF.

L

= GND, V

SS

REF =VSS

100

VDD = 5.5 V

90

VDD = 2.5 V

80

70

(dB)

60

50

Power Supply Rejection Ratio

10 100 1000 10000 100000

40

FIGURE 2-16: PSRR vs. Frequency.

10,000

VDD = 5.5 V

1,000

100

10

Input Bias Current (pA)

1

0.0 0.5 1.0 1. 5 2. 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

, G= +1 V/V,

Input Referred

1k 10 k 100k10 100

Frequency (Hz)

TA = +125°C

TA = +85°C

Input Voltage (V)

FIGURE 2-14: Input Bias Current vs. Ambient Temperature.

100

G = +1
G = +4

10

G = +16

Bandwidth (MHz)

1

10 100 1000

Capacitive Load (pF)

FIGURE 2-15: Bandwidth vs. Capacitive Load.

FIGURE 2-17: Input Bias Current vs. Input Voltage.

7

6

5

4

3

2

Gain Peaking (dB)

1

0

10 100 1000

G = +1
G = +4

G = +16

Capacitive Load (pF)

FIGURE 2-18: Gain Peaking vs. Capacitive Load.

 2003 Microchip Technology Inc. DS21117A-page 11

MCP6S21/2/6/8

Note: Unless otherwise indicated, T

=+25°C, V

A

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

40

30

20

10

Gain (dB)

0

G = +10

G = +8

-10

G = +5
G = +4

1.E+05 1.E+06 1.E+07 1.E+08

-20
1M 10M 100M100k

Frequency (Hz)

G = +2
G = +1

G = +32
G = +16

FIGURE 2-19: Gain vs. Frequency.

100%

420 Samp les

90%

V

= 5.0 V

DD

80%

70%

60%

50%

40%

30%

20%

10%

Percentage of Occurrences

0%

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Quiescent Current in Shutdown (µA)

= +5.0V, V

DD

=10kΩ to VDD/2, and CL = 60 pF.

L

= GND, V

SS

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Quiescent Current (mA)

0.1

0.0

0.0 0.5 1. 0 1.5 2. 0 2. 5 3.0 3. 5 4. 0 4.5 5. 0 5.5

REF =VSS

FIGURE 2-22: Quiescent Current vs. Supply Voltage.

1.0
In Shutdown Mode

0.9
VDD = 5.0 V

0.8

0.7

0.6

0.5

(µA)

0.4

0.3

0.2

0.1

Quiescent Current in Shutdown

0.9

1.0

0.0

-50 -25 0 25 50 75 100 125

, G= +1 V/V,

TA = +125°C
TA = +85°C
TA = +25°C
T

= -40°C

A

Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-20: Histogram of Quiescent Current in Shutdown Mode.

100

SS

- V

OL

10

and V

OH

- V

DD

V

1

Output Voltage Headroom (mV)

0.1 1 10

Output Current Magnitude (mA)

VDD = +5.5V

VDD = +2.5V

FIGURE 2-21: Output Voltage Headroom vs. Output Current.

FIGURE 2-23: Quiescent Current in Shutdown Mode vs. Ambient Temperature.

40

35

30

25

20

(mA)

15

10

5

Output Short Circuit Current

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

TA = +125°C
T

= +85°C

A

TA = +25°C
TA = -40°C

Power Supply Voltage (V)

FIGURE 2-24: Output Short Circuit Current vs. Supply Voltage.

DS21117A-page 12  2003 Microchip Technology Inc.

MCP6S21/2/6/8

Note: Unless otherwise indicated, T

=+25°C, V

A

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

1

Measur ement BW = 80 kHz
V

= 2 V

OUT

P-P

VDD = 5.0 V

0.1

G = +16

0.01

THD + Noise (%)

G = +4

G = +1

1.E+02 1.E+03 1.E+04 1.E+05

0.001
100 1k 100k10k

Frequency (Hz)

FIGURE 2-25: THD plus Noise vs.
Frequency, V

80

70

60

50

40

30

20

10

(10 mV/div)

0

Output Voltage

-10

-20

-30

-40

0.00E+00 2.00E-07 4.00E-07 6.00E-07 8.00E-07 1.00E-06 1.20E-06 1.40E-06 1.60E-06 1.80E-06 2.00E-06

= 2 V

OUT

V

, G = +1

OUT

G = +5
G = +32

Time (200 ns/div)

P-P

.

VDD = +5.0V

GV

IN

= +5.0V, V

DD

=10kΩ to VDD/2, and CL = 60 pF.

L

= GND, V

SS

REF =VSS

1

Measur ement BW = 80 kHz
V

OUT

VDD = 5.0 V

0.1

0.01

THD + Noise (%)

1.E+02 1.E+03 1.E+04 1.E+05

0.001
100 1k 100k10k

FIGURE 2-28: THD plus Noise vs.
Frequency, V

250

200

150

100

50

0

-50

(50 mV/div)

-100

-150

Normalized Input Voltage

-200

-250

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

Output Voltage (V)

1.0

0.5

0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06

0.0

= 4 V

G = +16

G = +4

G = +1

OUT

P-P

= 4 V

, G= +1 V/V,

Frequency (Hz)

.

P-P

V

, G = +1

OUT

G = +5
G = +32

Time (500 ns/div)

VDD = +5.0V

GV

7.5

6.5

5.5

4.5

3.5

2.5

1.5

(1V/div)

IN

0.5

-0.5

Normalized Input Voltage

-1.5

-2.5

FIGURE 2-26: Small Signal Pulse Response.

0.65

0.60

V

0.55

0.50

0.45

0.40

0.35

Output Voltage (V)

OUT

(CH0 = 0.6V, G = +1)

CS

CS

V

OUT

(CH1 = 0.3V, G = +1)

0.30

0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06

0.25

Time (500 ns/div)

FIGURE 2-27: Channel Select Timing.

20

15

10

5

5

0

0

-5

-10

Chip Select Voltage (V)

-15

-20

FIGURE 2-29: Large Signal Pulse Response.

1.6

1.4

1.2

1.0

0.8

0.6

Output Voltage (V)

0.4

V

OUT

(CH0 = 0.3V, G = +5)

CS

CS

V

OUT

(CH0 = 0.3V, G = +1)

0.2

0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06

0.0

Time (500 ns/div)

FIGURE 2-30: Gain Select Timing.

20

15

10

5

5

0

0

-5

-10

Chip Select Voltage (V)

-15

-20

 2003 Microchip Technology Inc. DS21117A-page 13