MCP6281/1R/2/3/4/5
V
IN
_
MCP6281
V
DD
1
2
3
4
8
7
6
5
+
NC
NC
NC
V
IN
+
V
SS
MCP6282
PDIP, SOIC, MSOP
MCP6284
1
2
3
4
14
13
12
11
-
+
-
+
10
9
8
5
6
7
+
-
-
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
+
-
+
V
OUT
MCP6283
1
2
3
4
8
7
6
5
+
V
INA
_
V
INA
+
V
SS
V
OUTA
V
OUTB
V
DD
V
INB
_
V
INB
+
V
SS
VIN+
V
IN
_
NC
CS
V
DD
V
OUT
NC
V
OUTA
V
INA
_
V
INA
+
V
DD
V
SS
V
OUTB
V
INB
_
V
INB
+
V
OUTC
V
INC
_
V
INC
+
V
OUTD
V
IND
_
V
IND
+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6285
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
+
-
V
INA
_
V
INA
+
V
SS
V
OUTA/VINB
+
V
OUTB
V
DD
V
INB
_
CS
-
+
MCP6281
SOT-23-5
4
1
2
3
-
+
5
V
DD
VIN–
V
OUT
V
SS
VIN+
MCP6281R
SOT-23-5
4
1
2
3
-
+
5
V
SS
VIN–
V
OUT
V
DD
VIN+
MCP6283
SOT-23-6
4
1
2
3
-
+
6
5
V
SS
VIN+
V
OUT
CS
V
DD
V
IN
_
450 µA, 5 MHz Rail-to-Rail Op Amp
Features
• Gain Bandwidth Product: 5 MHz (typical)
• Supply Current: IQ = 450 µA (typical)
• Supply Voltage: 2.2V to 6.0V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual, and Quad Packages
• Single with C
S (MCP6283)
• Dual with CS (MCP6285)
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description
The Microchip Technology Inc. MCP6281/1R/2/3/4/5
family of operational amplif iers (op amps) provide wi de
bandwidth for the current. This family has a 5 MHz Gain
Bandwidth Product (GBWP) and a 65° phase margin.
This family also operates from a single supply voltage
as low as 2.2V, while drawing 450 µA (typical) quiescent
current. Additionally, the MCP6281/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of V
This family of operational amplifiers is designed with
Microchip’s advanced CMOS process.
The MCP6285 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
input puts the device in Low-power mode.
CS
The MCP6281/1R/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 6.0V.
+300mV to VSS– 300 mV.
DD
Package Types
© 2008 Microchip Technology Inc. DS21811E-page 1
MCP6281/1R/2/3/4/5
1.0 ELECTRICAL CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings †
VDD–VSS........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
All Other Inputs and Outputs ......... V
Difference Input Voltage ...................................... |V
+, VIN–) ††........ VSS–1.0VtoVDD+1.0V
IN
– 0.3V to VDD+0.3V
SS
DD–VSS
|
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (T
)..........................+150°C
J
ESD Protection On All Pins (HBM; MM).............. ≥ 4 kV; 400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25 C, VDD= +2.2V to +5.5V, VSS=GND, V
V
= VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low. (refer to Figure 1-2 and Figure 1-3).
CM
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage V
Input Offset Voltage
OS
V
OS
(Extended Temperature)
Input Offset Temperature Drift ΔV
OS
/ΔT
Power Supply Rejection Ratio PSRR 70 90 — dB V
Input Bias, Input Offset Current and Impedance
Input Bias Current I
At Temperature I
At Temperature I
Input Offset Current I
Common Mode Input Impedance Z
Differential Input Impedance Z
B
B
B
OS
CM
DIFF
Common Mode (Note 4)
Common Mode Input Range V
CMR
Common Mode Rejection Ratio CMRR 70 85 — dB V
Common Mode Rejection Ratio CMRR 65 80 — dB V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) A
OL
Output
Maximum Output Voltage Swing V
Output Short Circuit Current I
, VOHV
OL
SC
Power Supply
Supply Voltage V
Quiescent Current per Amplifier I
Note 1: The MCP6285’s V
for op amp B (pins V
CM
2: The current at the MCP6285’s V
DD
Q
– pin is specified by IB only.
INB
3: This specification does not apply to the MCP6285’s V
4: The MCP6285’s V
The MCP6285’s V
– pin (op amp B) has a common mode range (V
INB
OUTA/VINB
+ pin (op amp B) has a voltage range specified by VOH and VOL.
5: All parts with date codes November 2007 and later have been screened to ensure operation at V
the other minimum and maximum specifications are measured at 2.4V and/or 5.5V.
-3.0 — +3.0 mV VCM = VSS (Note 1)
-5.0 — +5.0 mV TA= -40°C to +125°C,
V
= V
CM
—±1.7—µV/°CT
A
= -40°C to +125°C,
A
V
= VSS (Note 1)
CM
= VSS (Note 1)
CM
— ±1.0 — pA Note 2
— 50 200 pA TA= +85°C (Note 2)
—2 5nAT
= +125°C (Note 2)
A
— ±1.0 — pA Note 3
—1013||6 — Ω||pF Note 3
—1013||3 — Ω||pF Note 3
V
− 0.3 — V
SS
90 110 — dB V
+ 15 — V
SS
+ 0.3 V
DD
= -0.3V to 2.5V, V
CM
= -0.3V to 5.3V, V
CM
= 0.2V to VDD – 0.2V,
OUT
V
CM=VSS
– 15 mV 0.5V input overdrive
DD
—±25—mA
2.2 — 6.0 V (Note 5)
300 450 570 µA IO = 0
OUTA/VINB
+ and V
OUTA/VINB
–) is VSS + 100 mV.
INB
+ pin.
) of VSS + 100 mV to VDD – 100 mV.
CMR
≈ VDD/2,
OUT
(Note 1)
SS
(Note 1)
= 6.0V. However,
DD
DD
DD
= 5V
= 5V
DS21811E-page 2 © 2008 Microchip Technology Inc.
MCP6281/1R/2/3/4/5
V
IL
Hi-Z
t
ON
V
IH
CS
t
OFF
V
OUT
-0.7 µA
Hi-Z
I
SS
I
CS
0.7 µA
0.7 µA
-0.7 µA
-450 µA
10 nA
(typical)
(typical)
(typical)
(typical)
(typical)
(typical)
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, V
V
= VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure1-2 and Figure 1-3).
CM
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 5.0 — MHz
Phase Margin at Unity-Gain PM — 65 — ° G = +1 V/V
Slew Rate SR — 2.5 — V/µs
Noise
Input Noise Voltage E
Input Noise Voltage Density e
Input Noise Current Density i
ni
ni
ni
—5.2— µV
P-P
—16—nV/√Hz f = 1 kHz
—3—fA/√Hz f = 1 kHz
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS
≈ VDD/2,
OUT
f = 0.1 Hz to 10 Hz
Electrical Characteristics: Unless otherwise indicated, T
V
= VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure1-2 and Figure 1-3).
CM
= +25°C, VDD = +2.2V to +5.5V, VSS = GND, V
A
Parameters Sym Min Typ Max Units Conditions
Low Specifications
CS
Logic Threshold, Low V
CS
Input Current, Low I
CS
IL
CSL
V
SS
—0.2VDDV
—0.01—µACS = V
CS High Specifications
Logic Threshold, High V
CS
Input Current, High I
CS
GND Current per Amplifier I
CSH
SS
0.8 V
IH
DD
—VDDV
—0.7 2µACS = V
—-0.7—µACS = V
Amplifier Output Leakage — — 0.01 — µA CS = V
Dynamic Specifications (Note 1)
Low to Valid Amplifier
CS
Output, Turn-on Time
High to Amplifier Output High-Z t
CS
Hysteresis V
Note 1: The input condition (V
at the output of op amp B (V
t
ON
OFF
HYST
) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested
IN
OUTB
).
—410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
V
= VDD/2, V
IN
V
= 5.0V
DD
—0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
V
= VDD/2, V
IN
—0.6—VV
DD
= 5V
SS
DD
DD
DD
OUT
≈ VDD/2,
OUT
OUT
= 0.9 VDD/2,
= 0.1 VDD/2
FIGURE 1-1: Timing Diagram for the Chip
Select (CS)
© 2008 Microchip Technology Inc. DS21811E-page 3
pin on the MCP6283 and MCP6285.
MCP6281/1R/2/3/4/5
V
DD
MCP628X
R
G
R
F
R
N
V
OUT
V
IN
VDD/2
1µF
C
L
R
L
V
L
0.1 µF
V
DD
MCP628X
R
G
R
F
R
N
V
OUT
VDD/2
V
IN
1µF
C
L
R
L
V
L
0.1 µF
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range T
Storage Temperature Range T
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θ
Thermal Resistance, 6L-SOT-23 θ
Thermal Resistance, 8L-PDIP θ
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 8L-MSOP θ
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Note: The Junction Temperature (T
) must not exceed the Absolute Maximum specification of +150°C.
J
A
A
JA
JA
JA
JA
JA
θ
JA
θ
JA
θ
JA
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
-40 — +125 °C Note
-65 — +150 °C
— 256 — °C/W
— 230 — °C/W
—85—°C/W
— 163 — °C/W
— 206 — °C/W
—
—
—
70
120
100
—
—
—
°C/W
°C/W
°C/W
FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.
DS21811E-page 4 © 2008 Microchip Technology Inc.
MCP6281/1R/2/3/4/5
0%
2%
4%
6%
8%
10%
12%
14%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Input Offset Voltage (mV)
Percentage of Occurrences
832 Samples
V
CM
= V
SS
0%
5%
10%
15%
20%
25%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
T
A
= +85°C
-100
-50
0
50
100
150
200
250
300
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.2V
TA = +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0%
5%
10%
15%
20%
25%
30%
-10-8-6-4-20246810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
832 Samples
V
CM
= V
SS
TA = -40°C to +125°C
0%
5%
10%
15%
20%
25%
30%
35%
0
200
400
800
1200
1600
2000
2400
2800
3200
3600
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
T
A
= +125°C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA = +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
= VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
V
L
OUT
≈ VDD/2,
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Current at
=+85 °C.
T
A
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current at
= +125 °C.
T
A
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage at V
© 2008 Microchip Technology Inc. DS21811E-page 5
FIGURE 2-6: Input Offset Voltage vs.
= 2.2V.
DD
Common Mode Input Voltage at V
= 5.5V.
DD
MCP6281/1R/2/3/4/5
-100
-50
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 2.2V
VCM = V
SS
Representative Part
VDD = 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+ 02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR+
PSRR-
CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
V
DD
= 5.5V
Input Bias Current
Input Offset Current
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = V
DD
VDD = 5.5V
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
V
CM
= V
SS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125°C
V
DD
= 5.5V
Input Bias Current
Input Offset Current
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
OUT
≈ VDD/2,
FIGURE 2-7: Input Offset Voltage vs. Output Voltage.
FIGURE 2-8: CMRR, PSRR vs. Frequency.
FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature.
FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature.
FIGURE 2-9: Input Bias, Offset Currents
vs. Common Mode Input Voltage at T
DS21811E-page 6 © 2008 Microchip Technology Inc.
=+85°C.
A
FIGURE 2-12: Input Bias, Offset Currents
vs. Common Mode Input Voltag e at TA= +125°C.
MCP6281/1R/2/3/4/5
0
100
200
300
400
500
600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5
Power Supply Voltage (V)
Quiescent Current
(µA/amplifier)
TA = +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1
1 10 100 1k 10k 100k 1M 10M 100M
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Swing (V
P-P
)
VDD = 2.2V
1k 10k 100k 1M
VDD = 5.5V
10M
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Ouput Voltage Headroom (mV)
VOL - V
SS
VDD - V
OH
0
1
2
3
4
5
6
-50-250 255075100125
Ambient Temperature (°C)
(MHz)
60
65
70
75
80
85
90
Phase Margin (°)
VDD = 5.5V
VDD = 2.2V
VDD = 2.2V
VDD = 5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Rising Edge, VDD = 2.2V
Rising Edge, VDD = 5.5V
Falling Edge, VDD = 5.5V
Falling Edge, VDD = 2.2V
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
5.
OUT
≈ VDD/2,
FIGURE 2-13: Quiescent Current vs. Power Supply Voltage.
FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency.
FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude.
Gain Bandwidth Product
Phase Margin
Gain Bandwidth Product
FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature.
Maximum Output Voltage
FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.
© 2008 Microchip Technology Inc. DS21811E-page 7
FIGURE 2-18: Slew Rate vs. Ambient Temperature.
MCP6281/1R/2/3/4/5
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/
√
Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
(mA)
TA = +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0
50
100
150
200
250
300
350
400
450
500
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Chip Select Voltage (V)
(µA/Amplifier)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.2V
CS swept
high to low
CS swept
low to high
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/
√
Hz)
f = 1 kHz
V
DD
= 5.0V
100
110
120
130
140
1 10 100
Frequency (kHz)
(dB)
0
100
200
300
400
500
600
700
800
900
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
(µA/Amplifier)
Hysteresis
Op Amp toggles On/Off here
VDD = 5.5V
CS swept
low to high
CS swept
high to low
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
OUT
≈ VDD/2,
FIGURE 2-19: Input Noise Voltage Density vs. Frequency.
Ouptut Short Circuit Current
FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage.
FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 1 kHz.
Channel-to-Channel Separation
FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6282 and MCP6284 only).
Quiescent Current
FIGURE 2-21: Quiescent Current vs.
Chip Select (CS
(MCP6283 and MCP6285 only).
DS21811E-page 8 © 2008 Microchip Technology Inc.
) Voltage at VDD = 2.2V
Quiescent Current
FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6283 and MCP6285 only).
MCP6281/1R/2/3/4/5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05
Time (2 µs/div)
Output Voltage (V)
G = +1V/V
V
DD
= 5.0V
Time (500 ns/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05
Time (5 µs/div)
Chip Select, Output Voltages
(V)
V
OUT
Output On
Output High-Z
VDD = 2.2V
G = +1V/V
V
IN
= V
SS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 2.E-06 4.E-06 6.E-06 8 .E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05
Time (2 µs/div)
Output Voltage (V)
G = -1V/V
V
DD
= 5.0V
Time (500 ns/div)
Output Voltage (10 mV/div)
G = -1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05
Time (5 µs/div)
Chip Select, Output Voltages
(V)
V
OUT
Output OnOutput High-Z
VDD = 5.5V
G = +1V/V
V
IN
= V
SS
CS Voltage
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
OUT
≈ VDD/2,
FIGURE 2-25: Large-Signal, Non-inverting Pulse Response.
FIGURE 2-26: Small-Signal, Non-inverting Pulse Response.
FIGURE 2-28: Large-Signal, Inverting Pulse Response.
FIGURE 2-29: Small-Signal, Inverting Pulse Response.
FIGURE 2-27: Chip Select (CS
Amplifier Output Response Time at V
(MCP6283 and MCP6285 only).
© 2008 Microchip Technology Inc. DS21811E-page 9
) to
= 2.2V
DD
FIGURE 2-30: Chip Select (CS
Amplifier Output Response Time at V
(MCP6283 and MCP6285 only).
) to
DD
= 5.5V
MCP6281/1R/2/3/4/5
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
-1
0
1
2
3
4
5
6
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2 V/V
V
IN
V
OUT
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, V
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
+125°C
+85°C
+25°C
-40°C
FIGURE 2-31: Measured Input Current vs.
Input Voltage (below V
SS
).
FIGURE 2-32: The MCP6281/1R/2/3/4/5 Show No Phase Reversal.
OUT
≈ VDD/2,
DS21811E-page 10 © 2008 Microchip Technology Inc.
MCP6281/1R/2/3/4/5
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6281 MCP6281R MCP6283
PDIP, SOIC,
MSOP
SOT-23-5 SOT-23-5
PDIP, SOIC,
MSOP
SOT-23-6
611 6 1V
244 2 4V
333 3 3V
752 7 6V
425 4 2V
——— 8 5CS
1,5,8 — — 1,5 — NC No Internal Connection
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6282 MCP6284 MCP6285
PDIP, SOIC, MSOP
11—V
222V
333V
848V
55—V
666V
777V
—8—V
—9—V
—10—V
4114V
—12—V
—13—V
—14—V
—— 1V
—— 5CS
PDIP, SOIC, TSSOP
PDIP, SOIC, MSOP
Symbol Description
Analog Output
OUT
– Inverting Input
IN
+ Non-inverting Input
IN
Positive Power Supply
DD
Negative Power Supply
SS
Chip Select
Symbol Description
Analog Output (op amp A)
OUTA
– Inverting Input (op amp A)
INA
+ Non-inverting Input (op amp A)
INA
Positive Power Supply
DD
+ Non-inverting Input (op amp B)
INB
– Inverting Input (op amp B)
INB
Analog Output (op amp B)
OUTB
Analog Output (op amp C)
OUTC
– Inverting Input (op amp C)
INC
+ Non-inverting Input (op amp C)
INC
Negative Power Supply
SS
+ Non-inverting Input (op amp D)
IND
– Inverting Input (op amp D)
IND
Analog Output (op amp D)
OUTD
/
OUTA
V
Analog Output (op amp A)/Non-
+
inverting Input (op amp B)
INB
Chip Select
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.4 Chip Select Digital Input (CS)
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.2 Analog Inputs
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3 MCP6285’s V
OUTA/VINB
For the MCP6285 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the V
OUTA/VINB
+ Pin
+ pin. This connection
3.5 Power Supply Pins
The positive power supply (VDD) is 2.2V to 6.0V higher
than the negative power supply (V
operation, the other pins are between V
Typically, these parts are used in a single (positive)
supply configuration. In this case, V
ground and V
is connected to the supply. VDD will
DD
need bypass capacitors.
). For normal
SS
and VDD.
SS
is connected to
SS
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
© 2008 Microchip Technology Inc. DS21811E-page 11
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