MICROCHIP MCP6241, MCP6242, MCP6244 Technical data

MCP6241/2/4

50 µA, 550 kHz Rail-to-Rail Op Amp

Features

• Gain Bandwidth Product: 550 kHz (typ.)

• Supply Current: I

= 50 µA (typ.)

Q

• Supply Voltage: 1.8V to 5.5V

• Rail-to-Rail Input/Output

• Extended Temperature Range: -40°C to +125°C

• Available in 5-pin SC-70 and SOT-23 packages

Applications

• Automotive

• Portable Equipment

• Photodiode (Transimpedance) Amplifier

• Analog Filters

• Notebooks and PDAs

• Battery-Powered Systems

Available Tools

• SPICE Macro Models (at www .m ic rochi p.c om )

•FilterLab® Software (at www.microchip.com)

Typical Application

R

G2

V

IN2

R

G1

V

IN1

V

DD

R

X

R

Y

R

Z

Summing Amplifier Circuit

R

F

–

MCP6241

+

V

OUT

Description

The Microchip Technology Inc. MCP6241/2/4
operational amplifiers (op amps) provide wide
bandwidth for the quiescent current. The MCP6241/2/4
has a 550 kHz Gain Bandwidth Pro duct (GBWP) and
68° (typ.) phase ma rgin. This family operates from a
single supply voltage as low as 1.8V, while drawing
50 µA (typ.) quiescent current. In addition, the
MCP6241/2/4 family supports rail-to-rail input and
output swing, with a common mode input voltage range

+ 300 mV to VSS– 300 mV. These op amps are

of V

DD

designed in one of Microchip’s advanced CMOS
processes.

Package Types

MCP6241

SOT-23-5

V

V

1

1

OUT

OUT

V

V

VIN+

SS

SS

+

+

2

2
3

3

–

MCP6241R

SOT-23-5

V

1

OUT

V

DD

VIN+

+

2

–

3

MCP6241U

SC-70-5, SOT-23-5

VIN+

1

V

VIN–

SS

+

2

–

3

V

V

5

5

DD

DD

VIN–

4

4

V

V

5

SS

VIN–

4

V

V

5

DD

V
V

V

4

OUT

V
V

V

MCP6241

PDIP, SOIC, MSOP

1

NC

2

–

V

IN

VIN+

V

–
+

3
4

SS

MCP6242

PDIP, SOIC, MSOP

1

OUTA

_

V

2

-

INA

V

INA

V

SS

+

+

3

+

-

4

MCP6244

PDIP, SOIC, TSSOP

OUTA

INA
INA

V

DD

INB
INB

OUTB

1

–

-

2

+

3
4

+

5

-

–

6
7

14

+-+

13
12
11

10

-

+

+

8

NC
V

7

DD

6

V

OUT

5

NC

V

8

DD

7

V

OUTB

_

6

V

INB

5

V

+

INB

V

OUTD

V

–

IND

V

+

IND

V

SS

+

V

INC

9

–

V

INC

8

V

OUTC

© 2005 Microchip Technology Inc. DS21882C-page 1

MCP6241/2/4

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

VDD – VSS........................................................................7.0V

All Inputs and Outputs ................... V

Difference Input Voltage ......................................|V

Output Short Circuit Current ..................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage Temperature.................................... .-65°C to +150°C

Maximum Junction Temperature (T

ESD Protection On All Pins (HBM;MM)............... ≥ 4 kV; 300V

– 0.3V to VDD + 0.3V

SS

– VSS|

DD

)..........................+150°C

J

† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

Electrica l Character istics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,

V

= VDD/2, RL = 100 kΩ to VDD/2 and V

CM

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage V
Extended Temperature V

Input Offset Drift with

ΔVOS/ΔT

Temperature
Power Supply Rejection PSRR — 83 — dB VCM = V

Input Bias Current and Impedance

Input Bias Current: I
At Temperature I
At Temperature I
Input Offset Current I
Common Mode Input Impedance Z
Differential Input Impedance Z

DIFF

Common Mode

Common Mode Input Range V

CMR

Common Mode Rejection Ratio CMRR 60 75 — dB V
Open-Loop G ain
DC Open-Loop Gain

A

(large signal)

Output

Maximum Output Voltage Swing VOL, VOHVSS + 35 — VDD – 35 mV RL = 10 kΩ, 0.5V Output

Output Short-Circuit Current I

I

Power Supply

Supply Voltage V
Quiescent Current per Amplifier I

Note:

The SC-70 package is only tested at +25°C.

OS
OS

OS

CM

OL

SC
SC

DD
Q

≈ V

OUT

/2.

DD

-5.0 — +5.0 mV VCM = V

SS

-7.0 — +7.0 mV TA= -40°C to +125°C,
= VSS (Note)

V

CM

—±3.0—µV/°CT

A

B
B
B

—±1.0—pA
—20—pAT
— 1100 — pA TA = +125°C

= -40°C to +125°C,

A

V

= V

CM

SS
SS

= +85°C

A

—±1.0—pA
—1013||6 — Ω||pF
—1013||3 — Ω||pF

V

– 0.3 — V

SS

90 110 — dB V

+ 0.3 V

DD

= -0.3V to 5.3V, V

CM

= 0.3V to VDD – 0.3V,

OUT

V

CM=VSS

Overdrive
—±6—mAV
—±23—mAV

DD
DD

= 1.8V
= 5.5V

1.8 — 5.5 V
30 50 70 µA IO = 0, VCM = VDD – 0.5V

DD

= 5V

DS21882C-page 2 © 2005 Microchip Technology Inc.

MCP6241/2/4

AC ELECTRICAL CHARACTERISTICS

Electrica l Character istics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,

≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.

V

OUT

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 550 — kHz
Phase Margin PM — 68 — ° G = +1
Slew Rate SR — 0.30 — V/µs

Noise

Input Noise Voltage E
Input Noise Voltage Density e
Input Noise Current Density i

ni
ni

ni

—10—µV
—45—nV/√Hz f = 1 kHz
—0.6—fA/√Hz f = 1 kHz

TEMPERATURE CHARACTERISTICS

Electrica l Character istics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Extended Temperature Range T
Operating Tempe rature Range T
Storage Temperature Range T

A
A
A

Thermal Package Resistances

Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-MSOP θ

Thermal Resistance, 8L-PDIP θ
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 14L-PDIP θ
Thermal Resistance, 14L-SOIC θ
Thermal Resistance, 14L-TSSOP θ

θ

JA

θ

JA
JA
JA
JA
JA
JA
JA

Note: The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

-40 — +125 °C

-40 — +125 °C (Note)

-65 — +150 °C

—
—

331
256

—
—

—206—°C/W
—85—°C/W
—163—°C/W
—70—°C/W
—120—°C/W
—100—°C/W

f = 0.1 Hz to 10 Hz

P-P

°C/W
°C/W

© 2005 Microchip Technology Inc. DS21882C-page 3

MCP6241/2/4

5

:

2.0 TYPICAL PERFORMANCE CURVES

Note: The grap hs and tables provided fol lowi ng this note are a st a tis tic al s umm ary based on a limite d number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 100 kΩ to VDD/2 and CL = 60 pF.

R

L

OUT

≈ VDD/2,

20%

630 Samples

Percentage of Occurrences

18%
16%
14%
12%
10%

8%
6%
4%
2%
0%

= V

V

CM

SS

0

1

2

-5

-4

-3

-2

-1

Input Offset Voltage (mV)

3

FIGURE 2-1: Input Offset Voltage.

110
100

90
80
70
60
50

PSRR, CMRR ( dB )

40
30
20

10 1k 10k 100k100

1.E+01 1.E+02 1.E+03 1.E+04 1.E+0

PSRR-

CMRR

PSRR+

Frequency (Hz)

90

85

80

75

CMRR, PSRR (dB)

4

5

CMRR (VCM = -0.3V to +5.3V,

70

-50-25 0 255075100125

PSRR (VCM = VSS)

= 5.0V)

V

DD

Ambient Temperature (°C)

FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature.

120

100

80

60

Phase

40

20

Open-Loop Gain (dB)

0

-20

0.1 1 10 100 1k 10k 100k 1M 10M

1.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+

Gain

Frequency (Hz)

RL = 10.0 k

= VDD/2

V

CM

0

-30

-60

-90

-120

-150
Open-Loop Phase (°)

-180

-210

07

FIGURE 2-2: PSRR, CMRR vs. Frequency.

25%

180 Samples

= VDD/2

V

CM

20%

= +85°C

T

A

15%

10%

5%

Percentage of Occurrences

0%

0

6

12

18

24

30

36

Input Bias Current (pA)

42

FIGURE 2-3: Input Bias Current at +85°C.

FIGURE 2-5: Open-Loop Gain, Phase vs.

Frequency.

30%

180 Samples
V

5%
0%

= VDD/2

CM

T

= +125°C

A

0.0

0.2

0.4

0.6

0.8

Input Bias Current (nA)

1.0

1.2

1.4

1.6

1.8

2.0

25%
20%
15%
10%

Percentage of Occurrences

FIGURE 2-6: Input Bias Current at +125°C.

DS21882C-page 4 © 2005 Microchip Technology Inc.

MCP6241/2/4



= +125°C

= +125°C

5

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 100 kΩ to VDD/2 and CL = 60 pF.

R

L

10,000

1,000

Hz)

(nV/

100

Input Noise Voltage Density

10

0.1 100 1k 10k 100k101

1.E-01 1.E+001.E+011.E+021.E+031.E+041.E+0

Frequency (Hz)

5

FIGURE 2-7: Input Noise Voltage Density

20%

628 Samples

18%

V

= V

CM

SS

TA = -40°C to +125°C

-8-6-4

-12

-10
Input Offset Voltage Drift (µV/°C)

-2

0

Percentage of Occurrences

16%
14%
12%
10%

8%
6%
4%
2%
0%

FIGURE 2-10: Input Offset Voltage Drift.

vs. Frequency.

700
650
600
550
500
450

VDD = 1.8V

400
350

Input Offset Voltage (µV)

300

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)

VCM = V

Input Offset Voltage (µV)

300
200
100

-100

-200

-300

0

TA = -40°C
T
T
T

-0.4

= +25°C

A

= +85°C

A
A

0.0

0.2

0.4

0.6

0.8

-0.2
Common Mode Input Voltage (V)

1.0

1.2

VDD = 1.8V

1.4

1.6

1.8

2.0

2.2

≈ VDD/2,

OUT

2

4

SS

VDD = 5.5V

6

8

10

12

FIGURE 2-8: Input Offset Voltage vs.
Common Mode Input Voltage at V

400
300
200
100

TA = -40°C

0

T

= +25°C

A

T

= +85°C

A

-100
T

-200

A

0.0

0.5

1.0

1.5

2.0

-0.5
Common Mode Input Voltage (V)

2.5

3.0

Input Offset Voltage (µV)

3.5

= 1.8V.

DD

VDD = 5.5V

4.0

4.5

5.0

5.5

6.0

FIGURE 2-9: Input Offset Voltage vs.
Common Mode Input Voltage at V

= 5.5V.

DD

FIGURE 2-11: Input Offset Voltage vs. Output Voltage.

35
30
25
20
15
10

5
0

-5

-10

-15

-20

-25

Short Circuit Current (mA)

-30

-35

0.00.51.01.52.02.53.03.54.04.55.05.
Power Supply Voltage (V)

+I

SC

-I

SC

TA = +125°C
T

= +85°C

A

T

= +25°C

A

T

= -40°C

A

FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature.

© 2005 Microchip Technology Inc. DS21882C-page 5

MCP6241/2/4

1

6

Max. Output Voltage Swing

:

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 100 kΩ to VDD/2 and CL = 60 pF.

R

L

0.50

0.45

0.40

Falling Edge

0.35

0.30

0.25

Slew Rate (V/µs)

0.20

0.15

Rising Edge

0.10

-50 -25 0 25 50 75 100 125

FIGURE 2-13: Slew Rate vs. Ambient Temperature.

1,000

100

(mV)

10

Output Voltage Headroom

1

1.E-02 1.E-01 1.E+00 1.E+0

VDD = 5.5V

VDD = 1.8V

Ambient Temperature (°C)

VDD – V

OH

VOL – V

100µ10µ

Output Current Magnitude (A )

Output Voltage (10 mV/div)

Time (1 µs/div)

FIGURE 2-16: Sm al l-Signal, Non-Inverting Pulse Response.

5.0

4.5

4.0

3.5

3.0

SS

10m1m

2.5

2.0

1.5

Output Voltage (V)

1.0

0.5

0.0
Time (10 µs/div)

OUT

≈ VDD/2,

G = +1 V/V

R

= 10 k

L

VDD = 5.0V
G = +1 V/V

FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude.

10

VDD = 5.5V

)

VDD = 1.8V

P-P

1

(V

0.1

1k 10k 100k 1M

1.E+03 1.E+04 1.E+05 1.E+0

Frequency (Hz)

FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.

FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response.

80

VCM = 0.9V

70
60
50
40
30
20

per Amplifier (µA)

Quiescent Current

10

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

DD

TA = +125°C
T
T
T

Power Supply Voltage (V)

= +85°C

A

= +25°C

A

= -40°C

A

FIGURE 2-18: Quiescent Current vs. Power Supply Voltage.

DS21882C-page 6 © 2005 Microchip Technology Inc.

MCP6241/2/4

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).

TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS

MCP6241

(PDIP, SOIC, MSOP)

6114V
2443V
3331V
7525V
4252V

1, 5, 8 — — — NC No Internal Connection

TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS

MCP6242 MCP6244 Symbol Description

11V
22V
33V
84V
55V
66V

77V
—8V
—9V
—10V

411V
—12V
—13V
—14V

MCP6241

(SOT-23-5)

MCP6241R

(SOT-23-5)

OUTA

– Inverting Input (op amp A)

INA

+ Non-inverting Input (op amp A)

INA

DD

+ Non-inverting Input (op amp B)

INB

– Inverting Input (op amp B)

INB
OUTB
OUTC

– Inverting Input (op amp C)

INC

+ Non-inverting Input (op amp C)

INC

SS

+ Non-inverting Input (op amp D)

IND

– Inverting Input (op amp D)

IND

OUTD

MCP6241U

(SOT-23-5)

Analog Output (op amp A)

Positive Power Supply

Analog Output (op amp B)
Analog Output (op amp C)

Negative Power Supply

Analog Output (op amp D)

Symbol Description

OUT

IN
IN

Analog Outp ut
– Inverting Input
+ Non-inverting Input

Positive Power Supply

DD

Negative Power Supply

SS

3.1 Analog Outputs

The output pins are low-impedance voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs are high­impedance CMOS inputs with low bias currents.

3.3 Power Supply (VSS and VDD)

The positive powe r s upp ly (VDD) is 1.8V to 5.5V h igh er
than the negative power supply (V
operation, the other pins are between V

Typically, these parts are used in a single-(positive)
supply configuration. In this case, V
ground and V

is connected to the supply. VDD will

DD

). For normal

SS

and VDD.

SS

is connected to

SS

need a local bypass capacitor (typically 0.01µF to

0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor (typically 1 µ F to 100 µF) with
other nearby analog part s; it needs to be within 100 mm
of the V

© 2005 Microchip Technology Inc. DS21882C-page 7

DD

pin.

MCP6241/2/4

4.0 APPLICATION INFORMATION

The MCP6241/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power and general­purpose applications. The low supply voltage, low
quiescent current and wide bandwidth makes the
MCP6241/2/4 ideal for battery-powered applications.

4.1 Rail-to-Rail Inputs

The MCP6241/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Fi gure 4-1 shows the input volt age excee ding
the supply voltage without any phase reversal.

6

V

5
4
3
2
1
0

Input, Output Voltage (V)

-1

V

OUT

IN

Time (1 ms/div)

FIGURE 4-1: The MCP6241/2/4 Show No Phase Reversal.

The input stage of the MCP6241/2/4 op amps use two
differential input s tages in paralle l. One op erates at low
common mode input voltage (VCM) and the other at
high V
V

CM

The Input Offset Voltage is measured at
VCM=VSS– 300 mV and VDD+ 300 mV to ensure
proper operation.

Input voltages that exceed the input voltage range
(V
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.

. With this topology, the device operates with

CM

up to 300 mV above VDD and 300 mV below VSS.

– 0.3V to VDD+ 0.3V at 25°C) can cause

SS

VDD = 5.0V
G = +2 V/V

–

IN

V

OUT

R

IN

V

IN

Maximum expected V

()VDD–

------------------------------------------------------------------------------ -

R

≥

IN

VSSMinimum expected V

----------------------------------------------------------------------------

R

≥

IN

MCP624X
+

IN

2 mA

()–

2 mA

FIGURE 4-2: Input Current-Limiting
Resistor (R

IN

).

4.2 Rail-to-Rail Output

The output volt age rang e of the MC P6241/2/4 op a mps

– 35 mV (max.) and VSS + 35 mV (min.) when

is V

DD

=10kΩ is connected to VDD/2 and VDD = 5.5V.

R

L

Refer to Figure 2 -14 for more information.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.

When driving large capacitive loads with these op
amps (e.g., > 70 pF when G = +1), a small series
resistor at the output (R
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capac itive load.

–
MCP624X

V

IN

+

in Figure 4-3) improves the

ISO

R

ISO

C

L

V

OUT

FIGURE 4-3: Output resistor, R

ISO

stabiliz es large capacitive loads.

Figure 4-4 gives recommended R
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C

L/GN

circuit’s nois e gain. For non -inverting ga ins, G
signal gain are equal. For inverting gains, G
1 + |Signal Gain| (e.g., –1 V/V gives G

DS21882C-page 8 © 2005 Microchip Technology Inc.

values for

ISO

), where GN is the

and the

N

is

= +2 V/V).

N

N

MCP6241/2/4

:

1.E+04

10k

)
(

ISO

1k

1.E+03

Recommended R

100

1.E+02

10p 100p 1n 10n

1.E+01 1.E+02 1.E+03 1.E+04

Normalized Load Capacitance; C

FIGURE 4-4: Recommended R

GN = +1 V/V
G

t +2 V/V

N

L/GN

(F)

ISO

Values

for Capacitive Loads.

After sele cting R
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6241/2/4 SPICE macro
model are very helpful. Modify R
response is reasonable.

for your circuit, double-check the

ISO

’s value until the

ISO

4.4 Supply Bypass

With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high­frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger ) within 100 mm to provide la rge,
slow currents. This bu lk capaci tor can be sh ar ed with
other nearby analog parts.

4.5 Unused Op Amps

An unused op amp in a quad package (MCP6244)
should be configured as shown in Figure 4-5. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.

¼ MCP6244 (A) ¼ MCP6244 (B)

V

DD

V

DD

4.6 PCB Surface Leakage

In applications where low input bias current is critical,
PCB (printed circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1 0
cause 5 pA of current to flow, which is greater than the
MCP6241/2/4 family’ s bias c urrent at 25°C (1 pA, typ.).

The easiest way to reduce surface leakage is to use a
guard ring around se nsi tiv e p ins (or t race s). The gua rd
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.

VIN-V

FIGURE 4-6: Example Guard Ring Layout for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (V

input with a wire that does not touch the
PCB surface.

b. Connect the guard ring to th e inverting input

–). This biases the g uard rin g t o th e

pin (V

IN

common mode input voltage.

2. Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):

a. Connect the guard ring to the non-inverting

input pin (V
to the same reference voltage as the op
amp (e.g., V

b. Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB
surface.

12

Ω. A 5V dif ference would

+

IN

V

SS

Guard Ring

+) to the

IN

+). This bi ases the gua rd ri ng

IN

/2 or ground).

DD

V

DD

FIGURE 4-5: Unused Op Amps.

© 2005 Microchip Technology Inc. DS21882C-page 9