MICROCHIP MCP6141, MCP6142, MCP6143, MCP6144 Technical data
M
MCP6141/2/3/4
600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps
Features
• Low Quiescent Current: 600 nA/Amplifier (typ.)
• Stable for gains of 10 V/V or higher
• Rail-to-Rail Input: -0.3V (min.) to V
+ 0.3V (max.)
DD
• Rail-to-Rail Output:
+10 mV (min.) to VDD-10 mV (max.)
-V
SS
• Gain Bandwidth Product: 100 kHz (typ.)
• Wide Supply Voltage Range: 1.4V to 5.5V (max.)
• Available in Single, Dual and Quad
• Chip Select (CS
) with MCP6143
Applications
• Toll Booth Tags
• Wearable Products
• Temperature Measurement
• Battery-Powered
Available Tools
• Spice macro models (at www.microchip.com)
• FilterLab
®
Software (at www.microchip.com)
Package Types
MCP6141
PDIP, SOIC, MSOP
NC
1
-IN
2
+
+IN
3
V
4
SS
MCP6143
PDIP, SOIC, MSOP
NC
1
2
-
-IN
+
3
+IN
V
4
SS
8
NC
7
V
OUT
6
NC
5
CS
8
V
7
OUT
6
NC
5
OUTA
DD
DD
MCP6142
PDIP, SOIC, MSOP
1
A
-
+
2
-INA
+INA
V
SS
PDIP, SOIC, TSSOP
OUTA
-INA1
+INA1
V
DD
+INB
-INB
3
4
MCP6144
1
A
2
-
+
3
4
5
-
+
6
B
7OUTB1
B
-
+
D
-
+
-
+
C
8
7
6
5
14
13
12
11
10
9
8
V
DD
OUTB
-INB
+INB
OUTD
-IND
+IND
V
SS
+INC
-INC
OUTC
Description
The MCP6141/2/3/4 family of non-unity gain stable
operational amplifiers (op amps) from Microchip
Technology, Inc. operate with a single supply voltage
as low as 1.4V, while drawing less than 1 µA (max.) of
quiescent current per amplifier. These devices are also
designed to support rail-to-rail input and output swing.
The MCP6141/2/3/4 op amps have a gain bandwidth
product of 100 kHz (typ.) and are stable for gains of
10 V/V or higher. This specification makes these
devices appropriate for battery-powered applications
where higher frequency responses from the amplifier
are required.
The MCP6141/2/3/4 family of op amps are offered in
single (MCP6141), single with a Chip Select (CS
) feature (MCP6143), dual (MCP6142) and quad
(MCP6144) configurations.
Typical Applications
V
DD
I
1k Ω
DD
+1.4V
to
5.5V
R
I
100 k Ω
High Side Battery Current Sensor
R
G
1
n
R
V
V
V
V
REF
1
1
R
2
2
R
3
3
------+
I
1
I
2
I
3
MCP614X
Summing Amplifier
1
1R
G
n
----- -
+ 10V/V≥=
F
R
1
MCP614X
R
F
R
I
R
F
1
----- -
R
2
V
DD
= 1 MΩ
F
10V/V≥=
I
F
1
----- -++
R
3
V
SS
V
OUT
2002 Microchip Technology Inc. 21668A-page 1
MCP6141/2/3/4
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings†
V
- VSS.........................................................................7.0V
DD
All inputs and outputs........................ V
Difference Input voltage ....................................... |V
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
-0.3V to VDD +0.3V
SS
DD
- VSS|
PIN FUNCTION TABLE
Name Function
+IN/+INA/+INB/+INC/+IND Non-inverting Inputs
-IN/-INA/-INB/-INC/-IND Inverting Inputs
V
DD
V
SS
OUT/OUTA/OUTB/OUTC/OUTD Outputs
CS
NC No internal connection
Positive Power Supply
Negative Power Supply
Chip Select
Storage temperature ..................................... -65°C to +150°C
Junction Temperature, T
............................................ +150°C
J
ESD protection on all pins (HBM:MM).................. ≥ 4kV:200V
†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C,
V
= VDD/2, R
CM
Input Offset
Input Offset Voltage V
Drift with Temperature ∆V
Power Supply Rejection PSRR 70 85 — dB
Input Bias Current and Impedance
Input Bias Current I
Input Bias Current Over-Temperature I
Input Offset Current I
Common Mode Input Impedance Z
Differential Input Impedance Z
Common Mode
Common-Mode Input Range VCMR V
Common-Mode Rejection Ratio CMRR 62 80 — dB V
Open Loop Gain
DC Open Loop Gain (large signal) A
Output
Maximum Output Voltage Swing VOL, VOHVSS + 10 — V
Output Short Circuit Current I
Power Supply
Supply Voltage V
Quiescent Current per amplifier I
= 1 MΩ to V
L
/2, and V
DD
OUT
~ VDD/2.
Parameters Sym Min Typ Max Units Conditions
VCM = V
SS
OS
OS
B
B
OS
CM
DIFF
OL
O
DD
Q
-3.0 — +3.0 mV
/∆T— ±1.5 — µV/°CT
= -40°C to +85°C
A
—1.0— pA
——100pAT
= -40°C to +85°C
A
—1.0— pA
—10
—10
− 0.3 — V
SS
60 75 — dB V
60 80 — dB V
95 115 — dB R
—21—mAV
13
||6 — Ω||pF
13
||6 — Ω||pF
+ 0.3 V
DD
− 10 mV RL = 50 kΩ to V
DD
= 5V,
DD
V
= -0.3V to 5.3V
CM
= 5V,
DD
V
= 2.5V to 5.3V
CM
= 5V,
DD
V
= -0.3V to 2.5V
CM
= 50 kΩ to V
L
100 mV < V
(V
− 100 mV)
DD
OUT
1.4 — 5.5 V
0.3 0.6 1.0 µA IO = 0
OUT
= 2.5V, VDD = 5 V
DD
<
DD
/2,
/2
21668A-page 2 2002 Microchip Technology Inc.
MCP6141/2/3/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +5V, VSS = GND, TA = 25 °C,
V
= VDD/2, R
CM
Gain Bandwidth Product GBWP — 100 — kHz
Slew Rate SR — 24 — V/ms
Phase Margin PM — 60 — ° G = +10
Input Voltage Noise E
Input Voltage Noise Density e
Input Current Noise Density i
SPECIFICATIONS FOR MCP6143 CHIP SELECT FEATURE
Electrical Characteristics: Unless otherwise indicated, all limits are specified for V
V
= VDD/2, R
CM
CS Low Specifications
CS Logic Threshold, Low V
CS
Input Current, Low I
CS High Specifications
CS Logic Threshold, High V
CS
Input Current, High I
CS Input High, GND Current I
Amplifier Output Leakage, CS High — 20 — pA CS = V
Dynamic Specifications
CS Low to Amplifier Output High
Turn-on Tim e
High to Amplifier Output High Z
CS
Hysteresis V
= 1 MΩ to V
L
/2, CL = 60 pF, and V
DD
OUT
~ VDD/2.
Parameters Sym Min Typ Max Units Conditions
— 5.0 — µVp-p f = 0.1 Hz to 10 Hz
—170—nV/√Hz f = 1 kHz
—0.6—fA/√Hz f = 1 kHz
= +1.4V to +5.5V, VSS = GND, TA = 25 °C,
DD
~ VDD/2.
= 1 MΩ to V
L
/2, CL = 60 pF, and V
DD
n
n
n
OUT
Parameters Sym Min Typ Max Units Conditions
CSL
CSH
t
ON
t
OFF
HYST
IL
V
SS
—5.0—pACS = V
VDD - 0.3 — V
IH
—5.0—pACS = V
Q
—20—pACS = V
—2.050msCS low = VSS + 0.3V, G = +1 V/V,
—10—µsCS high = VDD - 0.3V, G = +1 V/V
—0.6— VV
—VSS + 0.3 V For entire VDD range
SS
DD
V For entire VDD range
DD
DD
DD
V
= 0.9 VDD/2
OUT
V
= 0.1 VDD/2
OUT
= 5V
DD
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for V
Parameters Symbol Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T
Operating Temperature Range T
Storage Temperature Range T
A
A
A
-40 — +85 °C
-40 — +125 °C Note 1
-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θ
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 8L-MSOP θ
Thermal Resistance, 14L-PDIP θ
Thermal Resistance, 14L-SOIC θ
Thermal Resistance, 14L-TSSOP θ
JA
JA
JA
JA
JA
JA
—
—
—
—
—
—
Note 1: The MCP6141/2/3/4 family of op amps operates over this extended range, but with reduced performance.
2002 Microchip Technology Inc. 21668A-page 3
85
163
206
70
108
100
= +1.4V to +5.5V, V
DD
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
SS
= GND.
MCP6141/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V
and V
OUT~VDD
/2.
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
= 1 MΩ to V
L
DD
/2, C
= 60 pF,
L
16%
1200 Samples
14%
VDD = 5.5 V
12%
10%
8%
6%
4%
2%
Percentage of Occurrences
0%
-3 -2 -1 0 1 2 3
Input Offset Voltage (mV)
FIGURE 2-1: Histogram of Input Offset
Voltage with V
16%
1200 Samples
14%
VDD = 1.4 V
12%
10%
8%
6%
4%
2%
Percentage of Occurrences
0%
-3 -2 -1 0 1 2 3
= 5.5V.
DD
Input Offset Voltage (mV)
35%
1200 Samples
30%
VDD = 1.4 V
25%
20%
15%
10%
5%
Percentage of Occurrences
0%
-10 -5 0 5 10
Input Offset Voltage Drift (µV/°C)
FIGURE 2-4: Histogram of Input Offset
Voltage Drift with V
600
VDD = 1.4 V
400
200
0
-200
-400
Input Offset Voltage (µV)
-600
-0.5 0.0 0.5 1.0 1.5 2.0
Common Mode Input Voltage (V)
= 1.4V.
DD
TA = +85°C
= +25°C
T
A
T
= -40°C
A
FIGURE 2-2: Histogram of Input Offset
Voltage with V
35%
1200 Samples
30%
VDD = 5.5 V
25%
20%
15%
10%
5%
Percentage of Occurrences
0%
-10 -5 0 5 10
= 1.4V.
DD
Input Offset Voltage Drift (µV/°C)
FIGURE 2-3: Histogram of Input Offset
Voltage Drift with V
= 5.5V.
DD
FIGURE 2-5: Input Offset Voltage vs.
Common Mode Input Voltage vs. Temperature
with V
= 1.4V.
DD
600
VDD = 5.5 V
400
200
0
-200
-400
Input Offset Voltage (µV)
-600
-0.5 0.5 1.5 2.5 3.5 4.5 5.5
TA = +85°C
T
T
Common Mode Input Voltage (V)
= +25°C
A
= -40°C
A
TA = +85°C
= +25°C
T
A
= -40°C
T
A
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage vs. Temperature
with V
= 5.5V.
DD
21668A-page 4 2002 Microchip Technology Inc.
MCP6141/2/3/4
Note: Unless otherwise indicated, V
and V
OUT~VDD
500
450
400
350
300
Input Offset Voltage (µV)
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
/2.
VDD = 1.4 V
Output Voltage (V)
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
RL = 50 k:
VDD = 5.5 V
FIGURE 2-7: Input Offset Voltage vs. Output Voltage vs. Power Supply Voltage.
1,000
Hz)
(nV/
Input Noise Voltage Density
100
0.1 1 10 100 1000
Eni = 4.7 µV
= 167 nV/Hz, f = 1 kHz
e
ni
Frequency (Hz)
, f = 0.1 to 10 Hz
P-P
= 1 MΩ to V
L
50
TA = 85°C
V
= 5.5 V
DD
40
30
20
10
0
Input Bias, Offset Currents (pA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
/2, C
DD
Input Bias Current
Input Offset Current
= 60 pF,
L
FIGURE 2-10: Input Bias, Offset Currents vs. Common Mode Input Voltage with Temperature = 85°C.
300
250
200
Hz)
150
(nV/
100
50
Input Noise Voltage Density
0
-0.5 0.5 1.5 2.5 3.5 4.5 5.5
Common Mode Input Voltage (V)
f = 1 kHz
VDD = 5.0 V
FIGURE 2-8: Input Noise Voltage Density vs. Frequency.
100
90
80
70
60
50
40
CMRR, PSRR (dB)
30
20
1 10 100 1000
PSRR-
CMRR
10 100
Frequency (Hz)
PSRR+
VDD = 5.0 V
Referred to Input
FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency.
FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage.
100
95
90
85
80
CMRR, PSRR (dB)
75
70
-40-20 0 20406080
CMRR (VDD = 5.0 V,
V
CM
Ambient Temperature (°C)
PSRR (VCM = VSS)
= -0.3 V to +5.3 V)
FIGURE 2-12: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature.
2002 Microchip Technology Inc. 21668A-page 5
MCP6141/2/3/4
k
k
r
Note: Unless otherwise indicated, V
and V
OUT~VDD
50
40
30
(pA)
20
10
Input Bias and Offset Currents
0
/2.
VCM = V
DD
VDD = 5.5 V
25 35 45 55 65 75 85
Ambient Temperature (°C)
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
Input Bias
Current
Input Offset
Current
FIGURE 2-13: Input Bias and Offset Currents vs. Ambient Temperature.
120
100
80
60
40
20
0
Open-Loop Gain (dB)
VDD = 5.5 V
-20
0.1
0.01
Phase
1
Frequency (Hz)
Gain
10
100
1
1000
10k
10000
100
100000
0
-30
-60
-90
-120
-150
-180
Open-Loop Phase (°)
-210
= 1 MΩ to V
L
0.7
0.6
0.5
0.4
(mA)
0.3
0.2
0.1
Quiescent Current per amplifie
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5 6.0 6.5 7.0
TA = 85°C
TA = 25°C
TA = -40°C
Power Supply Voltage (V)
DD
/2, C
= 60 pF,
L
FIGURE 2-16: Quiescent Current Vs. Power Supply Voltage vs. Temperature.
140
130
120
110
100
90
80
DC Open-Loop Gain (dB)
70
60
100
VDD = 5.5 V
V
= 0.5 V to 5.0 V
OUT
VDD = 1.4 V
V
= 0.5 V to 0.9 V
OUT
1k 10k 100k
Load Resistance (:)
FIGURE 2-14: Open Loop Gain, Phase vs.
Frequency with V
140
130
120
110
100
90
80
70
DC Open Loop Gain (dB)
60
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
= 5.5V.
DD
RL = 50 k:
V
= 100 mV to VDD - 100 mV
OUT
Power Supply Voltage (V)
FIGURE 2-15: DC Open Loop Gain vs. Power Supply Voltage.
FIGURE 2-17: DC Open Loop Gain vs. Load Resistance vs. Power Supply Voltage.
140
RL = 50 k:
130
120
110
100
(dB)
90
80
70
60
Small Signal DC Open Loop Gain
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Output Voltage Headroom;
V
DD-VOUT
VDD = 5.5 V
VDD = 1.4 V
or V
OUT-VSS
(V)
FIGURE 2-18: Small Signal DC Open Loop Gain vs. Output Voltage Headroom vs. Power Supply.
21668A-page 6 2002 Microchip Technology Inc.
MCP6141/2/3/4
p
p
Note: Unless otherwise indicated, V
and V
OUT~VDD
140
130
120
(dB)
110
100
90
Channel-to-Channel Separation
/2.
Input-Referred
1000 10000
Frequency (Hz)
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only).
120
Gain Bandwidth Product
100
80
60
(kHz)
40
20
Gain Bandwidth Product
0
-40-20 0 20406080
Phase Margin
VDD = 5.5 V
Ambient Temperature (°C)
10k1k
90
75
60
45
30
Phase Margin (°)
15
0
180
160
140
120
100
80
(kHz)
60
40
20
Gain Bandwidth Product
0
-0.5
Phase Margin
Gain Bandwidth Product
0.0
0.5
1.0
Common Mode Input Voltage (V)
= 1 MΩ to V
L
1.5
2.0
2.5
3.0
3.5
DD
4.0
/2, C
4.5
= 60 pF,
L
90
80
70
60
50
40
30
20
10
0
5.0
5.5
FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage.
120
100
80
60
(kHz)
40
20
Gain Bandwidth Product
VDD = 1.4 V
C
= 60 pF
L
0
-40-200 20406080
Gain Bandwidth Product
Phase Margin
Ambient Te mperature ( °C)
90
75
60
45
30
Phase Margin (°)
15
0
Phase Margin (°)
FIGURE 2-20: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
V
= 5.5V.
DD
12
10
8
6
4
Frequency (kHz)
Closed Loop Gain
2
0
0.00 0.00 0.00
10
Closed Loop Gain Frequency
Phase Margin
G = +10 V/V
VDD = 5.5 V
Load Capacitance (F)
90
75
60
45
30
15
0
1n100
Phase Margin (°)
FIGURE 2-21: Closed Loop Gain
Frequency, Phase Margin vs. Load Capacitance
with V
DD
=5.5V.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
= 1.4V.
V
DD
40
35
30
25
20
(pA)
15
+ISC, VDD = 1.4 V
10
-ISC, VDD = 1.4 V
5
Output Short Circuit Current
0
-40-200 20406080
Ambient Temperature (°C)
-ISC, VDD = 5.5 V
+ISC, VDD = 5.5 V
FIGURE 2-24: Output Short Circuit Current vs. Ambient Temperature vs. Power Supply Voltage.
2002 Microchip Technology Inc. 21668A-page 7
MCP6141/2/3/4
Note: Unless otherwise indicated, V
and V
OUT~VDD
/2.
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
50
45
40
Falling Edge
35
30
25
20
15
Slew Rate (V/ms)
10
Rising Edge
5
0
-40-20 0 20406080
Ambient Temperature (°C)
FIGURE 2-25: Slew Rate vs. Ambient Temperature.
1,000
100
VOL-VSS, VDD = 1.4 V
10
1
Output Voltage Headroom (mV)
1.E-05 1.E-04 1.E-03 1.E-02
10µ 10m1m100µ
Output Current Magnitude (A)
VOL-VSS, VDD = 5.5 V
= 1 MΩ to V
L
DD
/2, C
= 60 pF,
L
10
VDD = 5.5 V
1
Output Voltage Swing (VP-P)
0.1
100 1k 10k
100 1000 10000
VDD = 1.4 V
Frequency (Hz)
FIGURE 2-28: Output Voltage Swing vs. Frequency vs. Power Supply Voltage.
4.0
VDD = 5.5 V
3.5
RL = 50 k:
3.0
2.5
2.0
1.5
1.0
0.5
Output Voltage Headroom (mV)
0.0
-40 -20 0 20 40 60 80
VOL - V
SS
VDD - V
OH
Ambient Temperature (°C)
FIGURE 2-26: Output Voltage Headroom vs. Output Current Magnitude vs. Power Supply Voltage.
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
Output Voltage (20 mV/div)
-0.08
0.E+00 1.E-04 2.E-04 3.E-04 4.E-04 5.E-04 6.E-04 7.E-04 8.E-04 9.E-04 1.E-03
G = +11 V/V
RL = 50 k:
Time (100 µs/div)
FIGURE 2-27: Small Signal Non-Inverting Pulse Response vs. Time.
FIGURE 2-29: Output Voltage Headroom
vs. Ambient Temperature with V
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
Output Voltage (20 mV/div)
-0.08
0.E+00 1.E-04 2.E-04 3.E-04 4.E-04 5.E-04 6.E-04 7.E-04 8.E-04 9.E-04 1.E-03
Time (100 µs/div)
= 5.5V.
DD
G = -10 V/V
= 50 k:
R
F
FIGURE 2-30: Small Signal Inverting Pulse Response vs. Time.
21668A-page 8 2002 Microchip Technology Inc.
MCP6141/2/3/4
Note: Unless otherwise indicated, V
and V
OUT~VDD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Output Voltage (V)
1.0
0.5
0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03
0.0
/2.
G = +11 V/V
RL = 50 k:
Time (200 µs/div)
= +5V, VSS = GND, TA = 25°C, VCM = VDD/2, R
DD
FIGURE 2-31: Large Signal Non-Inverting Pulse Response vs. Time.
27.5
25.0
V
on V
OUT
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0.E+00 1.E-03 2.E-03 3.E-03 4.E-03 5.E-03 6.E-03 7.E-03 8.E-03 9.E-03 1.E-02
0.0
Chip Select Voltage (V)
G = +11 V/V
V
= 3.0 V
IN
V
Hi-Z
OUT
CS Voltage
Time (1 ms/div)
OUT
on
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
FIGURE 2-34: Large Signal Inverting Pulse Response vs. Time.
Output Voltage (V)
= 1 MΩ to V
L
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Output Voltage (V)
1.0
0.5
0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03
0.0
5.5
5.0
V
on
OUT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Output Voltage (V)
1.0
G = +11 V/V
0.5
VIN = 3.0 V
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Time (200 µs/div)
Hysteresis
CS swept
high to low
Chip Select Voltage (V)
/2, C
DD
CS swept
low to high
= 60 pF,
L
G = -10 V/V
RF = 50 k:
V
HI-Z
OUT
FIGURE 2-32: Chip Select (CS
) to
Amplifier Output Response Time
(MCP6143 only).
6
G = +11 V/V
5
4
3
2
1
0
Input, Output Voltages (V)
0.E+00 5.E-03 1.E-02 2.E-02 2.E-02 3.E-02
-1
V
OUT
V
IN
Time (5 ms/div)
FIGURE 2-33: The MCP6141/2/3/4 family
shows no phase reversal (for information only–
the Maximum Absolute Input Voltage is still
V
- 0.3V and V
SS
DD
+ 0.3V).
FIGURE 2-35: Output Voltage vs. Chip
Select (CS
) Voltage (MCP6143 only).
2002 Microchip Technology Inc. 21668A-page 9
MCP6141/2/3/4
3.0 APPLICATIONS INFORMATION
The MCP6141/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are stable for noise gain of 10 V/V or
higher. Microchip also produces a unity gain stable
product, the MCP6041/2/3/4 family, which has similar
specifications. The MCP6041/2/3/4 family has a bandwidth of 1.4 kHz at a noise gain of 10 V/V, while the
MCP6141/2/3/4 family has a bandwidth of 10 kHz at a
noise gain of 10 V/V. These devices are suitable for a
wide range of applications requiring very low power
consumption. With these op amps, the power supply
pin needs to be bypassed with a 0.1 µF capacitor.
3.1 Rail-to-Rail Input
The input stage of these devices uses two differential
input stages in parallel; one operates at low V
mon mode input voltage) and the other at high V
With this topology, the MCP6141/2/3/4 family operates
with V
Offset Voltage is measured at both V
and V
up to 300 mV past either supply rail. The Input
CM
+ 0.3V to ensure proper operation.
DD
CM=VSS
3.2 Output Loads and Battery Life
The MCP6141/2/3/4 op amp family has low quiescent
current, which supports battery-powered applications.
There is minimal quiescent current glitch when chip
select (CS
sive current draw and reduced battery life when the
part is turned off or on.
Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across
a 100 kΩ load resistor will cause the supply current to
increase by 25 µA, depleting the battery 43 times as
fast as I
High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current.
For instance, a 0.1 µF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz
sinewave. It can be shown that the average power
drawn from the battery by a 5.0 V
(1.77 Vrms) under these conditions is:
EQUATION
P
This will drain the battery 18 times as fast as IQ alone.
) is raised or lowered. This prevents exces-
(0.6 µA typ) alone.
Q
SUPPLY
V
–()I
DDVSS
5V()0.6µA5.0V
V
()=
+ fC
Q
Lp p–()
100Hz 0.1µF⋅⋅+()=
pp–
3.0 µW50µW+=
CM
sinewave
p-p
L
(com-
CM
-0.3V
3.3 Rail-to-Rail Output
The MCP6141/2/3/4 family Maximum Output Voltage
Swing defines the maximum swing possible under a
particular output load. According to the specification
table, the output can reach up to 10 mV of either supply
rail with a 50 kΩ load.
3.4 Input Voltage and Phase Reversal
The MCP6141/2/3/4 op amp family uses CMOS transistors at the input. It is designed to prevent phase
reversal when the input pins exceed the supply voltages. Figure 2-33 shows an input voltage exceeding
both supplies without output phase reversal.
The maximum operating V
inputs is V
-0.3V and VDD + 0.3V. Voltage on the
SS
that can be applied to the
CM
input that exceeds this absolute maximum rating can
cause excessive current to flow in or out of the input
.
pins. Current beyond ±2 mA can cause possible reliability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 3-1.
R
IN
V
IN
Maximum expected V
()V
≥
R
--------------------------- ------------ ------------------------------ ----------
IN
V
SS
R
≥
----------------------------- ------------ ------------------------------ ---- -
IN
MCP614X
IN
2 mA
Minimum expected V
()–
2 mA
FIGURE 3-1: An input resistor, R
V
OUT
–
DD
IN
,
IN
should be used to limit excessive input current if
the inputs exceed the absolute maximum
specification.
3.5 Stability
The MCP6141/2/3/4 op amp family is designed to give
high bandwidth and faster slew rate for circuits with
high noise (G
stable MCP6041/2/3/4 op amp family has lower AC
performance, but it is preferable for low noise gain
applications.
Noise gain is defined to be the gain from a voltage
source at the non-inverting input to the output when all
other voltage sources are zeroed (shorted out). Noise
gain is independent of signal gain and depends only on
components in the feedback loop.
) or signal gain. The related unity-gain
n
21668A-page 10 2002 Microchip Technology Inc.
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