MICROCHIP MCP6001, MCP6002, MCP6004 Technical data

MCP6001/2/4

1 MHz, Low-Power Op Amp

Features

• Available in SC-70-5 and SOT-23-5 packages

• Gain Bandwidth Product: 1 MHz (typ.)

• Rail-to-Rail Input/Output

• Supply Voltage: 1.8V to 5.5V

• Supply Current: I

= 100 µA (typ.)

Q

• Phase Margin: 90° (typ.)

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Available in Single, Dual and Quad Packages

Applications

• Automotive

• Portable Equipment

• Photodiode Amplifier

• Analog Filters

• Notebooks and PDAs

• Battery-Powered Systems

Available Tools

SPICE Macro Models (at www .m ic rochi p.c om )

®

FilterLab

Software (at www.microchip.com)

Typical Application

V

DD

V

IN

R

2

Non-Inverting Amplifier

V

REF

+

MCP6001

–

R

1

Gain 1

V

OUT

V

SS

R

1

----- -

+=

R

2

Description

The Microchip T echnology Inc. MCP6001/2/4 family of operational amplifiers (op amps) is specifically designed for general-purpose applications. This family has a 1 MHz Gain Bandwidth Product (GBWP) and 90° phase margin (typ.). It also maintains 45° phase margin (typ.) with a 500 pF capacitive load. This family operates from a single supply voltage as low as 1.8V, while drawing 100 µA (typ.) quiescent current. Additionally, the MCP6001/2/4 supports rail-to-rail input and output swing, with a common mode input voltage range of V

+300mV to VSS– 300 mV. This

DD

family of op amps is designed with Microchip’s advanced CMOS process.

The MCP6001/2/4 family is available in the industrial and extended tempera ture ranges, w ith a power sup ply range of 1.8V to 5.5V.

Package Types

MCP6001

SC-70-5, SOT-23-5

V

1

OUT

V

VIN+

SS

+

2

2 3

3

-

MCP6001R

SOT-23-5

V

1

OUT

V

VIN+

DD

+

2 3

-

MCP6001U

SOT-23-5

VIN+

1

V

VIN–

SS

+

2

-

3

V

DD

VIN–

V

SS

VIN–

V

DD

V

OUT

V

V V

V

5

4

5

4

5

4

MCP6002

PDIP, SOIC, MSOP

V

OUTA

INA

V

1

–

2

-

+

3 4

SS

8

DD

7

+

V

OUTB

6

+

-

V

–

INB

V

+

5

INB

MCP6004

PDIP, SOIC, TSSOP

V

1

OUTA

–

V

2

V

V V

OUTB

INA INA

V

INB INB

-

+

3 4

DD

+V

5

-

–

6 7

14

OUTD

V

–

13

+

-

+

IND

+

V

12

IND

V

11

SS

+

10

INC

-

–

V

9

INC

V

8

OUTC

MCP6001/2/4

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

VDD – VSS........................................................................7.0V

All Inputs and Outputs ...................V

Difference Input Voltage ......................................|V

Output Short-Circuit Current .................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage Temperature........................... .... ..... .-65°C to +150°C

Maximum Junction Temperature (T

ESD Protection On All Pins (HBM;MM)...............≥ 4 kV; 200V

– 0.3V to VDD + 0.3V

SS

– VSS|

DD

)..........................+150°C

J

† Notice: S tresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at tho se or any oth er conditions ab ove those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2,

R

= 10 kΩ to VDD/2 and V

L

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage V Input Offset Drift with Temperature ΔV

Power Supply Rejection Ratio PSRR — 86 — dB VCM = V

Input Bias Current and Impedance

Input Bias Current: I

Industrial Tempe ratu r e I

Extended Temperature I Input Offset Current I Common Mode Input Impedance Z Differential Input Impedance Z Common Mode Common Mode Input Range V Common Mode Rejection Ratio CMRR 60 76 — dB V

Open-Loop Gain

DC Open-Loop Gain (Large Signal) A

Output

Maximum Output Voltage Swing V Output Short-Circuit Current I

Power Supply

Supply Voltage V Quiescent Current per Amplifier I Note 1: MCP6001/2/4 parts w ith date codes prior to De cemb er 2004 (week code 49) were teste d to ± 7mV minimum/

maximum limits.

OUT

≈ VDD/2.

OS

/ΔT

OS

B B B

OS

CM

DIFF

CMR

OL

, VOHVSS + 25 — VDD – 25 mV VDD = 5.5V

OL

SC

DD

Q

-4.5 — +4.5 mV VCM = VSS (Note 1) —±2.0—µV/°CT

A

= -40°C to +125°C,

A

= V

V

CM

—±1.0—pA —19—pAT

= +85°C

A

— 1100 — pA TA = +125°C —±1.0—pA —1013||6 — Ω||pF —1013||3 — Ω||pF

V

− 0.3 — V

SS

88 112 — dB V

—±6—mAV —±23—mAV

+ 0.3 V

DD

CM

V

DD

OUT

V

CM=VSS

DD DD

1.8 — 5.5 V 50 100 170 µA IO = 0, VDD = 5.5V, VCM = 5V

SS SS

= -0.3V to 5.3V, = 5V

= 0.3V to VDD – 0.3V,

= 1.8V = 5.5V

MCP6001/2/4

AC ELECTRICAL SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,

≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.

V

OUT

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 1.0 — MHz Phase Margin PM — 90 — ° G = +1 Slew Rate SR — 0.6 — V/µs

Noise

Input Noise Voltage E Input Noise Voltage Density e Input Noise Current Density i

ni

TEMPERATURE SPECIFICATIONS

Electrica l Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Industrial Tempe rature Range T Extended Temperature Range T Operating Temperature Range T Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 5L-SC70 Thermal Resistance, 5L-SOT-23 Thermal Resistance, 8L-PDIP θ Thermal Resistance, 8L-SOIC (150 mil) θ Thermal Resistance, 8L-MSOP θ

Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP

Note: The industrial temperature devices operate over this extended temperature range, but with reduced

performance. In any case, the internal Junction Temperature (T specification of +150°C.

A A A A

θ

JA

θ

JA JA JA JA

θ

JA

θ

JA

θ

JA

— 6.1 — µVp-p f = 0.1Hz to 10 Hz —28—nV/√Hz f = 1 kHz —0.6—fA/√Hz f = 1 kHz

-40 — +85 °C

-40 — +125 °C

-40 — +125 °C Note

-65 — +150 °C

— —

331 256

— —

°C/W

°C/W —85—°C/W —163—°C/W —206—°C/W — — —

70 120 100

— — —

) must not exceed the Absolute Maximum

J

°C/W °C/W °C/W

MCP6001/2/4

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and t a ble s prov id ed fol low i ng thi s n ote are a statistical summary based on a l im ite d n um ber of

samples and are prov ided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 10 kΩ to VDD/2 and CL = 60 pF.

R

L

OUT

≈ VDD/2,

20%

64,695 Samples

18%

V

= V

CM

SS

5

-4

-3

-2

Input Offset Voltage (mV)

0

1

2

-1

3

Percentage of Occurrences

16% 14% 12% 10%

8% 6% 4% 2% 0%

FIGURE 2-1: Input Offset Voltage.

100

90 80 70 60 50 40

PSRR, CMRR ( dB )

30 20

10 100 1k 10k 100k

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

PSRR+

CMRR

Frequency (Hz)

VCM = V

PSRR–

100

95 90 85 80

PSRR, CMRR (dB)

75

4

5

70

-50 -25 0 25 50 75 100 125

PSRR (VCM = VSS)

CMRR (VCM = -0.3V to +5.3V)

Ambient Temperature (°C)

FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature.

SS

120 100

80 60 40 20

Open-Loop Gain (dB)

0

VCM = V

+00

SS

1.E

+01

-20

0.1 1 10 100 10k 100k 1M 10M

1.E-011.E

1.E

+02

1k

1.E

+03

Gain

1.E

+04

+05

Phase

1.E

+06

1.E

+07Frequency (Hz)

0

-30

-60

-90

-120

-150

-180

-210

Open-Loop Phase (°)

FIGURE 2-2: PSRR, CMRR vs. Frequency.

14%

1230 Samples

Percentage of Occurrences

12% 10%

8% 6% 4% 2% 0%

= 5.5V

V

DD

= V

V

CM

DD

TA = +85°C

0

3

6

9

12

15

18

Input Bias Current (pA)

21

24

27

30

FIGURE 2-3: Input Bias Current at +85°C.

FIGURE 2-5: Open-Loop Gain, Phase vs.

Frequency.

55%

605 Samples

50%

V

45% 40% 35% 30% 25% 20% 15% 10%

5%

Percentage of Occurrences

0%

= 5.5V

DD

= V

V

CM

DD

TA = +125°C

0

150

300

450

600

750

900

Input Bias Current (pA)

1050

1200

1350

1500

FIGURE 2-6: Input Bias Current at +125°C.

MCP6001/2/4



= -40°C

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 10 kΩ to VDD/2 and CL = 60 pF.

R

L

1,000

Hz)

100

(nV/

Input Noise Voltage Density

10

0.1 101 100 10k1k 100k

1.E-01 1.E+001.E+011.E+021.E+031.E+041.E+0 5Frequency (Hz)

FIGURE 2-7: Input Noise Voltage Density

18%

1225 Samples

16% 14% 12% 10%

Percentage of Occurrences

8% 6% 4% 2% 0%

T

A

VCM = V

-12

= -40°C to +125°C

SS

-8-6-4

-10 Input Offset Voltage Drift (µV/°C)

0

-2

FIGURE 2-10: Input Offset Voltage Drift.

vs. Frequency.

0

VDD = 1.8V

-100

-200

-300

-400

-500

-600

Input Offset Voltage (µV)

-700

-0.4

-0.2 Common Mode Input Voltage (V)

TA = -40°C T

= +25°C

A

T

= +85°C

A

= +125°C

T

A

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

200 150 100

50

0

VDD = 1.8V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)

Input Offset Voltage (µV)

-50

-100

-150

-200

≈ VDD/2,

OUT

2

4

VDD = 5.5V

6

8

VCM = V

10

12

SS

FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at V

0

VDD = 5.5V

-100

-200

-300

-400

-500

-600

Input Offset Voltage (µV)

-700

0.0

0.5

-0.5

1.0

Common Mode Input Voltage (V)

1.5

2.0

TA = -40°C

T

= +25°C

A

T

= +85°C

A

= +125°C

T

A

2.5

3.0

3.5

= 1.8V.

DD

4.0

4.5

5.0

5.5

6.0

FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at V

= 5.5V.

DD

FIGURE 2-11: Input Offset Voltage vs. Output Voltage.

30

25

T

A

TA = +25°C

20

T

= +85°C

A

T

= +125°C

A

15

10

Magnitude (mA)

Short Circuit Current

5

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)

FIGURE 2-12: Output Short-Circuit Current vs. Power Supply Voltage.

MCP6001/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, V

= 10 kΩ to VDD/2 and CL = 60 pF.

R

L

1.0 Falling Edge, VDD = 5.5V

0.9

Falling Edge, VDD = 1.8V

0.8

0.7

0.6

0.5

0.4

0.3

Slew Rate (V/µs)

0.2

Rising Edge, VDD = 5.5V

Rising Edge, VDD = 1.8V

0.1

0.0

-50 -25 0 25 50 75 100 125 Ambient Temperature (°C)

FIGURE 2-13: Slew Rate vs. Ambient Temperature.

1,000

VDD – V

100

(mV)

10

Output Voltage Headroom

1

10µ 10m1m100µ

1.E-05 1.E-04 1.E-03 1.E-02

Output Current Magnitude (A)

OH

VOL – V

SS

0.08

G = +1 V/V

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

Output Voltage (20 mV/div)

-0.08

0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6. E-06 7.E-06 8.E-06 9. E-06 1.E-05

Time (1 µs/div)

FIGURE 2-16: Smal l-Signal, Non-Inverting Pulse Response.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

Output Voltage (V)

1.0

0.5

0.E+00 1.E -05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04

0.0 Time (10 µs/div)

OUT

≈ VDD/2,

G = +1 V/V V

= 5.0V

DD

FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude.

10

)

P-P

1

Output Voltage Swing (V

0.1

1.E+03 1.E+04 1.E+05 1.E+06

VDD = 5.5V

VDD = 1.8V

1k 10k 100k 1M

Frequency (Hz)

FIGURE 2-15: Output Voltage Swing vs. Frequency.

FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response.

180

VCM = VDD - 0.5V

160 140 120 100

80 60

per amplifier (µA)

40

Quiescent Current

20

TA = +125°C

T

= +85°C

A

T

= +25°C

A

= -40°C

T

A

0

0.00.51.01.52.02.53.03.54.04.55.05.5 Power Supply Voltage (V)

FIGURE 2-18: Quiescent Current vs. Power Supply Voltage.

MCP6001/2/4

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6001 MCP6001R MCP6001U MCP6002 MCP6004 Symbol Description

11411V 44322V 33133V

52584VDDPositive Power Supply ——— 5 5V ——— 6 6

——— 7 7V ————8V ————9V ————10V

252411V ————12V ————13V ————14V

OUT

IN IN

, V –, V +, V

INB

V

INB OUTB OUTC

INC

IND

IND OUTD

SS

Analog Output (op amp A)

OUTA

– Inverting Input (op amp A)

INA

+ Non-inverting Input (op amp A)

INA

+ Non-inverting Input (op amp B)

Inverting Input (op amp B)

–

Analog Output (op amp B)

Analog Output (op amp C) – Inverting Input (op amp C) + Non-inverting Input (op amp C)

Negative Power Supply + Non-inverting Input (op amp D) – Inverting Input (op amp D)

Analog Output (op amp D)

3.1 Analog Outputs

The output pins are low-impedance voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.

3.3 Power Supply (VSS and VDD)

The positive powe r s upp ly (VDD) is 1.8V to 5.5V h igh er than the negative power supply (V operation, the other pins are at voltages between V and VDD.

Typically, these parts are used in a single (positive) supply configuration. In this case, V ground and V

is connected to the supply. VDD will

DD

need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the VDD pin. These parts can share a bulk capacitor with analog parts (typically

2.2 µF to 10 µF) within 100 mm of the VDD pin.

). For normal

SS

is connected to

SS

MCP6001/2/4

4.0 APPLICATION INFORMATION

The MCP6001/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6001/2/4 ideal for battery-powered applications. This device has high phase margin, which makes it stable for larger capacitive load applications.

4.1 Rail-to-Rail Input

The MCP6001/2/4 op amps are designed to prev ent phase reversal when the input pins exceed the supply voltages. Fi gure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal.

6 5 4 3 2 1 0

Input, Output Voltages (V)

0.E+00 1.E-05 2.E-0 5 3.E-05 4.E-05 5.E-05 6.E-05 7. E-05 8.E-05 9.E-05 1.E-04

-1

V

OUT

Time (10 µs/div)

IN

FIGURE 4-1: The MCP6001/2/4 Show No Phase Reversal.

The input stage of the MCP6001/2/4 op amps use two differential input stages in parallel. One operates at a low common mode inp ut vol t age (V operates at a high V operates with a V 300 mV below V measured at V

CM=VSS

to ensure proper operation. Input voltages that exceed the input voltage range

– 0.3V to VDD+ 0.3V at 25°C) can cause

(V

SS

excessive current to flow i nto or out of the input pins , while current beyond ±2mA can cause reliability problems. Applications tha t exceed thi s rating mu st be externally limited with a resistor, as shown in Figure 4-2.

. With this topology, the device

CM

up to 300 mV above VDD and

CM

. The input offset voltage is

SS

– 300 mV and VDD+300mV

VDD = 5.0V G = +2 V/V

), while the other

CM

–

IN

V

OUT

R

IN

V

IN

Maximum expected V

()VDD–

-------------------------------------------------------------------------------

R

≥

IN

V

SS

----------------------------------------------------------------------------

R

≥

IN

MCP600X +

IN

2 mA

Minimum expected V

()–

2 mA

FIGURE 4-2: Input Current Limiting Resistor (R

IN

).

4.2 Rail-to-Rail Output

The output volt age rang e of the MCP6001 /2/4 op a mps

–25mV (min.) and VSS + 25 mV (max.) when

is V

DD

=10kΩ is connected to VDD/2 and VDD = 5.5V.

R

L

Refer to Figure 2-14 for more information.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability problems for volt age f eedbac k op amp s. As the load cap acitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain pe aking in th e frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same general behavior.

When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (R feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will b e generally lower than the bandwid th with n o capacitance load.

– MCP600X

V

IN

+

in Figure 4-3) improves the

ISO

R

ISO

C

L

V

OUT

FIGURE 4-3: Output resistor, R

ISO

stabiliz es large capacitive loads.

MCP6001/2/4

:

Figure 4-4 gives recommended R

values for

ISO

different capacitive loads and gains. The x-axis is the normalized lo ad ca paci tan c e (CL/GN), where GN is the

L/GN

ISO

and the

N

10n

(F)

values

is

N

circuit's noise gain. For non-inverti ng gains, G Signal Gain are equal. For inverting gains, G 1+|Signal Gain| (e.g., -1 V/V gives G

1000

) (

Recommended R

VDD = 5.0V R

= 100 k

L

ISO

100

GN = 1

t 2

G

N

10

10p

1.E-11 1.E-10 1.E-09 1.E-08

Normalized Load Capacitance; C

100p 1n 10n

= +2 V/V).

N

FIGURE 4-4: Recommended R for Capacitive Loads.

After sele cting R resulting frequency response peaking and step response overshoot. Modify R response is reasonable. Bench evaluation and simulations with the MCP6001/2/4 SPICE macro model are very helpful.

for your circuit, double-check the

ISO

’s value until the

ISO

4.4 Supply Bypass

With this family of operational amplifiers, the power supply pin (V bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It also needs a bulk capacito r (i.e., 1 µF or la rger) within 100 mm to provide large, s low current s. This bulk c apac itor can b e shared with other analog parts.

for single-supply) should have a local

DD

4.5 PCB Surface Leakage

In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1 0 cause 5 pA of current to flow; which is greater than the MCP6001/2/4 family’ s bias c urrent at 25°C (1 pA, typ.).

The easiest way to reduce surface leakage is to use a guard ring around se nsi tiv e p ins (or t race s). The gua rd ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-5.

VIN-V

FIGURE 4-5: Example Guard Ring Layout for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (V

input with a wire that does not touch the PCB surface.

b. Connect the guard ring to the inverting input

pin (V common mode input voltage.

2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors):

a. Connect the guard ring to the non-inverting

input pin (V to the same reference voltage as the op amp (e.g., V

b. Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB surface.

–). This biases the g uard rin g t o th e

IN

12

Ω. A 5V dif ference would

+

IN

V

SS

Guard Ring

+) to the

IN

+). This bi ases the gua rd ri ng

IN

/2 or ground).

DD