MICROCHIP MCP414X, MCP416X, MCP424X, MCP426X Technical data

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MCP414X/416X/424X/426X

1 2 3 4

P0W

P0B P0A

MCP41X1

Single Potentiometer

PDIP, SOIC, MSOP,

SDI/SDO

SCK

1 2 3 4

P0B

SDO P0W

MCP41X2

Single Rheostat

PDIP, SOIC, MSOP,

1 2 3 4

SHDN

SDO WP

MCP42X1 Dual Potentiometers

PDIP, SOIC, TSSOP

5 6 7

P0W

P0B P0A

P1A

P1W

P1B

SDI

SCK

SDI

SCK

1 2

3 4

SDO

SHDN

4x4 QFN

P0B

P0W

P0A

P1A

P1W

SCK

SDI

P1B

1 2 3 4

SDO

MCP42X2 Dual Rheostat

MSOP, DFN

P0B P0W P1W

P1B

SDI

SCK

3x3 DFN

7/8-Bit Single/Dual SPI Digital POT with

Non-Volatile Memory

Features

• Single or Dual Resistor Network options

• Potentiometer or Rheostat configuration options

• Resistor Network Resolution

- 7-bit: 128 Resistors (129 Steps)

- 8-bit: 256 Resistors (257 Steps) Resistances options of:

•R

-5kΩ

-10kΩ

-50kΩ

- 100 kΩ

Description

The MCP41XX and MCP42XX devices offer a wide range of product offerings using an SPI interface. This family of devices support 7-bit and 8-bit resistor networks, Non-Volatile memory configurations, and Potentiometer and Rheostat pinouts.

WiperLock Technology allows application-specific calibration settings to be secured in the EEPROM.

Package Types

• Zero-Scale to Full-Scale Wiper operation

• Low Wiper Resistance: 75Ω (typ.)

• Low Tempco:

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

- Ratiometric (Potentiometer): 15 ppm typical

• Non-volatile Memory

- Automatic Recall of Saved Wiper Setting

- WiperLock™ Technology

• SPI serial interface (10 Mhz, modes 0,0 & 1,1)

- High-Speed Read/Writes to wiper registers

- Read/Write to Data EEPROM registers

- Serially enabled EEPROM write protect

- SDI/SDO multiplexing (MCP41X1 only)

• Resistor Network Terminal Disconnect Feature via:

- Shutdown pin (SHDN

- Terminal Control (TCON) Register

• Write Protect Feature:

- Hardware Write Protect (WP

- Software Write Protect (WP) Configuration bit

• Brown-out reset protection (1.5V typical)

)

) Control pin

• Serial Interface Inactive current (2.5 uA typ.)

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Supports Split Rail Applications

• Internal weak pull-up on all digital inputs

Specified

• Wide Operating Voltage:

- 2.7V to 5.5V - Device Characteristics

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3dB) Operation:

- 2 MHz (typ.) for 5.0 kΩ device

• Extended temperature range (-40°C to +125°C)

MCP414X/416X/424X/426X

Power-up/ Brown-out Control

VDD

SPI Serial Interface Module & Control Logic (WiperLock™ Technology)

Resistor Network 0

(Pot 0) Wiper 0

& TCON Register

Resistor Network 1

(Pot 1) Wiper 1

& TCON Register

SCK

SDI

SDO

SHDN

Memory (16x9)

Wiper0 (V & NV) Wiper1 (V & NV)

TCON STATUS

Data EEPROM (10 x 9-bits)

P0A

P0W

P0B

P1A

P1W

P1B

For Dual Resistor Network Devices Only

For Dual Potentiometer Devices Only

Device Block Diagram

Device Features

Resistance (typical)

Device

MCP4131 MCP4132

(3)

1 Potentiometer

(3)

1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V

MCP4141 1 Potentiometer

Wiper

Configuration

# of POTs

Type

Memory

Control

Interface

(1)

SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V

(1)

SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V

WiperLock

Technology

POR Wiper

Setting

Options (kΩ)

MCP4142 1 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4151 MCP4152

(3)

1 Potentiometer

(3)

1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4161 1 Potentiometer MCP4162 1 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4231 MCP4232

(3)

2 Potentiometer

(3)

2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4241 2 Potentiometer MCP4242 2 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4251 MCP4252 MCP4261 2 Potentiometer MCP4262 2 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V

Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

(3)

2 Potentiometer

(3)

2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. 3: Please check Microchip web site for device release and availability

(1)

SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V

(1)

SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V

(1)

SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V

(1)

SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V

(1)

SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V

(1)

SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V

Wiper

- RW (Ω)

# of Steps

VDD

Operating

Range

(2)

MCP414X/416X/424X/426X

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on VDD with respect to VSS............... -0.6V to +7.0V

Voltage on CS SHDN Voltage on all other pins (PxA, PxW, PxB, and SDO) with respect to V Input clamp current, I (V

< 0, VI > VDD, VI > VPP ON HV pins)......................±20 mA

Output clamp current, I (V

< 0 or VO > VDD) ..................................................±20 mA

Maximum output current sunk by any Output pin

......................................................................................25mA

Maximum output current sourced by any Output pin

......................................................................................25mA

Maximum current out of V Maximum current into V Maximum current into P

Storage temperature ....................................-65°C to +150°C

Ambient temperature with power applied

-40°C to +125°C

Total power dissipation (Note 1)................................400 mW

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins ..................................≥ 4 kV (HBM),

.......................................................................... ≥ 300V (MM)

Maximum Junction Temperature (T

Note 1: Power dissipation is calculated as follows:

, SCK, SDI, SDI/SDO, WP, and

with respect to VSS

......................................

SS ............................

pin....................................100 mA

XA, PXW & PXB pins ............±2.5 mA

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

-0.6V to 12.5V

-0.3V to VDD + 0.3V

pin.................................100 mA

) ......................... +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (extended)

DC Characteristics

Parameters Sym Min Typ Max Unit s Conditions

Supply Voltage V

, SDI, SDO,

VHV V SCK, WP, SHDN pin Voltage Range

DD Start Voltage

BOR

to ensure Wiper Reset

DD Rise Rate to

DDRR

ensure Power-on Reset

Delay after device

BORD

exits the reset state (VDD > V

Supply Current

BOR

)

(Note 10)

Note 1: Resistance is defined as the resistance between te rminal A to terminal B.

2: INL and DNL are measured at V 3: MCP4XX1 only. 4: MCP4XX2 only, inclu des V 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for VDD = 5.5V, TA = +25°C.

2.7 — 5.5 V

1.8 — 2.7 V Serial Interface only. — 12.5V V VDD ≥

VSS —VDD +

VVDD <

8.0V

4.5V

The CS pin will be at one of three input levels (VIL, VIH or V

IHH

— — 1.65 V RAM retention voltage (V

(Note 9)V/ms

—1020µS

— — 450 µA Serial Interface Active,

VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all

0’s to volatile Wiper 0 (address

0h)

— — 1 mA EE Write Current,

= 5.5V, CS = VIL, SCK @ 5 MHz,

write all 0’s to non-volatile Wiper 0 (address 2h)

— 2.5 5 µA Serial Interface Inactive,

= VIH, VDD = 5.5V

— 0.55 1 mA Serial Interface Active,

= 5.5V, CS = V

IHH

, SCK @ 5 MHz, decrement non-volatile Wiper 0 (address 2h)

with VA = VDD and VB = VSS.

WZSE

and V

WFSE

), which changes significantly over voltage and

). (Note 6)

) < V

RAM

BOR

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Unit s Conditions

Resistance (± 20%)

4.0 5 6.0 kΩ -502 devices (Note 1)

8.0 10 12.0 kΩ -103 devices (Note 1)

40.0 50 60.0 kΩ -503 devices (Note 1)

80.0 100 120.0 kΩ -104 devices (Note 1)

Resolution N 257 Taps 8-bit No Missing Codes

129 Taps 7-bit No Missing Codes

Step Resistance R

—RAB /

— Ω 8-bit Note 6

(256)

—R

— Ω 7-bit Note 6

(128)

- R

Nominal Resistance Match

Wiper Resistance (Note 3, Note 4)

Nominal Resistance Tempco

Ratiometeric

AB0

AB1

/ RAB

- R

BW0

BW1

/ R

ΔRAB/ΔT — 50 — ppm/°C TA = -20°C to +70°C

/ΔT — 15 — ppm/°C Code = Midscale (80h or 40h)

ΔV

— 0.2 1.25 % MCP42X1 devices only

—0.251.5%MCP42X2 devices only,

— 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h — 75 300 Ω V

— 100 — ppm/°C T — 150 — ppm/°C TA = -40°C to +125°C

Tempco Resistor Terminal

A,VW,VB

Vss — V

Input Voltage Range (Terminals A, B and W)

Maximum current

——2.5mANote 6, Worst case current through

through A, W or B

Leakage current into A, W or B

—100—nAMCP4XX1 PxA = PxW = PxB = V —100—nAMCP4XX2 PxB = PxW = VSS

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, inclu des V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

Code = Full-Scale

= 2.7 V, IW = 2.0 mA, code = 00h

= -40°C to +85°C

V Note 5, Note 6

wiper when wiper is either Full Scale or Zero Scale.

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error (MCP4XX1 only) (8-bit code = 100h, 7-bit code = 80h)

WFSE

-6.0 -0.1 — LSb 5 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V

-4.0 -0.1 — LSb 7-bit 3.0V ≤ VDD ≤ 5.5V

-3.5 -0.1 — LSb 10 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V

-2.0 -0.1 — LSb 7-bit 3.0V ≤ VDD ≤ 5.5V

-0.8 -0.1 — LSb 50 kΩ 8-bit 3.0V ≤ V

-0.5 -0.1 — LSb 7-bit 3.0V ≤ VDD ≤ 5.5V

-0.5 -0.1 — LSb 100 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V

-0.5 -0.1 — LSb 7-bit 3.0V ≤ VDD ≤ 5.5V

Zero-Scale Error (MCP4XX1 only) (8-bit code = 00h, 7-bit code = 00h)

WZSE

—+0.1+6.0LSb5kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V — +0.1 +3.0 LSb 7-bit — +0.1 +3.5 LSb 10 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V — +0.1 +2.0 LSb 7-bit — +0.1 +0.8 LSb 50 kΩ 8-bit 3.0V ≤ V — +0.1 +0.5 LSb 7-bit — +0.1 +0.5 LSb 100kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V — +0.1 +0.5 LSb 7-bit

Potentiometer Integral Non-linearity

Potentiometer Differential Non-linearity

Bandwidth -3 dB (See Figure 2-58, load = 30 pF)

INL -1 ±0.5 +1 LSb 8-bit 3.0V ≤ V

-0.5 ±0.25 +0.5 LSb 7-bit

DNL -0.5 ±0.25 +0.5 LSb 8-bit 3.0V ≤ V

-0.25 ±0.125 +0.25 LSb 7-bit

BW — 2 — MHz 5 kΩ 8-bit Code = 80h

— 2 — MHz 7-bit Code = 40h —1—MHz10kΩ 8-bit Code = 80h — 1 — MHz 7-bit Code = 40h —200—kHz50kΩ 8-bit Code = 80h — 200 — kHz 7-bit Code = 40h —100—kHz100kΩ 8-bit Code = 80h — 100 — kHz 7-bit Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, includes V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configura tions of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

MCP4XX1 devices only (Note 2)

≤ 5.5V

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only

R-INL -1.5 ±0.5 +1.5 LSb 5 kΩ 8-bit 5.5V, I

-8.25 +4.5 +8.25 LSb 3.0V, IW = 480 µA

-1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I

-6.0 +4.5 +6.0 LSb 3.0V, IW = 480 µA

(Note 4)

-1.5 ±0.5 +1.5 LSb 10 kΩ 8-bit 5.5V, I

-5.5 +2.5 +5.5 LSb 3.0V, IW = 240 µA

-1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I

-4.0 +2.5 +4.0 LSb 3.0V, IW = 240 µA

-1.5 ±0.5 +1.5 LSb 50 kΩ 8-bit 5.5V, I

-2.0 +1 +2.0 LSb 3.0V, IW = 48 µA

-1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I

-1.5 +1 +1.5 LSb 3.0V, IW = 48 µA

-1.0 ±0.5 +1.0 LSb 100 kΩ 8-bit 5.5V, I

-1.5 +0.25 +1.5 LSb 3.0V, IW = 24 µA

-0.8 ±0.5 +0.8 LSb 7-bit 5.5V, IW = 45 µA

-1.125 +0.25 +1.125 LSb 3.0V, IW = 24 µA

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, includes V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configura tions of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

(Note 7)

= 900 µA

= 450 µA

= 90 µA

= 45 µA

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only

(Note 4)

R-DNL -0.5 ±0.25 +0.5 LSb 5 kΩ 8-bit 5.5V, I

-1.0 +0.5 +1.0 LSb 3.0V (Note 7)

-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I

-0.75 +0.5 +0.75 LSb 3.0V (Note 7)

-0.5 ±0.25 +0.5 LSb 10 kΩ 8-bit 5.5V, I

-1.0 +0.25 +1.0 LSb 3.0V (Note 7)

-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I

-0.75 +0.5 +0.75 LSb 3.0V (Note 7)

-0.5 ±0.25 +0.5 LSb 50 kΩ 8-bit 5.5V, I

-0.5 ±0.25 +0.5 LSb 3.0V (Note 7)

-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I

-0.375 ±0.25 +0.375 LSb 3.0V (Note 7)

-0.5 ±0.25 +0.5 LSb 100kΩ 8-bit 5.5V, I

-0.5 ±0.25 +0.5 LSb 3.0V (Note 7)

-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I

-0.375 ±0.25 +0.375 LSb 3.0V (Note 7) Capacitance (P Capacitance (P Capacitance (PB)C

)CW— 120 — pF f =1 MHz, Code = Full-Scale

— 75 — pF f =1 MHz, Code = Full-Scale

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, includes V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configura tions of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

= 900 µA

= 450 µA

= 90 µA

= 45 µA

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, SHDN)

Schmitt Trigger

0.45 V

——V2.7V ≤ VDD ≤ 5.5V

High Input Threshold

——V1.8V ≤ VDD ≤ 2.7V

Schmitt Trigger

0.5 V

— — 0.2V Low Input Threshold

Hysteresis of

HYS

—0.1VDD—V Schmitt Trigger Inputs

High Voltage Input

IHH

8.5 — 12.5

(6)

V Threshold for WiperLock™ Technolog y

Entry Voltage High Voltage Input

Exit Voltage High Voltage Limit V Output Low

Voltage (SDO) Output High

Voltage (SDO) Weak Pull-up /

Pull-down Current

Pull-up /

——V

IHH

MAX

——12.5

—0.3VDD VIOL = 5 mA, VDD = 5.5V

VSS —0.3VDD VIOL = 1 mA, VDD = 1.8V

0.7VDD —VDD VIOH = -2.5 mA, VDD = 5.5V

0.7VDD —VDD VIOL = -1 mA, VDD = 1.8V

— — 375 uA Internal VDD pull-up, V

—170—µACS pin, V

—16—kΩ V

(6)

0.8V

(6)

V Pin can tolerate V

Pull-down Resistance

Input Leakage

-1 — 1 µA VIN = VDD and VIN = VSS

Current Pin Capacitance C

, C

OUT

—10—pFf

RAM (Wiper) Value

Value Range N 0h — 1FFh hex 8-bit device

0h — 1FFh hex 7-bit device

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, includes V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configura tions of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

(Allows 2.7V Digital V 5V Analog VDD)

= 5.5V, VCS = 3V

= 20 MHz

or less.

MAX

= 5.5V, VCS = 3V

IHH

with

pull-down

MCP414X/416X/424X/426X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V

Parameters Sym Min Typ Max Units Conditions

EEPROM

Endurance E

ndurance

— 1M — Cycles EEPROM Range N 0h — 1FFh hex Initial Factory

Setting EEPROM Pro-

N 80h hex 8-bit WiperLock Technology = Off

40h hex 7-bit WiperLock Technology = Off

—510ms

gramming Write Cycle Time

Power Requirements

Power Supply

PSS — 0.0015 0.0035 %/% 8-bit V Sensitivity (MCP41X2 and MCP42X2 only)

— 0.0015 0.0035 %/% 7-bit V

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V

with VA = VDD and VB = VSS.

3: MCP4XX1 only. 4: MCP4XX2 only, includes V

WZSE

and V

WFSE

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R

), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configura tions of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network

≤ +125°C (extended)

= 5.5V, TA = +25°C.

= 2.7V to 5.5V,

VA = 2.7V, Code = 80h

= 2.7V to 5.5V,

VA = 2.7V, Code = 40h

MCP414X/416X/424X/426X

SCK

SDO

SDI

75, 76

SDI

MSb LSb

BIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

IHH

1.1 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1: SPI Timing Waveform (Mode = 11).

TABLE 1-1: SPI REQUIREMENTS (MODE =

# Characteristic Symbol Min Max Units Conditions

SCK Input Frequency F

70 CS

Active (VIL or V

71 SCK input high time TscH 45 — ns VDD = 2.7V to 5.5V

72 SCK input low time TscL 45 — ns V

73 Setup time of SDI input to SCK↑ edge T 74 Hold time of SDI input from SCK↑ edge TscH2 77 CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ — 50 ns Note 1 80 SDO data output valid after SCK↓ edge TscL2

83 CS

84 Hold time of CS

Inactive (VIH) after SCK↑ edge TscH2csI 100 — ns VDD = 2.7V to 5.5V

CS Active (VIL or V

Note 1: This specification by design.

) to SCK↑ input TcsA2scH 60 — ns

IHH

Inactive (VIH) to

)

IHH

11)

—10MHzVDD = 2.7V to 5.5V

SCK

—1MHzV

500 — ns V

500 — ns VDD = 1.8V to 2.7V

DIV2scH 10 — ns

DIL20—ns

DOV — 70 ns V

1msV

TcsA2csI 50 — ns

170 ns V

DD DD

= 1.8V to 2.7V

= 1.8V to 2.7V = 2.7V to 5.5V

= 2.7V to 5.5V = 1.8V to 2.7V

= 1.8V to 2.7V

MCP414X/416X/424X/426X

SCK

SDO

SDI

71 72

SDI

75, 76

MSb BIT6 - - - - - -1 LSb

MSb IN BIT6 - - - -1 LSb IN

IHH

FIGURE 1-2: SPI Timing Waveform (Mode = 00).

TABLE 1-2: SPI REQUIREMENTS (MODE =

00)

# Characteristic Symbol Min Max Units Conditions

SCK Input Frequency F

—10MHzVDD = 2.7V to 5.5V

SCK

—1MHzVDD = 1.8V to 2.7V

70 CS

Active (VIL or V

71 SCK input high time TscH 45 — ns V

) to SCK↑ input TcsA2scH 60 — ns

IHH

= 2.7V to 5.5V

500 — ns VDD = 1.8V to 2.7V

72 SCK input low time TscL 45 — ns V

500 — ns V

73 Setup time of SDI input to SCK↑ edge T

DIV2scH 10 — ns

= 2.7V to 5.5V

= 1.8V to 2.7V

74 Hold time of SDI input from SCK↑ edge TscH2DIL20—ns 77 CS 80 SDO data output valid after SCK↓ edge TscL2

82 SDO data output valid after

83 CS

84 Hold time of CS

Inactive (VIH) to SDO output hi-impedance TcsH2DOZ — 50 ns Note 1

DOV— 70nsV

170 ns V

= 2.7V to 5.5V

= 1.8V to 2.7V

TssL2doV — 70 ns

Active (VIL or V

IHH

)

Inactive (VIH) after SCK↓ edge TscH2csI 100 — ns VDD = 2.7V to 5.5V

= 1.8V to 2.7V

Active (VIL or V

Inactive (VIH) to

)

IHH

1msV

TcsA2csI 50 — ns

Note 1: This specification by design.

MCP414X/416X/424X/426X

T ABLE 1-3: SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPERATION ONLY)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency F

Active (VIL or V

CS SCK input high time TscH 1.8 — us SCK input low time TscL 1.8 — ns Setup time of SDI input to SCK↑ edge T Hold time of SDI input from SCK↑ edge TscH2 CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ — 50 ns Note 1 SDO data output valid after SCK↓ edge TscL2 SDO data output valid after

Active (VIL or V

Inactive (VIH) after SCK↓ edge TscH2csI 100 — ns

CS Hold time of CS Inactive (VIH) to

Active (VIL or V

Note 1: This specification by design

2: This table is for the devices where the SPI’s SDI and SDO pins are multiplexed (SDI/SDO) and a Read

command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write commands. This data rate can be increased by having external pull-up resistors to increase the rising edges of each bit.

) to SCK↑ input TcsA2scH 60 — ns

IHH

TssL2doV — 50 ns

)

IHH

)

IHH

—250kHzVDD = 2.7V to 5.5V

SCK

DIV2scH 40 — ns

DIL40—ns

DOV—1.6us

TcsA2csI 50 — ns

(2)

MCP414X/416X/424X/426X

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD= +2.7V to +5.5V, VSS=GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T Operating Temperature Range T Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 8L-PDIP θ Thermal Resistance, 8L-SOIC θ Thermal Resistance, 8L-MSOP θ Thermal Resistance, 8L-DFN (3x3) θ Thermal Resistance, 10L-PDIP θ Thermal Resistance, 10L-MSOP θ Thermal Resistance, 14L-PDIP θ Thermal Resistance, 14L-SOIC θ Thermal Resistance, 14L-MSOP θ Thermal Resistance, 16L-QFN θ

A A A

JA JA JA JA JA JA JA JA JA JA

-40 — +125 °C

-65 — +150 °C

— 84.6 — °C/W — 145.5 — °C/W —211—°C/W — 68.5 — °C/W —82—°C/W —202—°C/W —70—°C/W —85—°C/W —N/A—°C/W —50—°C/W

MCP414X/416X/424X/426X

100

150

200

250

300

350

400

450

500

550

600

650

0.00 2.00 4.00 6.00 8.00 10.00 12.00 f

SCK

(MHz)

Operating Current (I

) (µA)

2.7V -40°C

2.7V 25°C

2.7V 85°C

2.7V 125°C

5.5V -40°C

5.5V 25°C

5.5V 85°C

5.5V 125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-40 25 85 125 Ambient Temperature (°C)

Standby Current (Istby) (µA)

5.5V

2.7V

300.0

400.0

500.0

600.0

700.0

800.0

900.0

-40 25 85 125 Ambient Temperature (°C)

EE Write Current (Iwrite) (µA)

5.5V

100

150

200

250

2345678910

(V)

(kOhms)

-1000

-800

-600

-400

-200

200

400

600

800

1000

(µA)

-40-200 20406080100120

Ambient Temperature (°C)

CS V

Threshold (V)

2.7V Exit

5.5V Exit

2.7V Entry

5.5V Entry

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-1: Device Current (IDD) vs. SPI Frequency (f (V

= 2.7V and 5.5V).

FIGURE 2-2: Device Current (I V

. (CS = VDD) vs. Ambient Temperature.

) and Ambient Temperature

SCK

SHDN

) and

FIGURE 2-4: CS Resistance (R Voltage (V

) and Current (ICS) vs. CS Input

) (V

FIGURE 2-5: CS

Pull-up/Pull-down

= 5.5V).

High Input Entry/Exit

Threshold vs. Ambient Temperature and V

FIGURE 2-3: Write Current (I Ambient Temperature and V

) vs.

WRITE

MCP414X/416X/424X/426X

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C 25°C

85°C

125°C

5050

5100

5150

5200

5250

5300

-40 0 40 80 120

Ambient Temperature (°C)

Nominal Resistance (R

(Ohms)

2.7V

5.5V

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-2

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C125°C

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-1.25

-0.75

-0.25

0.25

0.75

1.25

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

1000

2000

3000

4000

5000

6000

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

(Ohms)

-40°C 25°C 85°C 125°C

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

)

FIGURE 2-6: 5kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 5.5V).

)

FIGURE 2-9: 5k

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 5.5V).

FIGURE 2-7: 5k INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

FIGURE 2-8: 5k (

) vs. Ambient Temperature and VDD.

Pot Mode – RW (Ω),

= 3.0V).

– Nominal Resistance

FIGURE 2-10: 5k

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

FIGURE 2-11: 5k

= 3.0V).

– RWB (Ω) vs. Wiper Setting and Ambient Temperature.

MCP414X/416X/424X/426X

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-12: 5kΩ – Low-Voltage Decrement Wiper Settling Time (V (1 µs/Div).

FIGURE 2-13: 5k Decrement Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

FIGURE 2-15: 5k Increment Wiper Settling Time (V (1 µs/Div).

FIGURE 2-16: 5k Increment Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

FIGURE 2-14: 5k Response Time (20 ms/Div).

– Power-Up Wiper

MCP414X/416X/424X/426X

100

120

0 25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

10000

10050

10100

10150

10200

10250

-40 0 40 80 120

Ambient Temperature (°C)

Nominal Resistance (R

(Ohms)

5.5V

2.7V

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-1

-0.5

0.5

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C85°C

125°C

100

140

180

220

260

300

0 25 50 75 100125150175200225250

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-2

-1

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL R

-40°C

25°C85°C

125°C

2000

4000

6000

8000

10000

12000

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

(Ohms)

-40°C 25°C 85°C 125°C

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

)

FIGURE 2-17: 10 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 5.5V).

)

FIGURE 2-20: 10 k

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 5.5V).

FIGURE 2-18: 10 k INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

FIGURE 2-19: 10 k (

) vs. Ambient Temperature and VDD.

Pot Mode – RW (Ω),

FIGURE 2-21: 10 k

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

= 3.0V).

– Nominal Resistance

Ambient Temperature (V

FIGURE 2-22: 10 k

= 3.0V).

– RWB (Ω) vs. Wiper Setting and Ambient Temperature.

MCP414X/416X/424X/426X

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-23: 10 kΩ – Low-Voltage Decrement Wiper Settling Time (V (1 µs/Div).

FIGURE 2-24: 10 k Decrement Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

FIGURE 2-25: 10 k Increment Wiper Settling Time (V (1 µs/Div).

FIGURE 2-26: 10 k Increment Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

MCP414X/416X/424X/426X

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

)

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

)

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

49400

49600

49800

50000

50200

50400

50600

50800

-40 0 40 80 120

Ambient Temperature (°C)

Nominal Resistance (R

(Ohms)

2.7V

5.5V

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

)

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

10000

20000

30000

40000

50000

60000

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

(Ohms)

-40°C 25°C 85°C 125°C

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-27: 50 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

FIGURE 2-28: 50 k

= 5.5V).

Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 3.0V).

FIGURE 2-30: 50 k

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

FIGURE 2-31: 50 k

= 5.5V).

Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

= 3.0V).

FIGURE 2-29: 50 k (

) vs. Ambient Temperature and VDD.

– Nominal Resistance

FIGURE 2-32: 50 k

– RWB (Ω) vs. Wiper Setting and Ambient Temperature.

MCP414X/416X/424X/426X

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-33: 50 kΩ – Low-Voltage Decrement Wiper Settling Time (V (1 µs/Div).

FIGURE 2-34: 50 k Decrement Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

FIGURE 2-35: 50 k Increment Wiper Settling Time (V (1 µs/Div).

FIGURE 2-36: 50 k Increment Wiper Settling Time (V (1 µs/Div).

– Low-Voltage

= 2.7V)

= 5.5V)

MCP414X/416X/424X/426X

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.2

-0.1

0.1

0.2

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C

85°C

125°C

99000

99500

100000

100500

101000

101500

-40 0 40 80 120 Ambient Temperature (°C)

Nominal Resistance (R

(Ohms)

5.5V

2.7V

100

120

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (R

(ohms)

-0.3

-0.2

-0.1

0.1

0.2

0.3

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C INL 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C85°C

125°C

100

140

180

220

260

300

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Wiper Resistance (Rw)

(ohms)

-0.6

-0.4

-0.2

0.2

0.4

0.6

Error (LSb)

-40C Rw 25C Rw 85C Rw 125C Rw

-40C INL 25C IN L 85C INL 125C INL

-40C DNL 25C DNL 85C DNL 125C DNL

INL

DNL

-40°C

25°C85°C

125°C

20000

40000

60000

80000

100000

120000

0 32 64 96 128 160 192 224 256

Wiper Setting (decimal)

Rwb (Ohms)

-40°C 25°C 85°C 125°C

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

)

FIGURE 2-37: 100 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

= 5.5V).

)

FIGURE 2-40: 100 k (

), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V

Rheo Mode – RW

= 5.5V).

FIGURE 2-38: 100 k INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V

)

FIGURE 2-39: 100 k Resistance ( V

Pot Mode – RW (Ω),

= 3.0V).

– Nominal

) vs. Ambient Temperature and

FIGURE 2-41: 100 k (

), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V

FIGURE 2-42: 100 k

Rheo Mode – RW

= 3.0V).

– RWB (Ω) vs. Wiper

Setting and Ambient Temperature.

MCP414X/416X/424X/426X

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-43: 100 kΩ – Low-Voltage Decrement Wiper Settling Time (V

= 2.7V)

(1 µs/Div).

FIGURE 2-44: 100 k Decrement Wiper Settling Time (V

– Low-Voltage

= 5.5V)

(1 µs/Div).

FIGURE 2-45: 100 kΩ – Power-Up Wiper Response Time (1 µs/Div).

FIGURE 2-46: 100 k Increment Wiper Settling Time (V

– Low-Voltage

= 2.7V)

(1 µs/Div).

MCP414X/416X/424X/426X

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

-40 0 40 80 120 Temperature (°C)

5.5V

3.0V

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

-40 0 40 80 120 Temperature (°C)

5.5V

3.0V

0.02

0.04

0.06

0.08

0.1

0.12

-40 0 40 80 120

Temperature (°C)

5.5V

3.0V

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

0.05

-40 10 60 110

Temperature (°C)

5.5V

3.0V

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-47: Resistor Network 0 to Resistor Network 1 R

(5 kΩ) Mismatch vs. VDD

and Temperature.

FIGURE 2-48: Resistor Network 0 to Resistor Network 1 R V

and Temperature.

(10 kΩ) Mismatch vs.

FIGURE 2-49: Resistor Network 0 to Resistor Network 1 R V

and Temperature.

(50 kΩ) Mismatch vs.

FIGURE 2-50: Resistor Network 0 to Resistor Network 1 R V

and Temperature.

(100 kΩ) Mismatch vs.

MCP414X/416X/424X/426X

1.2

1.4

1.6

1.8

2.2

2.4

-40 0 40 80 120 Temperature (°C)

(V)

5.5V

2.7V

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-40 0 40 80 120

Temperature (°C)

(V)

5.5V

2.7V

-45

-40

-35

-30

-25

-20

-15

-10

-5

-40 0 40 80 120

Temperature (°C)

(mA)

5.5V

2.7V

-40 0 40 80 120 Temperature (°C)

(mA)

5.5V

2.7V

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-51: VIH (SDI, SCK, CS, WP, and SHDN

) vs. VDD and Temperature.

FIGURE 2-52: V SHDN

) vs. VDD and Temperature.

(SDI, SCK, CS, WP, and

FIGURE 2-53: I Temperature.

FIGURE 2-54: I Temperature.

(SDO) vs. VDD and

MCP414X/416X/424X/426X

3.0

3.2

3.4

3.6

3.8

4.0

4.2

-40 0 40 80 120 Temperature (°C)

(ms)

0.2

0.4

0.6

0.8

1.2

-40 0 40 80 120 Temperature (°C)

(V)

2.7V

5.5V

12.0

12.5

13.0

13.5

14.0

14.5

15.0

-40 0 40 80 120 Temperature (°C)

fsck (MHz)

2.7V

5.5V

OUT

2.5V DC

+5V

Offset GND

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

FIGURE 2-55: Nominal EEPROM Write Cycle Time vs. V

and Temperature.

2.1 Test Circuits

FIGURE 2-58: -3 db Gain vs. Frequency Test.

FIGURE 2-56: POR/BOR T rip point vs. V and Temperature.

FIGURE 2-57: SCK Input Frequency vs. Voltage and Temperature.

MCP414X/416X/424X/426X

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows.

TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP414X/416X/424X/426X

Single Dual

Rheo Pot

(1)

Rheo Pot

8L 8L 10L 14L 16L

Symbol I/O

Buffer

Type

Weak Pull-up/ down

(2)

Standard Function

111116

I HV w/ST “smart” SPI Chip Select Input

2 2 2 2 1 SCK I HV w/ST “smart” SPI Clock Input 3 — 3 3 2 SDI I HV w/ST “smart” SPI Serial Data Input

— 3 — — — SDI/SDO

44443, 4V

(1, 3)

I/O HV w/ST “smart” SPI Serial Data Input/Output

— P — Ground — — 5 5 5 P1B A Analog No Potentiometer 1 Terminal B — — 6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal — — — 7 7 P1A A Analog No Potentiometer 1 Terminal A — 5 — 8 8 P0A A Analog No Potentiomete r 0 Terminal A

5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal 6 7 8 10 10 P0B A Analog No Potentiometer 0 Terminal B

———1112

I I “smart” Hardware EEPROM Write

Protect

———1213

SHDN

I HV w/ST “smart” Hardware Shutdown 7 — 9 13 14 SDO O O No SPI Serial Data Out 8 8 10 14 15 V

— P — Positive Power Supply Input

— — — — 11 NC — — — No Connection

(4)

—

(4)

Exposed Pad — — — Note 4

Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)

A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power

Note 1: The 8-lea d Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin

(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.

2: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-

down current.

3: The SDO is an open drain outp ut, which uses the internal “smart” pull-up. The SDI input data rate can be

at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up, customers can increase the rate with external pull-up resistors.

4: The DFN and QFN packages have a contact on the bott om of the package. This contact is conductively

connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V

pin.

MCP414X/416X/424X/426X

3.1 Chip Select (CS)

The CS pin is the serial interface’s chip select input. Forcing the CS Forcing the CS pin to V serial commands.

pin to VIL enables the serial commands.

enables the high-voltage

IHH

3.2 Serial Data In (SDI)

The SDI pin is the serial interfaces Serial Data In pin. This pin is connected to the Host Controllers SDO pin.

3.3 Serial Data In / Serial Data Out (SDI/SDO)

On the MCP41X1 devices, pin-out limitations do not allow for individual SDI and SDO pins. On these devices, the SDI and SDO pins are multiplexed.

The MCP41X1 serial interface knows when the pin needs to change from being an input (SDI) to being an output (SDO). The Host Controller’s SDO pin must be properly protected from a drive conflict.

3.4 Ground (VSS)

The VSS pin is the device ground reference.

3.5 Potentiometer Terminal B

3.7 Potentiometer Terminal A

The terminal A pin is available on the MCP4XX1 devices, and is connected to the internal potentiometer’s terminal A.

The potentiometer’s terminal A is the fixed connection to the Full Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices.

The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between V

The terminal A pin is not available on the MCP4XX2 devices, and the internally terminal A signal is floating.

MCP42X1 devices have two terminal A pins, one for each resistor network.

and VDD.

3.8 Write Protect (WP)

The WP pin is used to force the non-volatile memory to be write protected.

3.9 Shutdown (SHDN)

The SHDN pin is used to force the resistor network terminals into the hardware shutdown state.

The terminal B pin is connected to the internal potentiometer’s terminal B.

The potentiometer’s terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices.

The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between V

MCP42XX devices have two terminal B pins, one for each resistor network.

and VDD.

3.6 Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between V

MCP42XX devices have two terminal W pins, one for each resistor network.

and VDD.

3.10 Serial Data Out (SDO)

The SDO pin is the serial interfaces Serial Data Out pin. This pin is connected to the Host Controllers SDI pin.

This pin allows the Host Controller to read the digital potentiometers registers, or monitor the state of the command error bit.

3.11 Positive Power Supply Input (VDD)

The VDD pin is the device’s positive po wer supply input. The input power supply is relative to V

While the device V performance of the device may not meet the data sheet specifications.

< V

(2.7V), the electrical

min

MCP414X/416X/424X/426X

4.0 FUNCTIONAL OVERVIEW

This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration.

As the Device Block Diagram shows, there are four main functional blocks. These are:

• POR/BOR Operation

• Memory Map

• Resistor Network

• Serial Interface (SPI) The POR/BOR operation and the Memory Map are

discussed in this section and the Resistor Network and SPI operation are described in their own sections. The

Device Commands commands are discussed in

Section 7.0.

4.1 POR/BOR Operation

The Power-on Reset is the case where the device is having power applied to it from V Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range.

The devices RAM retention voltage (V than the POR/BOR voltage trip point (V maximum V

When V

POR/VBOR

voltage is less then 1.8V.

< VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed.

4.1.1 POWER-ON RESET

When the device powers up, the device VDD will cross the V

POR/VBOR

the V

POR/VBOR

• Volatile wiper register is loaded with value in the

corresponding non-volatile wiper register

• The TCON register is loaded it’s default value

• The device is capable of digital operation

voltage. Once the VDD voltage crosses voltage the following happens:

. The Brown-out

) is lower

RAM

POR/VBOR

). The

4.1.2 BROWN-OUT RESET

When the device powers down, the device VDD will cross the V

Once the V

POR/VBOR DD

voltage.

voltage decreases below the V

POR/VBOR

voltage the following happens:

• Serial Interface is disabled

• EEPROM Writes are disabled If the V

voltage decreases below the V

RAM

voltage

the following happens:

• Volatile wiper registers may become corrupted

• TCON register may become corrupted As the voltage recovers above the V

POR/VBOR

voltage

see Section 4.1.1 “Power-on Reset”. Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and non-volatile) to become corrupted.

4.2 Memory Map

The device memory is 16 locations that are 9-bits wide (16x9 bits). This memory space contains both volatile and non-volatile locations (see Table 4-1).

TABLE 4-1: MEMORY MAP

Address Function Memory Type

00h Volatile Wiper 0 RAM 01h Volatile Wiper 1 RAM 02h Non-Volatile Wiper 0 EEPROM 03h Non-Volatile Wiper 1 EEPROM 04h Volatile TCON Register RAM 05h Status Register RAM 06h Data EEPROM EEPROM 07h Data EEPROM EEPROM 08h Data EEPROM EEPROM 09h Data EEPROM EEPROM 0Ah Data EEPROM EEPROM 0Bh Data EEPROM EEPROM 0Ch Data EEPROM EEPROM 0Dh Data EEPROM EEPROM 0Eh Data EEPROM EEPROM 0Fh Data EEPROM EEPROM

MCP414X/416X/424X/426X

4.2.1 NON-VOLATILE MEMORY (EEPROM)

This memory can be grouped into two uses of non-volatile memory. These are:

• General Purpose Registers

• Non-V olatile W iper Registers

The non-volatile wipers starts functioning below the devices V

POR/VBOR

trip point.

4.2.1.1 General Purpose Registers

These locations allow the user to store up to 10 (9-bit) locations worth of information.

4.2.1.2 Non-Volatile Wiper Registers

These locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are up to two registers, one for each resistor network.

The non-volatile wiper register enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value.

4.2.1.3 Factory Initialization of Non-Volatile

Memory (EEPROM)

The Non-Volatile Wiper values will be initialized to mid-scale value. This is shown in Table 4-2.

The General purpose EEPROM memory will be programmed to a default value of 0xFF.

It is good practice in the manufacturing flow to configure the device to your desired settings.

TABLE 4-2: DEFAULT FACTORY

SETTINGS SELECTION

Wiper

Code

Resistance

-502 5.0 kΩ Mid-scale 80h 40h Disabled

-103 10.0 kΩ Mid-scale 80h 40h Disabled

-503 50.0 kΩ Mid-scale 80h 40h Disabled

-104 100.0 kΩ Mid-scale 80h 40h Disabled

Value

Typical

8-bit 7-bit

Default POR

Wiper Setting

WiperLock™

Technology and

4.2.1.4 Special Features

There are 3 non-volatile bits that are not directly mapped into the address space. These bits control the following functions:

• EEPROM Write Protect

• WiperLock Technology for Non-Volatile Wiper 0

• WiperLock Technology for Non-Volatile Wiper 1 The operation of WiperLock T echnology is discussed in

Section 5.3. The state of the WL0, WL1, and WP bits is reflected in the STATUS register (see Register 4-1).

EEPROM Write Protect

All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write commands to the internal EEPROM are prevented.

Write Protect (WP methods. These are:

• External WP only)

• Non-Volatile configuration bit

High Voltage commands are required to enable and disable the nonvolatile WP bit. These commands are shown in Section 7.9 “Modify Write Protect or Wip- erLock Technology (High Voltage)”.

To write to EEPROM, both the external WP internal WP EEPROM bit must be disabled. Write Protect does not block commands to the volatile registers.

4.2.2 VOLATILE MEMORY (RAM)

There are four Volatile Memory locations. Th e se are:

• Volatile Wiper 0

• Volatile Wiper 1 (Dual Resistor Network devices only)

• Status Register

• Terminal Control (TCON) Register

The volatile memory starts functioning at the RAM retention voltage (V

Write Protect Setting

) can be enabled/disabled by two

Hardware pin (MCP42X1 devices

pin and the

RAM

MCP414X/416X/424X/426X

4.2.2.1 Status (STATUS) Register

This register contains 5 status bits. These bits show the state of the WiperLock bits, the Shutdown bit the Write Protect bit, and if an EEPROM write cycle is active. The

STATUS register can be accessed via the READ commands. Register 4-1 describes each STATUS register bit.

The STATUS register is placed at Address 05h.

R-1 R-1 R-1 R-1 R-0 R-x R-x R-x R-x

D8:D5 EEWA WL1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 8-5 D8:D5: Reserved. Forced to “1” bit 4 EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory

locations are allowed (addresses 00h, 01h, 04h, and 05h)

0 = An EEPROM Write cycle is NOT currently occurring

bit 3 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology”

for further information) WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bits

R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wi per and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are

“Locked” (Write Protected)

0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified

Note: The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1

bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value.

bit 2 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology”

for further information) The WiperLock T echnology bits (WLx) prevents the V olatile and Non-V olatile Wiper 0 addresses and the

TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wi per and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are

“Locked” (Write Protected)

0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified

Note: The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0

bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value.

bit 1 SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.4 “Shutdown” for further information)

This bit indicates if the Hardware shutdown pin (SHDN T erminal A and forces the wiper (Terminal W) to T erminal B (see Figure 5-2). While the device is in Hardware Shutdown (the SHDN read.

1 = MCP4XXX is in the Hardware Shutdown state 0 = MCP4XXX is NOT in the Hardware Shutdown state

Note 1: Requires a High Voltage command to modify the st ate of this bit (for Non-V olatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

pin is low) the serial interface is operational so the STATUS register may be

(1)

) is low. A hardware shutdown disconnects the

WL0

(1)

SHDN WP

(1)

MCP414X/416X/424X/426X

bit 0 WP: EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further infor-

mation) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is

enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON register value (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP Voltage commands are required to enable and disable the internal WP EEPROM bit.

1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written

Note 1: Requires a High Voltage command to modify the st ate of this bit (for Non-V olatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

) and the internal non-volatile WP bit. High

MCP414X/416X/424X/426X

4.2.2.2 Terminal Control (TCON) Register

This register contains 8 control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register 4-2 describes each bit of the TCON register.

The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer.

R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

D8 R1HW R1A R1W R1B R0HW R0A R0W R0B

bit 8 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 8 D8: Reserved. Forced to “1” bit 7 R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin

1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 1 is forced to the hardware pin “shutdown” configuration

bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resisto r 1 Network

1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network

bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network

1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network

bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resisto r 1 Network

1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network

bit 3 R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin

1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration

bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resisto r 0 Network

1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network

(1, 2)

The value that is written to this register will appear on the resistor network terminals when the serial command has completed.

When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited.

When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited.

On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The Host Controller needs to detect the POR/BOR event and then update the Volatile TCON register value.

Note 1: The hardware SHDN

inactive state, the TCON register will control the state of the terminals. The SHDN state of the TCON bits.

2: These bits do not affect the wiper register values.

pin (when active) overrides the state of these bits. When the SHDN pin returns to the

pin does not modify the

MCP414X/416X/424X/426X

bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network

1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resisto r 0 Network

1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network

Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the

inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the state of the TCON bits.

2: These bits do not affect the wiper register values.

(1, 2)

(CONTINUED)

MCP414X/416X/424X/426X

257

256

255

(1)

(01h)

Analog Mux

(1)

(00h)

(1)

(FEh)

(1)

(FFh)

(1)

(100h)

Note 1: The wiper resistance is dependent on

several factors including, wiper code, device V

, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This R

variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 kΩ) compared to larger resistance devices (100.0 kΩ).

8-Bit

N =

128

127

126

(01h)

(00h)

(7Eh)

(7Fh)

(80h)

7-Bit

N =

256()

-------------=

128()

------------- -=

8-bit Device

7-bit Device

5.0 RESISTOR NETWORK

The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full scale connections. Figure 5-1 shows a block diagram for the resistive network of a device.

The Resistor Network is made up of several parts. These include:

• Resistor Ladder

•Wiper

• Shutdown (Terminal Connections) Devices have either one or two resistor networks,

These are referred to as Pot 0 and Pot 1.

5.1 Resistor Ladder Module

The resistor ladder is a series of equal value resistors

) with a connection point (tap) between the two

resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see

Figure 5-1). The en d points of the resistor ladder are

connected to analog switches which are connected to the device Terminal A and Terminal B pins. The R (and RS) resistance has small variations over voltage and temperature.

For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B).

For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B).

Equation 5-1 shows the calculation for the step

resistance.

EQUATION 5-1: RS CALCULATION

FIGURE 5-1: Resistor Block Diagram.

MCP414X/416X/424X/426X

RABN

256()

------------- -R

N = 0 to 256 (decimal)

RABN

128()

------------- -R

N = 0 to 128 (decimal)

8-bit Device

7-bit Device

5.2 Wiper

Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin.

A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder.

The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full-scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations the only resistance between the T erminal W and the other Terminal (A or B) is that of the analog switches.

A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map.

Equation 5-2 illustrates the calculation used to deter-

mine the resistance between the wiper and terminal B.

EQUATION 5-2: RWB CALCULATION

5.3 WiperLock™ Technology

The MCP4XXX device’s WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. There are two WiperLock Technology configuration bits (WL0 and WL1). These bits prevent the Non-Volatile and V olatile addresses and bits for the specified resistor network from being written.

The WiperLock technology prevents the serial commands from doing the following:

• Changing a volatile wiper value

• Writing to a non-volatile wiper memory location

• Changing the volatile TCON register value For either Resistor Network 0 or Resistor Network 1

(Potx), the WLx bit controls the following:

• Non-Volatile Wiper Register

• Volatile Wiper Register

• Volatile TCON register bits RxHW , RxA, RxW , and RxB

High Voltage commands are required to enable and disable WiperLock. Please refer to the Modify Write

Protect or WiperLock Technology (High Voltage)

command for operation.

5.3.1 POR/BOR OPERATION WHEN

WIPERLOCK TECHNOLOGY ENABLED

The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile Wiper register value with the Non-Volatile Wiper register value, refer to Section 4.1.

TABLE 5-1: VOLATILE WIPER VALUE VS.

Wiper Setting

7-bit Pot 8-bit Pot

3FFh 081h

080h 100h Full Scale (W = A),

07Fh 041h

040h 080h W = N (Mid-Scale) 03Fh

001h 000h 000h Zero Scale (W = B)

WIPER POSITION MAP

Properties

3FFh 101h

0FFh

081

07Fh

001

Reserved (Full Scale (W = A)), Increment and Decrement commands ignored

Increment commands ignored W = N

W = N

Decrement command ignored

MCP414X/416X/424X/426X

Resistor Network

SHDN (from pin) RxHW

(from TCON register)

To Pot x Hardware Shutdown Control

5.4 Shutdown

Shutdown is used to minimize the device’s current consumption. The MCP4XXX has two methods to achieve this. These are:

• Hardware Shutdown Pin (SHDN)

• Terminal Control Register (TCON) The Hardware Shutdown pin is backwards compatible

with the MCP42XXX devices.

5.4.1 HARDWARE SHUTDOWN PIN (SHDN

The SHDN pin is available on the dual potentiometer devices. When the SHDN

• The P0A and P1A terminals are disconnected

• The P0W and P1W terminals are simultaneously

connect to the P0B and P1B terminals, respectively (see Figure 5-2)

• The Serial Interface is NOT disabled, and all

Serial Interface activity is executed

• Any EEPROM write cycles are completed

The Hardware Shutdown pin mode does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When the Shutdown mode is exited

pin is inactive (VIH)):

(SHDN

• The device returns to the Wiper setting specified

by the Volatile Wiper value

• The TCON register bits return to controlling the

terminal connection state

)

pin is forced active (VIL):

5.4.2 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. This register is shown in

The RxHW bits forces the selected resistor network into the same state as the SHDN power configurations may be achieved with the RxA, RxW, and RxB bits.

Note: When the RxHW bit forces the resistor

network into the hardware SHDN state, the state of the TCON register RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits.

state, the TCON register RxA,

pin. Alternate low

5.4.3 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 5-3 shows how the SHDN pin signal and the

RxHW bit signal interact to control the hardware shutdown of each resistor network (independently). Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually “shutdown” while the hardware pin forces both resistor networks to be “shutdown” at the same time.

FIGURE 5-2: Hardware Shutdown Resistor Network Configuration.

FIGURE 5-3: RxHW bit and SHDN pin Interaction.

MCP414X/416X/424X/426X

NOTES:

MCP414X/416X/424X/426X

SDI/SDO

SDI

SDO

SDI

200 kΩ

MCP41X1

SCK

SDI

SDO

MCP4XXX

SDO

SDI

SCK

( Master Out - Slave In (MOSI) ) ( Master In - Slave Out (MISO) )

Host

Controller

Host

Controller

Typical SPI Interface Connections

Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI)

SDI/SDO

SDI

SDO

I/O

MCP41X1

I/O

SCK

Host

Controller

Alternate MCP41X1 SPI Interface Connections (Host Controller Firmware SPI)

(SDO/SDI)

(SCK)

I/O

(1)

I/O

(1)

I/O

(1)

Note 1: If High voltage commands are desired, some type of external circuitry needs to be

implemented.

6.0 SERIAL INTERFACE (SPI)

The MCP4XXX devices support the SPI serial protocol. This SPI operates in the slave mode (does not generate the serial clock).

The SPI interface uses up to four pins. These are:

- Chip Select

•CS

• SCK - Serial Clock

• SDI - Serial Data In

• SDO - Serial Data Out

Typical SPI Interfaces are shown in Figure 6-1. In the SPI interface, The Master’s Output pin is connected to the Slave’s Input pin and the Master’s Input pin is connected to the Slave’s Output pin.

The MCP4XXX SPI’s module supports two (of the four)

IHH

0,0 and 1,1.

standard SPI modes. These are Mode The SPI mode is determined by the state of the SCK pin (V inactive (VIH) to active (VIL or V

All SPI interface signals are high-voltage tolerant.

or VIL) on the when the CS pin transitions from

FIGURE 6-1: Typical SPI Interface Block Diagram.

MCP414X/416X/424X/426X

SDI/SDO

SDI

SDO

Control

“smart” pull-up

Open drain

Logic

6.1 SDI, SDO, SCK, and CS Operation

The operation of the four SPI interface pins are discussed in this section. These pins are:

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock) (Chip Select)

•CS

The serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. The Chip Select (CS

6.1.1 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal into the device. The value on this pin is latched on the rising edge of the SCK signal.

6.1.2 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out of the device. The value on this pin is driven on the falling edge of the SCK signal.

Once the CS V

), the SDO pin will be driven. The state of the SDO

IHH

pin is determined by the serial bit’s position in the command, the command selected, and if there is a command error state (CMDERR).

) pin frames the SPI commands.

pin is forced to the active level (VIL or

6.1.3 SDI/SDO

Note: MCP41X1 Devices Only .

For device packages that do not have enough pins for both an SDI and SDO pin, the SDI and SDO functionality is multiplexed onto a single I/O pin called SDI/ SDO.

The SDO will only be driven for the command error bit (CMDERR) and during the data bits of a read command (after the memory address and command has been received).

6.1.3.1 SDI/SDO Operation

Figure 6-2 shows a block diagram of the SDI/SDO pin.

The SDI signal has an internal “smart” pull-up. The value of this pull-up determines the frequency that data can be read from the device. An external pull-up can be added to the SDI/SDO pin to improve the rise time and therefore improve the frequency that data can be read.

Note: To support the High volt age requirement of

the SDI function, the SDO function is an open drain output.

Data written on the SDI/SDO pin can be at the maximum SPI frequency.

Note: Care must be take to ensure that a Drive

conflict does not exist between the Host Controllers SDO pin (or software SDI/SDO pin) and the MCP41x1 SDI/SDO pin (see

Figure 6-1).

On the falling edge of the SCK pin during th e C0 bit (see Figure 7-1), the SDI/SDO pin will start outputting the SDO value. The SDO signal overrides the control of the smart pull-up, such that whenever the SDI /SDO pin is outputting data, the smart pull-up is enabled.

The SDI/SDO pin will change from an input (SDI) to an output (SDO) after the state machine has received the Address and Command bits of the Command Byte. If the command is a Read command, then the SDI/SDO pin will remain an output for the remainder of the command. For any other command, the SDI/SDO pin returns to an input.

FIGURE 6-2: Serial I/O Mux Block

Diagram.

MCP414X/416X/424X/426X

6.1.4 SERIAL CLOCK (SCK) (SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 10 MHz. The actual clock rate depends on the configuration of the system and the serial command used. Table 6-1 shows the SCK frequency for different configurations.

TABLE 6-1: SCK FREQUENCY

Command

Memory Type Access

Non-Volatile Memory

Volatile Memory

SDI, SDO 10 MHz 10 MHz

SDI/SDO

(1)

250 kHz

SDI, SDO 10 MHz 10 MHz

SDI/SDO

(1)

250 kHz

Note 1: MCP41X1 devices only

2: Non-Volatile memory does not support

the Increment or Decrement command .

3: After a Write command, the internal write

cycle must complete before the next SPI command is received.

4: This is the maximum clock frequency

without an external pull-up resistor.

Read

Write,

Increment,

Decrement

(4)

10 MHz

(4)

10 MHz

(2, 3) (2, 3)

6.1.5 THE CS

SIGNAL

The Chip Select (CS) signal is used to select the device and frame a command sequence. To st art a command, or sequence of commands, the CS

signal must

transition from the inactive state (VIH) to an active state

or V

After the CS

IHH

signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

Note: There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

If an error condition occurs for an SPI command, then the Command byte’s Command Error (CMDERR) bit (on the SDO pin) will be driven low (V

). To exit the

error condition, the user must take the CS pin to the V level.

When the CS

pin returns to the inactive state (VIH) the SPI module resets (including the address pointer). While the CS

pin is in the inactive state (VIH), the serial interface is ignored. This allows the Host Controller to interface to other SPI devices using the same SDI, SDO, and SCK signals.

pin has an internal pull-up resistor. The resistor

The CS is disabled when the voltage on the CS pin is at the V level. This means that when the CS pin is not driven, the internal pull-up resistor will pull this signal to the V level. When the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption.

The high voltage capability of the CS

pin allows High Voltage commands. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled.

MCP414X/416X/424X/426X

SCK

Write to SSPBUF

SDI

Input Sample

SDO

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

CMDERR bit

IHH

SCK

Write to SSPBUF

SDI

Input Sample

SDO

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

CMDERR bit

IHH

6.2 The SPI Modes

The SPI module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The mode is determined by the state of the SDI pin on the rising edge of the 1st clock bit (of the 8-bit byte).

6.2.1 MODE 0,0

In Mode 0,0: SCK idle state = low (VIL), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.

6.2.2 MODE 1,1

In Mode 1,1: SCK idle state = high (VIH), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.

6.3 SPI Waveforms

Figure 6-3 thro ugh Figure6-8 show the different SPI

command waveforms. Figure 6-3 and Figure 6-4 are read and write commands. Figure 6-5 and Figure 6-6 are read commands when the SDI and SDO pins are multiplexed on the same pin (SDI/SDO). Figure 6-7 and Figure 6-8 are increment and decrement commands. The high voltage increment and decrement commands are used to enable and disable WiperLock Technology and Write Protect.

FIGURE 6-3: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).

FIGURE 6-4: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).

MCP414X/416X/424X/426X

SCK

Write to SSPBUF

SDI

Input Sample

SDO

bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12

AD3 AD2 AD1 AD0 C1 C0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CMDERR bit

Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

IHH

SCK

Write to SSPBUF

SDI

Input Sample

SDO

bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12

AD3 AD2 AD1 AD0 C1 C0

D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

CMDERR bit

Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

IHH

FIGURE 6-5: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 1,1).

FIGURE 6-6: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 0,0).

MCP414X/416X/424X/426X

bit7

bit0

bit7

bit6

bit5 bit4

bit3

bit2

bit1 bit0

SCK

Write to SSPBUF

SDI

Input Sample

SDO

AD3

AD2

AD1

AD0

“1” = “Valid” Command/Address “0” = “Invalid” Command/Address

CMDERR bit

IHH

SCK

Input Sample

SDI

bit7

bit0

SDO bit7

bit6

bit5 bit4

bit3

bit2

bit1 bit0

Write to SSPBUF

VIH

AD3

AD2

AD1

AD0

“1” = “Valid” Command/Address “0” = “Invalid” Command/Address

CMDERR bit

IHH

FIGURE 6-7: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 1,1).

FIGURE 6-8: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 0,0).

MCP414X/416X/424X/426X

A D

A D 1

A D

C1C0D9D

Memory

Command Byte

Data

Address

Bits

Command

Bits

A D

C1C0D9D8D7D6D5D4D3D2D1D

Memory

16-bit Command

Data

Address

Bits

Command

Bits

0 0 = Write Data

0 1 = INCR 1 0 = DECR 1 1 = Read Data

C C 1 0

Command

Bits

8-bit Command

Command Byte

Data Byte

7.0 DEVICE COMMANDS

The MCP4XXX’s SPI command format supports 16 memory address locations and four commands. Each command has two modes. These are:

• Normal Serial Commands

• High-Voltage Serial Commands Normal serial commands are those where the CS

driven to V CS pin is driven to V possible commands. These commands are shown in

Table7-1.

The 8-bit commands (Increment Wiper and Decre-

ment Wiper commands) contain a Command Byte,

see Figure 7-1, while 16-bit commands (Read Data and Wri t e D a ta commands) contain a C ommand Byte and a Data Byte. The Command Byte contains two data bits, see Figure 7-1.

Table7-2 shows the supported commands for each

memory location and the corresponding values on the SDI and SDO pins.

Table7-3 sho ws an overview o f all the SPI co mmands

and their interaction with other device features.

. With High-Voltage Serial Commands, the

. In each mode, there are four

IHH

pin is

7.1 Command Byte

The Command Byte has three fields, the Address, the Command, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). This is for the Write command.

The device memory is accessed when the master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte’s AD3:AD0 bits. The action desired is contained in the Command Byte’s C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock Technology and Software Write Protect.

As the Command Byte is being loaded into the device (on the SDI pin), the device’s SDO pin is driving. The SDO pin will output high bits for the first six bits of that command. On the 7th bit, the SDO pin will output the CMDERR bit state (see Section 7.3 “Error Condi- tion”). The 8th bit state depends on the the command selected.

T ABLE 7-1: COMMAND BIT OVERVIEW

C1:C0

Bit

Command

States

Read Data 16-Bits Both

Write Data 16-Bits Both

Increment

Decrement

Note 1: High Voltage Increment and Decrement

(1)

commands on select non-volatile memory locations enable/disable WiperLock Technology and the software Write Protect feature.

# of

Bits

8-Bits Volatile Only

(1)

8-Bits Volatile Only

Operates on Volatile/ Non-Volatile memory

FIGURE 7-1: General SPI Command Formats.

MCP414X/416X/424X/426X

TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS

Address

Value Function MOSI (SDI pin) MISO (SDO pin)

Command

Data

(10-bits)

(1)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111

Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0000 0100 1111 1111 Decrement Wiper — 0000 1000 1111 1111

01h Volatile Wiper 1 Write Data nn nnnn nnnn 0001 00nn nnnn nnnn 1111 1111 1111 1111

Read Data nn nnnn nnnn 0001 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0001 0100 1111 1111 Decrement Wiper — 0001 1000 1111 1111

02h NV Wiper 0 Write Data nn nnnn nnnn 0010 00nn nnnn nnnn 1111 1111 1111 1111

Read Data nn nnnn nnnn 0010 11nn nnnn nnnn 1111 111n nnnn nnnn

(3)

HV Inc. (WL0 DIS) HV Dec. (WL0 EN)

— 0010 0100 1111 1111

(4)

— 0010 1000 1111 1111

03h NV Wiper 1 Write Data nn nnnn nnnn 0011 00nn nnnn nnnn 1111 1111 1111 1111

Read Data nn nnnn nnnn 0011 11nn nnnn nnnn 1111 111n nnnn nnnn

(3)

HV Inc. (WL1 DIS) HV Dec. (WL1 EN)

(5)

Volatile

04h

TCON Register

(5)

Status Register Read Data nn nnnn nnnn 0101 11nn nnnn nnnn 1111 111n nnnn nnnn

05h

(5)

Data EEPROM Write Data nn nnnn nnnn 0110 00nn nnnn nnnn 1111 1111 1111 1111

06h

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

— 0011 0100 1111 1111

(4)

— 0011 1000 1111 1111

Read Data nn nnnn nnnn 0110 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 0111 00nn nnnn nnnn 1111 1111 1111 1111

07h

Read Data nn nnnn nnnn 0111 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1000 00nn nnnn nnnn 1111 1111 1111 1111

08h

Read Data nn nnnn nnnn 1000 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1001 00nn nnnn nnnn 1111 1111 1111 1111

09h

Read Data nn nnnn nnnn 1001 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1010 00nn nnnn nnnn 1111 1111 1111 1111

0Ah

Read Data nn nnnn nnnn 1010 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1011 00nn nnnn nnnn 1111 1111 1111 1111

0Bh

Read Data nn nnnn nnnn 1011 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1100 00nn nnnn nnnn 1111 1111 1111 1111

0Ch

Read Data nn nnnn nnnn 1100 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1101 00nn nnnn nnnn 1111 1111 1111 1111

0Dh

Read Data nn nnnn nnnn 1101 11nn nnnn nnnn 1111 111n nnnn nnnn

(5)

Data EEPROM Write Data nn nnnn nnnn 1110 00nn nnnn nnnn 1111 1111 1111 1111

0Eh

Read Data nn nnnn nnnn 1110 11nn nnnn nnnn 1111 111n nnnn nnnn

0Fh Data EEPROM Write Data nn nnnn nnnn 1111 00nn nnnn nnnn 1111 1111 1111 1111

Read Data nn nnnn nnnn 1111 11nn nnnn nnnn 1111 111n nnnn nnnn

(3)

HV Inc. (WP DIS) HV Dec. (WP EN)

— 1111 0100 1111 1111

(4)

— 1111 1000 1111 1111

Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device.

2: All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combi-

nation is a command error state and the CMDERR bit will be clear.

3: Disables WiperLock Technology for wiper 0 or wiper 1, or disables Write Protect. 4: Enables WiperLock Technology for wiper 0 or wiper 1, or enables Write Protect. 5: Reserved addresses: Increment or Decrement commands are invalid for these addresses.

SPI String (Binary)

(2)

MCP414X/416X/424X/426X

7.2 Data Byte

Only the Read Command and the Write Command use the Data Byte, see Figure 7-1. These commands concatenate the 8-bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to Full Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B.

The D9 bit is currently unused, and corresponds to the position on the SDO data of the CMDERR bit.

7.3 Error Condition

The CMDERR bit indicates if the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination (see

Table4-1). The CMDERR bit is high if the combination

is valid and low if the combination is invalid. The command error bit will also be low i f a write to a

Non-Volatile Address has been specified and another SPI command occurs before the CS inactive (VIH).

SPI commands that do not have a multiple of 8 clocks are ignored.

Once an error condition has occurred, any following commands are ignored. All following SDO bits will be low until the CMDERR condition is cleared by forcing

pin to the inactive state (VIH).

the CS

pin is driven

7.3.1 ABORTING A TRANSMISSION

All SPI transmissions must have the correct number of SCK pulses to be executed. The command is not executed until the complete number of clocks have been received. Some commands also require the CS pin to be forced inactive (VIH). If the CS pin is forced to the inactive state (VIH) the serial interface is reset. Partial commands are not executed.

SPI is more susceptible to noise than other bus protocols. The most likely case is that this noise corrupts the value of the data being clocked into the MCP4XXX or the SCK pin is injected with extra clock pulses. This may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. The extra SCK pulse will also cause the SPI data (SDI) and clock (SCK) to be out of sync. Forcing the CS inactive state (V interface will ignore activity on the SDI and SCK pins until the CS pin transition to the active state is detected

to VIL or VIH to V

Note 1: Wh en data is not being received by the

2: It is also recommended that long continu-

) resets the serial interface. The SPI

IHH

MCP4XXX, It is recommended that the

pin be forced to the inactive level (VIL)

ous command strings should be broken down into single commands or shorter continuous command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI commands.

pin to the

MCP414X/416X/424X/426X

7.4 Continuous Commands

The device supports the ability to execute commands continuously. While the CS or V

). Any sequence of valid commands may be

IHH

received. The following example is a valid sequence of events:

1. CS pin driven active (VIL or V

2. Read Command.

3. Increment Command (Wiper 0).

4. Increment Command (Wiper 0).

5. Decrement Command (Wiper 1).

pin is in the active state (V

IHH

Note 1: It is recommended that while the CS pin is

active, only one type of command should be issued. When changing commands, it is recommended to take the CS inactive then force it back to the active state.

2: It is also recommended that long

command strings should be broken down into shorter command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI command string.

6. Write Command (Volatile memory).

7. Write Command (Non-Volatile memory).

8. CS

pin driven inactive (VIH).

TABLE 7-3: COMMANDS

Writes

Value in

EEPROM

Command Name

# of

Bits

Write Data 16-Bits Yes

Operates on

Volatile/

Non-Volatile

memory

(1)

Both — unlocked

Read Data 16-Bits — Both — unlocked Increment Wiper 8-Bits — Volatile Only — unlocked Decrement Wiper 8-Bits — Volatile Only — unlocked

High

Voltage

) on

IHH

pin?

Impact on WiperLock or Write Protect

(1) (1) (1) (1)

High Voltage Write D ata 16-Bits Yes Both Yes unchanged No High Voltage Read Data 16-Bits — Both Yes unchanged Y e s High Voltage Increment Wiper 8-Bits — Volatile Only Yes unchanged No High Voltage Decrement Wiper 8-Bits — Volatile Only Yes unchanged No

Modify Write Protect or WiperLock Technology (High Voltage) -

8-Bits —

(2)

Non-Volatile

Only

(2)

Yes locked/

protected

(2)

Enable

Modify Write Protect or WiperLock Technology (High Voltage) -

8-Bits —

Non-Volatile

Only

(3)

Yes unlocked/

unprotected

(3)

Disable

Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).

2: If th e command is executed using address 02h or 03h, then that corresponding wiper is locked or

if with address 0Fh, then Write Protect is enabled.

3: If th e command is executed using with address 02h or 03h, then that corresponding wiper is unlocked or

if with address 0Fh, then Write Protect is disabled.

Works

when

Wiper is

“locked”?

No No No No

Yes

(3)

Yes

MCP414X/416X/424X/426X

A D 2

A D

00D9D8D7D6D5D4D3D2D1D

1111111111111111Valid Address/Command combination 111111

0 0 0 0 0 0 0 0 0 0 Invalid Address/Command combination

(1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS

pin is forced to the inactive state).

7.5 Write Data Normal and High Voltage

The Write command is a 16-bit command. The Write Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-2.

A Write command to a Volatile memory location changes that location after a properly formatted Write Command (16-clock) have been received.

A Write command to a Non-Volatile memory location will only start a write cycle after a properly formatted Write Command (16-clock) have been received and the

pin transitions to the inactive state (VIH).

Note: Writes to certain memory locations will be

dependant on the state of the WiperLock Technology bits and the Write Protect bit.

7.5.1 SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the active state (VILor V the inactive state (VIH) and is driven to the active state

). The 16-bit Write Command (Command Byte and

Data Byte) is then clocked in on the SCK and SDI pins. Once all 16 bits have been received, the specified volatile address is updated. A write will not occur if the write command isn’t exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations.

Figure 6-3 and Figure 6-4 show possible waveforms

for a single write.

). Typically, the CS pin will be in

IHH

7.5.2 SINGLE WRITE TO NON-VOLATILE MEMORY

The sequence to write to to a single non-volatile memory location is the same as a single write to volatile memory with the exception that after the CS driven inactive (VIH), the EEPROM write cycle (twc) is started. A write cycle will not start if the write command isn’t exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations.

After the CS interface may immediately be re-enabled by driving the

pin to the active state (VILor V

CS During an EEPROM write cycle, only serial commands

to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (t allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register . The EEW A bit in the S tatus register indicates the status of an EEPROM Write Cycle.

Once a write command to a Non-Volatile memory location has been received, NO other SPI commands should be received before the CS inactive state (VIH) or the current SPI command will have a Command Error (CMDERR) occur.

pin is driven inactive (VIH), the serial

IHH

) completes. This

pin transitions to the

pin is

FIGURE 7-2: Write Command - SDI and SDO States.

MCP414X/416X/424X/426X

A D 1

00D9D8D7D6D5D4D3D2D1D

1111111*111111111

A D 1

00D9D8D7D6D5D4D3D2D1D

1111111*111111111

A D 1

00D9D8D7D6D5D4D3D2D1D

1111111*111111111

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS

pin is driven inactive (VIH).

7.5.3 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h).

Figure 7-3 shows the sequence for three continuous

writes. The writes do not need to be to the same volatile memory address.

7.5.4 CONTINUOUS WRITES TO NON-VOLATILE MEMORY

Continuous writes to non-volatile memory are not allowed, and attempts to do so will result in a command error (CMDERR) condition.

FIGURE 7-3: Continuous Write sequence (Volatile Memory only).

MCP414X/416X/424X/426X

A D

11XXXXXXXXXX

1111111D8D7D6D5D4D3D2D1D0Valid Address/Command combination

1111110000000000Attempted Non-Volatile Memory Read

during Non-Volatile Memory Write Cycle

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

7.6 Read Data Normal and High Voltage

The Read command is a 16-bit command. The Rea d Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-4.

The first 6-bits of the Read command determine the address and the command. The 7th clock will output the CMDERR bit on the SDO pin. The remaining 9-clocks the device will transmit the 9 data bits (D8:D0) of the specified address (AD3:AD0).

Figure 7-4 shows the SDI and SDO information for a

Read command. During a write cycle (Write or High Voltage Write to a

Non-Volatile memory location) the Read command can only read the Volatile memory locations. By reading the Status Register (04h), the Host Controller can determine when the write cycle has completed (via the state of the EEWA bit).

7.6.1 SINGLE READ

The read operation requires that the CS pin be in the

or V

active state (V the inactive state (VIH) and is driven to the active state (VILor V Byte and Data Byte) is then clocked in on the SCK and SDI pins. The SDO pin starts driving data on the 7th bit (CMDERR bit) and the addressed data comes out on the 8th through 16th clocks. Figure 6-3 through

Figure 6-6 show possible waveforms for a single read. Figure 6-5 and Figure 6-6 sh ow the single read wave-

forms when the SDI and SDO signals are multiplexed on the same pin. For additional information on the multiplexing of these signals, refer to Section 6.1.3 “SDI/ SDO”.

). The 16-bit Read Command (Command

IHH

). Typically, the CS pin will be in

IHH

FIGURE 7-4: Read Command - SDI and SDO States.

MCP414X/416X/424X/426X

11XXXXXXXXXX

1111111*D8D7D6D5D4D3D2D1D

11XXXXXXXXXX

1111111*D8D7D6D5D4D3D2D1D

11XXXXXXXXXX

1111111*D8D7D6D5D4D3D2D1D

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS pin is driven inactive (VIH).

7.6.2 CONTINUOUS READS

Continuous reads allows the devices memory to be read quickly. Continuous reads are possible to all memory locations. If a non-volatile memory write cycle is occurring, then Read commands may only access the volatile memory locations.

Figure 7-5 shows the sequence for three continuous

reads. The reads do not need to be to the same memory address.

FIGURE 7-5: Continuous Read Sequence.

MCP414X/416X/424X/426X

A D 3

A D

01XX

1111111*1Note 1, 2 111111

0 0 Note 1, 3

(INCR COMMAND (n+1) )

SDI

SDO

COMMAND BYTE

Note 1: Only functions when writing the volatile

wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination. 3: Invalid Address/Command combination

all following SDO bits will be low until the CMDERR condition is cleared. (the CS

pin is forced to the inactive

state).

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).

7.7 Increment Wiper Normal and High Voltage

The Increment Command is an 8-bit command. The Increment Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6.

An Increment Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received.

Increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead.

7.7.1 SINGLE INCREMENT

Typically, the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command.

Figure 6-7 through Figure6-8 show possible

waveforms for a single increment. The increment operation requires that the CS (VILor V state (V The 8-bit Increment Command (Command Byte) is then clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock.

The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full Scale (8-bit =100h, 7-bit = 80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled. See Table 7-4 for additional information on the Increment Command versus the current volatile wiper value.

The Increment operations only require the Increment command byte while the CS for a single increment.

After the wiper is incremented to the desired position, the CS unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS should occur as soon as possible (within device specifications) after the last desired increment occurs.

). Typically, the CS pin will be in the inactive

IHH

) and is driven to the active state (VILor V

pin should be forced to VIH to ensure that

pin be in the active state

pin is active (VIL or V

pin to V

IHH

)

FIGURE 7-6: Increment Command SDI and SDO States.

Note: Table7-2 shows the valid addresses for

the Increment Wiper command. Other addresses are invalid.

TABLE 7-4: INCREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

7-bit

Pot

3FFh

081h 080h 100h Full Scale (W = A) No 07Fh

041h 040h 080h W = N (Mid-Scale) Yes 03Fh

001h 000h 000h Zero Scale (W = B) Yes

8-bit

Pot

3FFh 101h

0FFh

081

07Fh

001

Wiper (W)

Properties

Reserved (Full Scale (W = A))

W = N

Increment Command

Operates?

MCP414X/416X/424X/426X

A D 3

A D

01XXA

A D 2

01XXA

A D 2

A D

01XX

1111111*11111111*11111111*1Note 1, 2 111111

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4

11111111111111

0 0 0 0 0 0 0 0 0 0 Note 3, 4

1111111111111111111111

0 0 Note 3, 4

(INCR COMMAND (n+1) ) ( INCR COMMAND (n+2) )

(INCR COMMAND (n+3) )

SDI

SDO

COMMAND BYTE

Note 1: Only fu nctions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination. 3: Invali d Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS

pin is forced to the inactive state).

7.7.2 CONTINUOUS INCREMENTS

Continuous Increments are possible only when writing to the volatile memory registers (address 00h, and 01h).

Figure 7-7 shows a Continuous Increment sequence

for three continuous writes. The writes do not need to be to the same volatile memory address.

When executing an continuous Increment commands, the selected wiper will be altered from n to n+1 for each Increment command received. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full Scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled.

Increment commands can be sent repeatedly without raising CS the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command.

When executing a continuous command string, The Increment command can be followed by any other valid command.

The wiper terminal will move after the command has been received (8th clock).

After the wiper is incremented to the desired position, the CS unexpected transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to V should occur as soon as possible (within device specifications) after the last desired increment occurs.

until a desired condition is met. The value in

pin should be forced to VIH to ensure that

FIGURE 7-7: Continuous Increment Command - SDI and SDO States.

MCP414X/416X/424X/426X

A D

A D 1

A D

10XX

1111111*1Note 1, 2 111111

0 0 Note 1, 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1: Only fu nctions when writing the volatile

wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination. 3: Invalid Address/Command combination

all following SDO bits will be low until the CMDERR condition is cleared. (the CS

pin is forced to the inactive

state).

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).

7.8 Decrement Wiper Normal and High Voltage

The Decrement Command is an 8-bit command. The Decrement Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6.

An Decrement Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received.

Decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead.

7.8.1 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command.

Figure 6-7 through Figure6-8 show possible

waveforms for a single Decrement. The decrement operation requires that the CS (VILor V state (V Then the 8-bit Decrement Command (Command Byte) is clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on th e 7th clock.

The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value.

The Decrement commands only require the Decrement command byte, while the CS for a single decrement.

After the wiper is decremented to the desired position, the CS unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS should occur as soon as possible (within device specifications) after the last desired decrement occurs.

). Typically the CS pin will be in the inactive

IHH

) and is driven to the active state (VILor V

pin should be forced to VIH to ensure that

pin be in the active state

IHH

pin is active (VIL or V

pin to V

IHH

)

FIGURE 7-8: Decrement Command SDI and SDO States.

Note: Table7-2 shows the valid addresses for

the Decrement Wiper command. Other addresses are invalid.

T ABLE 7-5: DECREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

7-bit

Pot

3FFh

081h 080h 100h Full Scale (W = A) Yes 07Fh

041h 040h 080h W = N (Mid-Scale) Yes 03Fh

001h 000h 000h Zero Scale (W = B) No

8-bit

Pot

3FFh 101h

0FFh

081

07Fh

001

Wiper (W)

Properties

Reserved (Full Scale (W = A))

W = N

Decrement

Command

Operates?

MCP414X/416X/424X/426X

A D 3

A D

10XXA

A D 2

10XXA

A D 2

A D

10XX

1111111*11111111*11111111*1Note 1, 2 111111

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4

11111111111111

0 0 0 0 0 0 0 0 0 0 Note 3, 4

1111111111111111111111

0 0 Note 3, 4

(DECR COMMAND (n-1) ) (DECR COMMAND (n-1) )

(DECR COMMAND (n-1) )

SDI

SDO

COMMAND BYTE

Note 1: Only fu nctions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination. 3: Inval id Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS

pin is forced to the inactive state).

7.8.2 CONTINUOUS DECREMENTS

Continuous Decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h).

Figure 7-9 sho ws a continuous Decrement sequence

for three continuous writes. The writes do not need to be to the same volatile memory address.

When executing an continuous Decrement commands, the selected wiper will be altered from n to n-1 for each Decrement command received. The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See

Table7-4 for a dditional information on the Decrement

Command vs. the current volatile wiper value.

Decrement commands can be sent repeatedly without raising CS the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command.

When executing a continuous command string, The Decrement command can be followed by any other valid command.

The wiper terminal will move after the command has been received (8th clock).

After the wiper is decremented to the desired position, the CS “unexpected” transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to V should occur as soon as possible (within device specifications) after the last desired decrement occurs.

until a desired condition is met. The value in

pin should be forced to VIH to ensure that

FIGURE 7-9: Continuous Decrement Command - SDI and SDO States.

MCP414X/416X/424X/426X

7.9 Modify Write Protect or WiperLock Technology (High Voltage) Enable and Disable

This command is a special case of the High Voltage

Decrement Wiper and High V oltage Increment Wip er

commands to the non-volatile memory locations 02h, 03h, and 0Fh. This command is used to enable or disable either the software Write Protect, wiper 0 WiperLock Techn olo gy, or wiper 1 WiperLock Technology. Table 7-6 shows the memory addresses, the High Voltage command and the result of those commands on the non-volatile WP, WL0, 0r WL1 bits. The format of the command is shown in Figure 7-8 (Enable) or

Figure 7-6 (Disable).

7.9.1 SINGLE ENABLE WRITE PROTECT OR WIPERLOCK TECHNOLOGY (HIGH VOLTAGE)

Figure 6-7 through Figure6-8 show possible

waveforms for a single Modify Write Protect or WiperLock Technology command.

A Modify Write Protect or WiperLock Technology Command will only start an EEPROM write cycle (t after a properly formatted Command (8-clocks) has been received and the CS pin transitions to the inactive state (V

After the CS interface may immediately be re-enabled by driving the CS pin to the active state (VIL or V

During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (t allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register . The EEW A bit in the S tatus register indicates the status of an EEPROM Write Cycle.

pin is driven inactive (VIH), the serial

IHH

) completes. This

TABLE 7-6: ADDRESS MAP TO MODIFY WR ITE PROTECT AND WIPERLOCK TECHNOLOGY

Memory

Address

00h Wiper 0 register is inc remented Wiper 0 register is incremented 01h Wiper 1 register is inc remented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled

(1)

04h

05h - 0Eh

0Fh WP is enabled WP is disabled

Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.

High Voltage Decrement Wiper High Voltage Increment Wiper

TCON register not changed, CMDERR bit is set TCON register not changed, CMDERR bit is set

(1)

Reserved Reserved

Command’s and Result

)

MCP414X/416X/424X/426X

NOTES:

MCP414X/416X/424X/426X

Voltage Regulator

PIC MCU

MCP4XXX

SDI CS SCK WP

SHDN

SDI

SCK

SHDN

SDO

Voltage Regulator

PIC MCU

MCP4XXX

SDI CS SCK WP SHDN

SDI

SCK

SHDN

SDO

8.0 APPLICATIONS EXAMPLES

Non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP414X/416X/424X/426X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations

= 2.7V to 5.5V).

8.1 Split Rail Applications

All inputs that would be used to interface to a Host Controller support High Voltage on their input pin. This allows the MCP4XXX device to be used in split power rail applications.

An example of this is a battery application where the

MCU is directly powered by the battery supply

PIC (4.8V) and the MCP4XXX device is powered by the

3.3V regulated voltage. For SPI applications, these inputs are:

•CS

•SCK

• SDI (or SDI/SDO)

•WP

• SHDN

Figure 8-1 through Figure 8-2 show three example split

rail systems. In this system, the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (V

In Example #1 (Figure 8-1), the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (V becomes too large, then the customer may be required to do some level shifting due to MCP4XXX V related to Host Controller V

In Example #2 (Figure 8-2), the MCP4XXX interface input signals need to be able to support the lower voltage of the PIC MCU output high voltage level (V

Table8-1 shows an example PIC microcontroller I/O

voltage specifications and the MCP4XXX specifications. So this PIC MCU operating at 3.3V will drive a

at 2.64V , and for the MCP4XXX operating at 5.5V ,

the V

is 2.47V. Therefore, the interface signal s meet

specifications.

). If the split rail voltage delta

levels.

levels

FIGURE 8-1: Example Split Rail System

FIGURE 8-2: Example Split Rail System

TABLE 8-1: V

(1)

PIC

MCP4XXX

DDVIH VOHVDDVIH

5.5 4.4 4.4 2.7 1.215 —

5.0 4.0 4.0 3.0 1.35 —

4.5 3.6 3.6 3.3 1.485 —

3.3 2.64 2.64 4.5 2.025 —

3.0 2.4 2.4 5.0 2.25 —

2.7 2.16 2.16 5.5 2.475 — Note 1: V

VIH minimum = 0.8 * VDD;

maximum = 0.2 * VDD;

2: V

minimum = 0.45 * VDD;

VIL maximum = 0.2 * VDD

3: The only MCP4XXX output pin is SDO,

which is Open-Drain (or Open-Drain with Internal Pull-up) with High Voltage Support

- VIH COMPARISONS

(2)

(3) (3) (3) (3) (3) (3)

minimum = 0.8 * VDD;

maximum = 0.6V

minimum (SDA only) =;

maximum = 0.2 * VDD

Comment

MCP414X/416X/424X/426X

PIC MCU

MCP402X

IO1

IO2

TC1240A

SHDN

C+

C-

OUT

PIC10F206

MCP4XXX

GP0

GP2

Balance Bias

Input

To b ase of Transistor (or Amplifier)

Common B

Common A

8.2 Techniques to force the CS pin to V

IHH

The circuit in Figure 8-3 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS

pin is controlled by the PIC® microcontrollers (MCUs) IO2 pin.

When the SHDN pin is low, the TC1240A is on and the

voltage is 2 * VDD. The resistor R1 allows the CS

OUT

pin to go higher than the voltage such that the PIC MCU’s IO2 pin “clamps” at approximately V

DD.

FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the V

voltage.

IHH

8.3 Using Shutdown Modes

Figure 8-5 shows a possi ble application circuit where

the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the R stat value to the Common B. Disconnecting T erminal B modifies the transistor input by the RAW rheostat value

FIGURE 8-3: Using the TC1240A to generate the V

The circuit in Figure 8-4 shows the method used on the MCP402X Non-volatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the CS wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User’s Guide (DS51546) cont ains a complete schematic.

GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock.

For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the CS

For high-voltage serial commands, force the GP0 output pin to output a high level (V GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS (when the system voltage is approximately 5V).

voltage.

IHH

pin to change the stored value of the

pin (VIL or VIH).

) and configure the

to the Common A. The Common A and Common B connections could be connected to V

and VSS.

FIGURE 8-5: Example Application Circuit using Terminal Disconnects.

rheo-

MCP414X/416X/424X/426X

MCP414X/416X/

424X/426X

0.1 µF

PIC

Microcontroller

0.1 µF

U/D

8.4 Design Considerations

In the design of a system with the MCP4XXX devices, the following considerations should be taken into account:

• Power Supply Considerations

• Layout Considerations

8.4.1 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-6 illustrates an appropriate bypass strategy.

In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as

) as

and

close (within 4 mm) to the device power pin (V possible.

The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, V

should reside on the analog plane.

8.4.2 LAYOUT CONSIDERATIONS

Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4XXX’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals.

If low noise is desired, breadboards and wire-wrapped boards are not recommended.

8.4.3 RESISTOR TEMPCO

Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-8,

Figure 2-19, Figure 2-29, and Figure 2-39.

These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is R

resistance.

8.4.4 HIGH VOLTAGE TOLERANT PINS

High Voltage support (V supports two features. These are:

• In-Circuit Accommodation of split rail applications and power supply sync issues

• User configuration of the Non-Volatile EEPROM, Write Protect, and WiperLock feature

Note: In many applications, the High Voltage will

only be present at the manufacturing stage so as to “lock” the Non-Volatile wiper value (after calibration) and the contents of the EEPROM. This ensures that the since High Voltage is not present under normal operating conditions, that these values can not be modified.

) on the Serial Interface pins

IHH

FIGURE 8-6: Typical Microcontroller Connections.

MCP414X/416X/424X/426X

NOTES:

MCP414X/416X/424X/426X

9.0 DEVELOPMENT SUPPORT

9.1 Development Tools

Several development tools are available to assist in your design and evaluation of the MCP4XXX devices. The currently available tools are shown in Table 9-1.

These boards may be purchased directly from the Microchip web site at www.microchip.com.

9.2 Technical Documentation

Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents.

TABLE 9-1: DEVELOPMENT TOOLS

Board Name Part # Supported Devices

MCP4XXX Digital Potentiometer Daughter Board

8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board SOIC8EV Any 8-pin device in DIP, SOIC, MSOP,

14-pin SOIC/MSOP/DIP Evaluation Board SOIC14EV Any 14-pin device in DIP, SOIC, or

Note 1: Requires the use of a PICDEM Demo board (see User’s Guide for details)

(1)

MCP4XXXDM-DB MCP42XXX, MCP42XX, MCP4021,

and MCP4011

or TSSOP package

MSOP package

TABLE 9-2: TECHNICAL DOCUMENTATION

Application Note Number

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS002 19 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825

Title Literature #

MCP414X/416X/424X/426X

NOTES:

10.0 PACKAGING INFORMATION

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

8-Lead DFN (3x3)

Example

Part Number Code Part Number Code

MCP4131-502E/MF DAAE MCP4132-502E/MF DAAY MCP4131-103E/MF DAAF MCP4132-103E/MF DAAZ MCP4131-104E/MF DAAH MCP4132-104E/MF DABB MCP4131-503E/MF DAAG MCP4132-503E/MF DABA MCP4141-502E/MF DAAJ MCP4142-502E/MF DABC MCP4141-103E/MF DAAK MCP4142-103E/MF DABD MCP4141-104E/MF DAAM MCP4142-104E/MF DABF MCP4141-503E/MF DAAL MCP4142-503E/MF DABE MCP4151-502E/MF DAAP MCP4152-502E/MF DAAA MCP4151-103E/MF DAAQ MCP4152-103E/MF DABD MCP4151-104E/MF DAAS MCP4152-104E/MF DAAD MCP4151-503E/MF DAAR MCP4152-503E/MF DAAC MCP4161-502E/MF DAAT MCP4162-502E/MF DABG MCP4161-103E/MF DAAU MCP4162-103E/MF DABH MCP4161-104E/MF DAAW MCP4162-104E/MF DABK MCP4161-503E/MF DAAV MCP4162-503E/MF DABJ

DAAE E733

256

XXXX XYWW

NNN

10.1 Package Marking Information

MCP414X/416X/424X/426X

Legend: XX...X Customer-specific information

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

8-Lead MSOP

XXXXXX YWWNNN

Example

413152

733256

Part Number Code Part Number Code

MCP4131-502E/MS 413152 MCP4132-502E/MS 413252 MCP4131-103E/MS 413113 MCP4132-103E/MS 413213 MCP4131-104E/MS 413114 MCP4132-104E/MS 413214 MCP4131-503E/MS 413153 MCP4132-503E/MS 413253 MCP4141-502E/MS 414152 MCP4142-502E/MS 414252 MCP4141-103E/MS 414113 MCP4142-103E/MS 414213 MCP4141-104E/MS 414114 MCP4142-104E/MS 414214 MCP4141-503E/MS 414153 MCP4142-503E/MS 414253 MCP4151-502E/MS 415152 MCP4152-502E/MS 415252 MCP4151-103E/MS 415113 MCP4152-103E/MS 415213 MCP4151-104E/MS 415114 MCP4152-104E/MS 415214 MCP4151-503E/MS 415153 MCP4152-503E/MS 415253 MCP4161-502E/MS 416152 MCP4162-502E/MS 416252 MCP4161-103E/MS 416113 MCP4162-103E/MS 416213 MCP4161-104E/MS 416114 MCP4162-104E/MS 416214 MCP4161-503E/MS 416153 MCP4162-503E/MS 416253

XXXXXNNN

8-Lead PDIP

XXXXXXXX

YYWW

E/P 256

Example

4131-502

0733

8-Lead SOIC

XXXXXXXX

XXXXYYWW

NNN

Example

4131502E

SN^^^0733

256

Package Marking Information (Continued)

MCP414X/416X/424X/426X

10-Lead DFN (3x3)

Example

Part Number Code Part Number Code

MCP4232-502E/MF BAEH MCP4252-502E/MF BAES MCP4232-103E/MF BAEJ MCP4252-103E/MF BAET MCP4232-104E/MF BAEL MCP4252-104E/MF BAEV MCP4232-503E/MF BAEK MCP4252-503E/MF BAEU MCP4242-502E/MF BAEM MCP4262-502E/MF BAEW MCP4242-103E/MF BAEP MCP4262-103E/MF BAEX MCP4242-104E/MF BAER MCP4262-104E/MF BAEZ MCP4242-503E/MF BAEQ MCP4262-503E/MF BAEY

BAEH

0733

256

XXXX

YYWW

NNN

10-Lead MSOP

XXXXXX YWWNNN

Example

423252

733256

Part Number Code Part Number Code

MCP4232-502E/MS 423252 MCP4252-502E/MS 425252 MCP4232-103E/MS 423213 MCP4252-103E/MS 425213 MCP4232-104E/MS 423214 MCP4252-104E/MS 425214 MCP4232-503E/MS 423253 MCP4252-503E/MS 425253 MCP4242-502E/MS 424252 MCP4262-502E/MS 426252 MCP4242-103E/MS 424213 MCP4262-103E/MS 426213 MCP4242-104E/MS 424214 MCP4262-104E/MS 426214 MCP4242-503E/MS 424253 MCP4262-503E/MS 426253

Package Marking Information (Continued)

MCP414X/416X/424X/426X

Legend: XX...X Customer-specific information

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

14-Lead TSSOP

XXXXXXXX

YYWW

NNN

Example

4261502E

0733

256

XXXXX

16-Lead QFN

XXXXXX

YYWWNNN

Example

14-Lead PDIP

XXXXXXXXXXXXXX XXXXXXXXXXXXXX

YYWWNNN

Example

14-Lead SOIC (.150”)

XXXXXXXXXXX XXXXXXXXXXX

YYWWNNN

Example

MCP4261 502E/SL^^

0733256

MCP4261 502E/P^^

0733256

XXXXXX

4261

502

0733256

E/ML^^

Package Marking Information (Continued)

MCP414X/416X/424X/426X

8-Lead Plastic Dual Flat, No Lead Package (MF) – 3x3x0.9 mm Body [DFN]

Notes:

1. Pin 1 visual index feature may vary, but must be located withi n the hatched area.

2. Package may have one or more exposed t ie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 3.00 BSC Exposed Pad Width E2 0.00 – 1.60 Overall Width E 3.00 BSC Exposed Pad Length D2 0.00 – 2.40 Contact Width b 0.25 0.30 0.35 Contact Length L 0.20 0.30 0.55 Contact-to-Exposed Pad K 0.20 – –

BOTTOM VIEW

TOP VIEW

NOTE 1

EXPOSED PAD

NOTE 1

NOTE 2

Microchip Technology Drawing C04-062B

MCP414X/416X/424X/426X

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimens ioning and tolerancing per ASME Y14.5M. BSC: Basic Di mension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1. 10 Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 – 0.15 Overall Width E 4.90 BSC Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L 0.40 0.60 0.80 Footprint L1 0.95 REF Foot Angle φ 0° – 8° Lead Thickness c 0.08 – 0.23 Lead Width b 0.22 – 0.40

NOTE 1

Microchip Technology Drawing C04-111B

MCP414X/416X/424X/426X

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensi ons D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimens ioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018B

MCP414X/416X/424X/426X

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimens ioning and tolerancing per ASME Y14.5M. BSC: Basic Di mension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1. 75 Molded Package Thickness A2 1.25 – – Standoff

§ A1 0.10 – 0.25

Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057B

MCP414X/416X/424X/426X

10-Lead Plastic Dual Flat, No Lead Package (MF) – 3x3x0.9 mm Body [DFN]

Notes:

1. Pin 1 visual index feature may vary, but must be located withi n the hatched area.

2. Package may have one or more exposed t ie bars at ends.

3. Package is saw singulated.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 10 Pitch e 0.50 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 3.00 BSC Exposed Pad Length D2 2.20 2.35 2.48 Overall Width E 3.00 BSC Exposed Pad Width E2 1.40 1.58 1.75 Contact Width b 0.18 0.25 0.30 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – –

NOTE 1

EXPOSED

PAD

BOTTOM VIEW

TOP VIEW

NOTE 2

Microchip Technology Drawing C04-063B

MCP414X/416X/424X/426X

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimens ioning and tolerancing per ASME Y14.5M. BSC: Basic Di mension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 10 Pitch e 0.50 BSC Overall Height A – – 1. 10 Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 – 0.15 Overall Width E 4.90 BSC Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L 0.40 0.60 0.80 Footprint L1 0.95 REF Foot Angle φ 0° – 8° Lead Thickness c 0.08 – 0.23 Lead Width b 0.15 – 0.33

NOTE 1

Microchip Technology Drawing C04-021B

MCP414X/416X/424X/426X

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensi ons D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimens ioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430

NOTE 1

b e

Microchip Technology Drawing C04-005B

MCP414X/416X/424X/426X

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located withi n the hatched area.

2. § Signi ficant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1. 27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15°

NOTE 1

2 3

Microchip Technology Drawing C04-065B

MCP414X/416X/424X/426X

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located withi n the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 4.90 5.00 5.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30

NOTE 1

Microchip Technology Drawing C04-087B

MCP414X/416X/424X/426X

16-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN]

Notes:

1. Pin 1 visual index feature may vary, but must be located withi n the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX Number of Pins N 16 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 4.00 BSC Exposed Pad Width E2 2.50 2.65 2.80 Overall Length D 4.00 BSC Exposed Pad Length D2 2.50 2.65 2.80 Contact Width b 0.25 0.30 0.35 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – –

EXPOSED

PAD

NOTE 1

TOP VIEW

BOTTOM VIEW

Microchip Technology Drawing C04-127B

MCP414X/416X/424X/426X

APPENDIX A: REVISION HISTORY

Revision A (August 2007)

• Original Release of this Document.

APPENDIX B: MIGRATING FROM

THE MCP41XXX AND MCP42XXX DEVICES

This is intended to give an overview of some of the differences to be aware of when migrating from the MCP41XXX and MCP42XXX devices.

B.1 MCP41XXX to MCP41XX

Differences

Here are some of the differences to be aware of:

1. SI pin is now SDI/SDO pin, and the contents of the device memory can be read

2. Need to address the Terminal Connect Feature (TCON register) of MCP41XX

3. MCP41XX supports software Shutdown mode

4. New 5 kΩ version

5. MCP41XX have 7-bit resolution options

6. MCP41XX are Non-Volatile

7. Alternate pinout versions (for Rheostat configuration)

8. Verify device’s electrical specifications

9. Interface signals are now high volt age tolerant

10. Interface signals now have internal pull-up resistors

B.2 MCP42XXX to MCP42XX

Differences

Here are some of the differences to be aware of:

1. Hardware Reset (RS Write Protect (WP

2. Daisy chaining of devices is no longer supported

3. SDO pin allows contents of device memory to be read

4. Need to address the Terminal Connect Feature (TCON register) of MCP42XX

5. MCP42XX supports software Shutdown mode

6. New 5 kΩ version

7. MCP42XX have 7-bit resolution options

8. MCP42XX are Non-Volatile

9. Alternate package/pinout versions (for Rheostat configuration)

10. Verify device’s electrical specifications

1 1. Interface signals are now high voltage tolerant

12. Interface signals now have internal pull-up resistors

) pin replace by Hardware

) pin

MCP414X/416X/424X/426X

NOTES:

MCP414X/416X/424X/426X

Device: MCP4131: Single Volatile 7-bit Potentiometer

MCP4131T: Single Volatile 7-bit Potentiometer

(Tape and Reel) MCP4132: Single Volatile 7-bit Rheostat MCP4132T: Single Volatile 7-bit Rheostat

(Tape and Reel) MCP4141: Single Non-Volatile 7-bit Potentiometer MCP4141T: Single Non-Volatile 7-bit Potentiometer

(Tape and Reel) MCP4142: Single Non-Volatile 7-bit Rheostat MCP4142T: Single Non-Volatile 7-bit Rheostat

(Tape and Reel) MCP4151: Single Volatile 8-bit Potentiometer MCP4151T: Single Volatile 8-bit Potentiometer

(Tape and Reel) MCP4152: Single Volatile 8-bit Rheostat MCP4152T: Single Volatile 8-bit Rheostat

(Tape and Reel) MCP4161: Single Non-Volatile 8-bit Potentiometer MCP4161T: Single Non-Volatile 8-bit Potentiometer

(Tape and Reel) MCP4162: Single Non-Volatile8-bit Rheostat MCP4162T: Single Non-Volatile 8-bit Rheostat

(Tape and Reel) MCP4231: Dual Volatile 7-bit Potentiometer MCP4231T: Dual Volatile 7-bit Potentiometer

(Tape and Reel) MCP4232: Dual Volatile 7-bit Rheostat MCP4232T: Dual Volatile 7-bit Rheostat

(Tape and Reel) MCP4241: Dual Non-Volatile 7-bit Potentiometer MCP4241T: Dual Non-Volatile 7-bit Potentiometer

(Tape and Reel) MCP4242: Dual Non-Volatile 7-bit Rheostat MCP4242T: Dual Non-Volatile 7-bit Rheostat

(Tape and Reel) MCP4251: Dual Volatile 8-bit Potentiometer MCP4251T: Dual Volatile 8-bit Potentiometer

(Tape and Reel) MCP4252: Dual Volatile 8-bit Rheostat MCP4252T: Dual Volatile 8-bit Rheostat

(Tape and Reel) MCP4261: Dual Non-Volatile 8-bit Potentiometer MCP4261T: Dual Non-Volatile 8-bit Potentiometer

(Tape and Reel) MCP4262: Dual Non-Volatile8-bit Rheostat MCP4262T: Dual Non-Volatile 8-bit Rheostat

(Tape and Reel)

Resistance Version: 502 = 5 kΩ

103 = 10 kΩ 503 = 50 kΩ 104 = 100 kΩ

Temperature Range: E = -40°C to +125°C

Package: MF = Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead

ML = Plastic Quad Flat No-lead (QFN), 16-lead MS = Plastic Micro Small Outline (MSOP), 8-lead P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead SL = Plastic Small Outline (SOIC), (150 mil), 14-lead ST = Plastic Thin Shrink Small Outline (TSSOP), 14-lead UN = Plastic Micro Small Outline (MSOP), 10-lead

PART NO. X /XX

PackageTemperature

Range

Device

Examples:

a) MCP4131-502E/XX: 5 kΩ, 8LD Device b) MCP4131T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4131-103E/XX: 10 kΩ, 8-LD Device d) MCP4131T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4131-503E/XX: 50 kΩ, 8LD Device f) MCP4131T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4131-104E/XX: 100 kΩ, 8LD Device h) MCP4131T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4132-502E/XX: 5 kΩ, 8LD Device b) MCP4132T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4132-103E/XX: 10 kΩ, 8-LD Device d) MCP4132T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4132-503E/XX: 50 kΩ, 8LD Device f) MCP4132T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4132-104E/XX: 100 kΩ, 8LD Device h) MCP4132T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4151-502E/XX: 5 kΩ, 8LD Device b) MCP4151T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4151-103E/XX: 10 kΩ, 8-LD Device d) MCP4151T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4151-503E/XX: 50 kΩ, 8LD Device f) MCP4151T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4151-104E/XX: 100 kΩ, 8LD Device h) MCP4151T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4152-502E/XX: 5 kΩ, 8LD Device b) MCP4152T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4152-103E/XX: 10 kΩ, 8-LD Device d) MCP4152T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4152-503E/XX: 50 kΩ, 8LD Device f) MCP4152T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4152-104E/XX: 100 kΩ, 8LD Device h) MCP4152T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4231-502E/XX: 5 kΩ, 8LD Device b) MCP4231T-502E/XX: T/R, 5 kΩ,

8LD Device c) MCP4231-103E/XX: 10 kΩ, 8-LD Device d) MCP4231T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4231-503E/XX: 50 kΩ, 8LD Device f) MCP4231T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4231-104E/XX: 100 kΩ, 8LD Device h) MCP4231T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4232-502E/XX: 5 kΩ, 8LD Device b) MCP4232T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4232-103E/XX: 10 kΩ, 8-LD Device d) MCP4232T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4232-503E/XX: 50 kΩ, 8LD Device f) MCP4232T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4232-104E/XX: 100 kΩ, 8LD Device h) MCP4232T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4251-502E/XX: 5 kΩ, 8LD Device b) MCP4251T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4251-103E/XX: 10 kΩ, 8-LD Device d) MCP4251T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4251-503E/XX: 50 kΩ, 8LD Device f) MCP4251T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4251-104E/XX: 100 kΩ, 8LD Device h) MCP4251T-104E/XX: T/R, 100 kΩ, 8LD Device

a) MCP4252-502E/XX: 5 kΩ, 8LD Device b) MCP4252T-502E/XX: T/R, 5 kΩ, 8LD Device

c) MCP4252-103E/XX: 10 kΩ, 8-LD Device d) MCP4252T-103E/XX: T/R, 10 kΩ, 8LD Device e) MCP4252-503E/XX: 50 kΩ, 8LD Device f) MCP4252T-503E/ XX: T/R, 50 kΩ, 8LD Device g) MCP4252-104E/XX: 100 kΩ, 8LD Device h) MCP4252T-104E/XX: T/R, 100 kΩ, 8LD Device

XX = MF for 8/10-lead 3x3 DFN

= ML for 16-lead QFN = MS for 8-lead MSOP = P for 8/14-lead PDIP = SN for 8-lead SOIC = SL for 14-lead SOIC = ST for 14-lead TSSOP = UN for 10-lead MSOP

XXX

Resistance

Version

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

MCP414X/416X/424X/426X

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and T empe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the desig n and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

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Tel: 44-118-921-5869 Fax: 44-118-921-5820

06/25/07

MICROCHIP MCP414X, MCP416X, MCP424X, MCP426X Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 ELECTRICAL CHARACTERISTICS

2.0 TYPICAL PERFORMANCE CURVES

3.0 PIN DESCRIPTIONS

4.0 FUNCTIONAL OVERVIEW

5.0 RESISTOR NETWORK

6.0 SERIAL INTERFACE (SPI)

7.0 DEVICE COMMANDS

8.0 APPLICATIONS EXAMPLES

9.0 DEVELOPMENT SUPPORT

10.0 PACKAGING INFORMATION