MICROCHIP MCP23008, MCP23S08 Technical data
MCP23008/MCP23S08
8-Bit I/O Expander with Serial Interface
Features
• 8-bit remote bidirectional I/O port
- I/O pins default to input
• High-speed I
-100kHz
-400kHz
-1.7MHz
• High-speed SPI™ interface (MCP23S08)
-10MHz
• Hardware address pins
- Three for the MCP23008 to allow up to eight
devices on the bus
- Two for the MCP23S08 to allow up to four
devices using the same chip-select
• Configurable interrupt output pin
- Configurable as active-high, active-low or
open-drain
• Configurable interrupt source
- Interrupt-on-change from confi gure d de faul t s
or pin change
• Polarity Inversion re giste r to co nfigure the p olarity
of the input port data
• External reset input
• Low standby current: 1 µA (max.)
• Operating voltag e:
- 1.8V to 5.5V @ -40°C to +85°C (I-Temp)
- 2.7V to 5.5V @ -40°C to +85°C (I-Temp)
- 4.5V to 5.5V @ -40°C to +125°C (E-Temp)
2
C™ interface (MCP23008)
Packages
18-pin PDIP (300 mil)
18-pin SOIC (300 mil)
20-pin SSOP
Package Types
MCP23008
SCL
SDA
A2
A1
A0
RESET
NC
INT
V
SS
SCL
SDA
A2
A1
A0
RESET
NC
INT
VSS
N/C
MCP23S08
SCK
SI
SO
A1
A0
RESET
CS
INT
VSS
SCK
SI
SO
A1
A0
RESET
CS
INT
VSS
N/C
PDIP/SOIC
1
2
3
4
5
6
MCP23008
7
8
9
SSOP
1
2
3
4
5
6
7
MCP23008
8
9
10
PDIP/SOIC
1
2
3
4
5
6
MCP23S08
7
8
9
SSOP
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
MCP23S08
13
12
11
DD
V
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
V
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
DD
V
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
V
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
DD
DD
GP7
© 2005 Microchip Technology Inc. DS21919B-page 1
MCP23008/MCP23S08
Block Diagram
MCP23S08
SCK
SI
SO
MCP23008
MCP23S08
A1:A0
SCL
SDA
A2:A0
RESET
INT
3
Serial
Interface
Decode
Interrupt
Logic
Serializer/
Deserializer
Control
8
GP0
8
GPIO
GP1
GP2
GP3
GP4
GP5
GP6
GP7
VDD
VSS
POR
Configuration/
Control
Registers
DS21919B-page 2 © 2005 Microchip Technology Inc.
MCP23008/MCP23S08
1.0 DEVICE OVERVIEW
The MCP23X08 device provides 8-bit, general
purpose, parallel I/O expansion for I
applications. The two devices differ in the number of
hardware address pins and the serial interface:
2
• MCP23008 – I
• MCP23S08 – SPI interface; two address pins
The MCP23X08 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writi ng the I/O configur ation bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register . All registers ca n be read by the sy stem maste r.
C interface; three address pins
2
C bus or SPI
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input stat e differs from a preconfigure d
register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initi ali zes the device state mach in e.
The hardware address pins are used to determine the
device address.
1.1 Pin Descriptions
TABLE 1-1: PINOUT DESCRIPTION
Pin
Name
SCL/SCK 1 1 I Serial clock input.
SDA/SI 2 2 I/O Serial data I/O (MCP23008)/Serial data input (MCP23S08).
A2/SO 3 3 I/O Hardware address input (MCP23008)/Serial data output (MCP23S08).
A1 4 4 I Hardware address input. Must be biased externally.
A0 5 5 I Hardware address input. Must be biased externally.
RESET
NC/CS 7 7 I No connect (MCP23008)/External chip select input (MCP23S08).
INT 8 8 O Interrupt output. Can be configured for active-high, active-low or open-drain.
SS 9 9 P Ground.
V
GP0 10 12 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP1 11 13 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP2 12 14 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP3 13 15 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP4 14 16 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP5 15 17 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP6 16 18 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
GP7 17 19 I/O Bidirectional I/O pin. Can be enabled for interrupt -on-change an d/or interna l weak
DD 18 20 P Power.
V
N/C 10, 1 1
PDIP/S
SSOP
OIC
6 6 I External reset input
Pin
Type
A2 must be biased externally.
pull-up resistor.
pull-up resistor.
pull-up resistor.
pull-up resistor.
pull-up resistor.
pull-up resistor.
pull-up resistor.
pull-up resistor.
Function
© 2005 Microchip Technology Inc. DS21919B-page 3
MCP23008/MCP23S08
1.2 Power-on Reset (POR)
The on-chip P OR c ircui t ho lds the device in r eset unt il
DD has reached a high enough voltage to deactivate
V
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 2.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequen cy, etc.) must be met to
ensure proper operation.
1.3 Serial Interface
This block handles the functionality of the I2C
(MCP23008) or SPI (MCP23S08) interface protocol.
The MCP23X08 contains eleven registers that can be
addressed through the serial interface block (Table 1-2):
TABLE 1-2: REGISTER ADDRESSES
Address Access to:
00h IODIR
01h IPOL
02h GPINTEN
03h DEFVAL
04h INTCON
05h IOCON
06h GPPU
07h INTF
08h INTCAP (Read-only)
09h GPIO
0Ah OLAT
1.3.1 SEQUENTIAL OPERATION BIT
The Sequential Operation (SEQOP) bit (IOCON
register) controls the operation of the address pointer.
The address pointer can either be enabled (default) to
allow the address pointer to increment automatically
after each data transfer, or it can be disabled.
When operating in Sequential mode
(IOCON.SEQOP = 0), the address pointer automatically increments to the next address after each byte
is clocked.
When operating in Byte mode (IOCON.SEQOP = 1),
the MCP23X08 does not increment its address
counter after each byte during the data transfer. This
gives the ability to contin ually read the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes.
1.3.2 I2C™ INTERFACE
1.3.2.1 I
The I2C Write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23008. The operation is ended with a STOP
or RESTART condition being generated by the master.
Data is written to the MCP23008 after every byte
transfer. If a STOP or RESTART condition is
generated during a data transfer, the data will not be
written to the MCP23008.
Byte writes and sequential writes are both supported
by the MCP23008. The MCP23008 increments its
address counter after each ACK during the data
transfer.
2
C Write Operation
1.3.2.2 I2C Read Operation
The I2C Read operation includes the control byte
sequence, as shown in the bottom of Figure 1-1. This
sequence is followed by another control byte (including the START condition and ACK) with the R/W bit
equal to a logic 1 (R/W = 1). The MCP23008 then
transmits the data contained in the addressed register.
The sequence is ended with the master generating a
STOP or RESTART condition.
1.3.2.3 I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a STOP or RESTART condition after the
data transfer , the master cl ocks the next byte pointe d to
by the address pointe r (see Section 1.3.1 “Sequ ential
Operation Bit” for details regarding sequential
operation control).
The sequence ends with the master sendin g a STOP or
REST AR T co ndi tio n.
The MCP23008 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
1.3.3 SPI™ INTERFACE
1.3.3.1 SPI Write Operation
The SPI Write opera tion is st arted by lowe ring CS . The
Write command (slave address with R/W bit cleared) is
then clocked into the dev ice. The opcod e is followed by
an address and at least one data byte.
1.3.3.2 SPI Read Operation
The SPI Read operation is st arted by lowe ring CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the dev ice. The opcod e is followed by
an address, with at least one data byte being clocked
out of the device.
DS21919B-page 4 © 2005 Microchip Technology Inc.
MCP23008/MCP23S08
FIGURE 1-1: MCP23008 I2C™ DEVICE PROTOCOL
- START
S
- RESTART
SR
P
w
R
- STOP
- Write
- Read
OP
S P
- Device opcode
OP ADDR
W
DIN DIN
SR
SR WOP
OP
....
D
OUT
R
D
IN
....
....
DOUT
DIN
P
P
ADDR
DOUT
DIN
- Device address
- Data out from MCP23008
- Data into MCP23008
OP
S
Byte
Sequential
S WOP ADDR
S PWOP ADDR
P
R
SR R
SR OP
P
Byte and Sequential Write
Byte and Sequential Read
DOUT DOUT
W
DIN
DIN
OP
....
ADDR
....
D
P
DIN
OUT
D
P
DOUT
....
IN
....
DIN
P
P
D
D
OUT
OUT
....
P
DOUT
P
Byte
S
OP SR ROP
Sequential
OP SR R
S
1.3.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS
pointed to by the address pointer.
The sequence ends by the raising of CS.
The MCP23S08 address pointer will roll over to
address zero after reaching the last register address.
© 2005 Microchip Technology Inc. DS21919B-page 5
, the master clocks the next byte
R
R
OP
1.4 Hardware Address Decoder
The hardware address pins are used to determine the
device address. To address a device, the corresponding address bits in the control byte must match the pin
state.
• MCP23008 has address pins A2, A1 and A0.
• MCP23S08 has address pins A1 and A0.
The pins must be biased externally.
MCP23008/MCP23S08
1.4.1 ADDRESSING I2C DEVICES
(MCP23008)
The MCP23008 is a slave I2C device that supports 7-bit
slave addressing, with the read/write bit filling out the
control byte. The slave address contains fo ur fixed bits
and three user-defined hardware address bits (pins A2,
A1 and A0). Figure 1-2 shows the control byte format.
1.4.2 ADDRESSING SPI DEVICES
(MCP23S08)
The MCP23S08 is a slave SPI device. The slave
address contains five fixed bits and two user-defined
hardware address bits (pins A1 and A0), with the
read/write bit filling out the control byte. Figure 1-3
shows the control byte format.
FIGURE 1-2: I2C™ CONTROL BYTE
FORMAT
Control Byte
S 0 1 0 0 A2A1A0R/WACK
Slave Address
Start
bit
R/W = 0 = write
R/W = 1 = read
R/W bit
ACK bit
FIGURE 1-3: SPI™ CONTROL BYTE
FORMAT
CS
Control Byte
01000A1A0R/W
Slave Address
R/W bit
R/W = 0 = write
R/W = 1 = read
FIGURE 1-4: I
S0100A2A1A00ACKA7A6A5A4A3A2A1A0ACK
2
C™ ADDRESSING REGISTERS
R/W = 0
Device Opcode Register Address
The ACKs are provided by the MCP23008.
FIGURE 1-5: SPI™ ADDRESSING REGISTERS
CS
01000A1A0R/W A7A6A5A4A3A2A1A0
Device Opcode Register Address
DS21919B-page 6 © 2005 Microchip Technology Inc.
MCP23008/MCP23S08
1.5 GPIO Port
The GPIO module contains the data port (GPIO),
internal pull up resistors and the Output Latches
(OLAT).
1.6 Configuration and Control Registers
The Configuration and Control blocks contain the
registers as shown in Table 1-3.
Reading the GPIO regi ster read s the va lue on th e port.
Reading the OLAT register only reads the OLAT, not
the actual value on the port.
Writing to the GPIO register actually causes a write to
the OLAT. Writing to the OLAT register forces the
associated output drivers to drive to the level in OLAT.
Pins configured as inpu ts turn of f the ass ociated outp ut
driver and put it in high-impedance.
TABLE 1-3: CONFIGURATION AND CONTROL REGISTERS
Register
Name
IODIR 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOL 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTEN 02 G PINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVAL 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCON 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 05
GPPU 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTF 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAP 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIO 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLAT 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
Address
(hex)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — SREAD DISSLW HAEN * ODR INTPOL — --00 000-
* Not used on the MCP23008.
POR/RST
value
© 2005 Microchip Technology Inc. DS21919B-page 7
MCP23008/MCP23S08
1.6.1 I/O DIRECTION (IODIR) REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 1-1: IODIR – I/O DIRECTION REGISTER (ADDR 0x00)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 0
bit 7-0 IO7:IO0: These bits control the direction of data I/O <7:0>.
1 = Pin is configured as an input.
0 = Pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS21919B-page 8 © 2005 Microchip Technology Inc.
MCP23008/MCP23S08
1.6.2 INPUT POLARITY (IPOL) REGISTER
The IPOL register allows the user to configure the
polarity on the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted va lue on the pin.
REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
bit 7 bit 0
bit 7-0 IP7:IP0: These bits control the polarity inversion of the input pins <7:0>.
1 = GPIO register bit will reflect the opposite logic state of the input pin.
0 = GPIO register bit will reflect the same logic state of the input pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc. DS21919B-page 9
MCP23008/MCP23S08
1.6.3 INTERRUPT-ON-CHANGE
CONTROL (GPINTEN) REGISTER
The GPINTEN register controls the interrupt-onchange feature for each pin.
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
bit 7 bit 0
bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0>.
1 = Enable GPIO input pin for interrupt-on-change event.
0 = Disable GPIO input pin for interrupt-on-change event.
Refer to INTCON and GPINTEN.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS21919B-page 10 © 2005 Microchip Technology Inc.
MCP23008/MCP23S08
1.6.4 DEFAULT COMPARE (DEFVAL)
REGISTER FOR INTERRUPT-ONCHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur .
REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0
bit 7 bit 0
bit 7-0 DEF7:DEF0: These bits set the compare value for pin s configured for interrupt-on-ch ange from
defaults <7:0>. Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc. DS21919B-page 11
MCP23008/MCP23S08
1.6.5 INTERRUPT CONTROL (INTCON)
REGISTER
The INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is
compared against the previous value.
REGISTER 1-5: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
bit 7-0 IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-
change <7:0>.
1 = Controls how the associated pin value is compared for interrupt-on-change.
0 = Pin value is compared against the previous pin value.
Refer to INTCON and GPINTEN.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS21919B-page 12 © 2005 Microchip Technology Inc.
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