The MCP201 provides a physical interface between a
microcontroller and a LIN half-du plex bus. It is i ntended
for automotive and industrial applications with serial
bus speeds up to 20 Kbaud.
The MCP201 provides a half-duplex, bidirectional
communications interface between a microcontroller
and the serial network bus. This device will translate
the CMOS/TTL logic levels to LIN level logic, and vice
versa.
The LIN specification 1.3 requires that the transceiver
of all nodes in the system be connected via the LIN pin,
referenced to ground and with a maximum external
termination resistance of 510Ω from LIN bus to battery
supply. The 510Ω corresponds to 1 Master and 16
Slave nodes.
The MCP201 pro vides a +5V 50 mA regulate d power
output. The regulator uses a LDO design, is shortcircuit-protected and will turn the regulator output off if
it falls below 3.5V. The MCP201 also includes thermal
shutdown protec tion. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections,
+40V load dump transients and double-battery jumps
(see Section 1.6 “Internal Voltage Regulator”).
1.1Optional External Protection
1.1.1TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 27V transient suppressor (TVS) diode,
between V
with the battery supply and the V
tect the device from power transients (see Figure 1-2)
and ESD events. While this protection is optional, it
should be considered as good engineering practice.
BAT and ground, with a 50Ω resistor in series
BAT pin, serves to pro-
1.2Internal Protection
1.2.1ESD PROTECTION
For component-level ESD ratings, please refer to the
maximum operation specifications.
1.2.2GROUND LOSS PROTECTION
The LIN bus specification states that the LIN pin must
transition to the recessive state when ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a hi-impedance level.
1.2.3THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down theLIN
transmitter and voltage regulator. Refer to T able 1-1 for
details.
There are three causes for a thermal overload. A
thermal shut down can be triggered by any one, or a
combination of, the following thermal overload
conditions.
• Volt a ge regu lator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
Driving the TXD and checking the RXD pin makes it
possible to determi ne whether there is a bus co ntention
(Rx = low, Tx = high) or a thermal overload condition
(Rx = high, Tx = low).
Note:After recovering from a thermal, bus or
voltage regulator overload condition, the
device will be in the Ready1 mode. In order
to go into Operational mode, the CS/
WAKE pin has to be toggled.
1.1.2REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode can be
used to provide polarity protection (see Figure 1-2).
This protection is opt ional, but shoul d be considered as
good engineering practice.
TABLE 1-1:SOURCES OF THERMAL OVERLOAD
TXDRXDComments
LHLIN transmitter shutdown, receiver and voltage regulator active, thermal overload
condition.
HLRegulator shutdown, rece iv er active, bus contention.
Legend: x = Don’t care, L = Low, H = High
Note 1:LIN transceiver overload current on the LIN pin is 200 mA.
2:Voltage regulator overload current on voltage regulator greater than 50mA.
For an overview of all operational modes, please refer
to Table 1-2.
1.3.1POWER-DOWN MODE
In the Power-down mode, the transmitter and the
voltage regulat or are both off . Only the rec eiver sectio n
and the CS/WAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g., a BREAK character) should
occur during Power-down mode, the device will
immediately enable the voltage regulator. Once the
output has stabilized, the device will enter Ready
mode.
The part will ente r the Operation mod e, if the CS/W AKE
pin should become active-high (‘1’).
1.3.2READY AND READY1 MODES
There are two states for the Ready mode. The only
difference be tween these states is the transitio n d uring
start-up. The state Ready1 mode ensures that the
transition from Read y to Opera tion mode (once a risin g
edge of CS/WAKE) occurs without disrupting bus
traffic.
Immediately upon entering either Ready1 or Ready
mode, the voltage regulator will turn on and provide
power. The transmitter portion of the circuit is off, with
all other circuit s (in cluding the re ceive r) of the MCP20 1
being fully operational. The LIN pin is kept in a
recessive state.
If a microcontroller is being driven by the voltage
regulator output, it will go through a power-on re set and
initialization sequ enc e. All o ther circuits, other than the
transmitter, are fully operational. The LIN pin is held in
the recessive state.
The device will stay in R eady mode unt il the CS/W AKE
pin transitions high (‘1’). After CS/WAKE is active, the
transmitter is enabled and the device enters Operation
mode.
The device may only enter Power-down mode after
going through the Operation mode step.
At power-on of the V
in either Ready or Ready1 mode, waiting for a
CS/WAKE rising edge.
The MCP201 will stay in either mode for 600 µs as the
regulator powers it s i nternal circuitry and wait s u ntil th e
CS/WAKE pin transitions high. During the 600 µs
delay, the MCP201 will not recognize a CS/WAKE
event. The CS/W AKE transition from low to high should
not occur until after this delay.
• The CS input is edge, no t level, sensitive.
• The CS pin is not monitored until approximately
600 µs after V
• The transistion f rom R eady 1 to Rea dy is made on
the falling edge of CS.
• The transition from Ready mode to Operational
mode is on the rising edge of CS.
BAT supply pin, the component is
REG has stabized.
1.3.3OPERATION MODE
In this mode, all internal modules are operational.
The MCP201 will go into Power-down mode on the
falling edge of CS/WAKE.
FIGURE 1-1:OPERATIONAL MODES
STATE DIAGRAMS
CS/WAKE = t rue
Operation
Mode
Note:After power-on, CS will not be sampled
Note:While the MCP201 is in shutdown, TXD
Power-down
Mode
CS/WAKE = false
T
L
F
CS/WAKE = t rue
Ready1
Mode
until V
REG has stabized and an additional
Bus Activity
T
L
F
Ready
Mode
CS/WAKE = false
CS/WAKE = true
CS/WAKE = false
POR
Start
600 µs has elapsed. The microcontroller
should toggle CS approx imately 1mS after
RESET to ensure that CS will be recognized.
should not be actively driven high. If TXD
is driven high actively, it may power
internal logic.
1.3.4DESCRIPTION OF BROWNOUT
CONDITIONS
As VBAT decreases VREG is regulated to 5.0 VDC (see
REG in Section 2.2 “DC Specifications”) while VBAT
V
is greater than 5.5 - 6.0 VDC.
BAT decreases further VREG tracks VBAT (VREG =
As V
BAT - (0.5 to 1.0) VDC.
V
The MCP201 monitors V
not fall below V
ifications”), V
BAT increases VREG will continue to track VBAT
As V
SD (see VSD in Section 2.2 “DC Spec-
REG will remain powered.
until VREG reaches 5.0 VDC.
REG falls below VSD, VREG is turned off and the
If V
MCP201 powers itself down.
The MCP201 will remain powered down until V
increases above VON (see VON in Section 2.2 “DCSpecifications”.
Note 1: The load capacitor, CG, should be a ceramic or t ant alum ra ted for e xtend ed temp erature s and b e in
RXD
I/O
I/O
VSS
the range of 1.0 - 22 µF with an ESR 0.4Ω - 5Ω..
F if the filter capacitor for the external voltage supply.
2: C
3: This diode is only needed if CS/WAKE is connected to 12V supply.
4: Transient suppressor diode. Vclamp L = 40V.
5: These components are for load dump protection.
D1
(3)
CG
+5V
100 kΩ
(1,2)
27V
REG
V
TXD
MCP201
RXD
CS/WAKE
FAULT/SLPS
SS
V
VREG or VSS
+12V
Optional components
Master Node Only
CF
10 uF
VBAT
LIN
1kΩ
(5)
+12V
(4)
D2
24V
Optional components
LIN bus
FIGURE 1-3 :TYPICAL LIN NETWORK C O NF I GUR AT ION
The Receive Data Output pin is a standard CMOS
output and follows the state of the LIN pin.
The LIN receiver monitors the state of the LIN pin and
generates the output signal RXD.
1.5.2CS/WAKE
Chip Select Input pin. This pi n controls whether the part
goes into READY1 or READY mode at power-up. The
internal pull-down resistor will keep the CS/WAKE pin
low. This is done to ensure that no disruptive data will
be present on the bus while the microcontroller is
executing a Power-on Reset and I/O initialization
sequence. The pin must see a low-to-high transition to
activate the transmitter.
After CS/WAKE transitions to ‘1’, the transmitter is
enabled. If CS/WAKE = ‘0’, the device is in Ready1
mode on power-up or in Low-Power mode. In LowPower mode, the voltage regulator is shut down, the
transmitter driver is disabled and the receiver logic is
enabled.
An external switch (see Figure 1-2) can then wake up
both the transceiver and the microcontroller. An
external-blocking di ode and current-limiti ng resistor are
necessary to protect the microcontroller I/O pin.
Note:On POR, the MCP201 enters Ready or
Ready1 mode (see Figure 1-1). In order to
enter Operational mode, the MCP201 has
to see one rising edge on CS/WAKE
600 µs after the voltage regulator reaches
5V.
Function
Normal Operation
(CMOS output)
input)
(TTL)
HV)
Slope Select Input
1.5.3POWER OUTPUT (VREG)
Positive Supply Voltage Regulator Output pin.
1.5.4TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up to
REG. The LIN pi n i s lo w (do m in an t) wh en T XD is l ow,
V
and high (recessive) when TXD is high.
In case the thermal protection detects an over-temperature condition while the signal TXD is low, the
transmitter is shut do wn. The r ecove ry fr om the therma l
shutdown is equal to adequate cooling time.
1.5.5GROUND (VSS)
Ground pin.
1.5.6LIN
The bidirectiona l L IN bus Interface pin is the driver unit
for the LIN pin and is contro lle d by the signal T XD. LIN
has an open collector output with a current limitation.
To reduce EMI, the edges during the signal changes
are slope-controlled.
1.5.7BATTERY (VBAT)
Battery Positive Supply Voltage pin. This pin is also the
input for the internal voltage regulator.
1.5.8FAULT/SLPS
FAULT Detect Output, Slope Select Input.
This pin is usually in Output mode. Its state is defined
as shown in Table 1-5.
The state of this pin is internally sample d during power-
on of V
(approximately 6 VDC) and V
5.25 VDC, the state of this pin selects which slew rate
profile to apply to the LIN output. It is only during this
time that the pin is used as an input (the output driver
is off during this t ime). The sl ope wil l st ay s electe d unti l
the next V
less of any power-down, wake-up or SLEEP events.
Only a V
FAULT
irrespective of the state of any other pin.
The FAULT
V
the slope selection. This large resistance allows the
FAULT indication function to overdrive the resistor in
normal operation mode.
If the FAULT
ing is selected (dv/dt = 2 V/µs). If FAULT
(‘0’) during this time, the alternate slope-shaping is
selected (dv/dt = 4 V/µs). This mode can be used if a
user desires to run at a faster slope. This mode is not
LIN compliant.
BAT. Once VBAT has reached a stable level,
REG is stable at 4.75 to
BAT power-off/power-on sequence, regard-
BAT rising state will cause a sampling of the
/SLPS pin. The Slope selection will be made
/SLPS pin is connected to either VREG or
SS through a resistor (app roximately 100 kΩ) to make
Note:This pin is ‘0’ whenever the internal circuits
have detected a short or thermal excursion
and have disabled the LIN output driver.
Note:Every time TX is togg led , a Fault condition
will occur for the length of time, depending
on the bus load. The Fault time is equal to
the propagation delay.
used for K-line applications.
TABLE 1-5:FAULT
TXD InRXD OutLIN Bus I/O
LHV
/ SLPS TRUTH TABLE
Thermal
Override
BATOFFLBus shorted to battery
/ SLPS OutComments
FAULT
HHVBATOFFHBus recessive
LLGNDOFFHBus dominant
HLGNDOFFLBus shorted to ground
xxV
BATONLThermal excursion
Legend: x = don’t care
1.6Internal Voltage Regulator
6.0V. The device will come up in either READY1 or
READY mode and will have to be transitioned to
The MCP201 has a low drop-out voltage, positive
regulator c apabl e of supp lyin g 5. 00 VDC ±5% at up to
50 mA of load current over the entire operating
temperature range. With a load current of 50 mA, the
minimum input-to-output voltage differential required
for the output to remain in regulation is typically +0.5V
(+1V maximum over the full operating temperature
range). Quiescent current is less than 1.0 mA, with a
full 50 mA load current, when the input-to-output
voltage differential is greater than +2V.
The regulator requires an external output bypass
capacitor for stability. The capacitor should be either a
ceramic or tantalum for stable operation over the
extended temperature range. The compensation
capacitor shou ld ra nge from 1.0 µf – 22 µf and have a
ESR or CSR of 0.4Ω – 5.0Ω. The input capaci tor, C
F, in
Figure 1.4 should be on the order of 8 t o 10 times larger
than the output capacitor, C
G.
Designed for automoti ve applica tions, the reg ulator will
protect itself from rev ers e b atte ry c on nec tio ns, doublebattery jum ps and up to +40V load dump transien ts.
The voltage regulator has both short-circuit and
Operational mode to re-enable data transmission.
In the start phase, V
BAT must be at least 6.0V
(Figure 1-4) to initiate operation during power-up. In
Power-down mode, the VBAT monitor will be turned of f.
The regulator has a thermal shutdown. If the thermal
protection circuit det ects an overtemperature condition
caused by an overcurrent condition (Figure1-6) of the
regulator, it will shut down.
The regulator has an overload current limiting. During
a short-circuit, V
REG is monitored. If VREG is lower than
3.5V , t he regu lator will t urn of f. After a thermal re covery
time, the VREG will be checked again. If there is no
short-circuit (V
REG > 3.5V), the regulator will be
switched back on. The MCP201 will come up in either
READY1 or READY mode and will have to be
transitioned to Operational mode to re-enable data
transmission.
The accuracy of the voltage regulator, when using a
pass transistor, will degrade due to the extra external
components needed. All performance characteristics
should be evaluated on every design.
thermal shutdown protection built-in.
Regarding the correlation between V
BAT, VREG and IDD,
please refer to Figure 1-4 through 1-6. Whe n the input
voltage (V
provide stable regulation, the output V
BAT) drops below the differential neede d to
REG will track the
input down to approxima tely 3.5V, at which po int the
regulator will turn off. This will allow microcontrollers
with internal POR circuits to generate a clean arming of
the Power-on Reset trip poi nt. The MCP201 will then
monitor V
VIN DC Voltage on Logic pins except CS/WAKE.................................................................................-0.3 to VREG+0.3V
IN DC Voltage on CS/WAKE...............................................................................................................-0.3 to VBAT+0.3V
V
BAT Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s)....................................-0.3 to +40V
V
BAT Battery Voltage, transient (Note 1)........................................................................................................-0.3 to +40V
V
BAT Battery Voltage, continuous ..................................................................................................................-0.3 to +30V
V
LBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
V
LBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +40V
V
LBUS Bus Short Circuit Current Limit....................................................................................................................200 mA
I
ESD protection on LIN, V
ESD protection on all other pins (Human Body Model) (Note 2).............................................................................>2 kV
Maximum Junction Temperature.............................................................................................................................150°C
Storage Temperature ..................................................................................................................................-55 to +150°C
BAT (Human Body Model) (Note 2)..................................................................................>4 kV
† NOTICE: Stresse s a bov e th os e l ist ed u nd er “M ax im um R atin gs ” ma y c au se perm an ent dam ag e to the device. This
is a stress rating only and func ti ona l op eration of the device at those or any other conditio ns abo ve those indicated in
the operational li stings of thi s specificati on is not im plied. Expos ure to maximum rat ing cond itions for extend ed periods
may affect device reliability.
Unless otherwise indicated, all limits are specified for:
DC Specifications
Sym.ParameterMin.Typ.Max.UnitsConditions
Power
I
BATQVBAT Quiescent Operating
Current (voltage regulator
without load and transceiver)
IBATVBAT Power-down Current
transceiver only
DDQVREG Quiesce nt Op er at ing
I
Current
VREGVREG maximum output
I
current
Microcontroller Interface
V
IHHigh-level Input Volta ge
(TXD, FAULT
V
ILLow-level Input Voltage
(TXD, FAULT
I
IHTXDHigh-level Output Current
/SLPS)
/SLPS)
(TXD)
ILTXDLow-level Output Current
I
(TXD)
V
IHCS/
WAKE
ILCS/
V
WAKE
IHCS/
I
WAKE
I
ILCS/
WAKE
V
OHRXDHigh-level Output Voltage
High-level Input Voltage
(CS/WAKE)
Low-level Input Voltage
(CS/WAKE)
High-level Input Current
(CS/WAKE)
Low-level Input Current
(CS/WAKE)
(RXD)
OLRXDLow-level Output Voltage
V
(RXD)
Note 1:Internal current limited. 2.0 ms typical recovery time (R
25C. Recovery time highly dependent on ambient temperature, package and thermal resistance).
2:For design guidance only, not tested.
3:This current is at the V
BAT pin.
4:The maximum power dissipation is a function of T
allowable power dissipation at an ambient temperature is P
exceeded, the die temperature will rise above 150°C and the MCP201 will go into thermal shutdown.
VBAT = 6.0V to 18.0V
AMB = -40°C to +125°C
T
LOADREG = 10 µF
C
—0.451.0mAIVREG = 0 mA, LIN bus pin
recessive, (Note 3)
—2350µACS/WAKE = High, voltage
regulator disabled
—500 — µA(Note 2)
—— 50 mA(Note 4)
2.0—V
-0.3—0.15 x V
REG + 0.3V
REGV
-90—+30µAInput voltage = 4V
-150—-10µAInput voltage = 1V (though
> 50 kΩ internal pull-up)
3.0—VBATVThrough an external currentlimiting resistor (10 kΩ)
-0.3—1.0V
-10—+80µAInput voltage = 4V (though
>100 kΩ internal pull-down)
Note 1:Internal current limited. 2.0 ms typical recovery time (R
25C. Recovery time highly dependent on ambient temperature, package and thermal resistance).
2:For design guidance only, not tested.
3:This current is at the V
BAT pin.
4:The maximum power dissipation is a function of T
allowable power dissipation at an ambient temperature is P
exceeded, the die temperature will rise above 150°C and the MCP201 will go into thermal shutdown.
8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
P
N
1
2
3
B
UNCH SINGULATED
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.m icrochip.com/packaging
D
NOTE 1
A
A1
N
1
TOPVIEW
φ
D1
E
E1
EXPOSED
2
A2
A3
b
PAD
2
D2
BOTTOM VIEW
NOTE 2
UnitsMILLIMETERS
Dimension LimitsMINNOMMAX
Number of PinsN8
Pitche1.27 BSC
Overall HeightA–0.851.00
Molded Package ThicknessA2–0.650.80
Standoff A10.000.010.05
Base ThicknessA30.20 REF
Overall LengthD4.92 BSC
Molded Package LengthD14.67 BSC
Exposed Pad LengthD23.854.004. 15
Overall WidthE5.99 BSC
Molded Package WidthE15.74 BSC
Exposed Pad WidthE22.162.312.46
Contact Widthb0.350.400.47
Contact LengthL0.500.600.75
Contact-to-Exposed PadK0.20––
Model Draft Angle Topφ––12°
otes:
. Pin 1 visual index feature may vary, but must be located within the hatched area.
. Package may have one or more exposed tie bars at ends.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
N
1
2
3
4
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
MCP201
E1
12
A
A1
b1
b
Number of PinsN8
Pitche.100 BSC
Top to Seating PlaneA––.210
Molded Package ThicknessA2.115.130.195
Base to Seating PlaneA1.015––
Shoulder to Shoulder WidthE.290.310.325
Molded Package WidthE1.240.250.280
Overall LengthD.348.365.400
Tip to Seating PlaneL.115.130.150
Lead Thicknessc.008.010.015
Upper Lead Widthb1.040.060.070
Lower Lead Widthb.014.018.022
Overall Row Spacing §eB––.430
otes:
. Pin 1 visual index feature may vary, but must be located with the hatched area.
. § Significant Characteristic.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
. Pin 1 visual index feature may vary, but must be located within the hatched area.
. § Significant Characteristic.
. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
. Dimens ioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
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Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445