MICROCHIP MCP201 Technical data

MCP201

LIN Transceiver with Voltage Regulator

Features

• Supports baud rates up to 20 Kbaud

• 40V load dump protected

• Wide supply voltage, 6.0 – 18.0V, continuous

- Maximum input voltage of 30V

• Extended Temperature Range: -40°C to +125°C

• Interfa ce to standard USARTs

• Compati ble with LIN Spec 1.3

• Local Interconnect Network (LIN) Line pin:

- Internal pull-up resistor and diode

- Protected against ground shorts (LIN pin to ground)

- Protected against LIN pin loss of ground

- High current drive, 40 mA ≤ I

• Automatic thermal shutdown

• On-board Voltage Regulator:

- Output voltage of 5V with ±5% tolerances over temperature range

- Maximum output current of 50 mA

- Able to drive an external series-pass transistor for increased current supply capability

- Internal thermal overload protection

- Internal short-circuit current limit

- External components limited to filter capacitor only and load capacitor

OL ≤ 200 mA

Package Types

PDIP, SOIC, DFN

RXD

CS/WAKE

REG

TXD

1 2 3 4

8 7 6

MCP201

FAULT/SLPS VBAT

LIN

Block Diagram

Voltage

Regulator

Ratiometric

VREG

RXD

CS/WAKE

TXD

FAULT/SLPS

Internal Circuits

POR

Slope

Control

Wake-Up

Logic

Thermal

Protection

Reference

approx. 30 kΩ

Vss

BAT

LIN

MCP201

NOTES:

MCP201

1.0 DEVICE OVERVIEW

The MCP201 provides a physical interface between a microcontroller and a LIN half-du plex bus. It is i ntended for automotive and industrial applications with serial bus speeds up to 20 Kbaud.

The MCP201 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN level logic, and vice versa.

The LIN specification 1.3 requires that the transceiver of all nodes in the system be connected via the LIN pin, referenced to ground and with a maximum external termination resistance of 510Ω from LIN bus to battery supply. The 510Ω corresponds to 1 Master and 16 Slave nodes.

The MCP201 pro vides a +5V 50 mA regulate d power output. The regulator uses a LDO design, is shortcircuit-protected and will turn the regulator output off if it falls below 3.5V. The MCP201 also includes thermal shutdown protec tion. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections, +40V load dump transients and double-battery jumps (see Section 1.6 “Internal Voltage Regulator”).

1.1 Optional External Protection

1.1.1 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP)

An external 27V transient suppressor (TVS) diode, between V with the battery supply and the V tect the device from power transients (see Figure 1-2) and ESD events. While this protection is optional, it should be considered as good engineering practice.

BAT and ground, with a 50Ω resistor in series

BAT pin, serves to pro-

1.2 Internal Protection

1.2.1 ESD PROTECTION

For component-level ESD ratings, please refer to the maximum operation specifications.

1.2.2 GROUND LOSS PROTECTION

The LIN bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a hi-impedance level.

1.2.3 THERMAL PROTECTION

The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. Refer to T able 1-1 for details.

There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions.

• Volt a ge regu lator overload

• LIN bus output overload

• Increase in die temperature due to increase in environment temperature

Driving the TXD and checking the RXD pin makes it possible to determi ne whether there is a bus co ntention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low).

Note: After recovering from a thermal, bus or

voltage regulator overload condition, the device will be in the Ready1 mode. In order to go into Operational mode, the CS/ WAKE pin has to be toggled.

1.1.2 REVERSE BATTERY PROTECTION

An external reverse-battery-blocking diode can be used to provide polarity protection (see Figure 1-2). This protection is opt ional, but shoul d be considered as good engineering practice.

TABLE 1-1: SOURCES OF THERMAL OVERLOAD

TXD RXD Comments

L H LIN transmitter shutdown, receiver and voltage regulator active, thermal overload

condition.

H L Regulator shutdown, rece iv er active, bus contention.

Legend: x = Don’t care, L = Low, H = High Note 1: LIN transceiver overload current on the LIN pin is 200 mA.

2: Voltage regulator overload current on voltage regulator greater than 50mA.

(1,2)

MCP201

1.3 Modes of Operation

For an overview of all operational modes, please refer to Table 1-2.

1.3.1 POWER-DOWN MODE

In the Power-down mode, the transmitter and the voltage regulat or are both off . Only the rec eiver sectio n and the CS/WAKE pin wake-up circuits are in operation. This is the lowest power mode.

If any bus activity (e.g., a BREAK character) should occur during Power-down mode, the device will immediately enable the voltage regulator. Once the output has stabilized, the device will enter Ready mode.

The part will ente r the Operation mod e, if the CS/W AKE pin should become active-high (‘1’).

1.3.2 READY AND READY1 MODES

There are two states for the Ready mode. The only difference be tween these states is the transitio n d uring start-up. The state Ready1 mode ensures that the transition from Read y to Opera tion mode (once a risin g edge of CS/WAKE) occurs without disrupting bus traffic.

Immediately upon entering either Ready1 or Ready mode, the voltage regulator will turn on and provide power. The transmitter portion of the circuit is off, with all other circuit s (in cluding the re ceive r) of the MCP20 1 being fully operational. The LIN pin is kept in a recessive state.

If a microcontroller is being driven by the voltage regulator output, it will go through a power-on re set and initialization sequ enc e. All o ther circuits, other than the transmitter, are fully operational. The LIN pin is held in the recessive state.

The device will stay in R eady mode unt il the CS/W AKE pin transitions high (‘1’). After CS/WAKE is active, the transmitter is enabled and the device enters Operation mode.

The device may only enter Power-down mode after going through the Operation mode step.

At power-on of the V in either Ready or Ready1 mode, waiting for a CS/WAKE rising edge.

The MCP201 will stay in either mode for 600 µs as the regulator powers it s i nternal circuitry and wait s u ntil th e CS/WAKE pin transitions high. During the 600 µs delay, the MCP201 will not recognize a CS/WAKE event. The CS/W AKE transition from low to high should not occur until after this delay.

• The CS input is edge, no t level, sensitive.

• The CS pin is not monitored until approximately 600 µs after V

• The transistion f rom R eady 1 to Rea dy is made on the falling edge of CS.

• The transition from Ready mode to Operational mode is on the rising edge of CS.

BAT supply pin, the component is

REG has stabized.

1.3.3 OPERATION MODE

In this mode, all internal modules are operational. The MCP201 will go into Power-down mode on the

falling edge of CS/WAKE.

FIGURE 1-1: OPERATIONAL MODES

STATE DIAGRAMS

CS/WAKE = t rue

Operation

Mode

Note: After power-on, CS will not be sampled

Note: While the MCP201 is in shutdown, TXD

Power-down

Mode

CS/WAKE = false

CS/WAKE = t rue

Ready1

Mode

until V

REG has stabized and an additional

Bus Activity

Ready

Mode

CS/WAKE = false

CS/WAKE = true

CS/WAKE = false

POR

Start

600 µs has elapsed. The microcontroller should toggle CS approx imately 1mS after RESET to ensure that CS will be recognized.

should not be actively driven high. If TXD is driven high actively, it may power internal logic.

1.3.4 DESCRIPTION OF BROWNOUT CONDITIONS

As VBAT decreases VREG is regulated to 5.0 VDC (see

REG in Section 2.2 “DC Specifications”) while VBAT

V is greater than 5.5 - 6.0 VDC.

BAT decreases further VREG tracks VBAT (VREG =

As V

BAT - (0.5 to 1.0) VDC.

V The MCP201 monitors V

not fall below V ifications”), V

BAT increases VREG will continue to track VBAT

As V

SD (see VSD in Section 2.2 “DC Spec-

REG will remain powered.

until VREG reaches 5.0 VDC.

REG falls below VSD, VREG is turned off and the

If V MCP201 powers itself down.

The MCP201 will remain powered down until V increases above VON (see VON in Section 2.2 “DC Specifications”.

REG and as long as V REG does

BAT

TABLE 1-2: OVERVIEW OF OPERATIONAL MODES

State Transmitter Voltage Regulator Operation Comments

POR OFF OFF Read CS/WAKE.

If low, then READY. If high, READY1 mode.

Ready OFF ON If CS/WAKE rising edg e, then

Operation mode.

Ready1 OFF ON If CS/WAKE falling edge,

then READY mode.

Operation ON ON If CS/WAKE falling edge,

then Power down.

Power-down OFF OFF On LIN bus falling, go to

READY mode. On CS/WAKE rising edg e, go to Operational mode

Note: After power-on, CS w ill no t be sa mpled until V

microcontroller should toggle CS approximately 1mS after RESET to ensure that CS will be recognized.

REG has sta bized and an addit ion al 600µs has elap sed . The

Sample FAULT/SLPS and select slope

Bus Off state

Normal Operation mode

Low-Power mode

MCP201

1.4 Typical Applications

FIGURE 1-2: TYPICAL MCP201 APPLICATI ON

+12V

10 kΩ

WAKE-UP

VDD

TXD

PIC MCU

Note 1: The load capacitor, CG, should be a ceramic or t ant alum ra ted for e xtend ed temp erature s and b e in

RXD

I/O I/O

VSS

the range of 1.0 - 22 µF with an ESR 0.4Ω - 5Ω..

F if the filter capacitor for the external voltage supply.

2: C 3: This diode is only needed if CS/WAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 40V. 5: These components are for load dump protection.

(3)

+5V

100 kΩ

(1,2)

27V

REG

V TXD

MCP201

RXD CS/WAKE

FAULT/SLPS

VREG or VSS

+12V

Optional components

Master Node Only

10 uF

VBAT

LIN

1kΩ

(5)

+12V

(4)

D2 24V

Optional components

LIN bus

FIGURE 1-3 : TYPICAL LIN NETWORK C O NF I GUR AT ION

40m

+ Return

LIN bus

BAT

1kΩ

LIN bus

MCP201

Master

µC

LIN bus

MCP201

Slave 1

µC

LIN bus

MCP201

Slave 2

µC

LIN bus

MCP201

Slave n <16

µC

MCP201

1.5 Pin Descriptions

TABLE 1-3: MCP201 PINOUT OVERVIEW

Devices

8-Pin PDIP/

SOIC/DFN

1 RXD Receive Data Output

2 CS/WAKE Chip Select (TTL-HV

3V 4 TXD Transmit Data Input

5V 6 LIN LIN bus (bidirectional-

7V 8FAULT/SLPS Fault Detect Output,

Legend: TTL = TTL input buffer,

Bond Pad

Name

REG Power Output

SS Ground

BAT Battery

HV = High Voltage (VBAT)

1.5.1 RECEIVE DATA OUTP UT (RX D)

The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin.

The LIN receiver monitors the state of the LIN pin and generates the output signal RXD.

1.5.2 CS/WAKE

Chip Select Input pin. This pi n controls whether the part goes into READY1 or READY mode at power-up. The internal pull-down resistor will keep the CS/WAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. The pin must see a low-to-high transition to activate the transmitter.

After CS/WAKE transitions to ‘1’, the transmitter is enabled. If CS/WAKE = ‘0’, the device is in Ready1 mode on power-up or in Low-Power mode. In LowPower mode, the voltage regulator is shut down, the transmitter driver is disabled and the receiver logic is enabled.

An external switch (see Figure 1-2) can then wake up both the transceiver and the microcontroller. An external-blocking di ode and current-limiti ng resistor are necessary to protect the microcontroller I/O pin.

Note: On POR, the MCP201 enters Ready or

Ready1 mode (see Figure 1-1). In order to enter Operational mode, the MCP201 has to see one rising edge on CS/WAKE 600 µs after the voltage regulator reaches 5V.

Function

Normal Operation

(CMOS output)

input)

(TTL)

HV)

Slope Select Input

1.5.3 POWER OUTPUT (VREG)

Positive Supply Voltage Regulator Output pin.

1.5.4 TRANSMIT DATA INPUT (TXD)

The Transmit Data Input pin has an internal pull-up to

REG. The LIN pi n i s lo w (do m in an t) wh en T XD is l ow,

V and high (recessive) when TXD is high.

In case the thermal protection detects an over-temperature condition while the signal TXD is low, the transmitter is shut do wn. The r ecove ry fr om the therma l shutdown is equal to adequate cooling time.

1.5.5 GROUND (VSS)

Ground pin.

1.5.6 LIN

The bidirectiona l L IN bus Interface pin is the driver unit for the LIN pin and is contro lle d by the signal T XD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled.

1.5.7 BATTERY (VBAT)

Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator.

1.5.8 FAULT/SLPS

FAULT Detect Output, Slope Select Input. This pin is usually in Output mode. Its state is defined

as shown in Table 1-5. The state of this pin is internally sample d during power-

on of V (approximately 6 VDC) and V

5.25 VDC, the state of this pin selects which slew rate profile to apply to the LIN output. It is only during this time that the pin is used as an input (the output driver is off during this t ime). The sl ope wil l st ay s electe d unti l the next V less of any power-down, wake-up or SLEEP events. Only a V FAULT irrespective of the state of any other pin.

The FAULT V the slope selection. This large resistance allows the FAULT indication function to overdrive the resistor in normal operation mode.

If the FAULT ing is selected (dv/dt = 2 V/µs). If FAULT (‘0’) during this time, the alternate slope-shaping is selected (dv/dt = 4 V/µs). This mode can be used if a user desires to run at a faster slope. This mode is not LIN compliant.

BAT. Once VBAT has reached a stable level,

REG is stable at 4.75 to

BAT power-off/power-on sequence, regard-

BAT rising state will cause a sampling of the

/SLPS pin. The Slope selection will be made

/SLPS pin is connected to either VREG or

SS through a resistor (app roximately 100 kΩ) to make

/SLPS is high (‘1’), the normal slo pe shap-

/SLPS is low

MCP201

TABLE 1-4: FAULT / SLPS SLOPE

SELECTION DURING POR

/SLPS Slope Shaping

FAULT

HNormal

LAlternate

Note 1: This mode does not conform to LIN bus

specification version 1.3, but might be

(1)

Note: This pin is ‘0’ whenever the internal circuits

have detected a short or thermal excursion and have disabled the LIN output driver.

Note: Every time TX is togg led , a Fault condition

will occur for the length of time, depending on the bus load. The Fault time is equal to the propagation delay.

used for K-line applications.

TABLE 1-5: FAULT

TXD In RXD Out LIN Bus I/O

LHV

/ SLPS TRUTH TABLE

Thermal

Override

BAT OFF L Bus shorted to battery

/ SLPS Out Comments

FAULT

HHVBAT OFF H Bus recessive

L L GND OFF H Bus dominant

H L GND OFF L Bus shorted to ground

xxV

BAT ON L Thermal excursion

Legend: x = don’t care

1.6 Internal Voltage Regulator

6.0V. The device will come up in either READY1 or

READY mode and will have to be transitioned to

The MCP201 has a low drop-out voltage, positive regulator c apabl e of supp lyin g 5. 00 VDC ±5% at up to 50 mA of load current over the entire operating temperature range. With a load current of 50 mA, the minimum input-to-output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 1.0 mA, with a full 50 mA load current, when the input-to-output voltage differential is greater than +2V.

The regulator requires an external output bypass capacitor for stability. The capacitor should be either a ceramic or tantalum for stable operation over the extended temperature range. The compensation capacitor shou ld ra nge from 1.0 µf – 22 µf and have a ESR or CSR of 0.4Ω – 5.0Ω. The input capaci tor, C

F, in

Figure 1.4 should be on the order of 8 t o 10 times larger than the output capacitor, C

Designed for automoti ve applica tions, the reg ulator will protect itself from rev ers e b atte ry c on nec tio ns, doublebattery jum ps and up to +40V load dump transien ts. The voltage regulator has both short-circuit and

Operational mode to re-enable data transmission. In the start phase, V

BAT must be at least 6.0V

(Figure 1-4) to initiate operation during power-up. In Power-down mode, the VBAT monitor will be turned of f.

The regulator has a thermal shutdown. If the thermal protection circuit det ects an overtemperature condition caused by an overcurrent condition (Figure1-6) of the regulator, it will shut down.

The regulator has an overload current limiting. During a short-circuit, V

REG is monitored. If VREG is lower than

3.5V , t he regu lator will t urn of f. After a thermal re covery

time, the VREG will be checked again. If there is no short-circuit (V

REG > 3.5V), the regulator will be

switched back on. The MCP201 will come up in either READY1 or READY mode and will have to be transitioned to Operational mode to re-enable data transmission.

The accuracy of the voltage regulator, when using a pass transistor, will degrade due to the extra external components needed. All performance characteristics should be evaluated on every design.

thermal shutdown protection built-in. Regarding the correlation between V

BAT, VREG and IDD,

please refer to Figure 1-4 through 1-6. Whe n the input voltage (V provide stable regulation, the output V

BAT) drops below the differential neede d to

REG will track the

input down to approxima tely 3.5V, at which po int the regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the Power-on Reset trip poi nt. The MCP201 will then monitor V

BAT and turn on th e regulator when VBAT is

FIGURE 1-4: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET

VBAT

------------- -

8 6 4 2

MCP201

VREG

--------------V

5.5

3.5

(1) (2) (3)

Note 1: Start-up, VBAT < 6.0V, regulator off.

2: VBAT > 6.0V, regulator on. 3: V

BAT ≤ 5.5V, regulator tracks VBAT, regulator will turn

off when V

REG < 3.5V.

MCP201

FIGURE 1-5: VOLTAGE REGULATOR OUTPUT ON POWER DIP

VBAT

------------- -

8 6 4

3.5 2

VREG

---------------

5 4

3.5 3

Note 1: Voltage regulator on.

2: V 3: VREG < 3. 5V, regulator is of f. If th e volt ag e regu lator shoul d shut

4: V

(1) (2) (3)

REG ≤ 5.5V, regulator tracks VBAT until VREG < 3.5V.

off due to V turn V

REG > 4.0V, voltage regulator tracks VDD, when VREG > 4.0V.

REG falling below 3 .5V, the VBAT must rise to 6.0V to

REG back on.

(4)

MCP201

FIGURE 1-6: VOL TAGE REGULATOR OU TP UT O N OV ER CU RR E N T SI TU AT I O N

IREG

------------mA

VRE G

-------------- -

6 5

3.5 3

Note 1: I

REG less than 50 mA, regulator on.

2: After IREG exceeds IREGmax, voltage regulator output will be reduced

until V

(1) (2)

REGoff is reached.

1.7 ICSP™ Considerations

The following should be considered when the MCP201 is connected to pins sup porting in-c ircuit progra mming:

• Power used for programming the microcontroller should be supplied from the progra mmer , not from the MCP201

• The MCP201 should be left unpowered

• The voltage on V maximum output voltage of V

• The TXD pin should not be brought high during programming

REG should not exceed the

REG

MCP201

NOTES:

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