MICROCHIP ENC28J60 Technical data

ENC28J60

Data Sheet

Stand-Alone Ethernet Controller

with SPI™ Interface

 2004 Microchip Technology Inc. Advance Information DS39662A

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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

DS39662A-page ii Advance Information  2004 Microchip Technology Inc.

ENC28J60

Stand-Alone Ethernet Controller with SPI™ Interface

Ethernet Controller Features

• IEEE 802.3 compatible Ethernet controller

• Integrated MAC and 10BASE-T PHY

• Receiver and collision squelch circuit

• Supports one 10BASE-T port with automatic

polarity detection and correction

• Supports Full and Half-Duplex modes

• Programmable automatic retransmit on collision

• Programmable padding and CRC generation

• Programmable automatic rejection of erroneous

packets

• SPI™ Interface with speeds up to 10 Mb/s

Buffer

• 8-Kbyte transmit/receive packet dual port SRAM

• Configurable transmit/receive buffer size

• Hardware-managed circular receive FIFO

• Byte-wide random and sequential access with

auto-increment

• Internal DMA for fast data movement

• Hardware assisted IP checksum calculation

Medium Access Controller (MAC) Features

• Supports Unicast, Multicast and Broadcast

packets

• Programmable receive packet filtering and

wake-up host on logical AND or OR of the following:

- Unicast destination address

- Multicast address

- Broadcast address

- Magic Packet™

- Group destination addresses as defined by 64-bit hash table

- Programmable pattern matching of up to 64 bytes at user-defined offset

• Loopback mode

Physical Layer (PHY) Features

Operational

• Two programmable LED outputs for LINK, TX, RX, collision and full/half-duplex status

• Seven interrupt sources with two interrupt pins

•25MHz clock

• Clock out pin with programmable prescaler

• Operating voltage range of 3.14V to 3.45V

• TTL level inputs

• Temperature range: -40°C to +85°C Industrial, 0°C to +70°C Commercial (SSOP only)

• 28-pin SPDIP, SSOP, SOIC, QFN packages

Package Types

28-Pin SPDIP, SSOP, SOIC

VCAP

CLKOUT

WOL

SCK

RESET

VSSRX

TPIN-

TPIN+

RBIAS

28-pin QFN

WOL

SCK

RESET

VSSRX

VSS

INT

1 2 3 4 5

6 7

1 2 3 4 5 6 7 8 9 10 11 12 13 14

INT

28 27 26 25 2423 22

CLKOUT

VSS

ENC28J60

LEDA

VCAP

VDD

ENC28J60

8910

1112 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

LEDB

LEDA LEDB V

DDOSC

OSC2 OSC1 VSSOSC VSSPLL VDDPLL

DDRX

V VSSTX

TPOUT+ TPOUTVDDTX

21 20 19 18 17 16 15

VDDOSC OSC2

OSC1 VSSOSC VSSPLL VDDPLL VDDRX

• Wave shapi ng out put filter

• Loopback mode

TPIN-

TPIN+

RBIAS

 2004 Microchip Technology Inc. Advance Information DS39662A-page 1

VSSTX

VDDTX

TPOUT-

TPOUT+

ENC28J60

1.0 Overview ......................................................................................................................................................................................3

2.0 External Connections ...................................................................................................................................................................5

3.0 Memory Organization................................................................................................................................................................. 11

4.0 Serial Peripheral Interface (SPI). ................................................................................................................................................25

5.0 Ethernet Overview......................................................... ..................... ..................... ................................................................... 31

6.0 Initialization................................................................................................................................................................................. 33

7.0 Transmitting and Receiving Packets.......................................................................................................................................... 39

8.0 Receive Filters............................................................................................................................................................................ 47

9.0 Duplex Mode Configuration and Negotiation.............................................................................................................................. 53

10.0 Flow Control............................................................................................................................................................................... 55

11.0 Reset.......................................................................................................................................................................................... 59

12.0 Interrupts....................................................................................................................................................................................65

13.0 Direct Memory Access Controller.......................................... ..................... ..................... ...........................................................75

14.0 Power-Down............................................................................................................................................................................... 77

15.0 Built-in Self-Test Controller ........................................................................................................................................................79

16.0 Electrical Characteristics............................................................................................................................................................83

17.0 Packaging Information.......................... ..................... ..................... ............................................................................................ 89

Index .................................................................................................................................................................................................... 95

On-Line Support........................................................................ .. .... .. ......... .... .. .... ......... .. ..................................................................... 97

Systems Information and Upgrade Hot Line........................................................................................................................................ 97

Reader Response................................................................................................................................................................................ 98

Product Identification System............................................................................................................................................................... 99

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Customer Notification System

DS39662A-page 2 Advance Information  2004 Microchip Technology Inc.

ENC28J60

1.0 OVERVIEW

The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI™). It is designed to serv e as an Ethe rnet n etw o rk interface for any controller equipped with SPI.

The ENC28J60 meets all of the IEEE 802.3 specifications. It incorporates a number of packet filtering schemes to limi t in comi ng packe ts. It also provi des an internal DMA mod ule for fast data thr oughput and hardware assisted IP checks um calc ulatio ns. Commu nication with the host controller is implemented via two interrupt pins and the SPI, with data rates of up to 10 Mb/s. Two dedicated pins are used for LED link and network activity indication.

A simple bloc k diagram of the ENC28J60 is shown in Figure 1-1. A typical applicati on circuit using the dev ice is shown in Figure 1-2. With the ENC28J60, two pulse transformers and a few p assive component s are all that is required to connect a microcontroller to a 10 Mbps Ethernet network.

FIGURE 1-1: ENC28J60 BLOCK DIAGRAM

The ENC28J60 consists of seven major functional blocks:

1. An SPI interface that serves as a communica-

tion channel betwee n the host cont roller an d the ENC28J60.

2. Control Registers which are us ed to cont rol an d

monitor the ENC28J60.

3. A dual port RAM buffer for received and

transmitted data packets.

4. An arbiter to control the access to the RAM

buffer when requests are made from DMA, transmit and receive blocks.

5. The bus interface that interprets data and

commands received via the SPI interface.

6. The MAC (Medium Access Contro l) module th at

implements IEEE 802.3 compliant MAC logic.

7. The PHY (Physical Layer) module that encodes

and decodes the analog data that is present on the twisted pair interface.

The device also contains other support blocks, such as the oscillator, on-chip volt age regulator, level translators to provide 5V tolerant I/Os and system control logic.

CLKOUT

INT

WOL

(1)

SCK

8 Kbytes

Dual Port RAM

Control

Registers

Bus Interface

SPI

Buffer

Arbiter

ch0

ch1

System Control

ch0

ch1

RXBM

RXF (Filter)

DMA &

IP Checksum

TXBM

Flow Control

Host Interface

Power-on

Reset

MAC

Voltage

Regulator

RMII

Interface

MIIM

Interface

PHY

25 MHz

Oscillator

LEDA

LEDB

TPOUT+

TPOUT-

TPIN+

TPIN-

RBIAS

OSC1

OSC2

(1)

RESET

Note 1: These pins are 5V tolerant.

 2004 Microchip Technology Inc. Advance Information DS39662A-page 3

VCAP

ENC28J60

FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE

MCU

I/O

SDO

SDI

SCK

INT

SCK

INT

, WOL

TX/RX Buffer

ENC28J60

MAC

PHY

TPIN+/-

TPOUT+/-

TRANSFORMER

LEDA LEDB

RJ45

ETHERNET

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

SPDIP,

SOIC, SSOP

QFN

VCAP 1 25 P — 2.5V output from internal regulator. A 10 µF capacitor to VSSTX must be

VSS 2 26 P — Ground reference. CLKOUT 3 27 O — Programmable clock output pin. INT 4 28 O — INT interrupt output pin. WOL 5 1 O — Wake-up on LAN interrupt out pin. SO 6 2 O — Data out pin for SPI™ interface. SI 7 3 I ST Data in pin for SPI interface. SCK 8 4 I ST Clock in pin for SPI interface.

CS 9 5 I ST Chip select input pin for SPI interface. RESET 10 6 I ST Active-low device Reset input. VSSRX 11 7 P — Ground reference for PHY RX. TPIN- 12 8 I ANA Differential signal input. TPIN+ 13 9 I ANA Differential signal input. RBIAS 14 10 I ANA Bias current pin for PHY . Must be tied to VSSRX through a 2 kΩ, 1% resistor. VDDTX 15 11 P — Positive supply for PHY TX. TPOUT- 16 12 O — Differential signal output. TPOUT+ 17 13 O — Differential signal output. VSSTX 18 14 P — Ground reference for PHY TX. VDDRX 19 15 P — Positive 3.3V supply for PHY RX. VDDPLL 20 16 P — Positive 3.3V supply for PHY PLL. VSSPLL 21 17 P — Ground reference for PHY PLL. VSSOSC 22 18 P — G round reference for oscillator. OSC1 23 19 I DIG Oscillator input. OSC2 24 20 O — Oscillator output. VDDOSC 25 21 P — Positive 3.3V supply for oscillator. LEDB 26 22 O — LEDB driver pin. LEDA 27 23 O — LEDA driver pin. VDD 28 24 P — Positive 3.3V supply.

Legend: I = Input, O = Output, P = Power, DIG = Digital input, ANA = Analog signal input, ST = Schmitt Trigger Note 1: Pins have a maximum current capacity of 8 mA.

2: Pins have a maximum current capacity of 4 mA. 3: Pins are 5V tolerant.

4: Pins have an internal weak pull-up to V 5: Pins have a maximum current capacity of 12 mA.

Type

Buffer

Type

DD.

Description

placed on this pin.

(1)

(2)

(3)

(3,4)

(3, 4)

(5) (5)

DS39662A-page 4 Advance Information  2004 Microchip Technology Inc.

ENC28J60

2.0 EXTERNAL CONNECTIONS

2.1 Oscillator

The ENC28J60 is designed to operate at 25 MHz with a crystal connected to the OSC1 and OSC2 pins. The ENC28J60 design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crysta l m anu fac ture r sp ec ifi cat ions. A typical oscillator circuit is shown in Figure 2-1.

The ENC28J60 may als o be driven by a n external clock source connected to the OSC1 pin as shown in Figure 2-2.

FIGURE 2-1: CRYSTAL OSCILLATOR

OPERATION

ENC28J60

OSC1

XTAL

(1)

OSC2

To Internal Logic

(2)

2.2 Oscillator Start-up Timer

The ENC28J60 contains an Oscillator Start-up Timer (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire until 7500 OSC1 clock cycles (300 µs) pass after Power-on Reset or wake-up from Power-Down mode occurs. During the delay, all Ethernet registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set ECON1.TXRTS), enable reception of packet s (set ECON1.RXEN) or access any MAC, MII or PHY registers during this period.

When the OST expires, the CLKRDY bit in the ESTAT register will be set . The applica tion softwa re should pol l this bit as necessary to determine when normal device operation can begin.

Note: After a Power-on Reset, or the ENC28J60

is removed from Power-Down mode, the CLKRDY bit must be polled before transmitting packets, enabling packet reception or accessing any MAC, MII or PHY registers.

Note 1: A series resistor, RS, may be required for AT

strip cut crystals.

2: The feedback resistor, R

range of 2 to 10 M Ω.

F, is typically in the

FIGURE 2-2 : EXTERNAL C LO C K

SOURCE

3.3V Clock from

External System

(2)

Open

Note 1: Duty cycle restrictions must be observed.

2: A resistor to ground may be used to reduce

system noise. This may increase system current.

(1)

ENC28J60

OSC1

OSC2

 2004 Microchip Technology Inc. Advance Information DS39662A-page 5

ENC28J60

2.3 CLKOUT Pin

The clock out pin is provided to the system designer for use as the host co ntro ller cloc k or as a c lock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register (Register 2-1).

To create a clean clock si gnal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting. When the OST expires , the CL KOUT pin w ill begin o utputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET tion will not be altered (ECOCON will not change

FIGURE 2-3: CLKOUT TRANSITION

ECOCON

Changed

pin, the CLKOUT func-

80 ns to 320 ns Delay

value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low.

The CLKOUT function is designed to ensure that minimum timings are preserved when the CLKOUT pin function is enabled, disabled or the prescaler value is changed. No high or low p ulses will be outputte d whic h exceed the frequency specified by the ECOCON configuration. Howe ve r, when switching frequenc ies , a delay between two and eight OSC1 clock periods will occur where no clock pulses will be produced (see Figure 2-3). During this period, CLKOUT will be held low.

REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — COCON2 COCON1 COCON0

bit 7 bit 0

bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 COCON2:COCON0: Clock Output Configuration bits

111 = Reserved for factory test. Do not use. Glitch p revention not assured. 110 = Reserved for factory test. Do not use. Glitch p revention not assured. 101 = CLKOUT outputs main clock divided by 8 (3.125 MHz) 100 = CLKOUT outputs main clock divided by 4 (6.25 MHz) 011 = CLKOUT outputs main clock divided by 3 (8.333333 MHz) 010 = CLKOUT outputs main clock divided by 2 (12.5 MHz) 001 = CLKOUT outputs main clock divided by 1 (25 MHz) 000 = CLKOUT is disabled. The pin is driven low.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39662A-page 6 Advance Information  2004 Microchip Technology Inc.

ENC28J60

2.4 Magnetics, Termination and Other External Components

To complete the Ethernet interface, the ENC28J60 requires several standard components to be installed externally. These component s s hou ld b e co nn ected as shown in Figure 2-4.

On the differential receive pins (TPIN+/TPIN-), a 1:1 pulse transformer rated for 10BASE-T operation is required. On the differential transmit pins (TPOUT+/TPOUT-), a 1:1 pulse transformer with a center tap is required. The transformers should be rated for isolation of 2 kV or more to protect against static voltages. See Secti on 16.0 “Electri c a l Ch ar ac - teristics” for specific tr ansformer requ irements. Both portions additional ly re qu ire two 50Ω, 1% resist ors an d a 0.01 µF capacitor for proper termination.

The internal analog circuitry in the ENC28J60 requires that an external 2 kΩ, 1% resistor be attached from RBIAS to ground.

FIGURE 2-4: EXTERNAL CONNECTIONS

MCU

I/O SCK SDO SDI

INT0 INT1

5.0V ← 3.3V

Level

Shift

(2)

Logic

CS SCK SI SO

ENC28J60

INT WOL

Some of the digital circuitry in the ENC28J60 operates at a nominal 2.5V to reduce power consumption. A

2.5V regulator is in corporated int ernally to gen erate the necessary voltage. The only external component required is a 10 µF capacitor for stability purposes. This capacitor should be attached from V

CAP to ground. The

internal regulator was not designed to drive external loads.

All power supply pins must be externally connected to the same 3.3V power source. Similarly, all ground references should be e xternally con nected to t he same ground node. Each V

DD and VSS pin pair should ha ve

a 0.1 µF ceramic bypass capacitor placed as close to the pins as possible. Relatively high currents are necessary to operate the twisted p air interfa ce, so all wire s should be kept as short as possible and reasonable wire widths should be used on power wires to reduce resistive loss.

TPOUT

TPOUT-

TPIN+

TPIN-

3.3V

50Ω 1%

Ferrite Bead

0.01 µF

(1)

1:1 CT

1:1

RJ-45

VCAP

LEDA

LEDB

10 µF

Note 1: Ferrite Bead should be rated for at least 100 mA.

2: Required only if the microcontroller is operating at 5V.

 2004 Microchip Technology Inc. Advance Information DS39662A-page 7

RBIAS

2K 1%

.001 µF 2kV

ENC28J60

2.5 I/O Levels

The ENC28J60 is a 3.3V part; however, it was designed to be easily integrated into 5V systems. The

, SCK and SI inputs, as well as the RESET pin,

SPI CS are all 5V tolerant. On the other hand, if the host controller is operated at 5V, it quite likely will not be within specifications when its SPI and interrupt inputs are driven by the 3.3V CMOS outputs on the ENC28J60. A unidirectiona l level translato r would be necessary.

An economical 74H CT08 (q uad A ND ga te), 7 4ACT125 (quad 3-state buffer) or many other 5V CMOS chips with TTL level input b uf fers may b e used t o provi de the necessary level shifting. The use of 3-state buffers permits easy integration into systems which share the SPI bus with other devices. Figure 2-5 and Figure 2-6 show example translation schemes.

FIGURE 2-5: LEVEL SHIFTING USING

AND GATES

MCU

I/O

SCK

OSC1

ENC28J60

CS SCK SI

SO CLKOUT

2.6 LED Configuration

The LEDA and LEDB pins support automatic polarity detection on Reset. The LEDs can be connected such that the pin must source current to turn the LED on, or alternately connected such that the pin must sink current to turn the LED on. Upon system Reset, the ENC28J60 will detect how the LED is connected and begin driving the LED to the de fault st ate conf igured by the PHLCON register. If the LED polarity is changed while the EN C28J60 is oper ating , the n ew polar ity wi ll not be detected until the next system Reset occurs.

LEDB is unique in that the connection of the LED is automatically read on Reset and determi nes how to initialize the PHCON1.PDPXMD bit. If the pin sources current to illuminate the LED, the bit is cleared on Reset and the PHY defau lt s t o h alf -d uplex operation. If the pin sinks curre nt to i llumi nate t he LED, the bit is set on Reset and the PHY defaults to ful l-duplex opera tion. Figure 2-7 shows the two available options. If no LED is attached to the LEDB pin, the PDPXM D bit will res et to an indeterminate value.

FIGURE 2-7: LEDB POLARITY AND

RESET CONFIGURATION OPTIONS

+3.3VFull-Duplex Operation:

PDPXMD = 1

INT0

INT1

INT

WOL

FIGURE 2-6: LEVEL SHIFTING USING

3-STATE BUFFERS

MCU

I/O

SCK

OSC1

INT0

INT1

ENC28J60

CS SCK SI

CLKOUT

INT

WOL

LEDB

Half-Duplex Operation: PDPXMD = 0

LEDB

DS39662A-page 8 Advance Information  2004 Microchip Technology Inc.

ENC28J60

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0

r r r r LACFG3 LACFG2 LACFG1 LACFG0

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-x

LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r

bit 7 bit 0

bit 15-12 Reserved: Write as ‘0’ bit 11-8 LACFG3:LACFG0: LEDA Configuration bits

0000 = Reserved 0001 = Display transmit activity (stretchable) 0010 = Display receive activity (stretchable) 0011 = Display collision activity (stretchable) 0100 = Display link status 0101 = Display duplex status 0110 = Reserved 0111 = Display transmit and receive activity (stretchable) 1000 = On 1001 = Off 1010 = Blink fast 1011 = Blink slow 1100 = Display link status and receive activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 1110 = Display duplex status and collision activity (always stretched) 1111 = Reserved

bit 7-4 LBCFG3:LBCFG0: LEDB Configuration bits

bit 3-2 LFRQ1:LFRQ0: LED Pulse Stretch Time Configuration bits

11 = Reserved 10 = Stretch LED events to approximately 139 ms 01 = Stretch LED events to approximately 73 ms 00 = Stretch LED events to approximately 40 ms

bit 1 STRCH: LED Pulse Stretching Enable bit

1 = Stretchable LED events will cause lengthened LED pulses based on the LFRQ configuration 0 = Stretchable LED events will only be displayed while they are occurring

bit 0 Reserved: Write as ‘0’

Legend:

R = Readable bit W = Writable bit r = Reserved bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Advance Information DS39662A-page 9

ENC28J60

NOTES:

DS39662A-page 10 Advance Information  2004 Microchip Technology Inc.

ENC28J60

3.0 MEMORY ORGANIZATION

The Ethernet buffer contains transmit and receive memory used by the Ethernet controller in a single

All memory in the ENC2 8J60 is im ple mente d as s tatic RAM. There are three types of memory in the ENC28J60:

• Control Registers

• Ethernet Buffer

• PHY Registers The control registers’ memory contains Control

Registers (CRs). These are used for configuration, control and status retrieval of the ENC28J60. The Control Registers are directly read and written to by the SPI interface.

memory space. The sizes of the memory areas are programmable by the host controller using the SPI interface. The Ethernet buffer memory can only be accessed via the read buffer memory and write buffer memory SPI commands (see Section 4.2.2 “Read

Buffer Memory Command” and Section 4.2.4 “Write Buffer Memory Command”).

The PHY registers are used for con figuration, c ontrol and status retriev al of th e PHY mod ule. T he regi ster s are no t directly accessible through the SPI interface; they can only be accessed through the Media Independent Interface (MII) implemented in the MAC.

Figure 3-1 shows the dat a memory org anizatio n for the ENC28J60.

FIGURE 3-1: ENC28J60 MEMORY ORGANIZATION

ECON1<1:0>

= 00

Bank 0

Control Registers

00h

19h

1Ah 1Fh

00h

Common

Registers

Buffer Pointers in Bank 0

Ethernet Buffer

0000h

= 01

= 10

= 11

Note: Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail.

Bank 1

Bank 2

Bank 3

19h

1Ah 1Fh

00h

19h

1Ah 1Fh

00h

19h 1Ah

1Fh

Common

Registers

Common

Registers

Common

Registers

1FFFh

PHY Registers

00h 1Fh

 2004 Microchip Technology Inc. Advance Information DS39662A-page 11

ENC28J60

3.1 Control Registers

Some of the available addresses are unimplemented. Any attempts to write to these locations are ignored

The Control Registers provide the main interface between the ho st controller and the on -chip Ethernet controller logic. Writing to these registers controls the operation of the interface, while reading t he registers allows the host controller to monitor operations.

The Control Register memory is partitioned into four banks, selectable by the bank select bits BSEL1:BSEL0 in the ECON1 register. Each bank is 32 bytes long and add resse d by a 5-bit addres s va lue.

The last five locations (1Bh to 1Fh) of all banks point to a common set of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key register s used in controll ing and monitoring t he operation of the device. Their common

while reads return ‘0’s. The register at address 1Ah in each bank is reserved; read and write operations should not be performed on this register. All other reserved registers ma y be read, but their content s must not be changed. When reading and writing to registers which contain reserved bits, any rules stated in the register definition shou ld be observ ed.

Control registers for the ENC28J60 are generically grouped as ETH, MAC and MII registers. Register names starting with “E” belong to the ETH group. Similarly, registers names starting with “MA” belong to the MAC group and registers prefixed with “MI” belong to the MII group.

mapping allows easy access without switching the bank. The ECON1 and ECON2 registers are discussed later in this section.

TABLE 3-1: ENC28J60 CONTROL REGISTER MAP

Bank 0 Bank 1 Bank 2 Bank 3

Address Name Address Name Address Name Address Name

00h ERDPTL 00h EHT0 00h MACON1 00h MAADR1 01h ERDPTH 01h EHT 1 01h MACON2 01h M AADR0 02h EWRPTL 02h EHT2 02h M ACO N3 02h MAADR3 03h EWRPTH 03h EHT3 03h MACON4 03h MAADR2 04h ETXSTL 04h EHT4 04h MABBIPG 04h MAADR5 05h ETXSTH 05h EHT5 05h 06h ETXNDL 06h EHT6 06h MAIPGL 06h EBSTSD 07h ETXNDH 07h EHT7 07h MAIPGH 07h EBSTCON 08h ERXSTL 08h EPMM0 08h MACLCON1 08h EBSTCSL

09h ERXSTH 09h EPMM1 09h MACLCON2 09h EBSTCSH 0Ah ERXNDL 0Ah EPMM2 0Ah MAMXFLL 0Ah MISTAT 0Bh ERXNDH 0Bh EPMM3 0Bh MAMXFLH 0Bh

0Ch ERXRDPTL 0Ch EPMM4 0Ch Reserved 0Ch 0Dh ERXRDPTH 0Dh EPMM5 0Dh MAPHSUP 0Dh

0Eh ERXW R PTL 0Eh EPMM6 0Eh Reserved 0Eh 0Fh ERXWRPTH 0Fh EPMM7 0Fh

10h EDMASTL 10h EPMCSL 10h Reserved 10h

11h EDMASTH 11h EPMCSH 11h MICON 11h

12h EDMANDL 12h

13h EDMANDH 13h

14h EDMADSTL 14h EPMOL 14h MIREGADR 14h

15h EDMADSTH 15h EPMOH 15h Reserved 15h ECOCON

16h EDMACSL 16h EWOLIE 16h MIWRL 16h Reserved

17h EDMACSH 17h EWOLIR 17h MIWRH 17h EFLOCON

18h

19h 1Ah Reserved 1Ah Rese rved 1Ah Reserved 1Ah Reserved 1Bh EIE 1Bh EIE 1Bh EIE 1Bh EIE

1Ch EIR 1Ch EIR 1Ch EIR 1Ch EIR 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT

1Eh ECON2 1Eh ECON2 1Eh ECON2 1Eh ECON2 1Fh ECON1 1Fh ECON1 1Fh ECON1 1Fh ECON1

— 18h ERXFCON 18h MIRDL 18h EPAUSL — 19h EPKTCNT 19h MIRDH 19h EPAUSH

— 12h MICMD 12h EREVID — 13h — 13h —

— 05h MAADR4

—0Fh—

— — — —

— —

—

DS39662A-page 12 Advance Information  2004 Microchip Technology Inc.

ENC28J60

TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY

EIE INTIE PKTIE DMAIE LINKIE TXIE WOLIE TXERIE RXERIE 0000 0000 67 EIR ESTAT INT r r LATECOL ECON2 AUTOINC PKTDEC PWRSV ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 0000 0000 15 ERDPTL Read Pointer Low Byte ERDPT<7:0>) 1111 1010 17 ERDPTH EWRPTL Write Pointer Low Byte (EWRPT<7:0>) 0000 0000 17 EWRPTH ETXSTL TX Sta rt Low Byte (ETXST<7:0>) 0000 0000 17 ETXSTH ETXNDL TX End Low Byte (ETXND<7:0>) 0000 0000 17 ETXNDH ERXSTL RX Start Low Byte (ERXST<7:0>) 1111 1010 17 ERXSTH ERXNDL RX End Low Byte (ERXND<7:0>) 1111 1111 17 ERXNDH ERXRDPTL RX RD Pointer Low Byte (ERXRDPT<7:0>) 1111 1010 17 ERXRDPTH ERXWRPTL RX WR Pointer Low Byte (ERXWRPT<7:0>) 0000 0000 17 ERXWRPTH EDMASTL DMA Start Low Byte (EDMAST<7:0>) 0000 0000 75 EDMASTH EDMANDL DMA End Low Byte (EDMAND<7:0>) 0000 0000 75 EDMANDH EDMADSTL DMA Destination Low Byte (EDMADST<7:0>) 0000 0000 75 EDMADSTH EDMACSL DMA Checksum Low Byte (EDMACS<7:0>) 0000 0000 76 EDMACSH DMA Checksum High Byte (EDMACS<15:8> ) 0000 0000 76 EHT0 Hash Table Byte 0 (EHT<7:0>) 0000 0000 52 EHT1 Hash Table Byte 1 (EHT<15:8>) 0000 0000 52 EHT2 Hash Table Byte 2 (EHT<23:16>) 0000 0000 52 EHT3 Hash Table Byte 3 (EHT<31:24>) 0000 0000 52 EHT4 Hash Table Byte 4 (EHT<39:32>) 0000 0000 52 EHT5 Hash Table Byte 5 (EHT<47:40>) 0000 0000 52 EHT6 Hash Table Byte 6 (EHT<55:48>) 0000 0000 52 EHT7 Hash Table Byte 7 (EHT<63:56>) 0000 0000 52 EPMM0 Pattern Match Mask Byte 0 (EPMM<7:0>) 0000 0000 51 EPMM1 Pattern Match Mask Byte 1 (EPMM<15:8>) 0000 0000 51 EPMM2 Pattern Match Mask Byte 2 (EPMM<23:16>) 0000 0000 51 EPMM3 Pattern Match Mask Byte 3 (EPMM<31:24>) 0000 0000 51 EPMM4 Pattern Match Mask Byte 4 (EPMM<39:32>) 0000 0000 51 EPMM5 Pattern Match Mask Byte 5 (EPMM<47:40>) 0000 0000 51 EPMM6 Pattern Match Mask Byte 6 (EPMM<55:48>) 0000 0000 51 EPMM7 Pattern Match Mask Byte 7 (EPMM<63:56>) 0000 0000 51 EPMCSL Pattern Match Checksum Low Byte (EPMCS<7:0>) 0000 0000 51 EPMCSH Pattern Match Checksum High Byte (EPMCS<15:0>) 0000 0000 51

Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition, r = reserved, do not modify. Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.

2: EREVID is a read-only register. 3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.

— PKTIF DMAIF LINKIF TXIF WOLIF TXERIF RXERIF -000 0000 68

— RXBUSY TXABRT CLKRDY

—VRPS — — — 100- 0--- 16

— — — Read Pointer High Byt e (ER DPT<12 :8>) ---0 0101 17

— — — Write Pointer High Byte (EWRPT<12:8>) ---0 0000 17

— — — TX Start High Byte (ETXST<12:8>) ---0 0000 17

— — — TX End High Byte (ETXND<12:8>) ---0 0000 17

— — — RX Start High Byte (ERXST<12:8>) ---0 0101 17

— — — RX End High Byte (ERXND<12:8>) ---1 1111 17

— — — RX RD Pointer High Byte (ERXRDPT<12:8>) ---0 0101 17

— — — RX WR Pointer High Byte (ERXWRPT<12:8>) ---0 0000 17

— — — DMA Start High Byte (EDMAST<12:8>) ---0 0000 75

— — — DMA End High Byte (EDMAND<12:8>) ---0 0000 75

— — — DMA Destination High Byte (EDMADST<12:8>) ---0 0000 75

Value Reset

(1)

0000 -000 66

Details

Page

 2004 Microchip Technology Inc. Advance Information DS39662A-page 13

ENC28J60

TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED)

EPMOL Pattern Match Offset Low Byte (EPMO<7:0>) 0000 0000 51 EPMOH EWOLIE UCWOLIE AWOLIE EWOLIR UCWOLIF AWOLIF ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 48 EPKTCNT Ethernet Packet Count 0000 0000 43 MACON1 MACON2 MARST RNDRST MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDRLEN HFRMEN FRMLNEN FULDPX 0000 0000 35 MACON4 MABBIPG MAIPGL MAIPGH MACLCON1 MACLCON2 MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>) 0000 0000 34 MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>) 0000 0110 34 MAPHSUP RSTINTFC MICON RSTMII MICMD MIREGADR MIWRL MII Write Data Low Byte (MIWR<7:0>) 0000 0000 19 MIWRH MII Write Data High Byte (MIWR<15:8>) 0000 0000 19 MIRDL MII Read Data Low Byte (MIRD<7:0>) 0000 0000 19 MIRDH MII Read Data High Byte(MIRD<15:8>) 0000 0000 19 MAADR1 MAC Address Byte 1 (MAADR<15:8>) 0000 0000 34 MAADR0 MAC Address Byte 0 (MAADR<7:0>) 0000 0000 34 MAADR3 MAC Address Byte 3 (MAADR<31:24>) 0000 0000 34 MAADR2 MAC Address Byte 2(MAADR<23:16>) 0000 0000 34 MAADR5 MAC Address Byte 5 (MAADR<48:41>) 0000 0000 34 MAADR4 MAC Address Byte 4 (MAADR<40:32>) 0000 0000 34 EBSTSD Built-in Self-Test Fill Seed (EBSTSD<7:0>) 0000 0000 80 EBSTCON PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST 0000 0000 79 EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) 0000 0000 80 EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) 0000 0000 80 MISTAT

(2)

EREVID ECOCON EFLOCON EPAUSL Pause Timer Value Low Byte (EPAUS<7:0>) 0000 0000 57 EPAUSH Pause Timer Value High Byte (EPAUS<15:8>) 0001 0000 57

(3)

2: EREVID is a read-only register. 3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.

— — — Pattern Match Offset High Byte (EPMO<12:8>) ---0 0000 51

— PMWOLIE MPWOLIE HTWOLIE MCWOLIE BCWOLIE 00-0 0000 72 — PMWOLIF MPWOLIF HTWOLIF MCWOLIF BCWOLIF 00-0 0000 73

— — — LOOPBK TXPAUS RXPAUS PASSALL MARXEN ---0 0000 34

— — MARXRST RFUNRST MATXRST TFUNRST 10-- 0000 61

— DEFER BPEN NOBKOFF — — LONGPRE PUREPRE -000 --00 36 — Back-to-Back Inter-Packet Gap (BBIPG<6:0>) -000 0000 37 — Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) -000 0000 34 — Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) -000 0000 34 — — — — Retransmission Maximum (RETMAX<3:0>) ---- 1111 34 — — Collision Window (COLWIN<5:0>) --11 0111 34

— —rRSTRMII— —r0--1 0--0 62

— — — — — — — 0--- ---- 21 — — — — — — MIISCAN MIIRD ---- --00 21 — — — MII Register Address (MI REG AD R<4:0 > ) ---0 0000 19

— — — — r NVALID SCAN BUSY ---- 0000 22 — — — Ethernet Revision ID (EREVID<4:0>) ---q qqqq 22 — — — — — COCON2 COCON1 COCON0 ---- -100 6 — — — — — FULDPXS FCEN1 FCEN0 ---- -000 56

Value Reset

Details

Page

DS39662A-page 14 Advance Information  2004 Microchip Technology Inc.

3.1.1 ECON1 REGISTER

The ECON1 register, shown in Register 3-1, is used to control the main functions of the ENC28J60. Receive enable, transmit request, DMA control and bank select bits can all be found in ECON1.

REGISTER 3-1: ECON1: ETHERNET CONTROL REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0

bit 7 bit 0

bit 7 TXRST: Transmit Logic Reset bit

1 = Transmit logic is held in Reset 0 = Normal operation

bit 6 RXRST: Receive Logic Reset bit

1 = Receive logic is held in Reset 0 = Normal operation

bit 5 DMAST: DMA Start and Busy Status bit

1 = DMA copy or checksum operation is in progress 0 = DMA hardware is Idle

bit 4 CSUMEN: DMA Checksum Enable bit

1 = DMA hardware calculates checksums 0 = DMA hardware copies buffer memory

bit 3 TXRTS: Transmit Request To Send bit

1 = The transmit logic is attempting to transmit a packet 0 = The transmit logic is Idle

bit 2 RXEN: Receive Enable bit

1 = Packets which pass the current filter configuration will be written into the receive buffer 0 = All packets received will be ignored

bit 1-0 BSEL1:BSEL0: Bank Select bit s

11 = SPI accesses registers in Bank 3 10 = SPI accesses registers in Bank 2 01 = SPI accesses registers in Bank 1 00 = SPI accesses registers in Bank 0

ENC28J60

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Advance Information DS39662A-page 15

ENC28J60

3.1.2 ECON2 REGISTER

The ECON2 register, shown in Register 3-2, is used to control other main functions of the ENC28J60.

REGISTER 3-2: ECON2: ETHERNET CONTROL REGISTER 2

R/W-1 W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 AUTOINC PKTDEC PWRSV bit 7 bit 0

bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit

1 = Automatically increment ERDP T and EW RP T when th e SPI RBM/W BM c ommand i s used 0 = Do not automatically change ERDPT and EWRPT after the buffer is accessed

bit 6 PKTDEC: Packet Decrement bit

1 = Decrement the EPKTCNT register by one 0 = Leave EPKTCNT unchanged

bit 5 PWRSV: Power Save Enable bit

1 = MAC, PHY and control logic are in Low-Power Sleep mode 0 = Normal operation

bit 4 Unimplemented: Read as ‘0’ bit 3 VRPS: Voltage Regulator Power Save Enable bit

When PWRSV =

1 = Internal voltage regulator is in Low-Current mode 0 = Internal voltage regulator is in Normal Current mode

When PWRSV = 0: The bit is ignored; the regulator always outputs as much current as the device requires.

bit 2-0 Unimplemented: Read as ‘0’

—VRPS— — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39662A-page 16 Advance Information  2004 Microchip Technology Inc.

ENC28J60

3.2 Ethernet Buffer

The Ethernet buffer contains transmit and receive memory used by the Ethernet controller. The entire buffer is 8 Kbytes, divided into separate receive and transmit buffer spaces. The sizes and locations of transmit and receive memory are fully programmable by the host controller using the SPI interface.

The relationship of the buffer spaces is shown in Figure 3-2.

3.2.1 RECEIVE BUFFER

The receive buffer constitutes a circular FIFO buffer managed by hardware. The register pairs ERXSTH:ERXSTL and ERXNDH:ERXNDL serve as pointers to define the buffer’s size and location within the memory. The byte pointed to by ERXST and the byte pointed to by ERXND are both included in the FIFO buffer.

As bytes of data are received from the Ethernet interface, they are written into the receive buffer sequentially. However, after the memory pointed to by ERXND is written to, the hardware will automatically write the next byte of received data to the memory pointed to by ERXST. As a re sult, the r eceive hardwa re will never write outside the boundaries of the FIFO.

The host controller may program the ERXST and ERXND pointers when the rec eive logic is no t enable d. The pointer s must not be modified w hile the receive logic is enabled (ECON1.RXEN is set). If desired, the pointers may span the 1FFFh to 0000h memory boundary; the hardware will still operate as a FIFO.

The ERXWRPTH:ERXWRPTL registers define a location within the FIFO where the hardware will write bytes that it receives. The pointer is read-only and is automatically updated by the hardware whenever a new packet is successfully received. The pointer is useful for determining how much free space is available within the FIFO.

The ERXRDPT registers define a location within the FIFO where the receive hardware is forbidden to write to. In normal operation, the receive hardware will write data up to, but not inc lu din g, the me mory pointed to by ERXRDPT. If the FIFO fills up with data and new data continues to arrive, the hardware will not overwrite the previously received data. Instead, the new data will be thrown away and the old data will be preserved. In order to continuously receive new data, the host controller must periodicall y adv an ce this poin ter w hen ev er it finishes processing some, or all, of the old received data.

3.2.2 TRANSMIT BU FFER

Any space within the 8-Kbyte memory, which is not programmed as part of the receive FIFO buffer, is considered to be the transmit buffer. The responsibility of managing where packets are located in the transmit buffer belongs to the host contro ller . Whenever the hos t controller decides to t rans mit a p ack et, the ETXST an d ETXND pointers are programmed with addresses specifying where, within the transmit buffer, the particular packet to transmit is located. The hardware does not check that the start and end addresses do not overlap with the receive buffer. To prevent buffer corruption, the host contr oller must make sure to not transmit a packet while the ETXST and ETXND pointers are overlappin g the recei ve buf fer , or w hile the ETXND pointer is too close to the receive buffer. See Section 7.1 “Transmitting Packets” for more information.

3.2.3 READING AND WRITING TO THE BUFFER

The Ethernet buffer contents are accessed from the host controller though separate read and write pointers (ERDPT and EWRPT) combined with the read buffer memory and write buffer memory SPI commands. While sequentially reading from the receive buffer, a wrapping condition will occur at the end of the receive buffer. While sequentially wri ting to the bu ff er, no wrapping conditions will occur. See Section 4.2.2 “Read

Buffer Memory Command” and Section 4.2.4 “Write Buffer Memory Command” for more information.

3.2.4 DMA ACCESS TO THE BUFFER

The integrated DMA controller must read from the buffer when calculating a checksum and it must read and write to the buffer when copying memory. The DMA follows the same wrapping rules that SPI accesses do. While it sequentially reads, it will be subject to a w rapping condition at the end of the receive buffer . All w rites it does w ill not be subject to any wrapping conditions. See Section 13.0 “Direct Memory Access Controller” for more information.

 2004 Microchip Technology Inc. Advance Information DS39662A-page 17

ENC28J60

FIGURE 3-2: ETHERNET BUFFER ORGANIZATION

Transmit Buffer Start (ETXSTH:ETXSTL)

Buffer Write Pointer (EWRPTH:EWRPTL)

Transmit Buffer End (ETXNDH:ETXNDL)

Receive Buffer Start (ERXSTH:ERXSTL)

Buffer Read Pointer (ERDPTH:ERDPTL)

AAh

Transmit

Buffer

Receive

Buffer

(Circular FIFO)

55h

0000h

Transmit Buffer Data (WBM AAh)

Receive Buffer Data (RBM 55h)

Receive Buffer End (ERXNDH:ERXNDL)

DS39662A-page 18 Advance Information  2004 Microchip Technology Inc.

1FFFh

ENC28J60

3.3 PHY Registers

The PHY registers provide con fig uration and control of the PHY module, as well as stat us inform ation ab out it s operation. All PHY registers are 16 bits in width. There are a total of 32 PHY addres se s; ho wev er, only 9 locations are implemented. Writes to unimplemented locations are ignored and any attempts to read the se locations will return ‘0’. All reserved locations shoul d be written as ‘0’; their contents should be ignored when read.

Unlike the ETH, MAC and MII control registers, or the buffer memory, the PHY registers are not directly accessible through the SPI control interface. Instead, access is accomplished through a special set of MAC control registers that implement a Media Independent Interface for Management (MIIM). These control registers are referred to as the MII registers. The registers that control access to the PHY registers are shown in Register 3-3 and Register 3-4.

3.3.1 READING PHY REGISTERS

When a PHY register is read, the entire 16 bits are obtained.

To read from a PHY register:

1. Write the address of the PHY register to read from into the MIREGADR register.

2. Set the MICMD.MIIRD bit. The read operation begins and the MISTAT.BUSY bit is set.

3. Wait 10.24 µs. Poll the MISTAT.BUSY bit to be certain that the operation is complete. While busy, the host controller should not start any MIISCAN operations or write to the MIWRH register. When the MAC has obtained the register contents, the BUSY bit will clear itself.

4. Clear the MICMD.MIIRD bit.

5. Read the desired data from the MIRDL and MIRDH registers. The order that these bytes are accessed is unimportant.

3.3.2 WRITING PHY REGISTERS

When a PHY regi ster is w ritte n to, the en tire 16 bits is written at once; selective bit writes are not implemented. If it is necessary to reprogram only select bits in the register, the controller must first read the PHY register, modify the resulting data and then write the data back to the PHY register.

To write to a PHY register:

1. Write the address of the PHY register to write to into the MIREGADR register.

2. Write the lower 8 bits of data to write into the MIWRL register.

3. Write the upper 8 bits of data to write into the MIWRH register. Writing to this register automatically begins the MII transaction, so it must be written to after MIWRL. The MISTAT.BUSY bit becomes set.

The PHY register will be written after the MII operation completes, which takes 10.24 µs. When the write operation has completed, the BUSY bit will clear itself. The host controller should not start any MIISCAN or MIIRD operations while busy.

3.3.3 SCANNING A PHY REGISTER

The MAC can be configured to perform automatic back-to-back read operations on a PHY register. This can significantly reduce the host controller complexity when periodic status information updates are desired. To perform the scan operation:

1. Write the address of the PHY register to read from into the MIREGADR register.

2. Set the MICMD.MIISCAN bit. The scan operation begins and the MISTA T.BUSY bit is set . The first read operation will complete after 10.24 µs. Subsequent reads will be done at the same interval until the operation is cancelled. The MISTAT.NVALID bit may be polled to determine when the first read operation is complete.

After setting the MIISCAN bit, the MIRDL and MIRDH registers will automatically be updated every 10.24 µs. There is no status information which can be used to determine when the MIR D registers are updated. Since the host controller can only read one MII register at a time through the SPI, it must not be assumed that the values of MIRDL and MIRDH were read from the PHY at exactly the same time.

When the MIISCAN operation is in progress, the host controller must not attempt to write to MIWRH or start an MIIRD operation. The MIISCAN operation can be cancelled by clearing the MICMD.MIISCAN bit and then polling the MISTAT.BUSY bit. New operations may be started after the BUSY bit is cleared.

 2004 Microchip Technology Inc. Advance Information DS39662A-page 19

ENC28J60

r — — — — — — — 00-- 10-q 0--- ----

(1)

— —PPWRSV r —PDPXMD

— — — PFDPX PHDPX — — — — — — — — LLSTAT JBSTAT — ---1 1--- ---- -00-

— FRCLNK TXDIS r r JABBER r HDLDIS r r r r r r r r -000 0000 0000 0000

— — — —PLRITY— — — — --00 00q- ---0 ----

(1)

— — TXSTAT RXSTAT COLSTAT LSTAT DPXSTAT

Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values

00h PHCON1 PRST PLOOPBK

01h PHSTAT1

02h PHID1 PHY Identifier (PID18:PID3) = 0083h 0000 0000 1000 0011

03h PHID2 PHY Identifier (PID24:PID19) = 000101 PHY P/N (PPN5:PPN0) = 00h PHY Revision (PREV3:PREV0 ) = 0 0h 0001 0100 0000 0000

10h PHCON2

12h PHIE r r r r r r r r r r r PLNKIE r r PGEIE r 0000 0000 0000 0000

13h PHIR r r r r r r r r r r r PLNKIF r PGIF r r xxxx xxxx xx00 00x0

14h PHLCON r r r r LACFG3:LACFG0 LBCFG3:LBCFG0 LFRQ1:LFRQ0 STRCH r 0011 0100 0010 001x

TABLE 3-3: ENC28J60 PHY REGISTER SUMMARY

11h PHSTAT2

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition, r = reserved, do not modify.

Note 1: Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see Section 2.6 “LED Configuration” for additional details).

DS39662A-page 20 Advance Information  2004 Microchip Technology Inc.

REGISTER 3-3: MICON: MII CONTROL REGISTER

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

RSTMII — — — — — — —

bit 7 bit 0

bit 7 RSTMII: MII Management Module Reset bit

1 = MII management module held in Reset 0 = Normal operation

bit 6-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 3-4: MICMD: MII COMMAND REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — MIISCAN MIIRD

bit 7 bit 0

ENC28J60

bit 7-2 Unimplemented: Read as ‘0’ bit 1 MIISCAN: MII Scan Enable bit

1 = PHY register at MIREGADR is continously read and the data is placed in MIRD 0 = No MII management scan operation is in progress

bit 0 MIIRD: MII Read Enable bit

1 = PHY register at MIREGADR is read once and the data is placed in MIRD 0 = No MII management read operation is in progress

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Advance Information DS39662A-page 21

ENC28J60

REGISTER 3-5: MISTAT: MII STATUS REGISTER

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — r NVALID SCAN BUSY

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’ bit 3 Reserved: Maintain ‘0’ bit 1 NVALID: MII Management Read Data Not Valid bit

1 = The contents of MIRD are not valid yet 0 = The MII management read cycle has completed and MIRD has been updated

bit 1 SCAN: MII Management Scan Operation bit

1 = MII management scan operation is in progress 0 = No MII management scan operation is in progress

bit 0 BUSY: MII Management Busy bit

1 = A PHY register is currently being read or written to 0 = The MII management interface is Idle

Legend:

R = Readable bit r = reserved, maintain as ‘0’ U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

3.3.4 PHSTAT REGISTERS

The PHSTAT1 and PHSTAT2 registers contain readonly bits that show the current status of the PHY module’s operations, particularly the conditions of the communications link to the rest of the network.

The PHSTAT1 register (Register 3-6) contains the LLSTAT bit; it clears and latches low if the physical layer link has gone down since the last read of the register. Periodic polling by the host controller can be used to determine exactly when the link fails. It may be particularly useful if the link change interrupt is not used.

The PHST AT1 register also contai ns a jabbe r status bit. An Ethernet controller is sa id to be “j abb erin g” if it continuously transmits data without stopping and allowing other nodes to share the medium. G enerally, the jabber condition indicates that the local controller may be grossly violating the maximum packet size defined by the IEEE specification. This bit latches high to indicate that a jabber con dition has occurr ed sin ce th e las t read of the register.

The PHSTAT2 register (Register 3-7) contains status bits which report if the PHY module is linked to the network and whether or not it is transmitting or receiving.

3.3.5 PHID1 AND PHID2 REGISTERS

The PHID1 and PHID2 registers are read-only registers. They hold cons tan t dat a th at help iden tify th e Ethernet controller and may be useful for debugging purposes. This includes:

• The part number of the PHY module (PPN5:PPN0)

• The revision level of the PHY module (PREV3:PREV0); and

• The PHY Identifier, as part of Microchip’s corporate Organizati onally Uni que Identi fier (OUI) (PID24:PID3)

The PHY part number and revision are part of PHID2. The upper two bytes of the PHY id entifier are loca ted in PHID1, with the remainder in PHID2. The exact locations within registers are shown in Table 3-3.

Revision inform ation is also st ored in EREVID. Th is is a read-only control register which contains a 5-bit identifier for the specific silicon revision level of the device. Details of this register are shown in Table3-2.

DS39662A-page 22 Advance Information  2004 Microchip Technology Inc.

ENC28J60

U-0 U-0 U-0 R-1 R-1 U-0 U-0 U-0

— — — PFDPX PHDPX — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/LL-0 R/LH-0 U-0

— — — — — LLSTAT JBRSTAT —

bit 7 bit 0

bit 15-13 Unimplemented: Read as ‘0’ bit 12 PFDPX: PHY Full-Duplex Capable bit

1 = PHY is capable of operating at 10 Mbps in Full-Duplex mode (this bit is always set)

bit 11 PHDPX: PHY Half-Duplex Capable bit

1 = PHY is capable of operating at 10 Mbps in Half-Duplex mode (this bit is always set) bit 10-3 Unimplemented: Read as ‘0’ bit 2 LLSTAT: PHY Latching Link Status bit

1 = Link is up and has been up continously since PHSTAT1 was last read

0 = Link is down or was down for a period since PHSTAT1 was last read

bit 1 JBRSTAT: PHY Latching Jabber Status bit

1 = PHY has detected a transmission meeting the jabber criteria since PHYSTAT1 was last read

0 = PHY has not detected any jabbering transmissions since PHYSTAT1 was last read

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Read-only bit R/L = Read-only latch bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set on POR ‘0’ = Bit is cleared on POR L L = Bit latches low LH = Bit latches high

 2004 Microchip Technology Inc. Advance Information DS39662A-page 23

ENC28J60

U-0 U-0 R-0 R-0 R-0 R-0 R-x U-0

— — TXSTAT RXSTAT COLSTAT LSTAT DPXSTAT

bit 15 bit 8

U-0 U-0 U-0 R-0 U-0 U-0 U-0 U-0

— — —PLRITY— — — —

bit 7 bit 0

bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXSTAT: PHY Transmit Status bit

1 = PHY is transmitting data 0 = PHY is not transmitting data

bit 12 RXSTAT: PHY Receive Status bit

1 = PHY is receiving data 0 = PHY is not receiving data

bit 11 COLSTAT: PHY Collision Status bit

1 = A collision is occuring 0 = A collision is not occuring

bit 10 LSTAT: PHY Link Status bit (non-latching)

1 =Link is up 0 =Link is down

bit 9 DPXSTAT: PHY Duplex Status bit

1 = PHY is configured for full-duplex operation (PHCON1.PDPXMD is set) 0 = PHY is configured for half-duplex operation (PHCON1.PDPXMD is clear)

Note 1: Reset values o f t he D upl ex m ode /s t atus bits depend on the co nne ct ion of the LED to the LEDB

pin (see Section 2.6 “LED Configuration” for additional details). bit 8-5 Unimplemented: Read as ‘0’ bit 4 PLRITY: Polarity Status bit

1 = The polarity of the signal on TPIN+/TPIN- is reversed 0 = The polarity of the signal on TPIN+/TPIN- is correct

bit 3-0 Unimplemented: Read as ‘0’

(1)

—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS39662A-page 24 Advance Information  2004 Microchip Technology Inc.

ENC28J60

4.0 SERIAL PERIPHERAL INTERFACE (SPI)

4.1 Overview

The ENC28J60 is des igned to interface d irectly with the Serial Peripheral Interface (SPI) po rt available on many microcontrollers. The implementation used on this device support s SPI mode 0 ,0 only. In addition, the SPI port requires that SCK be at Idle in a low state; selectable clock polarity is not supported.

FIGURE 4-1: SPI™ INPUT TIMING

SCK

MSB In

High-Impedance State

Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the ENC28J60 on the SO line, on the falling edge of SCK. The CS held low while an y operatio n is perform ed and ret urned high when finished.

LSB In

pin must be

FIGURE 4-2: SPI™ OUTPUT TIMING

SCK

MSB Out

LSB Out

Don’t Care

 2004 Microchip Technology Inc. Advance Information DS39662A-page 25

ENC28J60

4.2 SPI Instruction Set

The operation of the ENC28J60 depends entirely on commands given b y an external host controller over th e SPI interface. These commands take the form of instructions, of one or more bytes, which are used to access the control mem ory and Ethernet buf fer spaces. At the least, instructions consist of a 3-bit opcode,

followed by a 5-bit argument that specifies either a register address or a data constant. Write and bit field instructions are also followed by one or more bytes of data.

A total of seven instructions are implemented on the ENC28J60. Table 4-1 shows the command codes for all operations.

TABLE 4-1: SPI™ INSTRUCTION SET FOR THE ENC28J60

Instruction

Name and Mnemonic

Read Control Register (RCR)

Read Buffer Memory (RBM)

Write Control Register (WCR)

Write Buffer Memory (WBM)

Bit Field Set (BFS)

Bit Field Clear (BFC)

System Command (Soft Reset) (SC)

Legend: a = control register address, d = data payload.

Opcode Argument Data

000aaaaa N/A

00111010 N/A

010aaaaad d d d d d d d

01111010d d d d d d d d

100aaaaad d d d d d d d

101aaaaad d d d d d d d

11111111 N/A

Byte 0 Byte 1 and Following

DS39662A-page 26 Advance Information  2004 Microchip Technology Inc.

ENC28J60

4.2.1 READ CONTROL REGISTER

COMMAND

The Read Control Register (RCR) command allows the host controller to read any of the ETH, MAC and MII registers in any order. The contents of the PHY registers are read via a special MII register interface (see Section 3.3.1 “Reading PHY Registers” for more information).

The RCR command is st arted by pulling the CS The RCR opcode is then sent to the ENC28J60, followed by a 5-bit register address (A4 through A0).

pin low.

registers in the current bank. If the 5-bit address is an ETH register, then data in the selected register will immediately start shifting out MSb first on the SO pin. Figure 4-3 shows the read sequence for these registers.

If the address specifi es one of the MAC or M II registers, a dummy byte will first be shifted out the SO pin. After the dummy byte, the data will be shifted out MSb first on the SO pin. The RCR operation is terminated by raising the CS

pin. Figure 4-4 shows the read

sequence for MAC and MII registers.

The 5-bit address identifies any of the 32 control

FIGURE 4-3: READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)

0 234567891011121314151

SCK

Opcode Address

High-Impedance State

2034000 1

Data Out

76543210

FIGURE 4-4: READ CONTROL REGISTER COMMAND SEQUENCE

(MAC AND MII REGISTERS)

0 23456789101112131415161718192021221

SCK

Opcode

High-Impedance State

Address

2034000 1

Dummy Byte

76543210

Data Byte Out

76543210

 2004 Microchip Technology Inc. Advance Information DS39662A-page 27

ENC28J60

4.2.2 READ BUFFER MEMORY COMMAND

The Read Buffer Memory (RBM) command allows the host controller to read bytes from the integrated 8-Kbyte transmit and receive buffer memory.

If the AUTOINC bit in the ECON2 register is set, the ERDPT pointer will automatically increment to point to the next address after the last bit of each byte is read. The next address will normally be the current address incremented by one. However, if the last byte in the receive buffer is read (ERDPT = ERXND), the ERDPT pointer will change to the beginning of the receive buffer (ERXST). This allows the host controller to read packets from the receive buffer in a continuous stream without keeping trac k of when a wra paround is needed. If AUTOINC is set when address 1FFFh is read and ERXND does not point to thi s address, the read poin ter will increment and wrap around to 0000h.

The RBM command is started by pulling the CS The RBM opcode is then sent to the ENC28J60, followed by the 5-bit c onst ant 1Ah . After the R BM co mmand and constant are sent, the data stored in the memory pointed to by ERDPT will be shifted out MSb first on the SO pin. If the host controller continues to provide clocks on the SCK pin, without raising CS byte pointed to by ERDP T will agai n be shifted o ut MSb first on the SO pin. In this manner, with AUTOINC enabled, it is possible to continuously read sequential bytes from the buffer memory without any extra SPI command overhead . The RBM c ommand is terminate d by raising the CS

pin.

pin low.

, the

4.2.3 WRITE CONTROL REGISTER COMMAND

The Write Control Register (WCR) command allows the host controller to write to any of the ETH, MA C and MII Control registers in any order. The PHY registers are written to via a special MII register interface (see Section 3.3.2 “Writing PHY Registers” for more information).

The WCR command is started by pulling the CS low. The WCR opcode is then sent to the ENC28J60, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the 32 control registers in the current bank. After the WCR command and address are sent, actual data that is to be written is sent, MSb first. The data will be written to the addressed register on the rising edge of the SCK line.

The WCR operation i s terminated by rais ing the CS If the CS loaded, the write will be aborted for that data byte. Refer to the timing diagram in Figure 4-5 for a more detailed illustration of the byte write sequence.

line is allowed to g o hi gh befo r e e igh t bi t s a re

pin.

FIGURE 4-5: WRITE CONTROL REGISTER COMMAND SEQUENCE

0 234567891011121314151

SCK

Opcode

Address

203A4010 1

Data Byte

D7 6 5 4

High-Impedance State

1D032

DS39662A-page 28 Advance Information  2004 Microchip Technology Inc.

+ 72 hidden pages

MICROCHIP ENC28J60 Technical data

Ethernet Controller Features

Buffer

Medium Access Controller (MAC) Features

Physical Layer (PHY) Features

Operational

Package Types

Table of Contents

1.0 OVERVIEW

FIGURE 1-1: ENC28J60 BLOCK DIAGRAM

FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE

TABLE 1-1: PINOUT I/O DESCRIPTIONS

2.0 EXTERNAL CONNECTIONS

2.1 Oscillator

2.2 Oscillator Start-up Timer

2.3 CLKOUT Pin

FIGURE 2-3: CLKOUT TRANSITION

REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER

2.4 Magnetics, Termination and Other External Components

FIGURE 2-4: EXTERNAL CONNECTIONS

2.5 I/O Levels

2.6 LED Configuration

3.0 MEMORY ORGANIZATION

FIGURE 3-1: ENC28J60 MEMORY ORGANIZATION

3.1 Control Registers

TABLE 3-1: ENC28J60 CONTROL REGISTER MAP

3.1.1 ECON1 REGISTER

REGISTER 3-1: ECON1: ETHERNET CONTROL REGISTER 1

3.1.2 ECON2 REGISTER

REGISTER 3-2: ECON2: ETHERNET CONTROL REGISTER 2

3.2 Ethernet Buffer

3.2.1 RECEIVE BUFFER

3.2.2 TRANSMIT BU FFER

3.2.3 READING AND WRITING TO THE BUFFER

3.2.4 DMA ACCESS TO THE BUFFER

FIGURE 3-2: ETHERNET BUFFER ORGANIZATION

3.3 PHY Registers

3.3.1 READING PHY REGISTERS

3.3.2 WRITING PHY REGISTERS

3.3.3 SCANNING A PHY REGISTER

TABLE 3-3: ENC28J60 PHY REGISTER SUMMARY

REGISTER 3-3: MICON: MII CONTROL REGISTER

REGISTER 3-4: MICMD: MII COMMAND REGISTER

REGISTER 3-5: MISTAT: MII STATUS REGISTER

3.3.4 PHSTAT REGISTERS

3.3.5 PHID1 AND PHID2 REGISTERS

4.0 SERIAL PERIPHERAL INTERFACE (SPI)

4.1 Overview

FIGURE 4-1: SPI™ INPUT TIMING

FIGURE 4-2: SPI™ OUTPUT TIMING

4.2 SPI Instruction Set

TABLE 4-1: SPI™ INSTRUCTION SET FOR THE ENC28J60

FIGURE 4-3: READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)

4.2.2 READ BUFFER MEMORY COMMAND

4.2.3 WRITE CONTROL REGISTER COMMAND

FIGURE 4-5: WRITE CONTROL REGISTER COMMAND SEQUENCE