MICROCHIP dsPIC33FJ32MC302, dsPIC33FJ32MC3304, dsPIC33FJ64MCX02, dsPIC33FJ64MCX04, dsPIC33FJ128MCX02 Technical data
...
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04
Data Sheet
High-Performance, 16-bit
Digital Signal Controllers
© 2008 Microchip Technology Inc. Preliminary DS70291B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC
32
logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS70291B-page ii Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, AND
dsPIC33FJ128MCX02/X04
High-Performance, 16-bit Digital Signal Controllers
Operating Range:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range
(-40°C to +85°C)
- Extended temperature range
(-40°C to +125°C)
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Two 40-bit accumulators with rounding and
saturation options
• Flexible and powerful addressing modes:
-Indirect
- Modulo
- Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
• 8-channel hardware DMA
• Up to 2 Kbytes dual ported DMA buffer area (DMA
RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code (no
cycle stealing)
• Most peripherals support DMA
Timers/Capture/Compare/PWM:
• Timer/Counters, up to five 16-bit timers:
- Can pair up to make two 32-bit timers
- One timer runs as a Real-Time Clock with an
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to four channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar, and alarm functions
Interrupt Controller:
• 5-cycle latency
• 118 interrupt vectors
• Up to 53 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Five processor exceptions
Digital I/O:
• Peripheral pin Select functionality
• Up to 35 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5V output with open drain configuration
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
On-Chip Flash and SRAM:
• Flash program memory (up to 128 Kbytes)
• Data SRAM (up to 16 Kbytes)
• Boot, Secure, and General Security for program
Flash
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 1
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to nine input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
Audio Digital-to-Analog Converter (DAC):
- 16-bit Dual Channel DAC module
- 100 Ksps maximum sampling rate
- Second-Order Digital Delta-Sigma Modulator
Comparator Module:
• Two analog comparators with programmable
input/output configuration
CMOS Flash Technology:
Motor Control Peripherals:
• 6-channel 16-bit Motor Control PWM:
- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• 2-channel 16-bit Motor Control PWM:
- One duty cycle generator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• 2-Quadrature Encoder Interface module:
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
DS70291B-page 2 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Communication Modules:
• 4-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
2
•I
C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
®
-IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active:
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
• Parallel Master Slave Port (PMP/EPSP):
- Supports 8-bit or 16-bit data
- Supports 16 address lines
• Programmable Cyclic Redundancy Check (CRC):
- Programmable bit length for the CRC
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
encoding and decoding in hardware
monitoring
Transmission Requests
generator polynomial (up to 16-bit length)
input
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
Note: See the device variant table for exact
peripheral features per device.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 3
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, AND
dsPIC33FJ128MCX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families
Remappable Peripheral
SPI
(4)
C™
2
I
RTCC
ECAN™
External Interrupts
1 1 1 9 1 1/1 11 35 QFN
3
(Channels)
CRC Generator
6-pin 16-bit DAC
10-bit/12-bit ADC
Analog Comparator
(2 Channels/Voltage Regulator)
I/O Pins
8-bit Parallel Master
Port (Address Lines)
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
(1)
(2)
Device
dsPIC33FJ128MC804 44 128 16 26 5 4 4 6, 2 2 2 2 1
dsPIC33FJ128MC802 28 128 16 16 5 4 4 6, 2 2 2 2 1 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ128MC204 44 128 8 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ128MC202 28 128 8 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ64MC804 44 64 16 26 5 4 4 6, 2 2 2 2 1 3 1 1 1 9 1 1/1 11 35 QFN
dsPIC33FJ64MC802 28 64 16 16 5 4 4 6, 2 2 2 2 1 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ64MC204 44 64 8 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ64MC202 28 64 8 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ32MC304 44 32 4 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ32MC302 28 32 4 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32MC302/304, which include 1 Kbyte of DMA RAM.
2: Only four out of five timers are remappable.
3: Only PWM fault pins are remappable.
4: Only two out of three interrupts are remappable.
Pins
(Kbyte)
RAM (Kbyte)
16-bit Timer
Input Capture
Program Flash Memory
Remappable Pins
(3)
UART
Interface
(Channels)
Standard PWM
Output Compare
Motor Control PWM
Quadrature Encoder
Packages
DS70291B-page 4 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams
28-Pin SDIP, SOIC
AVDD
28
AVSS
27
PWM1L1/RP15
26
PWM1H1/RTCC/RP14
25
PWM1L2/RP13
24
PWM1H2/RP12
23
PGC2/EMUC2/TMS/PWM1L3/RP11
22
PGD2/EMUD2/TDI/PWM1H3/RP10
21
VCAP/VDDCORE
20
V
SS
19
TDO/PWM2L1/SDA1/RP9
18
TCK/PWM2H1/SCL1/RP8
17
INT0/RP7
16
PGC3/EMUC3/ASCL1/RP6
15
(1)
/CN11/PMCS1/RB15
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN23/PMD5/RB7
(1)
/CN12/PMWR/RB14
(1)
(1)
/CN16/PMD2/RB10
(1)
/CN21/PMD3/RB9
(1)
/CN22/PMD4/RB8
(1)
/CN24/PMD6/RB6
/CN15/PMD1/RB11
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/ AN3/C2IN+/RP1
OSCO/CLKO/CN29/PMA0/RA3
SOSCI/RP4
SOSCO/T1CK/CN0/PMA1/RA4
PGD3/EMUD3/ASDA1/RP5
28-Pin QFN-S
AN0/VREF+/CN2/RA0
AN1/V
AN4/C1IN-/RP2
AN5/C1IN+/RP3
OSCI/CLKI/CN30/RA2
(1)
/CN1/PMBE/RB4
(1)
/CN27/PMD7/RB5
MCLR
REF-/CN3/RA1
(1)
/CN4/RB0
(1)
/CN5/RB1
(1)
/CN6/RB2
(1)
/CN7/RB3
VSS
VDD
1
2
3
dsPIC33FJ32MC302
dsPIC33FJ64MC202
dsPIC33FJ64MC802
dsPIC33FJ128MC202
dsPIC33FJ128MC802
4
5
6
7
8
9
10
11
12
13
14
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/AN3/C2IN+/RP1
AN4/C1IN-/RP2
AN5/C1IN+/RP3
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
(1)
/CN4/RB0
(1)
/CN5/RB1
(1)
/CN6/RB2
(1)
/CN7/RB3
VSS
REF-/CN3/RA1
DD
AN1/V
AV
MCLR
AN0/VREF+/CN2/RA0
8
6
7
5
2
2
2
2
1
2
dsPIC33FJ32MC302
3
dsPIC33FJ64MC202
4
dsPIC33FJ64MC802
dsPIC33FJ128MC202
5
dsPIC33FJ128MC802
6
7
11
9
10
8
VDD
/CN1/PMBE/RB4
SOSCI/RP4
SOSCO/T1CK/CN0/PMA1/RA4
/CN27/PMD7/RB5
(1)
(1)
AVSS
4
2
12
/CN24/PMD6/RB6
(1)
/CN11/PMCS1/RB15
(1)
PWM1L1/RP15
3
2
3
1
/CN23/PMD5/RB7
(1)
INT0/RP7
/CN12/PMWR/RB14
(1)
PWM1H1/RTCC/RP14
2
2
PWM1L2/RP13
21
PWM1H2/RP12
20
PGC2/EMUC2/TMS/PWM1L3/RP11
19
PGD2/EMUD2/TDI/PWM1H3/RP10
18
V
CAP/VDDCORE
17
VSS
16
TDO/PWM2L1/SDA1/RP9
15
(1)
14
/CN22/PMD4/RB8
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
TCK/PWM2H1/SCL1/RP8
PGD3/EMUD3/ASDA1/RP5
PGC3/ EMUC3/ASCL1/RP6
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families” in this section for the list of available
peripherals.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 5
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin QFN
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/DAC1RM/RP16
AN7/DAC1LM/RP17
AN8/CV
REF/RP18
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
(1)
/CN9/RC1
/PMA2/CN10/RC2
V
DD
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN1/RB4
/CN5/RB1
/CN4/RB0
(1)
(1)
REF-/CN3/RA1
REF+/CN2/RA0
AN0/V
PGD1/EMUD1/AN2/C2IN-/RP0
21
MCLR
AVDDAVSS
AN1/V
20
17
18
19
PGC1/EMUC1/AN3/C2IN+/RP1
23
22
24
25
26
27
dsPIC33FJ64MC804
28
dsPIC33FJ128MC804
29
30
31
33
35
34
39
38
37
36
SS
V
TDI/PMA9/RA9
/CN26/PMA3/RC5
/CN25/PMA4/RC4
/CN28/PMBE/RC3
(1)
(1)
(1)
SOSCO/T1CK/CN0/RA4
RP21
RP20
RP19
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
PWM1H1/DAC1LP/RTCC/RP14
TCK/PMA7/RA7
TMS/PMA10/RA10
PWM1L1/DAC1LN/RP15
(1)
16
40
DD
V
41
/CN27/PMD7/RB5
(1)
42
/CN24/PMD6/RB6
(1)
43
/CN23/PMD5/RB7
(1)
INT0/RP7
12
PWM1H2/DAC1RP/RP12
10
PGC2/EMUC2/PWM1L3/RP11
9
PGD2/EMUD2/PWM1H3/RP10
8
V
CAP/VDDCORE
7
VSS
44
/CN22/PMD4/RB8
(1)
6
5
4
3
232
1
(1)
RP25
/CN19/PMA6/RC9
(1)
RP24
/CN20/PMA5/RC8
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
SCL1/RP8
(1)
/CN17/PMA0/RC7
(1)
(1)
/CN21/PMD3/RB9
PWM1L2/DAC1RN/RP13
11
13
14
15
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
/CN18/PMA1/RC6
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
DS70291B-page 6 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin QFN
/CN5/RB1
/CN4/RB0
(1)
(1)
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGD1/EMUD1/AN2/C2IN-/RP0
AN8/CV
AN5/C1IN+/RP3
AN6/RP16
AN7/RP17
REF/RP18
(1)
/PMA2/CN10/RC2
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
/CN9/RC1
(1)
/CN1/RB4
V
VSS
DD
AN1/V
PGC1/EMUC1/AN3/C2IN+/RP1
AN0/V
MCLR
23
20
21
18
19
22
24
25
26
dsPIC33FJ32MC304
27
dsPIC33FJ64MC204
28
29
dsPIC33FJ128MC204
30
31
33
34
38
37
36
35
AVDDAVSS
17
39
SS
V
40
DD
V
PWM1H1/RTCC/RP14
TMS/PMA10/RA10
PWM1L1/RP15
TCK/PMA7/RA7
16
12
PWM1H2/RP12
10
PGC2/EMUC2/PWM1L3/RP11
9
PGD2/EMUD2/PWM1H3/RP10
8
V
CAP/VDDCORE
7
VSS
6
5
4
3
232
41
1
44
43
42
(1)
RP25
(1)
RP24
PWM2L1/RP23
PWM2H1/RP2
SDA1/RP9
PWM1L2/RP13
11
13
14
15
(1)
/CN13/PMRD/RB13AN4/C1IN-/RP2
(1)
/CN14/PMD0/RB12
/CN19/PMA6/RC9
/CN20/PMA5/RC8
(1)
/CN17/PMA0/RC7
(1)
2/CN18/PMA1/RC6
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
TDI/PMA9/RA9
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
/CN26/PMA3/RC5
/CN25/PMA4/RC4
SOSCO/T1CK/CN0/RA4
/CN28/PMBE/RC3
(1)
(1)
RP20
RP19
(1)
RP21
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 7
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin TQFP
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/DAC1RM/RP16
AN7/DAC1LM/RP17
AN8/CV
REF/RP18
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
(1)
/CN9/RC1
/PMA2/CN10/RC2
V
DD
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN1/RB4
/CN5/RB1
/CN4/RB0
(1)
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGC1/EMUC1/AN3/C2IN+/RP1
AN1/V
AN0/V
MCLR
PGD1/EMUD1/AN2/C2IN-/RP0
21
22
23
24
25
AVDDAVSS
17
18
19
20
26
27
dsPIC33FJ64MC804
28
dsPIC33FJ128MC804
29
30
31
32
33
39
363435937
38
SS
V
TDI/PMA9/RA9
/CN26/PMA3/RC5
/CN25/PMA4/RC4
/CN28/PMBE/RC3
(1)
(1)
(1)
SOSCO/T1CK/CN0/RA4
RP21
RP20
RP19
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
TMS/PMA10/RA10
PWM1L1/DAC1LN/RP15
TCK/PMA7/RA7
PWM1H1/DAC1LP/RTCC/RP14
16
40
DD
V
12
13
14
15
11
PWM1L2/DAC1RN/RP13
10
PWM1H2/DAC1RP/RP12
PGC2/EMUC2/PWM1L3/RP11
8
PGD2/EMCD2/PWM1H3/RP10
7
CAP/VDDCORE
V
6
VSS
5
4
3
2
1
44
43
42
41
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
(1)
RP25
/CN19/PMA6/RC9
(1)
/CN20/PMA5/RC8
RP24
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
(1)
(1)
/CN21/PMD3/RB9
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
/CN17/PMA0/RC7
(1)
/CN18/PMA1/RC6
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families” in this section for the list of available
peripherals.
DS70291B-page 8 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin TQFP
/CN5/RB1
/CN4/RB0
(1)
(1)
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/AN3/C2IN+/RP1
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/RP16
AN7/RP17
AN8/CV
REF/RP18/PMA2/CN10/RC2
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
SOSCI/RP4
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
/CN9/RC1
V
DD
VSS
TDO/PMA8/RA8
(1)
/CN1/RB4
AN1/V
AVDDAVSS
AN0/V
MCLR
18
19
20
21
22
23
24
25
26
dsPIC33FJ32MC304
27
28
dsPIC33FJ64MC204
29
dsPIC33FJ128MC204
30
17
31
32
33
39
363435937
38
16
40
TMS/PMA10/RA10
PWM1L1/RP15
TCK/PMA7/RA7
PWM1H1/RTCC/RP14
12
13
14
15
11
PWM1L2/RP13
10
PWM1H2/RP12
PGC2/EMUC2/PWM1L3/RP11
8
PGD2/EMCD2/PWM1H3/RP10
7
CAP/VDDCORE
V
6
VSS
5
4
3
2
1
44
43
42
41
(1)
RP25
(1)
RP24
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
/CN19/PMA6/RC9
/CN20/PMA5/RC8
(1)
/CN17/PMA0/RC7
(1)
/CN18/PMA1/RC6
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
SS
DD
V
V
TDI/PMA9/RA9
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
/CN26/PMA3/RC5
/CN25/PMA4/RC4
SOSCO/T1CK/CN0/RA4
/CN28/PMBE/RC3
(1)
(1)
RP20
RP19
(1)
RP21
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 9
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Table of Contents
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Product Families............................................ 4
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 CPU............................................................................................................................................................................................ 19
3.0 Memory Organization ................................................................................................................................................................. 31
4.0 Flash Program Memory.............................................................................................................................................................. 67
5.0 Resets ....................................................................................................................................................................................... 73
6.0 Interrupt Controller ..................................................................................................................................................................... 81
7.0 Direct Memory Access (DMA) .................................................................................................................................................. 123
8.0 Oscillator Configuration............................................................................................................................................................ 135
9.0 Power-Saving Features............................................................................................................................................................ 147
10.0 I/O Ports ................................................................................................................................................................................... 149
11.0 Timer1 ...................................................................................................................................................................................... 181
12.0 Timer2/3 And TImer4/5 feature ............................................................................................................................................... 183
13.0 Input Capture............................................................................................................................................................................ 189
14.0 Output Compare....................................................................................................................................................................... 191
15.0 Motor Control PWM Module ..................................................................................................................................................... 195
16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 209
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 213
18.0 Inter-Integrated Circuit (I
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 227
20.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 233
21.0 10-bit/12-bit Analog-to-Digital Converter (ADC1) ..................................................................................................................... 259
22.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 273
23.0 Comparator Module.................................................................................................................................................................. 279
24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 285
25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 295
26.0 Parallel Master Port (PMP)....................................................................................................................................................... 299
27.0 Special Features ...................................................................................................................................................................... 307
28.0 Instruction Set Summary .......................................................................................................................................................... 317
29.0 Development Support............................................................................................................................................................... 325
30.0 Electrical Characteristics .......................................................................................................................................................... 329
31.0 Packaging Information.............................................................................................................................................................. 375
Appendix A: Revision History............................................................................................................................................................. 385
Index ................................................................................................................................................................................................. 387
The Microchip Web Site..................................................................................................................................................................... 393
Customer Change Notification Service .............................................................................................................................................. 393
Customer Support .............................................................................................................................................................................. 393
Reader Response .............................................................................................................................................................................. 394
Product Identification System............................................................................................................................................................. 395
2
C™) ................................................................................................................................................. 219
DS70291B-page 10 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2008 Microchip Technology Inc. Preliminary DS70291B-page 11
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
NOTES:
DS70291B-page 12 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com)
This document contains device specific information for
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 Digital Signal
Controller (DSC) Devices. The dsPIC33F devices
contain extensive Digital Signal Processor (DSP)
functionality with a high performance 16-bit
microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the
core and peripheral modules in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 families of devices.
Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 13
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
23
Address Latch
Program Memory
Data Latch
OSC2/CLKO
OSC1/CLKI
Interrupt
Controller
23
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
23
Control
Address Bus
Decode and
Control Signals
to Various Blocks
8
PCH PCL
PCU
Program Counter
Stack
Logic
Loop
Control
Logic
24
Instruction
Control
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
16
X Data Bus
16
Data Latch
X RAM
Address
Latch
16
Address Generator Units
ROM Latch
Instruction Reg
DSP Engine
Divide Support
16
Data Latch
Y RAM
Address
Latch
W Register Array
16
16
EA MUX
16
16 x 16
16
Literal Data
16-bit ALU
DMA
RAM
DMA
Controller
16
16
16
16
PORTA
PORTB
PORTC
Remappable
Pins
VDDCORE/VCAP
PMP/
EPSP
RTCC
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
Compar-
ator1, 2
DAC1
present on each device.
DD, VSS
V
ECAN1
SPI1, 2
MCLR
Timers
1-5
IC1, 2, 7, 8
UART1, 2
CNx
ADC1
I2C1
OC/
PWM1-4
QEI1, 2
PWM
2 Ch
PWM
6 Ch
DS70291B-page 14 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN8
CLKI
CLKO
OSC1
OSC2
SOSCI
SOSCO
CN0-CN30 I ST Change notification inputs.
IC1-IC2
IC7-IC8
OCFA
OC1-OC4
INT0
INT1
INT2
RA0-RA4
RA7-RA10
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC0-RC9 I/O ST PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
U1CTS
U1RTS
U1RX
U1TX
2CTS
U
U2RTS
U2RX
U2TX
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
2
SS
SCL1
SDA1
ASCL1
ASDA1
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Pin
Type
I Analog Analog input channels.
I
O
I
I/O
I
O
I
I
I
O
I
I
I
I/O
I/O
I
I
I
I
I
I
O
I
O
I
O
I
O
I/O
I
O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST/CMOS—External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
Can be software programmed for internal weak pull-ups on all inputs.
STSTCapture inputs 1/2
Capture inputs 7/8.
ST—Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
ST
ST
ST
STSTPORTA is a bidirectional I/O port.
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
PORTA is a bidirectional I/O port.
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
UART1 clear to send.
—
UART1 ready to send.
UART1 receive.
—
UART1 transmit.
UART2 clear to send.
—
UART2 ready to send.
UART2 receive.
—
UART2 transmit.
Synchronous serial clock input/output for SPI1.
SPI1 data in.
—
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
—
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
Description
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 15
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
TMS
TCK
TDI
TDO
INDX1
QEA1
QEB1
UPDN1
INDX2
QEA2
QEB2
UPDN2
C1RX
C1TX
RTCC O — Real-Time Clock Alarm Output.
REF O ANA Comparator Voltage Reference Output.
CV
C1IN-
C1IN+
C1OUT
C2INC2IN+
C2OUT
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
DAC1RN
DAC1RP
DAC1RM
DAC2RN
DAC2RP
DAC2RM
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Pin
Type
I
I
I
O
I
I
I
O
I
I
I
O
I
O
I
I
O
I
I
O
I/O
I/O
O
O
O
I/O
O
O
O
O
O
O
O
O
Buffer
Type
ST
ST
ST
ST
ST
ST
CMOS
ST
ST
ST
CMOS
ST—ECAN1 bus receive pin.
ANA
ANA
ANA
ANA
TTL/ST
TTL/ST
TTL/ST
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
—
JTAG test data output pin.
Quadrature Encoder Index1 Pulse input.
Quadrature Encoder Phase A input in QEI1 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI1 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
Quadrature Encoder Index2 Pulse input.
Quadrature Encoder Phase A input in QEI2 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI2 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
ECAN1 bus transmit pin.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
—
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
—
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output
(Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output
(Master modes).
—
Parallel Master Port Address (Demultiplexed Master Modes).
—
Parallel Master Port Byte Enable Strobe.
—
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/Data
(Multiplexed Master modes).
—
Parallel Master Port Read Strobe.
—
Parallel Master Port Write Strobe.
—
DAC1 Negative Output.
—
DAC1 Positive Output.
—
DAC1 Output indicating middle point value (typically 1.65V).
—
DAC2 Negative Output.
—
DAC2 Positive Output.
—
DAC2 Output indicating middle point value (typically 1.65V).
Description
DS70291B-page 16 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
Description
FLTA1
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
FLTA2
PWM2L1
PWM2H1
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
MCLR
I
O
O
O
O
O
O
I
O
O
I/O
I/O
I/O
ST
—
—
—
—
—
—
ST
—
—
ST
I
ST
ST
I
ST
ST
I
ST
PWM1 Fault A input.
PWM1 Low output 1
PWM1 High output 1
PWM1 Low output 2
PWM1 High output 2
PWM1 Low output 3
PWM1 High output 3
PWM2 Fault A input.
PWM2 Low output 1
PWM2 High output 1
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD P P Positive supply for analog modules.
SS P P Ground reference for analog modules.
AV
VDD P — Positive supply for peripheral logic and I/O pins.
VDDCORE P — CPU logic filter capacitor connection.
Vss P — Ground reference for logic and I/O pins.
REF+ I Analog Analog voltage reference (high) input.
V
VREF- I Analog Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 17
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
NOTES:
DS70291B-page 18 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.0 CPU
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, “Section 2. CPU”
(DS70204), which is available from the
Microchip website (www.microchip.com).
2.1 Overview
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 devices have sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 2-1, and
the programmer’s model for the dsPIC33FJ32MC302/
304, dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 is shown in Figure 2-2.
2.2 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
2.3 DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal realtime performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 19
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.4 Special MCU Features
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 supports 16/16
and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 2-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
23
Address Latch
Controller
23
Interrupt
23
8
PCH PCL
PCU
Program Counter
Stac k
Control
Logic
Control
16
Loop
Logic
Y Data Bus
X Data Bus
16
Data Latch
X RAM
Address
Latch
Address Generator Units
16
16
16
Data Latch
Y RAM
Address
Latch
16
DMA
RAM
16
DMA
Controller
Program Memory
Data Latch
Address Bus
24
Instruction
Decode &
Control
Control Signals
to Various Blocks
ROM Latch
Instruction Reg
DSP Engine
Divide Support
EA MUX
16
16
Literal Data
16 x 16
W Register Array
16-bit ALU
16
16
16
To Peripheral Modules
DS70291B-page 20 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 2-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 PROGRAMMER’S MODEL
D0D15
DSP Operand
Registers
DSP Address
Registers
W0/WREG
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Working Registers
PUSH.S Shadow
DO Shadow
Legend
DSP
Accumulators
PC22
7
TBLPAG
7
22
22
PSVPAG
AD39 AD0AD31
ACCA
ACCB
0
Data Table Page Address
0
SPLIM Stack Pointer Limit Register
Program Space Visibility Page Address
15
RCOUNT
15
DCOUNT
DOSTART
DOEND
PC0
AD15
Program Counter
0
0
REPEAT Loop Counter
0
DO Loop Counter
0
DO Loop Start Address
DO Loop End Address
15
CORCON
OA OB SA SB
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 21
OAB SAB
SRH
DA DC
IPL2 IPL1
RA
IPL0 OV
SRL
0
Core Configuration Register
N
C
Z
STATUS Register
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.5 CPU Control Registers
REGISTER 2-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA
(1)
bit 15 bit 8
SB
(1)
OAB SAB DA DC
R/W-0
(3)
IPL<2:0>
R/W-0
(3)
(2)
R/W-0
(3)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit 7 bit 0
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit
(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
DS70291B-page 22 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
bit
(2)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 23
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)
DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(2)
PSV RND IF
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70291B-page 24 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 25
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.6 Arithmetic Logic Unit (ALU)
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are two’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
and Digit Borrow bits, respectively, for
Borrow
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and
support hardware for 16-bit-divisor division.
2.6.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
2.6.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
2.7 DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 2-3.
DS70291B-page 26 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 2-1: DSP INSTRUCTIONS SUMMARY
Instruction Algebraic Operation ACC Write Back
CLR A = 0
ED A = (x – y)2 No
EDAC A = A + (x – y)2 No
MAC A = A + (x • y) Yes
MAC A = A + x2 No
MOVSAC No change in A Yes
MPY A = x • y No
MPY A = x 2 No
MPY.N A = – x • y No
MSC A = A – x • y Yes
FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM
40
Carry/Borrow Out
Carry/Borrow In
40-bit Accumulator A
40-bit Accumulator B
Saturate
Adder
Negate
40
Round
Logic
Yes
S
a
t
16
u
r
a
t
e
40
16
40
Barrel
Shifter
32
32
40
16
X Data Bus
16
Zero Backfill
40
Sign-Extend
Y Data Bus
33
17-bit
Multiplier/Scaler
16
To/From W Array
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 27
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.7.1 MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed two’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit two’s complement integer is -2
N-1
to 2
N-1
– 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is 2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 2
1-N
). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10
-10
.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified registers in the W array.
2.7.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
2.7.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/B
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow
is active-low and the other input is complemented.
orrow input is
input
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described previously and the SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
Section 6.0 “Interrupt Controller”). This allows the
user application to take immediate action, for example,
to correct system gain.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and is saturated (if saturation is enabled).
When saturation is not enabled, SA and SB default to
bit 39 overflow and thus indicate that a catastrophic
overflow has occurred. If the COVTE bit in the
INTCON1 register is set, the SA and SB bits generate
an arithmetic warning trap when saturation is disabled.
DS70291B-page 28 Preliminary © 2008 Microchip Technology Inc.
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