MICROCHIP dsPIC33FJ32MC302, dsPIC33FJ32MC3304, dsPIC33FJ64MCX02, dsPIC33FJ64MCX04, dsPIC33FJ128MCX02 Technical data
...
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04
Data Sheet
High-Performance, 16-bit
Digital Signal Controllers
© 2008 Microchip Technology Inc. Preliminary DS70291B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC
32
logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS70291B-page ii Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, AND
dsPIC33FJ128MCX02/X04
High-Performance, 16-bit Digital Signal Controllers
Operating Range:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range
(-40°C to +85°C)
- Extended temperature range
(-40°C to +125°C)
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Two 40-bit accumulators with rounding and
saturation options
• Flexible and powerful addressing modes:
-Indirect
- Modulo
- Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
• 8-channel hardware DMA
• Up to 2 Kbytes dual ported DMA buffer area (DMA
RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code (no
cycle stealing)
• Most peripherals support DMA
Timers/Capture/Compare/PWM:
• Timer/Counters, up to five 16-bit timers:
- Can pair up to make two 32-bit timers
- One timer runs as a Real-Time Clock with an
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to four channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar, and alarm functions
Interrupt Controller:
• 5-cycle latency
• 118 interrupt vectors
• Up to 53 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Five processor exceptions
Digital I/O:
• Peripheral pin Select functionality
• Up to 35 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5V output with open drain configuration
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
On-Chip Flash and SRAM:
• Flash program memory (up to 128 Kbytes)
• Data SRAM (up to 16 Kbytes)
• Boot, Secure, and General Security for program
Flash
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 1
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to nine input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
Audio Digital-to-Analog Converter (DAC):
- 16-bit Dual Channel DAC module
- 100 Ksps maximum sampling rate
- Second-Order Digital Delta-Sigma Modulator
Comparator Module:
• Two analog comparators with programmable
input/output configuration
CMOS Flash Technology:
Motor Control Peripherals:
• 6-channel 16-bit Motor Control PWM:
- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• 2-channel 16-bit Motor Control PWM:
- One duty cycle generator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• 2-Quadrature Encoder Interface module:
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
DS70291B-page 2 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Communication Modules:
• 4-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
2
•I
C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
®
-IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active:
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
• Parallel Master Slave Port (PMP/EPSP):
- Supports 8-bit or 16-bit data
- Supports 16 address lines
• Programmable Cyclic Redundancy Check (CRC):
- Programmable bit length for the CRC
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
encoding and decoding in hardware
monitoring
Transmission Requests
generator polynomial (up to 16-bit length)
input
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
Note: See the device variant table for exact
peripheral features per device.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 3
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, AND
dsPIC33FJ128MCX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families
Remappable Peripheral
SPI
(4)
C™
2
I
RTCC
ECAN™
External Interrupts
1 1 1 9 1 1/1 11 35 QFN
3
(Channels)
CRC Generator
6-pin 16-bit DAC
10-bit/12-bit ADC
Analog Comparator
(2 Channels/Voltage Regulator)
I/O Pins
8-bit Parallel Master
Port (Address Lines)
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
TQFP
SOIC
QFN-S
(1)
(2)
Device
dsPIC33FJ128MC804 44 128 16 26 5 4 4 6, 2 2 2 2 1
dsPIC33FJ128MC802 28 128 16 16 5 4 4 6, 2 2 2 2 1 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ128MC204 44 128 8 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ128MC202 28 128 8 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ64MC804 44 64 16 26 5 4 4 6, 2 2 2 2 1 3 1 1 1 9 1 1/1 11 35 QFN
dsPIC33FJ64MC802 28 64 16 16 5 4 4 6, 2 2 2 2 1 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ64MC204 44 64 8 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ64MC202 28 64 8 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
dsPIC33FJ32MC304 44 32 4 26 5 4 4 6, 2 2 2 2 0 3 1 1 1 9 0 1/1 11 35 QFN
dsPIC33FJ32MC302 28 32 4 16 5 4 4 6, 2 2 2 2 0 3 1 1 1 6 0 1/0 2 21 SDIP
Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32MC302/304, which include 1 Kbyte of DMA RAM.
2: Only four out of five timers are remappable.
3: Only PWM fault pins are remappable.
4: Only two out of three interrupts are remappable.
Pins
(Kbyte)
RAM (Kbyte)
16-bit Timer
Input Capture
Program Flash Memory
Remappable Pins
(3)
UART
Interface
(Channels)
Standard PWM
Output Compare
Motor Control PWM
Quadrature Encoder
Packages
DS70291B-page 4 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams
28-Pin SDIP, SOIC
AVDD
28
AVSS
27
PWM1L1/RP15
26
PWM1H1/RTCC/RP14
25
PWM1L2/RP13
24
PWM1H2/RP12
23
PGC2/EMUC2/TMS/PWM1L3/RP11
22
PGD2/EMUD2/TDI/PWM1H3/RP10
21
VCAP/VDDCORE
20
V
SS
19
TDO/PWM2L1/SDA1/RP9
18
TCK/PWM2H1/SCL1/RP8
17
INT0/RP7
16
PGC3/EMUC3/ASCL1/RP6
15
(1)
/CN11/PMCS1/RB15
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN23/PMD5/RB7
(1)
/CN12/PMWR/RB14
(1)
(1)
/CN16/PMD2/RB10
(1)
/CN21/PMD3/RB9
(1)
/CN22/PMD4/RB8
(1)
/CN24/PMD6/RB6
/CN15/PMD1/RB11
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/ AN3/C2IN+/RP1
OSCO/CLKO/CN29/PMA0/RA3
SOSCI/RP4
SOSCO/T1CK/CN0/PMA1/RA4
PGD3/EMUD3/ASDA1/RP5
28-Pin QFN-S
AN0/VREF+/CN2/RA0
AN1/V
AN4/C1IN-/RP2
AN5/C1IN+/RP3
OSCI/CLKI/CN30/RA2
(1)
/CN1/PMBE/RB4
(1)
/CN27/PMD7/RB5
MCLR
REF-/CN3/RA1
(1)
/CN4/RB0
(1)
/CN5/RB1
(1)
/CN6/RB2
(1)
/CN7/RB3
VSS
VDD
1
2
3
dsPIC33FJ32MC302
dsPIC33FJ64MC202
dsPIC33FJ64MC802
dsPIC33FJ128MC202
dsPIC33FJ128MC802
4
5
6
7
8
9
10
11
12
13
14
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/AN3/C2IN+/RP1
AN4/C1IN-/RP2
AN5/C1IN+/RP3
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
(1)
/CN4/RB0
(1)
/CN5/RB1
(1)
/CN6/RB2
(1)
/CN7/RB3
VSS
REF-/CN3/RA1
DD
AN1/V
AV
MCLR
AN0/VREF+/CN2/RA0
8
6
7
5
2
2
2
2
1
2
dsPIC33FJ32MC302
3
dsPIC33FJ64MC202
4
dsPIC33FJ64MC802
dsPIC33FJ128MC202
5
dsPIC33FJ128MC802
6
7
11
9
10
8
VDD
/CN1/PMBE/RB4
SOSCI/RP4
SOSCO/T1CK/CN0/PMA1/RA4
/CN27/PMD7/RB5
(1)
(1)
AVSS
4
2
12
/CN24/PMD6/RB6
(1)
/CN11/PMCS1/RB15
(1)
PWM1L1/RP15
3
2
3
1
/CN23/PMD5/RB7
(1)
INT0/RP7
/CN12/PMWR/RB14
(1)
PWM1H1/RTCC/RP14
2
2
PWM1L2/RP13
21
PWM1H2/RP12
20
PGC2/EMUC2/TMS/PWM1L3/RP11
19
PGD2/EMUD2/TDI/PWM1H3/RP10
18
V
CAP/VDDCORE
17
VSS
16
TDO/PWM2L1/SDA1/RP9
15
(1)
14
/CN22/PMD4/RB8
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
TCK/PWM2H1/SCL1/RP8
PGD3/EMUD3/ASDA1/RP5
PGC3/ EMUC3/ASCL1/RP6
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families” in this section for the list of available
peripherals.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 5
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin QFN
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/DAC1RM/RP16
AN7/DAC1LM/RP17
AN8/CV
REF/RP18
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
(1)
/CN9/RC1
/PMA2/CN10/RC2
V
DD
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN1/RB4
/CN5/RB1
/CN4/RB0
(1)
(1)
REF-/CN3/RA1
REF+/CN2/RA0
AN0/V
PGD1/EMUD1/AN2/C2IN-/RP0
21
MCLR
AVDDAVSS
AN1/V
20
17
18
19
PGC1/EMUC1/AN3/C2IN+/RP1
23
22
24
25
26
27
dsPIC33FJ64MC804
28
dsPIC33FJ128MC804
29
30
31
33
35
34
39
38
37
36
SS
V
TDI/PMA9/RA9
/CN26/PMA3/RC5
/CN25/PMA4/RC4
/CN28/PMBE/RC3
(1)
(1)
(1)
SOSCO/T1CK/CN0/RA4
RP21
RP20
RP19
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
PWM1H1/DAC1LP/RTCC/RP14
TCK/PMA7/RA7
TMS/PMA10/RA10
PWM1L1/DAC1LN/RP15
(1)
16
40
DD
V
41
/CN27/PMD7/RB5
(1)
42
/CN24/PMD6/RB6
(1)
43
/CN23/PMD5/RB7
(1)
INT0/RP7
12
PWM1H2/DAC1RP/RP12
10
PGC2/EMUC2/PWM1L3/RP11
9
PGD2/EMUD2/PWM1H3/RP10
8
V
CAP/VDDCORE
7
VSS
44
/CN22/PMD4/RB8
(1)
6
5
4
3
232
1
(1)
RP25
/CN19/PMA6/RC9
(1)
RP24
/CN20/PMA5/RC8
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
SCL1/RP8
(1)
/CN17/PMA0/RC7
(1)
(1)
/CN21/PMD3/RB9
PWM1L2/DAC1RN/RP13
11
13
14
15
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
/CN18/PMA1/RC6
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
DS70291B-page 6 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin QFN
/CN5/RB1
/CN4/RB0
(1)
(1)
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGD1/EMUD1/AN2/C2IN-/RP0
AN8/CV
AN5/C1IN+/RP3
AN6/RP16
AN7/RP17
REF/RP18
(1)
/PMA2/CN10/RC2
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
/CN9/RC1
(1)
/CN1/RB4
V
VSS
DD
AN1/V
PGC1/EMUC1/AN3/C2IN+/RP1
AN0/V
MCLR
23
20
21
18
19
22
24
25
26
dsPIC33FJ32MC304
27
dsPIC33FJ64MC204
28
29
dsPIC33FJ128MC204
30
31
33
34
38
37
36
35
AVDDAVSS
17
39
SS
V
40
DD
V
PWM1H1/RTCC/RP14
TMS/PMA10/RA10
PWM1L1/RP15
TCK/PMA7/RA7
16
12
PWM1H2/RP12
10
PGC2/EMUC2/PWM1L3/RP11
9
PGD2/EMUD2/PWM1H3/RP10
8
V
CAP/VDDCORE
7
VSS
6
5
4
3
232
41
1
44
43
42
(1)
RP25
(1)
RP24
PWM2L1/RP23
PWM2H1/RP2
SDA1/RP9
PWM1L2/RP13
11
13
14
15
(1)
/CN13/PMRD/RB13AN4/C1IN-/RP2
(1)
/CN14/PMD0/RB12
/CN19/PMA6/RC9
/CN20/PMA5/RC8
(1)
/CN17/PMA0/RC7
(1)
2/CN18/PMA1/RC6
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
TDI/PMA9/RA9
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
/CN26/PMA3/RC5
/CN25/PMA4/RC4
SOSCO/T1CK/CN0/RA4
/CN28/PMBE/RC3
(1)
(1)
RP20
RP19
(1)
RP21
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 7
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin TQFP
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/DAC1RM/RP16
AN7/DAC1LM/RP17
AN8/CV
REF/RP18
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
(1)
/CN9/RC1
/PMA2/CN10/RC2
V
DD
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4
(1)
/CN1/RB4
/CN5/RB1
/CN4/RB0
(1)
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGC1/EMUC1/AN3/C2IN+/RP1
AN1/V
AN0/V
MCLR
PGD1/EMUD1/AN2/C2IN-/RP0
21
22
23
24
25
AVDDAVSS
17
18
19
20
26
27
dsPIC33FJ64MC804
28
dsPIC33FJ128MC804
29
30
31
32
33
39
363435937
38
SS
V
TDI/PMA9/RA9
/CN26/PMA3/RC5
/CN25/PMA4/RC4
/CN28/PMBE/RC3
(1)
(1)
(1)
SOSCO/T1CK/CN0/RA4
RP21
RP20
RP19
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
TMS/PMA10/RA10
PWM1L1/DAC1LN/RP15
TCK/PMA7/RA7
PWM1H1/DAC1LP/RTCC/RP14
16
40
DD
V
12
13
14
15
11
PWM1L2/DAC1RN/RP13
10
PWM1H2/DAC1RP/RP12
PGC2/EMUC2/PWM1L3/RP11
8
PGD2/EMCD2/PWM1H3/RP10
7
CAP/VDDCORE
V
6
VSS
5
4
3
2
1
44
43
42
41
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
(1)
RP25
/CN19/PMA6/RC9
(1)
/CN20/PMA5/RC8
RP24
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
(1)
(1)
/CN21/PMD3/RB9
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
/CN17/PMA0/RC7
(1)
/CN18/PMA1/RC6
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
Controller Families” in this section for the list of available
peripherals.
DS70291B-page 8 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Pin Diagrams (Continued)
44-Pin TQFP
/CN5/RB1
/CN4/RB0
(1)
(1)
/CN12/PMWR/RB14
(1)
/CN11/PMCS1/RB15
(1)
REF-/CN3/RA1
REF+/CN2/RA0
PGD1/EMUD1/AN2/C2IN-/RP0
PGC1/EMUC1/AN3/C2IN+/RP1
AN4/C1IN-/RP2
AN5/C1IN+/RP3
AN6/RP16
AN7/RP17
AN8/CV
REF/RP18/PMA2/CN10/RC2
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
SOSCI/RP4
(1)
/CN6/RB2
(1)
/CN7/RB3
(1)
/CN8/RC0
(1)
/CN9/RC1
V
DD
VSS
TDO/PMA8/RA8
(1)
/CN1/RB4
AN1/V
AVDDAVSS
AN0/V
MCLR
18
19
20
21
22
23
24
25
26
dsPIC33FJ32MC304
27
28
dsPIC33FJ64MC204
29
dsPIC33FJ128MC204
30
17
31
32
33
39
363435937
38
16
40
TMS/PMA10/RA10
PWM1L1/RP15
TCK/PMA7/RA7
PWM1H1/RTCC/RP14
12
13
14
15
11
PWM1L2/RP13
10
PWM1H2/RP12
PGC2/EMUC2/PWM1L3/RP11
8
PGD2/EMCD2/PWM1H3/RP10
7
CAP/VDDCORE
V
6
VSS
5
4
3
2
1
44
43
42
41
(1)
RP25
(1)
RP24
PWM2L1/RP23
PWM2H1/RP22
SDA1/RP9
(1)
/CN13/PMRD/RB13
(1)
/CN14/PMD0/RB12
/CN19/PMA6/RC9
/CN20/PMA5/RC8
(1)
/CN17/PMA0/RC7
(1)
/CN18/PMA1/RC6
(1)
/CN21/PMD3/RB9
(1)
/CN15/PMD1/RB11
(1)
/CN16/PMD2/RB10
SS
DD
V
V
TDI/PMA9/RA9
/CN22/PMD4/RB8
/CN23/PMD5/RB7
/CN24/PMD6/RB6
/CN27/PMD7/RB5
/CN26/PMA3/RC5
/CN25/PMA4/RC4
SOSCO/T1CK/CN0/RA4
/CN28/PMBE/RC3
(1)
(1)
RP20
RP19
(1)
RP21
(1)
(1)
(1)
(1)
INT0/RP7
SCL1/RP8
PGC3/EMUC3/ASCL1/RP6
PGD3/EMUD3/ASDA1/RP5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04
peripherals.
Controller Families” in this section for the list of available
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 9
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
Table of Contents
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/X04 Product Families............................................ 4
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 CPU............................................................................................................................................................................................ 19
3.0 Memory Organization ................................................................................................................................................................. 31
4.0 Flash Program Memory.............................................................................................................................................................. 67
5.0 Resets ....................................................................................................................................................................................... 73
6.0 Interrupt Controller ..................................................................................................................................................................... 81
7.0 Direct Memory Access (DMA) .................................................................................................................................................. 123
8.0 Oscillator Configuration............................................................................................................................................................ 135
9.0 Power-Saving Features............................................................................................................................................................ 147
10.0 I/O Ports ................................................................................................................................................................................... 149
11.0 Timer1 ...................................................................................................................................................................................... 181
12.0 Timer2/3 And TImer4/5 feature ............................................................................................................................................... 183
13.0 Input Capture............................................................................................................................................................................ 189
14.0 Output Compare....................................................................................................................................................................... 191
15.0 Motor Control PWM Module ..................................................................................................................................................... 195
16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 209
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 213
18.0 Inter-Integrated Circuit (I
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 227
20.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 233
21.0 10-bit/12-bit Analog-to-Digital Converter (ADC1) ..................................................................................................................... 259
22.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 273
23.0 Comparator Module.................................................................................................................................................................. 279
24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 285
25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 295
26.0 Parallel Master Port (PMP)....................................................................................................................................................... 299
27.0 Special Features ...................................................................................................................................................................... 307
28.0 Instruction Set Summary .......................................................................................................................................................... 317
29.0 Development Support............................................................................................................................................................... 325
30.0 Electrical Characteristics .......................................................................................................................................................... 329
31.0 Packaging Information.............................................................................................................................................................. 375
Appendix A: Revision History............................................................................................................................................................. 385
Index ................................................................................................................................................................................................. 387
The Microchip Web Site..................................................................................................................................................................... 393
Customer Change Notification Service .............................................................................................................................................. 393
Customer Support .............................................................................................................................................................................. 393
Reader Response .............................................................................................................................................................................. 394
Product Identification System............................................................................................................................................................. 395
2
C™) ................................................................................................................................................. 219
DS70291B-page 10 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2008 Microchip Technology Inc. Preliminary DS70291B-page 11
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
NOTES:
DS70291B-page 12 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com)
This document contains device specific information for
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 Digital Signal
Controller (DSC) Devices. The dsPIC33F devices
contain extensive Digital Signal Processor (DSP)
functionality with a high performance 16-bit
microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the
core and peripheral modules in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 families of devices.
Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 13
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
23
Address Latch
Program Memory
Data Latch
OSC2/CLKO
OSC1/CLKI
Interrupt
Controller
23
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
23
Control
Address Bus
Decode and
Control Signals
to Various Blocks
8
PCH PCL
PCU
Program Counter
Stack
Logic
Loop
Control
Logic
24
Instruction
Control
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
16
X Data Bus
16
Data Latch
X RAM
Address
Latch
16
Address Generator Units
ROM Latch
Instruction Reg
DSP Engine
Divide Support
16
Data Latch
Y RAM
Address
Latch
W Register Array
16
16
EA MUX
16
16 x 16
16
Literal Data
16-bit ALU
DMA
RAM
DMA
Controller
16
16
16
16
PORTA
PORTB
PORTC
Remappable
Pins
VDDCORE/VCAP
PMP/
EPSP
RTCC
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
Compar-
ator1, 2
DAC1
present on each device.
DD, VSS
V
ECAN1
SPI1, 2
MCLR
Timers
1-5
IC1, 2, 7, 8
UART1, 2
CNx
ADC1
I2C1
OC/
PWM1-4
QEI1, 2
PWM
2 Ch
PWM
6 Ch
DS70291B-page 14 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN8
CLKI
CLKO
OSC1
OSC2
SOSCI
SOSCO
CN0-CN30 I ST Change notification inputs.
IC1-IC2
IC7-IC8
OCFA
OC1-OC4
INT0
INT1
INT2
RA0-RA4
RA7-RA10
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC0-RC9 I/O ST PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
U1CTS
U1RTS
U1RX
U1TX
2CTS
U
U2RTS
U2RX
U2TX
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
2
SS
SCL1
SDA1
ASCL1
ASDA1
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Pin
Type
I Analog Analog input channels.
I
O
I
I/O
I
O
I
I
I
O
I
I
I
I/O
I/O
I
I
I
I
I
I
O
I
O
I
O
I
O
I/O
I
O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST/CMOS—External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
Can be software programmed for internal weak pull-ups on all inputs.
STSTCapture inputs 1/2
Capture inputs 7/8.
ST—Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
ST
ST
ST
STSTPORTA is a bidirectional I/O port.
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
PORTA is a bidirectional I/O port.
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
UART1 clear to send.
—
UART1 ready to send.
UART1 receive.
—
UART1 transmit.
UART2 clear to send.
—
UART2 ready to send.
UART2 receive.
—
UART2 transmit.
Synchronous serial clock input/output for SPI1.
SPI1 data in.
—
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
—
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
Description
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 15
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
TMS
TCK
TDI
TDO
INDX1
QEA1
QEB1
UPDN1
INDX2
QEA2
QEB2
UPDN2
C1RX
C1TX
RTCC O — Real-Time Clock Alarm Output.
REF O ANA Comparator Voltage Reference Output.
CV
C1IN-
C1IN+
C1OUT
C2INC2IN+
C2OUT
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
DAC1RN
DAC1RP
DAC1RM
DAC2RN
DAC2RP
DAC2RM
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Pin
Type
I
I
I
O
I
I
I
O
I
I
I
O
I
O
I
I
O
I
I
O
I/O
I/O
O
O
O
I/O
O
O
O
O
O
O
O
O
Buffer
Type
ST
ST
ST
ST
ST
ST
CMOS
ST
ST
ST
CMOS
ST—ECAN1 bus receive pin.
ANA
ANA
ANA
ANA
TTL/ST
TTL/ST
TTL/ST
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
—
JTAG test data output pin.
Quadrature Encoder Index1 Pulse input.
Quadrature Encoder Phase A input in QEI1 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI1 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
Quadrature Encoder Index2 Pulse input.
Quadrature Encoder Phase A input in QEI2 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI2 mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
ECAN1 bus transmit pin.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
—
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
—
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output
(Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output
(Master modes).
—
Parallel Master Port Address (Demultiplexed Master Modes).
—
Parallel Master Port Byte Enable Strobe.
—
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/Data
(Multiplexed Master modes).
—
Parallel Master Port Read Strobe.
—
Parallel Master Port Write Strobe.
—
DAC1 Negative Output.
—
DAC1 Positive Output.
—
DAC1 Output indicating middle point value (typically 1.65V).
—
DAC2 Negative Output.
—
DAC2 Positive Output.
—
DAC2 Output indicating middle point value (typically 1.65V).
Description
DS70291B-page 16 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
Description
FLTA1
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
FLTA2
PWM2L1
PWM2H1
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
MCLR
I
O
O
O
O
O
O
I
O
O
I/O
I/O
I/O
ST
—
—
—
—
—
—
ST
—
—
ST
I
ST
ST
I
ST
ST
I
ST
PWM1 Fault A input.
PWM1 Low output 1
PWM1 High output 1
PWM1 Low output 2
PWM1 High output 2
PWM1 Low output 3
PWM1 High output 3
PWM2 Fault A input.
PWM2 Low output 1
PWM2 High output 1
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD P P Positive supply for analog modules.
SS P P Ground reference for analog modules.
AV
VDD P — Positive supply for peripheral logic and I/O pins.
VDDCORE P — CPU logic filter capacitor connection.
Vss P — Ground reference for logic and I/O pins.
REF+ I Analog Analog voltage reference (high) input.
V
VREF- I Analog Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 17
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
NOTES:
DS70291B-page 18 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.0 CPU
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, “Section 2. CPU”
(DS70204), which is available from the
Microchip website (www.microchip.com).
2.1 Overview
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 devices have sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 2-1, and
the programmer’s model for the dsPIC33FJ32MC302/
304, dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 is shown in Figure 2-2.
2.2 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
2.3 DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal realtime performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 19
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.4 Special MCU Features
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 supports 16/16
and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 2-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
23
Address Latch
Controller
23
Interrupt
23
8
PCH PCL
PCU
Program Counter
Stac k
Control
Logic
Control
16
Loop
Logic
Y Data Bus
X Data Bus
16
Data Latch
X RAM
Address
Latch
Address Generator Units
16
16
16
Data Latch
Y RAM
Address
Latch
16
DMA
RAM
16
DMA
Controller
Program Memory
Data Latch
Address Bus
24
Instruction
Decode &
Control
Control Signals
to Various Blocks
ROM Latch
Instruction Reg
DSP Engine
Divide Support
EA MUX
16
16
Literal Data
16 x 16
W Register Array
16-bit ALU
16
16
16
To Peripheral Modules
DS70291B-page 20 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 2-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 PROGRAMMER’S MODEL
D0D15
DSP Operand
Registers
DSP Address
Registers
W0/WREG
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Working Registers
PUSH.S Shadow
DO Shadow
Legend
DSP
Accumulators
PC22
7
TBLPAG
7
22
22
PSVPAG
AD39 AD0AD31
ACCA
ACCB
0
Data Table Page Address
0
SPLIM Stack Pointer Limit Register
Program Space Visibility Page Address
15
RCOUNT
15
DCOUNT
DOSTART
DOEND
PC0
AD15
Program Counter
0
0
REPEAT Loop Counter
0
DO Loop Counter
0
DO Loop Start Address
DO Loop End Address
15
CORCON
OA OB SA SB
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 21
OAB SAB
SRH
DA DC
IPL2 IPL1
RA
IPL0 OV
SRL
0
Core Configuration Register
N
C
Z
STATUS Register
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.5 CPU Control Registers
REGISTER 2-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA
(1)
bit 15 bit 8
SB
(1)
OAB SAB DA DC
R/W-0
(3)
IPL<2:0>
R/W-0
(3)
(2)
R/W-0
(3)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit 7 bit 0
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit
(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
DS70291B-page 22 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
bit
(2)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 23
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)
DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(2)
PSV RND IF
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70291B-page 24 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 2-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 25
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.6 Arithmetic Logic Unit (ALU)
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are two’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
and Digit Borrow bits, respectively, for
Borrow
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and
support hardware for 16-bit-divisor division.
2.6.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
2.6.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
2.7 DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 2-3.
DS70291B-page 26 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 2-1: DSP INSTRUCTIONS SUMMARY
Instruction Algebraic Operation ACC Write Back
CLR A = 0
ED A = (x – y)2 No
EDAC A = A + (x – y)2 No
MAC A = A + (x • y) Yes
MAC A = A + x2 No
MOVSAC No change in A Yes
MPY A = x • y No
MPY A = x 2 No
MPY.N A = – x • y No
MSC A = A – x • y Yes
FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM
40
Carry/Borrow Out
Carry/Borrow In
40-bit Accumulator A
40-bit Accumulator B
Saturate
Adder
Negate
40
Round
Logic
Yes
S
a
t
16
u
r
a
t
e
40
16
40
Barrel
Shifter
32
32
40
16
X Data Bus
16
Zero Backfill
40
Sign-Extend
Y Data Bus
33
17-bit
Multiplier/Scaler
16
To/From W Array
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 27
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.7.1 MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed two’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit two’s complement integer is -2
N-1
to 2
N-1
– 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is 2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 2
1-N
). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10
-10
.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified registers in the W array.
2.7.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
2.7.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/B
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow
is active-low and the other input is complemented.
orrow input is
input
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described previously and the SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
Section 6.0 “Interrupt Controller”). This allows the
user application to take immediate action, for example,
to correct system gain.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and is saturated (if saturation is enabled).
When saturation is not enabled, SA and SB default to
bit 39 overflow and thus indicate that a catastrophic
overflow has occurred. If the COVTE bit in the
INTCON1 register is set, the SA and SB bits generate
an arithmetic warning trap when saturation is disabled.
DS70291B-page 28 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
The Overflow and Saturation Status bits can
optionally be viewed in the STATUS Register (SR) as
the logical OR of OA and OB (in bit OAB) and the
logical OR of SA and SB (in bit SAB). Programmers
can check one bit in the STATUS register to
determine if either accumulator has overflowed, or
one bit to determine if either accumulator has
saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31 value
(0x8000000000) into the target accumulator. The
SA or SB bit is set and remains set until cleared by
the user application. This condition is referred to as
‘super saturation’ and provides protection against
erroneous data or unexpected algorithm problems
(such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
2.7.3 ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
2.7.3.1 Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a succession of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (bit 16 of the accumulator) of ACCxH is
examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 2.7.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator writeback operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 29
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
2.7.3.2 Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2.7.4 BARREL SHIFTER
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
DS70291B-page 30 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.0 MEMORY ORGANIZATION
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”,
“Section 4. Program Memory” (DS70203),
which is available from the Microchip
website (www.microchip.com).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
3.1 Program Address Space
The program address memory space of the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 3.6
“Interfacing Program and Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory map for the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 devices is shown in
Figure 3-1.
FIGURE 3-1: PROGRAM MEMORY MAP FOR dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, AND dsPIC33FJ128MCX02/X04 DEVICES
dsPIC33FJ32MC302/304
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(11264 instructions)
User Memory Space
Unimplemented
(Read ‘0’s)
dsPIC33FJ64MCX02/X04
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(22016 instructions)
Unimplemented
(Read ‘0’s)
dsPIC33FJ128MCX02/X04
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44032 instructions)
Unimplemented
(Read ‘0’s)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FE
0x005800
0x00ABFE
0x00AC00
0x0157FE
0x015800
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
Reserved
Configuration Memory Space
Note: Memory areas are not shown to scale.
DEVID (2)
Reserved
Reserved
Device Configuration
Registers
Reserved
DEVID (2)
Reserved
Reserved
Device Configuration
Registers
Reserved
DEVID (2)
Reserved
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 31
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 3-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the device interrupt sources to be
handled by separate Interrupt Service Routines (ISRs).
A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Tabl e”.
3.1.2 INTERRUPT AND TRAP VECTORS
All dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 devices reserve
the addresses between 0x00000 and 0x000200 for
FIGURE 3-2: PROGRAM MEMORY ORGANIZATION
msw
Address (lsw Address)
0x000001
0x000003
0x000005
0x000007
most significant word
23
00000000
00000000
00000000
00000000
least significant word
PC Address
0816
0x000000
0x000002
0x000004
0x000006
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70291B-page 32 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.2 Data Address Space
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU has a
separate 16-bit-wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in Figure 3-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 3.6.3 “Reading Data From
Program Memory Using Program Space Visibility”).
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices implement up
to 16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all-zero word or byte is
returned.
3.2.1 DATA SPACE WIDTH
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
3.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC
devices and improve data space memory usage
efficiency, the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 instruction set supports
both word and byte operations. As a consequence of
byte accessibility, all effective address calculations are
internally scaled to step through word-aligned memory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] results in a
value of Ws + 1 for byte operations and Ws + 2 for word
operations.
A data byte read, reads the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
®
MCU
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
3.2.3 SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note: The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
3.2.4 NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 33
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ32MC302/304 DEVICES WITH 4 KB RAM
2 Kbyte
SFR Space
4 Kbyte
SRAM Space
MSb
Address
0x0000
0x07FF
0x0801
0x0FFF
0x1001
0x13FF
0x1401
0x17FF
0x1801
0x8001 0x8000
16 bits
LSbMSb
SFR Space
X Data RAM (X)
Y Data RAM (Y)
DMA RAM
LSb
Address
0x0000
0x07FE
0x0800
0x0FFE
0x1000
0x13FE
0x1400
0x17FE
0x1800
6 Kbyte
Near
Data
Space
Optionally
Mapped
into Program
Memory
0xFFFF
X Data
Unimplemented (X)
0xFFFE
DS70291B-page 34 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 3-4: DATA MEMORY MAP FOR dsPIC33FJ128MC202/204 AND dsPIC33FJ64MC202/
204 DEVICES WITH 8 KB RAM
2 Kbyte
SFR Space
8 Kbyte
SRAM Space
MSb
Address
0x0001
0x07FF
0x0801
0x17FF
0x1801
0x1FFF
0x2001
0x27FF 0x27FE
0x8001
16 bits
SFR Space
X Data RAM (X)
Y Data RAM (Y)
DMA RAM
LSbMSb
LSb
Address
0x0000
0x07FE
0x0800
0x17FE
0x1800
0x1FFE
0x2000
0x28000x2801
0x8000
8 Kbyte
Near
Data
Space
Optionally
Mapped
into Program
Memory
0xFFFF
X Data
Unimplemented (X)
0xFFFE
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 35
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 3-5: DATA MEMORY MAP FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/
804 DEVICES WITH 16 KB RAM
2 Kbyte
SFR Space
16 Kbyte
SRAM Space
MSb
Address
0x0001
0x07FF
0x0801
0x1FFF
0x27FF
0x2801
0x3FFF
0x4001
0x47FF 0x47FE
0x8001
16 bits
SFR Space
X Data RAM (X)
Y Data RAM (Y)
DMA RAM
LSbMSb
LSb
Address
0x0000
0x07FE
0x0800
0x1FFE
0x27FE
0x2800
0x3FFE
0x4000
0x48000x4801
0x8000
8 Kbyte
Near
Data
Space
Optionally
Mapped
into Program
Memory
0xFFFF
X Data
Unimplemented (X)
0xFFFE
DS70291B-page 36 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.2.5 X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
3.2.6 DMA RAM
Every dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 device contains
up to 2 Kbytes of dual ported DMA RAM located at
the end of Y data space. Memory locations in the
DMA RAM space are accessible simultaneously by
the CPU and the DMA controller module. DMA RAM
is utilized by the DMA controller to store data to be
transferred to various peripherals using DMA, as well
as data transferred from various peripherals using
DMA. The DMA RAM can be accessed by the DMA
controller without having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
Note: DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 37
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
Resets
xxxx
DOSTARTH<5:0> 00xx
DOENDH 00xx
0000
0000
SATA SATB SATDW ACCSAT IPL3 PSV RND IF
BWM<3:0> YWM<3:0> XWM<3:0> 0000
— —
— — — — — — — — — —
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — — — — — — — — —
SFR
Addr
SFR Name
WREG0 0000 Working Register 0
WREG1 0002 Working Register 1
WREG2 0004 Working Register 2
WREG3 0006 Working Register 3
WREG4 0008 Working Register 4
WREG5 000A Working Register 5
WREG6 000C Working Register 6
WREG7 000E Working Register 7
WREG8 0010 Working Register 8
WREG9 0012 Working Register 9
WREG10 0014 Working Register 10
WREG11 0016 Working Register 11
WREG12 0018 Working Register 12
WREG13 001A Working Register 13
WREG14 001C Working Register 14
WREG15 001E Working Register 15
SPLIM 0020 Stack Pointer Limit Register
ACCAL 0022 ACCAL
ACCAH 0024 ACCAH
ACCAU 0026 ACCA<39> ACCAU
ACCBL 0028 ACCBL
ACCBH 002A ACCBH
ACCBU 002C ACCB<39> ACCBU
PCL 002E Program Counter Low Word Register
PCH 0030 — — — — — — — — Program Counter High Byte Register
TABLE 3-1: CPU CORE REGISTERS MAP
TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register
0038 DCOUNT<15:0> xxxx
003A DOSTARTL<15:1> 0xxxx
PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register
RCOUNT 0036 Repeat Loop Counter Register
DCOUNT
DOSTARTL
003C
DOSTARTH
0040
003E DOENDL<15:1> 0xxxx
DOENDL
DOENDH
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CORCON 0044 — — — US EDT DL<2:0>
MODCON 0046 XMODEN YMODEN
DS70291B-page 38 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
xxxx
Register
All
0000
Resets
0000
CN16IE
— — — —
0000
0000
CN16PUE
— — — —
All
0000
0000
0000
Resets
0000
CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
CN24IE CN23IE CN22IE CN21IE
CN24PUE CN23PUE CN22PUE CN21PUE
— — —
— —
— — —
— —
CN27IE
CN27PUE
—
—
— Disable Interrupts Counter
CN30IE CN29IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CN30PUE CN29PUE
CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
—
TABLE 3-1: CPU CORE REGISTERS MAP (CONTINUED)
SFR
Addr
SFR Name
XMODSRT 0048 XS<15:1> 0xxxx
XMODEND 004A XE<15:1> 1xxxx
YMODSRT 004C YS<15:1> 0xxxx
YMODEND 004E YE<15:1> 1xxxx
XBREV 0050 BREN XB<14:0> xxxx
00C2
CNEN2
—
0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
006A
CNPU1
CNPU2
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
SFR
TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
0060 CN15IE CN14IE CN13IE CN12IE CN11IE
Addr
SFR
TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302
Name
CNEN1
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DISICNT 0052 —
—
—
0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE
Addr
Name
CNEN1
00C2
CNEN2
006A
CNPU1
CNPU2
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 39
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
— 0000
— INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
SPI2IF SPI2EIF 0000
(1)
C1RXIF
(1)
DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000
(1)
— INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
SPI2IE SPI2EIE 0000
(1)
C1RXIE
(1)
DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000
(1)
— SPI2IP<2:0> — SPI2EIP<2:0> 4444
(1)
— DMA7IP<2:0> — DMA6IP<2:0> 0444
(1)
— — — — — — — — 4400
(2)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
— — — — — — — — — — — INT2EP INT1EP INT0EP 0000
— DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
— C1RXIP<2:0>
— — QEI1IF PWM1IF — — — — — — — — — 0000
— — QEI2IF FLTA2IF PWM2IF — —C1TXIF
(2)
DAC1RIF
(2)
— DMA4IF PMPIF — — — — — — — — DMA3IF C1IF
— DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
— —QEI1IEPWM1IE— — — — — — — — — 0000
(1)
— — QEI2IE FLTA2IE PWM2IE — —C1TXIE
(2)
DAC1RIE
(2)
— DMA4IE PMPIE — — — — — — — — DMA3IE C1IE
— T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0>— INT0IP<2:0> 4444
— T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0>— DMA0IP<2:0> 4444
— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
— — — — — DMA1IP<2:0> —AD1IP<2:0>— U1TXIP<2:0> 0444
— CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
—IC8IP<2:0>—IC7IP<2:0> — — — — — INT1IP<2:0> 4404
— T4IP<2:0> —OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
— U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
— C1IP<2:0>
— — — — — — — — — — — — — DMA3IP<2:0> 0004
— — — — — DMA4IP<2:0> — PMPIP<2:0> — — — — 0440
— — — — — QEI1IP<2:0> — PWM1IP<2:0> — — — — 0440
— FLTA1IP<2:0> —RTCIP<2:0> — DMA5IP<2:0> — — — — 4440
— CRCIP<2:0> — U2EIP<2:0> —U1EIP<2:0>— — — — 4440
— — — — — C1TXIP<2:0>
—DAC1RIP<2:0>
(2)
— QEI2IP<2:0> — FLTA2IP<2:0> — PWM2IP<2:0> — — — — 4440
— DAC1LIP<2:0>
— — — — ILR<3:0>> — VECNUM<6:0> 4444
2: Interrupts disabled on devices without DAC.
SFR
Name
INTCON2 0082 ALTIVT DISI
IFS0 0084
TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF
IFS4 008C DAC1LIF
IFS2 0088
IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE
IEC0 0094
IFS3 008A FLTA1IF RTCIF DMA5IF
IEC4 009C DAC1LIE
IPC0 00A4
IPC1 00A6
IPC2 00A8
IPC3 00AA
IPC4 00AC
IPC5 00AE
IPC6 00B0
IPC7 00B2
IEC3 009A FLTA1IE RTCIE DMA5IE
IEC2 0098
IPC8 00B4
IPC14 00C0
IPC15 00C2
IPC16 00C4
IPC17 00C6
IPC19 00CA
IPC9 00B6
IPC11 00BA
INTTREG 00E0
IPC18 00C8
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Interrupts disabled on devices without ECAN™ modules.
DS70291B-page 40 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
All
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
xxxx
FFFF
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
Resets
—
TSYNC TCS
—
TGATE TCKPS<1:0>
—
—
TCS
TCS
—
— —
TGATE TCKPS<1:0> T32
TGATE TCKPS<1:0>
0000
—
—
TCS
TCS
—
— —
TGATE TCKPS<1:0> T32
TGATE TCKPS<1:0>
Resets
0000
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
— — — — — —
TSIDL
—
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — — — — —
— — — — — —
TSIDL
TSIDL
—
—
— — — — — —
— — — — — —
TSIDL
TSIDL
—
—
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — — — —
— — — — —
— — — — —
— — — — —
ICSIDL
ICSIDL
ICSIDL
ICSIDL
— —
— —
— —
— —
SFR
Addr
SFR
Name
TABLE 3-5: TIMER REGISTER MAP
TMR1 0100 Timer1 Register
PR1 0102 Period Register 1
T1CON 0104 TON
TMR2 0106 Timer2 Register
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)
TMR3 010A Timer3 Register
PR2 010C Period Register 2
PR3 010E Period Register 3
T2CON 0110 TON
T3CON 0112 TON
TMR4 0114 Timer4 Register
TMR5HLD 0116 Timer5 Holding Register (for 32-bit timer operations only)
TMR5 0118 Timer5 Register
PR4 011A Period Register 4
PR5 011C Period Register 5
T4CON 011E TON
T5CON 0120 TON
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Addr
SFR
Name
IC1BUF 0140 Input 1 Capture Register
IC1CON 0142
IC2BUF 0144 Input 2 Capture Register
IC2CON 0146
IC7BUF 0158 Input 7 Capture Register
IC7CON 015A
IC8BUF 015C Input 8Capture Register
IC8CON 015E
TABLE 3-6: INPUT CAPTURE REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 41
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
Resets
0000
0000
0000
0000
0000
00FF
0000
0000
0000
0000
FF00
0000
0000
State
Reset
0000
OCFLT OCTSEL OCM<2:0>
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
— — — — — — — —
SFR
TABLE 3-7: OUTPUT COMPARE REGISTER MAP
OCSIDL
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr
SFR Name
— —
OC1RS 0180 Output Compare 1 Secondary Register
OC1R 0182 Output Compare 1 Register
OC1CON 0184
OCSIDL
— —
OC2RS 0186 Output Compare 2 Secondary Register
OC2R 0188 Output Compare 2 Register
OC2CON 018A
OCSIDL
— —
OC3RS 018C Output Compare 3 Secondary Register
OC3R 018E Output Compare 3 Register
OC3CON 0190
OCSIDL
—PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>
— —
OC4RS 0192 Output Compare 4 Secondary Register
OC4R 0194 Output Compare 4 Register
OC4CON 0196
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
SFR Name
P1TCON 01C0 PTEN
TABLE 3-8: 6-OUTPUT PWM1 REGISTER MAP
P1TMR 01C2 PTDIR PWM Timer Count Value Register
P1TPER 01C4 — PWM Time Base Period Register
01C8 — — — — — PMOD3 PMOD2 PMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L
01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS
P1SECMP 01C6 SEVTDIR PWM Special Event Compare Register
PWM1CON1
PWM1CON2
P1DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0>
P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I
P1FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN2 FAEN1 FAEN0
P1OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
P1DC1 01D6 PWM Duty Cycle #1 Register
P1DC2 01D8 PWM Duty Cycle #2 Register
P1DC3 01DA PWM Duty Cycle #3 Register
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
DS70291B-page 42 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000
—PTSIDL— — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000
— PWM Time Base Period Register 0000
— — — — — — —PMOD1— — — PEN1H — — — PEN1L 00FF
— — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000
— — — — — — — — — — — — — —DTS1ADTS1I0000
— — — — — — FAOV1H FAOV1L FLTAM — — — — — —FAEN10000
— — — — — — POVD1H POVD1L — — — — — — POUT1H POUT1L FF00
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TABLE 3-9: 2-OUTPUT PWM2 REGISTER MAP
P2TCON 05C0 PTEN
P2TMR 05C2 PTDIR PWM Timer Count Value Register 0000
P2TPER 05C4
P2SECMP 05C6 SEVTDIR PWM Special Event Compare Register 0000
PWM2CON1 05C8
PWM2CON2 05CA
P2DTCON1 05CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0> 0000
P2DTCON2 05CE
P2OVDCON 05D4
P2FLTACON 05D0
P2DC1 05D6 PWM Duty Cycle #1 Register 0000
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
TABLE 3-10: QEI1 REGISTER MAP
—
— — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
SFR
Name
POS1CNT 01E4 Position Counter<15:0> 0000
MAX1CNT 01E6 Maximum Count<15:0> FFFF
QEI1CON 01E0 CNTERR
DFLT1CON 01E2
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
TABLE 3-11: QEI2 REGISTER MAP
QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000
—
— — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
SFR
Name
POS2CNT 01F4 Position Counter<15:0> 0000
MAX2CNT 01F6 Maximum Count<15:0> FFFF
QEI2CON 01F0 CNTERR
DFLT2CON 01F2
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 43
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
All
0000
0110
xxxx
0000
0000
00FF
0000
1000
0000
0000
Resets
0000
Resets
0000
All
0000
0110
xxxx
0000
Resets
0000
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
SFR Name
I2C1RCV 0200 — — — — — — — — Receive Register
I2C1TRN 0202 — — — — — — — —Transmit Register
I2C1BRG 0204 — — — — — — — Baud Rate Generator Register
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF
I2C1ADD 020A — — — — — — Address Register
I2C1MSK 020C — — — — — — Address Mask Register
TABLE 3-12: I2C REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
SFR Name
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
U1TXREG 0224 — — — — — — — UTX8 UART Transmit Register
U1RXREG 0226 — — — — — — — URX8 UART Received Register
U1BRG 0228 Baud Rate Generator Prescaler
TABLE 3-13: UART1 REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
SFR Name
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
U2TXREG 0234 — — — — — — — UTX8 UART Transmit Register
U2RXREG 0236 — — — — — — — URX8 UART Receive Register
U2BRG 0238 Baud Rate Generator Prescaler
TABLE 3-14: UART2 REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70291B-page 44 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
0000
0000
0000
Resets
0000
All
0000
0000
0000
Resets
0000
All
Resets
0000
DMABL<2:0>
— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000
— ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
— — SAMC<4:0> ADCS<7:0> 0000
— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000
— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
— — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
— — — — — — — — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
Addr
SFR Name
SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — —FRMDLY—
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register
TABLE 3-15: SPI1 REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
TABLE 3-16: SPI2 REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr
SFR Name
SPI2STAT 0260 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>
SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — —FRMDLY—
SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-17: ADC1 REGISTER MAP FOR dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC1BUF0 0300 ADC Data Buffer 0 xxxx
AD1CON3 0324 ADRC
AD1CON2 0322 VCFG<2:0>
AD1CON1 0320 ADON
AD1CHS0 0328 CH0NB
AD1CHS123 0326
— — — — — — — — — — — — —
AD1PCFGL 032C
AD1CSSL 0330
AD1CON4 0332
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 45
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
0000
DMABL<2:0>
All
0000
0000
0000
0000
Resets
0000
— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000
— DACSIDL AMPON — — —FORM—DACFDIV<6:0>
— ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
— — SAMC<4:0> ADCS<7:0> 0000
— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000
— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
— — — — — — — PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
— — — — — — — CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
— — — — — — — — — — — — —
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-18: ADC1 REGISTER MAP FOR dsPIC33FJ64MC204/804, dsPIC33FJ128MC204/804 AND dsPIC33FJ32MC304
ADC1BUF0 0300 ADC Data Buffer 0 xxxx
AD1CON2 0322 VCFG<2:0>
AD1CON1 0320 ADON
AD1CHS0 0328 CH0NB
AD1CON3 0324 ADRC
AD1PCFGL 032C
AD1CHS123 0326
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
AD1CSSL 0330
AD1CON4 0332
TABLE 3-19: DAC1 REGISTER MAP FOR dsPIC33FJ128MC804 AND dsPIC33FJ64MC804
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR
SFR Name
—LMVOEN— — LITYPE LFULL LEMPTY ROEN —RMVOEN— — RITYPE RFULL REMPTY
Addr
DAC1CON 03F0 DACEN
DAC1DFLT 03F4 DAC1DFLT<15:0>
DAC1STAT 03F2 LOEN
DAC1LDAT 03F8 DAC1LDAT<15:0>
DAC1RDAT 03F6 DAC1RDAT<15:0>
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70291B-page 46 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
— — — — —AMODE<1:0> — —MODE<1:0>0000
— — — — — — — — IRQSEL<6:0> 0000
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-20: DMA REGISTER MAP
DMA0CON 0380 CHEN SIZE DIR HALF NULLW
DMA0REQ 0382 FORCE
DMA0STA 0384 STA<15:0> 0000
DMA0STB 0386 STB<15:0> 0000
DMA0PAD 0388 PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA0CNT 038A
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA1CON 038C CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA1STA 0390 STA<15:0> 0000
DMA1REQ 038E FORCE
DMA1STB 0392 STB<15:0> 0000
DMA1PAD 0394 PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA1CNT 0396
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA2CON 0398 CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA2STA 039C STA<15:0> 0000
DMA2REQ 039A FORCE
DMA2STB 039E STB<15:0> 0000
DMA2PAD 03A0 PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA2CNT 03A2
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA3CON 03A4 CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA3STA 03A8 STA<15:0> 0000
DMA3REQ 03A6 FORCE
DMA3STB 03AA STB<15:0> 0000
DMA3PAD 03AC PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA3CNT 03AE
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA4CON 03B0 CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA4REQ 03B2 FORCE
DMA4STA 03B4 STA<15:0> 0000
DMA4STB 03B6 STB<15:0> 0000
DMA4PAD 03B8 PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA4CNT 03BA
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA5CON 03BC CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA5STA 03C0 STA<15:0> 0000
DMA5REQ 03BE FORCE
DMA5STB 03C2 STB<15:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 47
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
— — — — —AMODE<1:0> — —MODE<1:0>0000
— — — — — — — — IRQSEL<6:0> 0000
— — — — — — CNT<9:0> 0000
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-20: DMA REGISTER MAP (CONTINUED)
DMA5PAD 03C4 PAD<15:0> 0000
DMA5CNT 03C6
DMA6CON 03C8 CHEN SIZE DIR HALF NULLW
DMA6STA 03CC STA<15:0> 0000
DMA6REQ 03CA FORCE
DMA6STB 03CE STB<15:0> 0000
DMA6PAD 03D0 PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA6CNT 03D2
— — — — —AMODE<1:0> — —MODE<1:0>0000
DMA7CON 03D4 CHEN SIZE DIR HALF NULLW
— — — — — — — — IRQSEL<6:0> 0000
DMA7STA 03D8 STA<15:0> 0000
DMA7REQ 03D6 FORCE
DMA7STB 03DA STB<15:0> 0000
DMA7PAD 03DC PAD<15:0> 0000
— — — — — — CNT<9:0> 0000
DMA7CNT 03DE
DMACS0 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000
— — — — LSTCH<3:0> PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000
DMACS1 03E2
DSADR 03E4 DSADR<15:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70291B-page 48 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
0000
FSA<4:0>
FFFF
All
Resets
0000
0000
0000
0000
REQOP<2:0> OPMODE<2:0> — CANCAP — —WIN0480
S
— — CSIDL ABAT CANCK
— — — — — — — — — — — DNCNT<4:0> 0000
— — — FILHIT<4:0> — ICODE<6:0> 0000
See definition when WIN = x
— — — — — — — —
— — FBP<5:0> — — FNRB<5:0> 0000
— — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000
— — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000
— — — — — — — — SJW<1:0> BRP<5:0> 0000
—WAKFIL— — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000
FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0
041E
0400-
TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0>
TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0>
TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0>
TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0>
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-21: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804)
C1CTRL2 0402
C1CTRL1 0400
C1VEC 0404
C1INTF 040A
C1INTE 040C
C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000
C1CFG1 0410
C1FEN1 0414
C1FCTRL 0406 DMABS<2:0>
C1FIFO 0408
C1CFG2 0412
C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000
C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-22: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804)
C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000
C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C1TR23CON 0432
C1TR45CON 0434
C1TR67CON 0436
C1RXD 0440 Received Data Word xxxx
C1TXD 0442 Transmit Data Word xxxx
C1TR01CON 0430
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 49
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
—MIDE—EID<17:16>xxxx
—MIDE—EID<17:16>xxxx
—MIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
See definition when WIN = x
041E
0400-
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804)
C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000
C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000
C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000
C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000
C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx
C1RXM1SID 0434 SID<10:3> SID<2:0>
C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx
C1RXM2SID 0438 SID<10:3> SID<2:0>
C1RXM2EID 043A EID<15:8> EID<7:0> xxxx
C1RXF0SID 0440 SID<10:3> SID<2:0>
C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx
C1RXF1SID 0444 SID<10:3> SID<2:0>
C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx
C1RXF2SID 0448 SID<10:3> SID<2:0>
C1RXF2EID 044A EID<15:8> EID<7:0> xxxx
C1RXF3SID 044C SID<10:3> SID<2:0>
C1RXF3EID 044E EID<15:8> EID<7:0> xxxx
C1RXF4SID 0450 SID<10:3> SID<2:0>
C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx
C1RXF5SID 0454 SID<10:3> SID<2:0>
C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx
C1RXF6SID 0458 SID<10:3> SID<2:0>
C1RXF6EID 045A EID<15:8> EID<7:0> xxxx
C1RXF7SID 045C SID<10:3> SID<2:0>
C1RXF7EID 045E EID<15:8> EID<7:0> xxxx
C1RXF8SID 0460 SID<10:3> SID<2:0>
C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx
C1RXF9SID 0464 SID<10:3> SID<2:0>
C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx
C1RXF10SID 0468 SID<10:3> SID<2:0>
C1RXF10EID 046A EID<15:8> EID<7:0> xxxx
C1RXM0SID 0430 SID<10:3> SID<2:0>
C1RXF11SID 046C SID<10:3> SID<2:0>
DS70291B-page 50 Preliminary © 2008 Microchip Technology Inc.
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
Resets
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
—EXIDE—EID<17:16>xxxx
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C1RXF11EID 046E EID<15:8> EID<7:0> xxxx
TABLE 3-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) (CONTINUED)
C1RXF12SID 0470 SID<10:3> SID<2:0>
C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx
C1RXF13SID 0474 SID<10:3> SID<2:0>
C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx
C1RXF14SID 0478 SID<10:3> SID<2:0>
C1RXF14EID 047A EID<15:8> EID<7:0> xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
C1RXF15SID 047C SID<10:3> SID<2:0>
C1RXF15EID 047E EID<15:8> EID<7:0> xxxx
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 51
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
1F00
001F
1F1F
1F1F
1F1F
1F1F
001F
001F
001F
1F1F
001F
1F1F
001F
1F1F
1F1F
1F1F
001F
1F1F
001F
Resets
001F
— — — — — — — — — — —INT2R<4:0>
— — —T3CKR<4:0> — — —T2CKR<4:0>
— — —T5CKR<4:0> — — —T4CKR<4:0>
— — — IC2R<4:0> — — — IC1R<4:0>
— — — IC8R<4:0> — — — IC7R<4:0>
— — — — — — — — — — —OCFAR<4:0>
— — — — — — — — — — —FLTA1R<4:0>
— — — — — — — — — — —FLTA2R<4:0>
— — — QEB1R<4:0> — — — QEA1R<4:0>
— — — — — — — — — — — INDX1R<4:0>
— — — QEB2R<4:0> — — — QEA2R<4:0>
— — — — — — — — — — — INDX2R<4:0>
— — — U1CTSR<4:0> — — —U1RXR<4:0>
— — — U2CTSR<4:0> — — —U2RXR<4:0>
— — —SCK1R<4:0> — — —SDI1R<4:0>
— — — — — — — — — — —SS1R<4:0>
— — —SCK2R<4:0> — — —SDI2R<4:0>
— — — — — — — — — — —SS2R<4:0>
0680 — — — INT1R<4:0> — — — — — — — —
0682
0686
0688
0694
0696
068E
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RPINR0
RPINR1
RPINR3
RPINR4
TABLE 3-24: PERIPHERAL PIN SELECT INPUT REGISTER MAP
RPINR7
0698
069A
069E
06A0
06A2
06A4
06A6
069C
RPINR10
RPINR11
RPINR12
RPINR13
RPINR14
RPINR15
RPINR16
RPINR17
06A8
06AA
RPINR18
RPINR19
RPINR20
RPINR21
06B4 — — — — — — — — — — —C1RXR<4:0>
06AE
06AC
(1)
RPINR22
RPINR23
RPINR26
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register is present for dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804 devices only.
DS70291B-page 52 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
0000
0000
0000
0000
0000
0000
0000
Resets
0000
All
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Resets
0000
— — —RP3R<4:0>— — —RP2R<4:0>
— — —RP5R<4:0>— — —RP4R<4:0>
— — —RP7R<4:0>— — —RP6R<4:0>
— — —RP9R<4:0>— — —RP8R<4:0>
— — —RP11R<4:0>— — —RP10R<4:0>
— — —RP13R<4:0>— — —RP12R<4:0>
dsPIC33FJ32MC302
TABLE 3-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND
— — —RP15R<4:0>— — —RP14R<4:0>
dsPIC33FJ32MC304
06C2
06C4
06C6
06C0 — — — RP1R<4:0> — — — RP0R<4:0>
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RPOR0
RPOR1
06C8
06CA
06CE
06CC
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — —RP3R<4:0>— — —RP2R<4:0>
— — —RP5R<4:0>— — —RP4R<4:0>
— — —RP7R<4:0>— — —RP6R<4:0>
— — —RP9R<4:0>— — —RP8R<4:0>
— — —RP11R<4:0>— — —RP10R<4:0>
06C2
06C4
06C6
06C0 — — — RP1R<4:0> — — — RP0R<4:0>
RPOR0
RPOR1
06C8
06CA
RPOR2
RPOR3
RPOR4
RPOR5
— — —RP13R<4:0>— — —RP12R<4:0>
— — —RP15R<4:0>— — —RP14R<4:0>
— — —RP17R<4:0>— — — RP16R<4:0>
— — —RP19R<4:0>— — — RP18R<4:0>
— — —RP21R<4:0>— — —RP20R<4:0>
— — —RP23R<4:0>— — —RP22R<4:0>
— — —RP25R<4:0>— — —RP24R<4:0>
06D0
06D2
06D4
06D6
06CE
06CC
RPOR6
RPOR7
RPOR8
RPOR9
06D8
RPOR10
RPOR11
RPOR12
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 53
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
0000
0000
0000
0000
0000
0000
0000
0000
Resets
ADDR<13:0>
0000
PTEN<1:0>
OB3E OB2E OB1E OB0E
— —
All
0000
0000
0000
0000
0000
0000
0000
0000
Resets
ADDR<13:0>
0000
OB3E OB2E OB1E OB0E
— —
PTEN<10:0>
TABLE 3-27: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND
dsPIC33FJ32MC302
IB3F IB2F IB1F IB0F OBE OBUF
— —
CS1
ADDR15
0604
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0>
PMADDR
PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1)
PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3)
PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1)
IBF IBOV
dsPIC33FJ32MC304
PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3)
PMAEN 060C —PTEN14— — — — — — — — — — — —
PMSTAT 060E
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-28: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
CS1
ADDR15
0604
PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0>
PMADDR
PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1)
PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3)
PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1)
IB3F IB2F IB1F IB0F OBE OBUF
— —
IBF IBOV
PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3)
PMAEN 060C —PTEN14— — —
PMSTAT 060E
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70291B-page 54 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
xxxx
0000
xxxx
Resets
0000
All
0000
0000
0000
Resets
0000
All
0000
0000
Resets
All
079F
xxxx
xxxx
Resets
xxxx
— — RA4 RA3 RA2 RA1 RA0
— — — —
02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ALRMVAL 0620 Alarm Value Register Window based on APTR<1:0>
ALCFGRPT 0622 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> ARPT<7:-0>
RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0>
RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CAL<7:0>
TABLE 3-29: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CRCCON 0640 — — CSIDL VWORD<4:0> CRCFUL CRCMPT — CRCGO PLEN<3:0>
CRCXOR 0642 X<15:0>
CRCDAT 0644 CRC Data Input Register
CRCWDAT 0646 CRC Result Register
TABLE 3-30: CRC REGISTER MAP
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS
CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR<3:0>
TABLE 3-31: DUAL COMPARATOR REGISTER MAP
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-32: PORTA REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TRISA
02C6 — — — — — — — — — — — — — — — —
02C2 — — — — —
02C4 — — — — — — — — — — — LATA 4 LATA 3 LATA2 LATA1 LATA 0
PORTA
LATA
ODCA
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 55
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
(2)
(1)
All
079F
xxxx
xxxx
Resets
xxxx
All
FFFF
xxxx
xxxx
Resets
xxxx
All
03FF
xxxx
xxxx
Resets
xxxx
All
xxxx
Resets
TABLE 3-33: PORTA REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304
RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304
— — — — ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 — — — — —
02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TRISA
02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0
PORTA
02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — — — — — —
02C4 — — — — — L ATA1 0 L ATA9 LATA 8 LAT A7 — — LATA4 L ATA3 L ATA2 L ATA1 L ATA0
LATA
ODCA
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TABLE 3-34: PORTB REGISTER MAP
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
ODCB 02CE
TABLE 3-35: PORTC REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
— — — — — —
— — — — — —
— — — — — —
— — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 — — —
0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
0742 —COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK —CF— LPOSCEN OSWEN 0300
0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4::0> 0040
TRISC 02D0
PORTC 02D2
LATC 02D4
ODCC 02D6
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RCON
OSCCON
TABLE 3-36: SYSTEM CONTROL REGISTER MAP
CLKDIV
0746 — — — — — — — PLLDIV<8:0> 0030
PLLFBD
0748 — — — — — — — — — — TUN<5:0> 0000
OSCTUN
— — SELACLK AOSCMD<1:0> APSTSCLR<2:0> ASRCSEL — — — — — — — 0000
074A
2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values dependent on type of Reset.
ACLKCON
DS70291B-page 56 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
All
0000
0000
Resets
RL_SSR
IR_SSR
All
0000
0000
Resets
All
Resets
C1MD AD1MD 0000
—
I2C1MD U2MD U1MD SPI2MD SPI1MD
—
— — — —IC2MDIC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
— — — — — — — — NVMKEY<7:0>
— — — — — CMPMD RTCCMD PMPMD CRCMD DAC1MD QEI2MD PWM2MD — — — — 0000
TABLE 3-37: SECURITY REGISTER MAP FOR dsPIC33FJ128MC204/804 AND dsPIC33FJ64MC204/804 ONLY
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR
SSRAM 0752 — — — — — — — — — — — — —IW_ SSR
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-38: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NVMCON 0760 WR WREN WRERR — — — — — —ERASE— —NVMOP<3:0>
NVMKEY 0766
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TABLE 3-39: PMD REGISTER MAP
PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWM1MD
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PMD3 0774
PMD2 0772 IC8MD IC7MD
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 57
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.2.7 SOFTWARE STACK
In addition to its use as a working register, the W15
register in the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 devices is also used as a
software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It pre-decrements for stack
pops and post-increments for stack pushes, as shown
in Figure 3-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the
push, ensuring that the MSb is always clear.
Note: A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap does not occur. The stack error trap occurs on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x2000 in RAM, initialize the SPLIM with the value
0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-6: CALL STACK FRAME
0x0000
Stack Grow s Toward
000000000
Higher Address
PC<15:0>
PC<22:16>
<Free Word>
015
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
3.2.8 DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 3-1 for an overview of the BSRAM and SSRAM
SFRs.
3.3 Instruction Addressing Modes
The addressing modes shown in Table 3-40 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
3.3.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
3.3.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note: Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
DS70291B-page 58 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 3-40: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
The sum of Wn and Wb forms the EA.
3.3.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note: For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note: Not all instructions support all the address-
ing modes given above. Individual instructions may support different subsets of
these addressing modes.
3.3.4 MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note: Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
3.3.5 OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 59
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.4 Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be configured to operate in only one direction as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers), based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
3.4.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-1).
Note: Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
3.4.2 W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that
operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
FIGURE 3-7: MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS70291B-page 60 Preliminary © 2008 Microchip Technology Inc.
MOV #0x1100, W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0, W0 ;increment the fill value
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.4.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note: The modulo corrected effective address is
written back to the register only when PreModify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (such as [W7 +
W2]) is used, Modulo Address correction
is performed but the contents of the register remain unchanged.
3.5 Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
3.5.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
N
If the length of a bit-reversed buffer is M = 2
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note: All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It
does not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing assumes
priority when active for the X WAGU and X
WAGU, Modulo Addressing is disabled.
However, Modulo Addressing continues to
function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
bytes,
FIGURE 3-8: BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12
b15 b14 b13 b12
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 61
b11 b10 b9 b8
b11 b10 b9 b8
b7 b6 b5 b4
b7 b6 b5 b1
Pivot Point
b3 b2 b1 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b2 b3 b4
Bit-Reversed Address
0
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 3-41: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 0 0000 0
0001 1 1000 8
0010 2 0100 4
0011 3 1100 12
0100 4 0010 2
0101 5 1010 10
0110 6 0110 6
0111 7 1110 14
1000 8 0001 1
1001 9 1001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
DS70291B-page 62 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.6 Interfacing Program and Data Memory Spaces
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 architecture uses
a 24-bit-wide program space and a 16-bit-wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Aside from normal execution, the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 architecture provides
two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
3.6.1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Table 3-42 and Figure 3-9 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
TABLE 3-42: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Type
Instruction Access
(Code Execution)
TBLRD/TBLWT
(Byte/Word Read/Write)
Program Space Visibility
(Block Remap/Read)
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
Access
Space
User 0 PC<22:1> 0
User TBLPAG<7:0> Data EA<15:0>
Configuration TBLPAG<7:0> Data EA<15:0>
User 0 PSVPAG<7:0> Data EA<14:0>
<23> <22:16> <15> <14:1> <0>
0xx xxxx xxxx xxxx xxxx xxx0
0xxx xxxx xxxx xxxx xxxx xxxx
1xxx xxxx xxxx xxxx xxxx xxxx
0 xxxx xxxx xxx xxxx xxxx xxxx
Program Space Address
(1)
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 63
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 3-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter
Table Operations
(1)
(2)
Program Space Visibility
(Remapping)
User/Configuration
0
1/0
(1)
0
Space Select
TBLPAG
8 bits
Select
PSVPAG
8 bits
23 bits
24 bits
1
23 bits
EA
16 bits
EA
15 bits
0Program Counter
1/0
0
Byte Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to main-
tain word alignment of data in the program and data spaces.
2: Table operations are not required to be word aligned. Table read operations are permitted
in the configuration memory space.
DS70291B-page 64 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.6.2 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDH and TBLWTH access the space that
contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
• TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space
location (P<15:0>) to a data address
(D<15:0>).
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
(D<15:8>), is always ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 4.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user application
and configuration spaces. When TBLPAG<7> = 0, the
table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
FIGURE 3-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
TBLPAG
02
23 15 0
0x000000
0x020000
0x030000
0x800000
Program Space
00000000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
081623
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 65
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
3.6.3 READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 3-11), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note: PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop allows the
instruction using PSV to access data, to execute in a
single cycle.
FIGURE 3-11: PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG
02
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
23 15 0
0x000000
0x010000
0x018000
0x800000
Data Space
PSV Area
0x0000
0x8000
0xFFFF
Data EA<14:0>
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
DS70291B-page 66 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
4.0 FLASH PROGRAM MEMORY
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”,
“Section 5. Flash Programming”
(DS70191), which is available from the
Microchip website (www.microchip.com).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire V
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 device to be serially
programmed while in the end application circuit. This is
done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGC1/PGD1, PGC2/PGD2 or PGC3/PGD3),
and three other lines for power (V
Master Clear (MCLR
manufacture boards with unprogrammed devices and
DD range.
programming capability
DD), ground (VSS) and
). This allows customers to
then program the digital signal controller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
4.1 Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 4-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Using
Table Instruction
User/Configuration
Space Sel ect
0
1/0
TBLPAG Reg
8 bits
Program Counter
Working Reg EA
24-bit EA
0
16 bits
Byte
Select
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 67
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
4.2 RTSP Operation
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user application to erase
a page of memory, which consists of eight rows (512
instructions) at a time, and to program one row or one
word at a time. Table 30-12 shows typical erase and
programming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes and
192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
4.3 Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 4-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 4.4
“Programming Operations” for further details.
4.4 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 4 ms in
duration and the processor stalls (waits) until the
operation is finished. Setting the WR bit
(NVMCON<15>) starts the operation, and the WR bit is
automatically cleared when the operation is finished.
DS70291B-page 68 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
R/SO-0
WR WREN WRERR
bit 15 bit 8
R/W-0
(1)
R/W-0
(1)
U-0 U-0 U-0 U-0 U-0
— — — — —
U-0 R/W-0
(1)
U-0 U-0 R/W-0
— ERASE — —NVMOP<3:0>
(1)
R/W-0
(1)
R/W-0
(2)
(1)
R/W-0
(1)
bit 7 bit 0
Legend: SO = Satiable only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation Select bits
(2)
If ERASE = 1:
1111 = Memory bulk erase operation
1110 = Reserved
1101 = Erase General Segment
1100 = Erase Secure Segment
1011 = Reserved
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE =
0:
1111 = No operation
1110 = Reserved
1101 = No operation
1100 = No operation
1011 = Reserved
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 69
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 4-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits
DS70291B-page 70 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
4.4.1 PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 4-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 4-2).
5. Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
6. Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 4-3.
EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
; Init pointer to row to be ERASED
MOV #0x4042, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0] ; Set base address of erase block
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 71
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
EXAMPLE 4-2: LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
; Perform the TBLWT instructions to write the latches
; 0th_program_word
; 1st_program_word
; 2nd_program_word
; 63rd_program_word
MOV #0x4001, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
MOV #0x0000, W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000, W0 ; An example program memory address
MOV #LOW_WORD_0, W2 ;
MOV #HIGH_BYTE_0, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
MOV #LOW_WORD_1, W2 ;
MOV #HIGH_BYTE_1, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
MOV #LOW_WORD_2, W2 ;
MOV #HIGH_BYTE_2, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
MOV #LOW_WORD_31, W2 ;
MOV #HIGH_BYTE_31, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
EXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE
DISI #5 ; Block all interrupts with priority <7
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the
NOP ; erase command is asserted
; for next 5 instructions
DS70291B-page 72 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
5.0 RESETS
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the dsPIC33F Family Reference Manual,
“Section 8. Reset” (DS70192), which is
available from the Microchip website
(www.microchip.com).
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
•MCLR
: Master Clear Pin Reset
•SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
. The
A simplified block diagram of the Reset module is
shown in Figure 5-1.
Any active source of reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
Note: Refer to the specific peripheral section or
Section 2.0 “CPU” of this manual for
register Reset states.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
Internal
VDD
Regulator
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
VDD Rise
Detect
BOR
POR
SYSRST
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 73
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 5-1: RCON: RESET CONTROL REGISTER
(1)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR
— — — —CMVREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
(2)
EXTR SWR SWDTEN
WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred.
0 = A configuration mismatch Reset has NOT occurred.
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR
) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit
(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70291B-page 74 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 5-1: RCON: RESET CONTROL REGISTER
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
(1)
(CONTINUED)
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 75
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
5.1 System Reset
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 family of devices
have two types of Reset:
•Cold Reset
•Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 5-2.
1. POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay TPOR has elapsed.
DD crosses the VPOR
2. BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
DD crosses the VBOR threshold and the
delay T
BOR has elapsed. The delay TBOR
ensures that the voltage regulator output
becomes stable.
3. PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
PWRT ensures that the system
PWRT) after a
power supplies have stabilized at the appropriate level for full-speed operation. After the delay
PWRT has elapsed, the SYSRST becomes
T
inactive, which in turn enables the selected
oscillator to start generating clock cycles.
4. Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 5-1. Refer to Section 8.0
“Oscillator Configuration” for more
information.
5. When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the reset address, which redirects program
execution to the appropriate start-up routine.
6. The Fail-Safe Clock Monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
FSCM
elapsed.
TABLE 5-1: OSCILLATOR DELAY
Oscillator Mode
FRC, FRCDIV16, FRCDIVN T
Oscillator
Startup Delay
OSCD ——TOSCD
FRCPLL TOSCD —TLOCK TOSCD + TLOCK
XT TOSCD TOST —TOSCD + TOST
HS TOSCD TOST —TOSCD + TOST
EC ————
XTPLL T
OSCD TOST TLOCK TOSCD + TOST +
HSPLL TOSCD TOST TLOCK TOSCD + TOST +
ECPLL — — TLOCK TLOCK
SOSC TOSCD TOST —TOSCD + TOST
LPRC TOSCD ——TOSCD
Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
OST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a
2: T
10 MHz crystal and T
LOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
3: T
OST = 32 ms for a 32 kHz crystal.
Oscillator
Startup Timer
PLL Lock Time Total Delay
LOCK
T
T
LOCK
DS70291B-page 76 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 5-2: SYSTEM RESET TIMING
VBOR
Vbor
VPOR
V
DD
TPOR
POR Reset
1
TBOR
BOR Reset
SYSRST
Oscillator Clock
FSCM
Device Status
2
3
TPWRT
Reset
Time
OSCD TOST
T
4
TLOCK
6
5
Run
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
active until V
DD crosses the VPOR threshold and the delay TPOR has elapsed.
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
the V
BOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (T
at the appropriate level for full-speed operation. After the delay T
PWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
PWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
Table 5-1. Refer to Section 8.0 “Oscillator Configuration” for more information.
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay T
FSCM elapsed.
T
FSCM
DD crosses
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 77
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 5-2: OSCILLATOR DELAY
Symbol Parameter Value
V
POR POR threshold 1.8V nominal
TPOR POR extension time 30 μs maximum
BOR BOR threshold 2.5V nominal
V
TBOR BOR extension time 100 μs maximum
TPWRT Programmable power-up time delay 0-128 ms nominal
FSCM Fail-Safe Clock Monitor Delay 900 μs maximum
T
Note: When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all operating parameters within
specification.
5.2 Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
DD crosses the VPOR threshold and the delay TPOR
V
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 30.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
5.2.1 Brown-out Reset (BOR) and
Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
(V
DD < VBOR) for proper device operation. The BOR cir-
cuit keeps the device in Reset until V
threshold and the delay TBOR has elapsed. The delay
T
BOR ensures the voltage regulator output becomes
stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
DD should rise to acceptable levels for full-speed
V
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST
The power-up timer delay (T
is released.
PWRT) is programmed by
the Power-on Reset Timer Value Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 27.0 “Special
Features” for further details.
Figure 5-3 shows the typical brown-out scenarios. The
reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
DD is too low
DD crosses VBOR
DS70291B-page 78 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 5-3: BROWN-OUT SITUATIONS
VDD
VBOR
BOR + TPWRT
T
SYSRST
DD
V
SYSRST
VDD dips before PWRT expires
V
DD
SYSRST
5.3 External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 30.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR
(RCON) register is set to indicate the MCLR
) Pin (EXTR) bit in the Reset Control
Reset.
5.3.0.1 EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly connected to the MCLR
pin to Reset the device when the
rest of system is Reset.
5.3.0.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR
be tied directly or resistively to V
pin will not be used to generate a Reset. The
MCLR
external reset pin (MCLR
) does not have an internal
DD. In this case, the
pull-up and must not be left unconnected.
) should
5.4 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST
special Reset state. This Reset state will not reinitialize the clock. The clock source in effect prior to the
RESET instruction will remain. SYSRST
the next instruction cycle, and the reset vector fetch will
commence.
, placing the device in a
is released at
BOR + TPWRT
T
TBOR + TPWRT
VBOR
VBOR
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
5.5 Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST
. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Reset. Refer to Section 27.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
5.6 Trap Conflict Reset
If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 6.0 “Interrupt Controller” for
more information on trap conflict Resets.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 79
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
5.7 Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the
configuration mismatch Reset. Refer to Section 10.0
“I/O Ports” for more information on the configuration
mismatch Reset.
Note: The configuration mismatch feature and
associated reset flag is not available on all
devices.
5.8 Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
5.8.0.1 ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
5.8.0.2 UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
5.8.0.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 27.8 “Code Protection and
CodeGuard Security” for more information on
Security Reset.
5.9 Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the reset.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Table 5-3 provides a summary of the reset flag bit
operation.
TABLE 5-3: RESET FLAG BIT OPERATION
Flag Bit Set by: Cleared by:
TRAPR (RCON<15>) Trap conflict event POR,BOR
IOPWR (RCON<14>) Illegal opcode or uninitialized W register
access or Security Reset
CM (RCON<9>)
EXTR (RCON<7>) MCLR
SWR (RCON<6>) RESET instruction POR,BOR
WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction,
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR,BOR
IDLE (RCON<2>) PWRSAV #IDLE instruction POR,BOR
BOR (RCON<1>) POR, BOR
POR (RCON<0>) POR
Note: All Reset flag bits can be set or cleared by user software.
DS70291B-page 80 Preliminary © 2008 Microchip Technology Inc.
Configuration Mismatch POR,BOR
Reset POR
POR,BOR
POR,BOR
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
6.0 INTERRUPT CONTROLLER
Note: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, “Section 6.
Interrupts” (DS70184), which is available
from the Microchip website
(www.microchip.com).
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 interrupt
controller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
traps
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
6.1 Interrupt Vector Table
6.1.1 ALTERNATE INTERRUPT VECTOR
TAB LE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 6-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
6.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins
program execution at location 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
The Interrupt Vector Table (IVT), shown in Figure 6-1,
resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bitwide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices implement up
to 53 unique interrupts and five nonmaskable traps.
These are summarized in Table 6-1.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 81
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
FIGURE 6-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/
X04 INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 0x000000
Reset – GOTO Address 0x000002
Reserved 0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0 0x000014
Interrupt Vector 1
~
~
Interrupt Vector 52 0x00007C
Interrupt Vector 53 0x00007E
Interrupt Vector 54 0x000080
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
Oscillator Fail Trap Vector
Decreasing Natural Order Priority
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Interrupt Vector 52 0x00017C
Interrupt Vector 53 0x00017E
Interrupt Vector 54 0x000180
Interrupt Vector 116
Interrupt Vector 117 0x0001FE
~
~
~
~
Reserved
Reserved 0x000102
Reserved
Reserved
Reserved
Interrupt Vector 0 0x000114
Interrupt Vector 1
~
~
~
~
~
~
Start of Code 0x000200
0x000100
Interrupt Vector Table (IVT)
Alternate Interrupt Vector Table (AIVT)
(1)
(1)
Note 1: See Table 6-1 for the list of implemented interrupt vectors.
DS70291B-page 82 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 6-1: INTERRUPT VECTORS
Vector
Number
0 0x000004 0x000104 Reserved
1 0x000006 0x000106 Oscillator Failure
2 0x000008 0x000108 Address Error
3 0x00000A 0x00010A Stack Error
4 0x00000C 0x00010C Math Error
5 0x00000E 0x00010E DMA Error
6 0x000010 0x000110 Reserved
7 0x000012 0x000112 Reserved
8 0x000014 0x000114 INT0 – External Interrupt 0
9 0x000016 0x000116 IC1 – Input Compare 1
10 0x000018 0x000118 OC1 – Output Compare 1
11 0x00001A 0x00011A T1 – Timer1
12 0x00001C 0x00011C DMA0 – DMA Channel 0
13 0x00001E 0x00011E IC2 – Input Capture 2
14 0x000020 0x000120 OC2 – Output Compare 2
15 0x000022 0x000122 T2 – Timer2
16 0x000024 0x000124 T3 – Timer3
17 0x000026 0x000126 SPI1E – SPI1 Error
18 0x000028 0x000128 SPI1 – SPI1 Transfer Done
19 0x00002A 0x00012A U1RX – UART1 Receiver
20 0x00002C 0x00012C U1TX – UART1 Transmitter
21 0x00002E 0x00012E ADC1 – ADC 1
22 0x000030 0x000130 DMA1 – DMA Channel 1
23 0x000032 0x000132 Reserved
24 0x000034 0x000134 SI2C1 – I2C1 Slave Events
25 0x000036 0x000136 MI2C1 – I2C1 Master Events
26 0x000038 0x000138 CM – Comparator Interrupt
27 0x00003A 0x00013A Change Notification Interrupt
28 0x00003C 0x00013C INT1 – External Interrupt 1
29 0x00003E 0x00013E Reserved
30 0x000040 0x000140 IC7 – Input Capture 7
31 0x000042 0x000142 IC8 – Input Capture 8
32 0x000044 0x000144 DMA2 – DMA Channel 2
33 0x000046 0x000146 OC3 – Output Compare 3
34 0x000048 0x000148 OC4 – Output Compare 4
35 0x00004A 0x00014A T4 – Timer4
36 0x00004C 0x00014C T5 – Timer5
37 0x00004E 0x00014E INT2 – External Interrupt 2
38 0x000050 0x000150 U2RX – UART2 Receiver
39 0x000052 0x000152 U2TX – UART2 Transmitter
40 0x000054 0x000154 SPI2E – SPI2 Error
41 0x000056 0x000156 SPI2 – SPI2 Transfer Done
42 0x000058 0x000158 C1RX – ECAN1 RX Data Ready
43 0x00005A 0x00015A C1 – ECAN1 Event
44 0x00005C 0x00015C DMA3 – DMA Channel 3
45 0x00005E 0x00015E Reserved
46 0x000060 0x000160 Reserved
IVT Address AIVT Address Interrupt Source
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 83
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
TABLE 6-1: INTERRUPT VECTORS (CONTINUED)
Vector
Number
47 0x000062 0x000162 Reserved
48 0x000064 0x000164 Reserved
49 0x000066 0x000166 Reserved
50 0x000068 0x000168 Reserved
51 0x00006A 0x00016A Reserved
52 0x00006C 0x00016C Reserved
53 0x00006E 0x00016E PMP – Parallel Master Port
54 0x000070 0x000170 DMA – DMA Channel 4
55 0x000072 0x000172 Reserved
56 0x000074 0x000174 Reserved
57 0x000076 0x000176 Reserved
58 0x000078 0x000178 Reserved
59 0x00007A 0x00017A Reserved
60 0x00007C 0x00017C Reserved
61 0x00007E 0x00017E Reserved
62 0x000080 0x000180 Reserved
63 0x000082 0x000182 Reserved
64 0x000084 0x000184 Reserved
65 0x000086 0x000186 PWM1 – PWM1 Period Match
66 0x000088 0x000188 QEI1 – Position Counter Compare
67 0x00008A 0x00018A Reserved
68 0x00008C 0x00018C Reserved
69 0x00008E 0x00018E DMA5 – DMA Channel 5
70 0x000090 0x000190 RTCC – Real Time Clock
71 0x000092 0x000192 FLTA1
72 0x000094 0x000194 Reserved
73 0x000096 0x000196 U1E – UART1 Error
74 0x000098 0x000198 U2E – UART2 Error
75 0x00009A 0x00019A CRC – CRC Generator Interrupt
76 0x00009C 0x00019C DMA6 – DMA Channel 6
77 0x00009E 0x00019E DMA7 – DMA Channel 7
78 0x0000A0 0x0001A0 C1TX – ECAN1 TX Data Request
79 0x0000A2 0x0001A2 Reserved
80 0x0000A4 0x0001A4 Reserved
81 0x0000A6 0x0001A6 PWM2 – PWM2 Period Match
82 0x0000A8 0x0001A8 FLTA2
83 0x0000AA 0x0001AA QEI2 – Position Counter Compare
84 0x0000AC 0x0001AC Reserved
85 0x0000AE 0x0001AE Reserved
86 0x0000B0 0x0001B0
87 0x0000B2 0x0001B2
88-126 0x0000B4-0x0000FE 0x0001B4-0x0001FE Reserved
IVT Address AIVT Address Interrupt Source
– PWM1 Fault A
– PWM2 Fault A
DAC1R – DAC1 Right Data Request
DAC1L – DAC1 Left Data Request
DS70291B-page 84 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
6.3 Interrupt Control and Status Registers
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices implement a
total of 30 registers for the interrupt controller:
• INTCON1
• INTCON2
•IFSx
•IECx
•IPCx
•INTTREG
6.3.1 INTCON1 AND INTCON2
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
6.3.2 IFSx
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
6.3.3 IECx
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
6.3.4 IPCx
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
6.3.5 INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 6-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
6.3.6 STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
software can change the current CPU priority
level by writing to the IPL bits.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 6-1
through Register 6-32 in the following pages.
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 85
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-1: SR: CPU STATUS REGISTER
(1)
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0
IPL2
(3)
(2)
R/W-0
IPL1
(2)
(3)
R/W-0
IPL0
(2)
(3)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit 7 bit 0
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 2-1: “SR: CPU STATUS Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 6-2: CORCON: CORE CONTROL REGISTER
(1)
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — — US EDT DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(2)
PSV RND IF
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70291B-page 86 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
bit 5 DMACERR: DMA Controller Error Status bit
1 = DMA controller error trap has occurred
0 = DMA controller error trap has not occurred
bit 4 MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
—
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 87
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
DS70291B-page 88 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3 Unimplemented: Read as ‘0’
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 89
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 SPI1EIF: SPI1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70291B-page 90 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 91
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IC8IF IC7IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 T5IF: Timer5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 T4IF: Timer4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 Unimplemented: Read as ‘0’
bit 4 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
— INT1IF CNIF CMIF MI2C1IF SI2C1IF
DS70291B-page 92 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 2 CMIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 93
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— DMA4IF PMPIF — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DMA3IF C1IF
(1)
C1RXIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5 Unimplemented: Read as ‘0’
bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
(1)
(1)
SPI2IF SPI2EIF
Note 1: Interrupts disabled on devices without ECAN™ modules
DS70291B-page 94 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0
FLTA1IF RTCIF DMA5IF — — QEI1IF PWM1IF —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-11 Unimplemented: Read as ‘0’
bit 10 QEI1IF: QEI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-0 Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 95
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0
(2)
DAC1LIF
DAC1RIF
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
—C1TXIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
(1)
(2)
— — QEI2IF FLTA2IF PWM2IF —
DMA7IF DMA6IF CRCIF U2EIF U1EIF —
bit 15 DAC1LIF: DAC Left Channel Interrupt Flag Status bit
(2)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 DAC1RIF: DAC Right Channel Interrupt Flag Status bit
(2)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11 QEI2IF: QEI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 PWM2IF: PWM2 Error Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-7 Unimplemented: Read as ‘0’
bit 6 C1TXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 U2EIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 Unimplemented: Read as ‘0’
Note 1: Interrupts disabled on devices without ECAN™ modules.
2: Interrupts disabled on devices without DAC modules.
DS70291B-page 96 Preliminary © 2008 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10 SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8 T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7 T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
© 2008 Microchip Technology Inc. Preliminary DS70291B-page 97
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, AND dsPIC33FJ128MCX02/X04
REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 INT0IE: External Interrupt 0 Flag Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DS70291B-page 98 Preliminary © 2008 Microchip Technology Inc.
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