MICROCHIP dsPIC33F Technical data

dsPIC33F Family

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology I ncorporat ed in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

code hopping devices, Serial

®

dsPIC33F

High-Performance, 16-bit Digital Signal Controllers

Operating Range:

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,

-40°C to +85°C)

• Industrial temperature range (-40°C to +85°C )

High-Performance DSC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 83 base instructions: mostly 1 word/ 1 cycle

• Sixteen 16-bit General Purpose Registers

• Two 40-bit accumulators:

- With rounding and saturation optio ns

• Flexible and powerful addressing modes:

- Indirect, Modulo and Bit-Reversed

• Software stack

• 16 x 16 fractional/integer multiply operations

• 32/16 and 16/16 divide operations

• Single-cycle multiply and accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Up to ±16-bit shifts for up to 40-bit data

Direct Memory Access (DMA):

Digital I/O:

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

On-Chip Flash and SRAM:

• Flash program memory, up to 256 Kbytes

• Data SRAM, up to 30 Kbytes (includes 2 Kbytes of DMA RAM):

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter P LL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monito r

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

• 8-channel hardware DMA:

• 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:

- Allows data transfer between RAM and a

peripheral while CPU is executing code (no cycle stealing)

• Most peripherals support DMA

Interrupt Controller:

• 5-cycle la tency

• 118 interrupt vectors

• Up to 67 available interrupt sources

• Up to 5 external interrupts

• 7 programmable priority levels

• 5 processor exceptions

Timers/Capture/Compare/PWM:

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- 1 timer runs as Real-T ime Clock wi th external

32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

dsPIC33F

Communication Modules:

• 3-wire SPI (up to 2 modules):

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

2

•I

C™ (up to 2 modules):

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to 2 modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

®

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Data Converter Interface (DCI) module:

- Codec interface

- Supports I

- Up to 16-bit data words, up to 16 words per

- 4-word deep TX and RX buffers

• Enhanced CAN (ECAN™ module) 2.0B active (up to 2 modules):

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

- Wake-up on CAN message

- Automatic processing of Remote

- FIFO mode using DMA

- DeviceNet™ addressing support

encoding and decodi ng in hardware

2

S and AC’97 protocols

frame

Messages modes for diagnostics and bus monitoring

Transmission Requests

Motor Control Peripherals:

• Motor Cont rol PWM (up to 8 channels):

- 4 duty cycle generators

- Independent or Complementary mode

- Programmable dead time and output polarity

- Edge or center-aligned

- Manual output override control

- Up to 2 Fault inputs

- Trigger for ADC conversions

- PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode

- PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode

• Quadrature Encoder Interface module:

- Phase A , Phase B and i ndex pulse i nput

- 16-bit up/down position counter

- Count direction status

- Position Measurement (x2 and x4) mode

- Programmable digital noise filters on inputs

- Alternate 16-bit Timer/Counter mode

- Interrupt on position counter rollover/underflow

Analog-to-Digit al Converters (ADCs):

• Up to two ADC modules in a device

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- 2, 4 or 8 simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash T echnology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial temperature

• Low-power consumption

Packaging:

• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)

• 80-pin TQFP (12x12x1 mm)

• 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact

peripheral features per device.

dsPIC33F

dsPIC33F PRODUCT FAMILIES

for Uninterrupted Power Supply (UPS), inverters, Switched mode power supplies, power factor correc-

There are two device subfamilies within the dsPIC33F family of devices. They are the General Purpose Family and the Motor Control Family.

The General Purpose Family is ideal for a wide variety of 16-bit MCU embedded applications. The variants with codec interfaces are well-suited for speech and

tion and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment.

The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams.

audio processing applications. The Motor Control Family supports a variety of motor

control applications, such as brushless DC motors, single and 3-phase induction motors and switched reluctance moto rs. The se pro duct s are also well-s uited

dsPIC33F General Purpose Family Variants

(2)

Program

Device Pins

dsPIC33FJ64GP206 64 64 8 9 8 8 1 1 ADC, 18 ch221 053 PT

dsPIC33FJ64GP306 64 64 16 9 8 8 1 1 ADC, 18 ch222 053 PT

Flash

Memory

(Kbyte)

RAM

(Kbyte)

CAN

Packages

I/O Pins (Max)

(1)

16-bit Timer

Input Capture

Codec

Interface

Std. PWM

Output Compare

ADC

UART

C™

SPI

2

I

Enhanced

dsPIC33FJ64GP310 100 64 16 9 8 8 1 1 ADC, 32 ch222 085PF, PT

dsPIC33FJ64GP706 64 64 16 9 8 8 1 2 ADC, 18 ch222 253 PT

dsPIC33FJ64GP708 80 64 16 9 8 8 1 2 ADC, 24 ch222 269 PT

dsPIC33FJ64GP710 100 64 16 9 8 8 1 2 ADC, 32 ch222 285PF, PT

dsPIC33FJ128GP2 06 64 128 8 9 8 8 1 1 ADC, 18 ch221 053 PT

dsPIC33FJ128GP306 64 128 16 9 8 8 1 1 ADC, 18 ch222 053 PT

dsPIC33FJ128GP310 100 128 16 9 8 8 1 1 ADC, 32 ch222 085PF, PT

dsPIC33FJ128GP706 64 128 16 9 8 8 1 2 ADC, 18 ch222 253 PT

dsPIC33FJ128GP708 80 128 16 9 8 8 1 2 ADC, 24 ch222 269 PT

dsPIC33FJ128GP710 100 128 16 9 8 8 1 2 ADC, 32 ch222 285PF, PT

dsPIC33FJ256GP506 64 256 16 9 8 8 1 1 ADC, 18 ch222 153 PT

dsPIC33FJ256GP510 100 256 16 9 8 8 1 1 ADC, 32 ch222 185PF, PT

dsPIC33FJ256GP710 100 256 30 9 8 8 1 2 ADC, 32 ch222 285PF, PT

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

dsPIC33F

Pin Diagrams

64-Pin TQFP

DDCORE

CSDO/RG13

CSDI/RG12

CSCK/RG14

RG1

RF1

RG0

OC8/CN16/RD7

V

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ64GP206

dsPIC33FJ128GP206

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

545352

55

27

26

SS

V

VDD

AN9/RB9

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2TX/CN18/RF5

U2RX/CN17/RF4

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

Pin Diagrams (Continued)

64-Pin TQFP

dsPIC33F

DDCORE

CSDO/RG13

CSDI/RG12

CSCK/RG14

RG1

RF1

RG0

OC8/CN16/RD7

V

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ64GP306

dsPIC33FJ128GP306

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

545352

55

27

26

SS

V

VDD

AN9/RB9

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

dsPIC33F

Pin Diagrams (Continued)

64-Pin TQFP

CSDO/RG13

DDCORE

CSDI/RG12

CSCK/RG14

RG1

C1TX/RF1

RG0

OC8/CN16/RD7

V

VDD

C1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ256GP506

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

55

27

26

SS

V

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

Pin Diagrams (Continued)

64-Pin TQFP

dsPIC33F

DDCORE

CSDO/RG13

CSDI/RG12

CSCK/RG14

C2TX/RG1

C1TX/RF1

C2RX/RG0

OC8/CN16/RD7

V

VDD

C1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ64GP706

dsPIC33FJ128GP706

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

55

27

26

SS

V

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

dsPIC33F

Pin Diagrams (Continued)

80-Pin TQFP

COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

V

V TMS/AN20/INT1/RA12 TDO/AN21/INT2/RA13

AN5/CN 7/RB 5 AN4/CN 6/RB 4 AN3/CN 5/RB 3

AN2/SS1

/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

DD

CSCK/RG14

AN23/CN23/RA7

AN22/CN22/RA6

C2RX/RG0

CSDO/RG13

CSDI/RG12

792280 1 2

3 4 5 6 7 8 9 10 11

SS

12 13 14 15 16 17 18 19 20

21

2324252627282930313233

C2TX/RG1

75

767877

dsPIC33FJ64GP708

dsPIC33FJ128GP708

DDVDDCORE

C1TX/RF1

C1RX/RF0

727473

OC8/CN16/RD7

OC6/CN14/RD5

V

7170696867666564636261

OC7/CN15/RD6

34

OC5/CN13/RD4

35

IC5/RD12

OC4/RD3

OC3/RD2

IC6/CN19/RD13

36

OC2/RD1

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

60

PGD2 /E M U D 2 / S O S C I /CN1/RC13

59

OC1/RD0

58

IC4/RD11

57

IC3/RD10

56

IC2/RD9

55

IC1/RD8

54

SDA2/INT4/RA3

53

SCL2/INT3/RA2

52

SS

V

51 50

OSC2/CLKO/RC15 OSC 1/ C L KIN/RC12

49

DD

V

48

SCL1/RG2

47

SDA1/RG3

46

SCK1 /INT0/RF6

45

SDI1/RF7

44 43

SDO1/RF8 U1RX/RF2

42

U1TX/RF3

41

40

39

38

37

SS

DD

AV

-/RA9 +/RA10

REF

V

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

U2CTS/AN8/RB8

SS

DD

V

AN11/RB1 1

AN10/RB10

TDI/AN13/RB13

TCK/AN12/RB12

U2RTS/AN14/RB14

IC7/U1CTS/CN20/RD14

AN15/OC FB/ C N1 2/ RB 15

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

COFS/RG15

AN29/RE5 AN30/RE6

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0 AN20 /INT1/RA12 AN21 /INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3

AN2/SS1

/CN4/RB2

1

V

2

DD

3 4 5 6 7 8 9 10 11 12 13 14

V

SS

15

DD

V

16 17 18 19 20 21 22 23 24 25

AN26/RE2

AN23/CN23/RA7

CSDO/RG13

CSDI/RG12

CSCK/RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

9294939190898887868584838281807978

dsPIC33FJ64GP310

dsPIC33FJ128GP310

dsPIC33F

DDCORE

RG0

DD

RF0

V

RG1

RF1

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

76

77

V

SS

75

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

74

PGD2/EMUD2/SOSCI/CN1/RC13

73

OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

IC1/RD8

68

INT4/R A15

67

INT3/R A14

66

V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

DD

V

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1 /INT0/RF6

55

SDI1/R F7

54

SDO1/RF8

53

U1RX/RF2

52

U1TX/RF3

51

26

2829303132333435363738

27

SS

DD

AV

-/RA9 +/RA10

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

REF

V

AN8/RB8

REF

V

AN9/RB9

AN10/RB10

41

40

39

SS

DD

V

TCK/RA1

AN11/RB1 1

AN12/RB12

U2RTS/RF13

U2CTS/RF12

42

AN13/RB13

43

AN14/RB14

44

AN15/OCFB/CN12/RB15

45

4647484950

SS

DD

V

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

U2RX/CN17/RF4

U2TX/CN18/RF5

dsPIC33F

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

COFS/RG15

AN29/RE5 AN30/RE6

AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0 AN20 /INT1/RA12 AN21 /INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3

AN2/SS1

/CN4/RB2

PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

1 2

DD

V

3 4 5 6 7 8 9 10 11 12 13 14

SS

V

15 16

DD

V

17 18 19 20 21 22 23 24 25

AN26/RE2

AN23/CN23/RA7

CSDO/RG13

CSDI/RG12

CSCK/RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

9294939190898887868584838281807978

dsPIC33FJ256GP510

RG0

RG1

C1TX/RF1

DD

C1RX/RF0

V

DDCORE

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

76

77

75

V

SS

74

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

73

PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

IC1/RD8

68

INT4/R A15

67 66

INT3/R A14 V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

V

DD

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1 /INT0/RF6

55

SDI1/R F7

54

SDO1/RF8

53

U1RX/RF2

52 51

U1TX/RF3

26

2829303132333435363738

27

SS

DD

AV

-/RA9 +/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6 /OCFA/RB 6

AN8/RB8

REF

V

AN9/RB9

AN10/RB10

41

40

39

SS

DD

V

TCK/RA1

AN11/RB1 1

AN12/RB12

U2CTS/RF12

U2RTS/RF13

45

44

43

42

AN13/RB13

AN14/RB14

SS

V

AN15/OCFB/CN12/RB15

4647484950

DD

V

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

COFS/RG15

AN29/RE5 AN30/RE6

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

PGC 3 /E M U C 3 /A N 1 /C N3/RB1 PGD 3 /E M U D 3 /A N 0 /C N2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3

AN2/SS1

/CN4/RB2

1

DD

V

2 3 4 5 6 7 8 9 10 11 12 13 14

V

SS

15

V

DD

16 17 18 19 20 21 22 23 24 25

AN26/RE2

AN23/CN23/RA7

CSDO/RG13

CSDI/RG12

CSCK/RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

9294939190898887868584838281807978

dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710

C2RX/RG0

dsPIC33F

DDCORE

DD

C1RX/RF0

V

C2TX/RG1

C1TX/RF1

OC6/CN1 4/R D5

OC5/CN1 3/R D4

IC6/CN19/RD 13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN1 6/R D7

OC7/CN1 5/R D6

OC2/RD1

76

77

V

SS

75 74

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13

73

OC1/RD0

72 71

IC4/RD11 IC3/RD10

70

IC2/RD9

69 68

IC1/RD8 INT4/RA15

67 66

INT3/RA14 V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC1 2

63

DD

V

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1/INT0/RF6

55

SDI1/RF7

54

SDO1/RF8

53

U1RX/RF2

52 51

U1TX/RF3

26

2829303132333435363738

27

SS

DD

AV

-/RA9 +/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

41

40

39

SS

DD

V

TCK/RA1

AN11/RB1 1

AN10/RB1 0

AN12/RB1 2

U2RTS/RF13

U2CTS/RF12

45

44

43

42

AN13/RB1 3

AN14/RB1 4

SS

V

AN15/OCFB/CN12/RB15

4647484950

DD

V

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

dsPIC33F

dsPIC33F Motor Control Family Variants

Progra

Device Pins

dsPIC33FJ64MC506 64 64 8 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ64MC508 80 64 8 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ64MC510 100 64 8 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ64MC706 64 64 16 9 8 8 8 ch 1 0 2 ADC,

dsPIC33FJ64MC710 100 64 16 9 8 8 8 ch 1 0 2 ADC,

dsPIC33FJ128MC506 64 128 8 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ128MC510 100 128 8 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ128MC706 64 128 16 9 8 8 8 ch 1 0 2 ADC,

dsPIC33FJ128MC708 80 128 16 9 8 8 8 ch 1 0 2 ADC,

dsPIC33FJ128MC710 100 128 16 9 8 8 8 ch 1 0 2 ADC,

dsPIC33FJ256MC510 100 256 16 9 8 8 8 ch 1 0 1 ADC,

dsPIC33FJ256MC710 100 256 30 9 8 8 8 ch 1 0 2 ADC,

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

m Flash

Memory

(Kbyte)

RAM

(Kbyte)

(1)

Timer 16-bit

Std. PWM

Input Capture

Output Comp are

Interface

Motor Control PWM

Quadrature Encoder

ADC

Codec Interface

16 ch

18 ch

24 ch

16 ch

24 ch

16 ch

24 ch

16 ch

18 ch

24 ch

(2)

Enhanced CAN

Packages

I/O Pins (Max)

C™

SPI

2

UART

222153 PT

222169 PT

222185PF, PT

222153 PT

222285PF, PT

222153 PT

222185PF, PT

222153 PT

222269 PT

222285PF, PT

222185PF, PT

222285PF, PT

I

Pin Diagrams

64-Pin TQFP

PWM3L/RE4

PWM2H/RE3

PWM2L/RE2

PWM1L/RE0

PWM1H/RE1

dsPIC33F

DDCORE

OC8/UPDN/CN16/RD7

V

C1TX/RF1

VDDC1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

SDO2/CN10/RG8

SS2/T5CK/CN11/RG9

AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

V V

/CN4/RB2

REF

-/CN3/RB1

REF

+/CN2/RB0

SS DD

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ64MC506

171819202122232425

SS

DD

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

545352

55

27

26

SS

DD

V

AN9/RB9

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/FLTB

43

IC1/FLTA

42 41

V

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

DD

V

38

SCL1/RG2

37

SDA1/RG3

36

U1RTS/SCK1/INT0/RF6

35

U1RX/SDI1/RF2

34 33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2TX/CN18/RF5

U2RX/CN17/RF4

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

/INT2/RD9

/INT1/RD8

dsPIC33F

Pin Diagrams (Continued)

64-Pin TQFP

PWM3L/RE4

PWM2H/RE3

PWM2L/RE2

PWM1H/RE1

PWM1L/RE0

C1TX/RF1

VDDC1RX/RF0

DDCORE

OC8/UPDN/CN16/RD7

V

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

SDO2/CN10/RG8

SS2/T5CK/CN11/RG9

AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

V V

/CN4/RB2

REF

-/CN3/RB1

REF

+/CN2/RB0

SS DD

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

dsPIC33FJ128MC506

dsPIC33FJ64MC506

dsPIC33FJ128MC706

171819202122232425

SS

DD

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

TDO/AN11/RB11

TMS/AN10/RB10

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

504951

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

PGC2/EMUC2/SOSCO/T1CK/CN0/RC 14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/ IC1/ V OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3

SS

DD

FLTA

FLTB

/INT2/RD9

/INT1/RD8

545352

55

27

26

SS

DD

V

TCK/AN12/RB12

Pin Diagrams (Continued)

80-Pin TQFP

PWM3L/RE4

PWM2L/RE2

PWM2H/RE3

PWM1H/RE1

PWM1L/RE0

dsPIC33F

DDVDDCORE

RG0

RG1

V

C1TX/RF1

C1RX/RF0

OC8/CN16/UPDN/RD7

OC6/CN14/RD5

OC7/CN15/RD6

OC5/CN13/RD4

IC5/RD12

OC4/RD3

OC3/RD2

IC6/CN19/RD13

OC2/RD1

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

V

FLTA

/INT1/RE8

TMS/ TDO/

FLTB

/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/IN DX/CN5/RB3

AN2/SS1

/CN4/RB2 PGC 3 /E M U C 3 /A N 1 /C N3/RB1 PGD 3 /E M U D 3 /A N 0 /C N2/RB0

SS DD

U2CTS/AN8/RB8

727473

7170696867666564636261

35

34

SS

DD

V

AN9/RB9

AN11/RB1 1

AN10/RB10

TDI/AN13/RB13

TCK/AN12/RB12

U2RTS/AN14/RB14

60

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13

59

OC1/RD0

58

IC4/RD11

57 56

IC3/RD10 IC2/RD9

55

IC1/RD8

54

SDA2/INT4/RA3

53 52

SCL2 /INT3/RA2

SS

V

51

OSC2/CLKO/RC15

50

OSC1/CLKIN/RC12

49

V

48 47 46 45 44 43 42 41

40

39

38

37

36

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

AN15/OCFB/CN12/RB15

DD

SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3

75

792280 1 2 3 4 5 6 7 8 9 10 11 12 13

14 15 16 17 18 19 20

21

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6 /OCFA/RB 6

767877

dsPIC33FJ64MC508

2324252627282930313233

SS

DD

AV

-/RA9 +/RA10

REF

V

REF

V

dsPIC33F

Pin Diagrams (Continued)

80-Pin TQFP

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/C N9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

V V

FLTA

/INT1/R E8

TMS/

FLTB

TDO/

PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

/INT2/R E9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

/CN4/RB2

SS DD

PWM2L/RE2

PWM1H/RE1

PWM1L/RE0

CRX2/RG0

PWM3L/RE4

PWM2H/RE3

792280 1 2 3 4 5 6 7 8 9 10 11 12 13

14 15 16 17 18 19 20

21

2324252627282930313233

C2TX/RG1

75

767877

dsPIC33FJ128MC708

DDVDDCORE

C1TX/RF1

C1RX/RF0

727473

OC8/CN16/UPDN/RD7

OC6/CN14/RD5

V

7170696867666564636261

OC7/CN15/RD6

IC5/RD12

OC4/RD3

OC3/RD2

OC5/CN13/RD4

IC6/CN19/R D1 3

36

35

34

OC2/RD1

60

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13

59

OC1/RD0

58

IC4/RD11

57

IC3/RD10

56

IC2/RD9

55

IC1/RD8

54

SDA2/INT4/RA3

53

SCL2 /INT3/RA2

52

SS

V

51

OSC2/CLKO/RC15

50

OSC1/CLKIN/RC12

49 48

DD

V SCL1/RG2

47

SDA1/RG3

46

SCK1/INT0/RF6

45

SDI1/RF7

44

SDO1/RF8

43

U1RX/RF2

42

U1TX/RF3

41

40

39

38

37

SS

DD

AV

-/RA9 +/RA10

REF

V

REF

V

PGD1/EMUD1/AN7 /RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

U2CTS/AN8/RB8

AN10/RB10

SS

DD

V

AN11/RB1 1

TDI/AN13/RB13

TCK/AN12/RB12

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

Pin Diagrams (Continued)

100-Pin TQFP

PWM3L/RE4

PWM2H/RE3

99

100

DD

1 2 3 4 5 6 7 8 9 10 11 12 13 14

SS

15 16 17 18 19 20 21 22 23 24 25

COFS/RG15

V

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/C N9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

FLTA

AN20/

AN21/

FLTB AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

V V

TMS/RA0 /INT1/R E8 /INT2/R E9

/CN4/RB2

dsPIC33F

DDCORE

DD

RG1

PWM2L/RE2

CSDO/RG13

CSDI/RG12

969897

AN23/CN23/RA7

CSCK/RG14

PWM1H/RE1

PWM1L/RE0

9294939190898887868584838281807978

95

C1TX/RF1

AN22/CN22/RA6

RG0

dsPIC33FJ64MC510

OC8/UPDN//CN16/RD7

OC7/CN15/RD6

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

C1RX/RF0

V

OC2/RD1

76

77

V

75

SS

74

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

73

PGD2/EMUD2/SOSCI/CN1/RC13

72

OC1/RD0 IC4/RD11

71

IC3/RD10

70

IC2/RD9

69 68

IC1/RD8 INT4/RA15

67 66

INT3/RA14 V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC1 2

63

DD

V

62

TDO/RA5

61

TDI/RA4

60

RA3

59

RA2

58 57

SCL1/RG2 SDA1/RG3

56

SCK1/INT0/RF6

55

SDI1/RF7

54

SDO1/RF8

53

U1RX/RF2

52

U1TX/RF3

51

26

2829303132333435363738

27

SS

DD

AV

-/RA9 +/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

AN10/RB10

41

40

39

SS

DD

V

TCK/RA1

AN11/RB1 1

AN12/RB12

U2RTS/RF13

U2CTS/RF12

42

AN13/RB13

43

AN14/RB14

44

AN15/OCFB/CN12/RB15

45

4647484950

SS

DD

V

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

U2RX/CN17/RF4

U2TX/CN18/RF5

dsPIC33F

Pin Diagrams (Continued)

100-Pin TQFP

PWM3L/RE4

PWM2H/RE3

99

100

COFS/RG15

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/C N9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/

FLTA

/INT1/R E8

AN21/

FLTB

/INT2/R E9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

1

V

DD

2 3 4 5 6 7 8 9 10 11 12 13 14

SS

V

15

V

DD

16 17 18 19 20 21 22 23 24 25

PWM2L/RE2

RG1

DD

C1RX/RF0

V

C1TX/RF1

AN23/CN23/RA7

CSDO/RG13

CSDI/RG12

CSCK/RG14

95

969897

AN22/CN22/RA6

PWM1H/RE1

PWM1L/RE0

RG0

9294939190898887868584838281807978

dsPIC33FJ128MC510 dsPIC33FJ256MC510

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/UPDN//CN16/RD7

OC7/CN15/RD6

OC2/RD1

76

77

V

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SS

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/R A15 INT3/R A14 V

SS

OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V

DD

TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1 /INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2

U1TX/RF3

DDCORE

26

2829303132333435363738

27

SS

DD

AV

-/RA9 +/RA10

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

REF

V

AN8/RB8

REF

V

AN9/RB9

41

40

39

SS

DD

V

TCK/RA1

AN11/RB1 1

AN10/RB10

AN12/RB12

U2RTS/RF13

U2CTS/RF12

45

44

43

42

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

4647484950

SS

DD

V

IC8/U1RTS / CN 2 1/R D 15

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

Pin Diagrams (Continued)

100-Pin TQFP

PWM3L/RE4

PWM2H/RE3

99

COFS/RG15

V

DD

PWM3H/RE5 PWM4L/RE6

PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN20/

FLTA

AN21/

FLTB AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0

V V

TMS/RA0 /INT1/RE8 /INT2/RE9

/CN4/RB2

DD

SS

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26

27

AN23/CN23/RA7

PWM2L/RE2

CSDO/RG13

CSDI/RG12

CSCK/RG14

95

969897

AN22/CN22/RA6

PWM1H/RE1

PWM1L/RE0

C2RX/RG0

C2TX/RG1

9294939190898887868584838281807978

dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710

2829303132333435363738

dsPIC33F

DDCORE

DD

C1RX/RF0

V

C1TX/RF1

40

39

OC6/CN1 4/R D5

OC5/CN1 3/R D4

IC6/CN19/RD 13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/UPDN//CN16/RD7

OC7/CN1 5/R D6

45

44

43

42

41

4647484950

OC2/RD1

76

77

75

V

SS

74

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

73

PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

IC1/RD8

68

INT4/RA15

67

INT3/RA14

66

V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

V

DD

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58 57

SCL1/RG2

56

SDA1/RG3 SCK1/INT0/RF6

55 54

SDI1/RF7

53

SDO1/RF8 U1RX/RF2

52 51

U1TX/RF3

SS

DD

AV

-/RA9 +/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

SS

DD

V

TCK/RA1

AN11/RB1 1

AN10/RB10

AN12/RB12

U2RTS/RF13

U2CTS/RF12

SS

DD

V

AN13/RB13

AN14/RB14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

IC7/U1CTS/CN20/RD14

AN15/OC F B/C N1 2/ RB 15

dsPIC33F

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Most Current Data Sheet

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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dsPIC33F

NOTES:

dsPIC33F

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of this group of dsPIC33F devices. It is not intended to be a compr ehensive refer ence source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).

This documen t conta i ns dev ic e spec if i c in for m at i on fo r the following devices:

• dsPIC33FJ64GP206

• dsPIC33FJ64GP306

• dsPIC33FJ64GP310

• dsPIC33FJ64GP706

• dsPIC33FJ64GP708

• dsPIC33FJ64GP710

• dsPIC33FJ128GP206

• dsPIC33FJ128GP306

• dsPIC33FJ128GP310

• dsPIC33FJ128GP706

• dsPIC33FJ128GP708

• dsPIC33FJ128GP710

• dsPIC33FJ256GP506

• dsPIC33FJ256GP510

• dsPIC33FJ256GP710

• dsPIC33FJ64MC506

• dsPIC33FJ64MC508

• dsPIC33FJ64MC510

• dsPIC33FJ64MC706

• dsPIC33FJ64MC710

• dsPIC33FJ128MC506

• dsPIC33FJ128MC510

• dsPIC33FJ128MC706

• dsPIC33FJ128MC708

• dsPIC33FJ128MC710

• dsPIC33FJ256MC510

• dsPIC33FJ256MC710 The dsPIC33F General Purpose and Motor Control

Families of devices include devices with a wide range of pin counts (64, 80 and 100), different program memory sizes (64 Kb ytes, 128 Kbytes and 25 6 Kbytes) and different RAM sizes (8 Kbytes, 16 Kbytes and 30 Kbytes)

This makes these families suitable for a wide variety of high-performance digital signal control application. The devices are pin compatible with the PIC24H family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration betwee n device families as may be necessitated by the specific functionality, computational resource and sys tem cost requirem ents of the applic ation.

The dsPIC33F device famil y employs a powe rful 16-b it architecture that seamlessly integrates the control features of a Microcontroller (MCU) with the computational ca pabil ities of a D igital Signal Process or (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive computations, as well as control.

The DSP engine, dual 40-bit accumulators, hardware support for division operations, barrel shifter, 17 x 17 multiplier, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the dsPIC33F Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the dsPIC33F devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use dsPIC33F devices.

Figure 1-1 shows a general block diagram of the various core and peripheral modules in the dsPIC33F family of devices, while Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

dsPIC33F

FIGURE 1-1: dsPIC33F GENERAL BLOCK DIAGRAM

PSV & Table Data Access

Control Block

Y Data Bus

23

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

Interrupt

Controller

23

Timing

Generation

FRC/LPRC

Oscillators

Precision Band Gap Reference

Voltage

Regulator

23

Control

Address Bus

Control Signals to Various Blocks

8

PCH PCL

PCU

Program Counter

Stack

Logic

Loop

Control

Logic

24

Instruction

Decode &

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

16

X Data Bus

16

Data Latch

X RAM

Address

Latch

16

Address Generator Units

ROM Latch

Instruction Reg

DSP Engine

Divide Support

16

Data Latch

Y RAM

Address

Latch

W Register Array

16

EA MUX

16

16 x 16

16

Literal Data

16-bit ALU

DMA RAM

DMA

Controller

16

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

VDDCORE/VCAP

Timers

1-9

IC1-8

DD, VSS

V

PWM

OC/

PWM1-8

MCLR

QEI

CN1-23

DCI

SPI1,2

ADC1,2

I2C1,2

ECAN1,2

UART1,2

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN31 I Analog Analog input ch annels. AV

DD P P Positive supply for analog modules. SS P P Ground reference for analog modules.

AV CLKI

CLKO

CN0-CN23 I ST Input change notification inputs.

COFS CSCK CSDI CSDO

C1RX C1TX C2RX C2TX

PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3

IC1-IC8 I ST Capture inputs 1 through 8. INDX

QEA QEB UPDN

INT0 INT1 INT2 INT3 INT4

FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

MCLR OCFA

OCFB OC1-OC8

OSC1 OSC2

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Type

I

O

I/O I/O

I

O

I

O

I

O

I/O

I

I/O

I

I/O

I

I I

I

O

I I I I I

I

I O O O O O O O O

I/P ST Master Clear (R es et ) input. This pin is an active-low R eset to the device.

I

I O

I

I/O

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST/CMOS—External clock source input. Always associated wit h O SC 1 pin function.

ST ST ST

—

ST

—

ST

—

ST ST ST ST ST ST

ST ST

ST

CMOS

ST ST ST ST ST

ST ST

— — — — — — — —

ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Oscillator crystal out put. Connects to crystal o r resonator in Crystal Osc illa to r mode. Optionally functions as CLKO in RC and EC mode s. A lw ays associated with OSC 2 pin function.

Can be software program med for internal weak pull- ups on al l in puts . Data Converter Interface fr am e synchronization pin.

Data Conve r ter Interface serial clock input/ output pin. Data Converter Interface ser ia l data input pin. Data Converter Interface serial data output pin.

ECAN1 bus receive pin. ECAN1 bus transmit pin . ECAN2 bus receive pin. ECAN2 bus transmit pin .

Data I/O pin for programming/debugging communication channel 1. Clock input pin for program m i ng/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for program m i ng/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for program m i ng/debugging communication channel 3.

Quadrature Encoder Index Pulse input. Quadrature Encoder P has e A i nput in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder P has e A i nput in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Cou nt er Dir ec tion State.

Externa l interrup t 0 . Externa l interrup t 1 . Externa l interrup t 2 . Externa l interrup t 3 . Externa l interrup t 4 .

PWM Fault A input. PWM Fault B input. PWM 1 low output. PWM 1 high output. PWM 2 low output. PWM 2 high output. PWM 3 low output. PWM 3 high output. PWM 4 low output. PWM 4 high output.

Compare Fault A i nput (for Compare Channels 1, 2, 3 and 4). Compare Fault B i nput (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8.

Oscillator crystal out put. Connects to crystal o r resonator in Crystal Osc illa to r mode. Optionally functions as CL KO i n RC and EC modes.

dsPIC33F

Description

dsPIC33F

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA0-RA7 RA9-RA10 RA12-RA15

RB0-RB15 I/O ST PORTB is a bidir ectional I/O port. RC1-RC4

RC12-RC15 RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE9 I/ O ST PORTE is a bidirectional I/O port. RF0-RF8

RF12-RF13 RG0-RG3

RG6-RG9 RG12-RG15

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL1 SDA1 SCL2 SDA2

SOSCI SOSCO

TMS TCK TDI TDO

T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK

U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX

DD P — Positive supply for peripheral logic and I/O pins.

V VDDCORE P — CPU logic filter capacitor connection.

SS P — Ground reference for logic and I/O pins.

V VREF+ I Analog Analog voltage reference (high) input.

REF- I Analog Analog voltage reference (low) input.

V

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Type

I/O I/O I/O

I/O I/O

I/O ST PORTF is a b idirectional I/O port.

I/O I/O I/O

I/O

I

O I/O I/O

I

O I/O

I/O I/O I/O I/O

I

O

I I I

O

I I I I I I I I I

I

O

I

O

I

O

I

O

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST ST ST

ST ST

ST ST ST

ST ST

ST ST ST

ST ST

ST ST ST

ST/CMOS—32.768 kHz low-pow er oscillator crystal input; CMOS ot herwise.

ST ST ST

ST ST ST ST ST ST ST ST ST

ST

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out.

—

SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out.

—

SPI2 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2.

32.768 kHz low-pow er oscillator crystal output. JTAG Test mode select pin.

JTAG test clock input pin. JTAG test data input pin.

—

JTAG test data output pin. Timer1 external clock input.

Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input.

UART1 clear to send.

—

UART1 ready to send. UART1 receive.

—

UART1 transmit. UART2 clear to send.

—

UART2 ready to send. UART2 receive.

—

UART2 transmit.

Description

dsPIC33F

2.0 CPU

Note: This data sheet summarizes the features

of this group of dsPIC33F devices. It is not intended to be a compr ehensive refer ence source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).

The dsPIC33F CPU module has a 16-bit (data) modified Harvard archit ecture with an enha nced instruction set, including significant support for DSP. The CPU has a 24-bit instructio n word with a variab le length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 2 4 bits of user prog ram memory space. The actual amount of program memory implemented varies by de v ice. A single-cycle instr uction prefetch mecha ni sm i s used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instructio n and the tabl e instructions . Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at an y po in t.

The dsPIC33F devices have sixteen, 16-bit working registers in th e programmer’s model . Each of the workin g registers can s erve as a d ata, ad dres s or ad dr es s offs et register. The 16th working register (W15) operates as a software S tack Pointer (SP) for interrupts a nd c alls .

The dsPIC33F instruction set has two classes of instructions: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the dsPIC33F is shown in Figure 2-2.

2.1 Data Addressing Overview

The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referr ed to as X and Y data memo ry. Each memory block has its own independent Address Genera tion Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y da t a space boundary is device-spec i fic .

Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also support s Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.

The upper 32 Kby tes of the data s pace mem ory map ca n optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data s p a ce .

The data space also includes 2 Kbytes of DMA RAM, which is primarily us ed for DMA dat a transfers, but may be used as general purpose RAM.

2.2 DSP Engine Overview

The DSP engine feature s a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel sh ifter is capa ble of shift ing a 40-bi t value, up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction an d other associated instructions can concurrentl y fetch two dat a operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality req uires that the RAM memory d ata sp ace be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible mann er thro ugh d edica ting c ert ain w orkin g registers to each address space.

2.3 Special MCU Features

The dsPIC33 F fea tur es a 17-bi t by 17-b it, sing le-c ycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0).

The dsPIC33F supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit, left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.

dsPIC33F

FIGURE 2-1: dsPIC33F CPU CORE BLOCK DIAGRAM

PSV & Table Data Access

Control Block

Y Data Bus

Interrupt

Controller

23

Address Latch

Program Memory

Data Latch

23

8

PCH PCL

PCU

Program Counter

Stack

Control

Logic

Address Bus

24

Instruction

Decode &

Control

Control Signals

to Various Blocks

16

Loop

Control

Logic

X Data Bus

16

Data Latch

X RAM

Address

Latch

Address Generator Units

ROM Latch

Instruction Reg

DSP Engine

Divide Support

16

Data Latch

Y RAM

Address

Latch

16

EA MUX

16

Literal Data

16 x 16

W Register Array

Controller

16

DMA RAM

DMA

16

16-bit ALU

16

To Peripheral Modules

MICROCHIP dsPIC33F Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Operating Range:

High-Performance DSC CPU:

Direct Memory Access (DMA):

Digital I/O:

On-Chip Flash and SRAM:

System Management:

Power Management:

Interrupt Controller:

Timers/Capture/Compare/PWM:

Communication Modules:

Motor Control Peripherals:

Analog-to-Digit al Converters (ADCs):

CMOS Flash T echnology:

Packaging:

dsPIC33F PRODUCT FAMILIES

dsPIC33F General Purpose Family Variants

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

dsPIC33F Motor Control Family Variants

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC33F GENERAL BLOCK DIAGRAM

2.0 CPU

2.1 Data Addressing Overview

2.2 DSP Engine Overview

2.3 Special MCU Features

FIGURE 2-1: dsPIC33F CPU CORE BLOCK DIAGRAM