MICROCHIP dsPIC30F5015, dsPIC30F5016 Technical data

dsPIC30F5015/5016

Data Sheet

High-Performance

Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEEL

code hopping

dsPIC30F5015/5016

dsPIC30F5015/5016 Enhanced Flash

16-bit Digital Signal Controller

Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the

Family Reference Manual

information on the device instruction set and programming, refer to the

Reference Manual

(DS70030).

(DS70046). For more

dsPIC30F Programmer’s

dsPIC30F

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

with flexible Addressing modes

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• 66 Kbytes on-chip Flash program space

(Instruction words)

• 2 Kbytes of on-chip data RAM

• 1 Kbytes of nonvolatile data EEPROM

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• 36 interrupt sources

- 5 external interrupt sources

- 8 user selectable priority levels for each interrupt source

- 4 processor trap sources

• 16 x 16-bit working register array

DSP Engine Features:

• Dual data fetch

• Accumulator write back for DSP operations

• Modulo and Bit-Reversed Addressing modes

• Two, 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier

• All DSP instructions single cycle

• ±16-bit single-cycle shift

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25 mA

•Timer module with programmable prescaler:

- Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

•3-wire SPITM modules (supports 4 Frame modes)

•I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing

• 1 UART modules with FIFO Buffers

• 1 CAN modules, 2.0B compliant

Motor Control PWM Module Features:

• 8 PWM output channels

- Complementary or Independent Output

modes

- Edge and Center-Aligned modes

• 4 duty cycle generators

• Dedicated time base

• Programmable output polarity

• Dead-Time control for Complementary mode

• Manual output control

• Trigger for A/D conversions

Quadrature Encoder Interface Module Features:

• Phase A, Phase B and Index Pulse input

• 16-bit up/down position counter

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Interrupt on position counter rollover/underflow

dsPIC30F5015/5016

Analog Features:

• 10-bit Analog-to-Digital Converter (A/D) with 4 S/H Inputs:

- 1 Msps conversion rate

- 16 input channels

- Conversion available during Sleep and Idle

• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip, low-power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation detects clock failure and switches to on-chip, low-power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes

- Sleep, Idle and Alternate Clock modes

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

CMOS Technology:

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low-power consumption

dsPIC30F Motor Control and Power Conversion Family*

Program

Device Pins

dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1

dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 -

dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1

dsPIC30F5015 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F5016 80 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

* This table provides a summary of the dsPIC30F5015/5016 peripheral features. Other available devices in the dsPIC30F Motor

Control and Power Conversion Family are shown for feature comparison.

Mem. Bytes/ Instructions

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

Input

Cap

Output

Comp/Std

PWM

Motor

Control

PWM

A/D 10-bit

1 Msps

Quad

Enc

UART

SPI

CAN

Pin Diagram

80-Pin TQFP

PWM3L/RE4

dsPIC30F5015/5016

CN16/UPDN/RD7

CN14/RD5

PWM2L/RE2

PWM1L/RE0

RG0

RG1

C1TX/RF1

C1RX/RF0

PWM2H/RE3

PWM1H/RE1

CN15/RD6

VSS

CN13/RD4

RD12

OC4/RD3

OC3/RD2

CN19/RD13

EMUD2/OC2/RD1

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

T2CK/RC1 T4CK/RC3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD

FLTA/INT1/RE8

FLTB/INT2/RE9

AN5/QEB/CN7/RB5

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

/CN4/RB2

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

2324252627282930313233

REF-/RA9

AN7/RB7

VREF+/RA10

AN6/OCFA/RB6

767877

AVSS

727473

7170696867666564636261

dsPIC30F5016

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI

CN17/RF4

AN12/RB12

AN13/RB13

CN20/RD14

AN14/RB14

CN21/RD15

AN15/CN12/RB15

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

U1RX/RF2

U1TX/RF3

CN18/RF5

Note: Pinout subject to change.

dsPIC30F5015/5016

Pin Diagram

64-Pin TQFP

PWM3L/RE4

PWM2H/RE3

PWM2L/RE2

PWM1H/RE1

UPDN/CN16/RD7

C1TX/RF1

VDD

C1RX/RF0

CN15/RD6

IC6/CN14/RD5

IC5/CN13/RD4

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

PWM1L/RE0

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1

AN1/V

AN0/V

MCLR

SS2

/CN11/RG9

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

VSS

VDD

545352

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 36 14 15 16

171819202122232425

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

dsPIC30F5015

AVSS

AN8/RB8

AN9/RB9

VDD

AN11/RB11

AN10/RB10

AN12/RB12

504951

48 47 46 45 44 43 42 41 40 39 38 37

35 34 33

CN18/RF5

CN17/RF4

AN13/RB13

AN14/RB14

AN15/CN12/RB15

EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V

OSC2/CLKO/RC15 OSC1/CLKI

V SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3

Note: Pinout subject to change.

dsPIC30F5015/5016

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 CPU Architecture Overview........................................................................................................................................................ 15

3.0 Memory Organization ................................................................................................................................................................. 23

4.0 Address Generator Units............................................................................................................................................................ 35

5.0 Interrupts.................................................................................................................................................................................... 41

6.0 Flash Program Memory.............................................................................................................................................................. 49

7.0 Data EEPROM Memory ............................................................................................................................................................. 55

8.0 I/O Ports ..................................................................................................................................................................................... 59

9.0 Timer1 Module ........................................................................................................................................................................... 65

10.0 Timer2/3 Module ........................................................................................................................................................................ 69

11.0 Timer4/5 Module ....................................................................................................................................................................... 75

12.0 Input Capture Module ................................................................................................................................................................ 79

13.0 Output Compare Module............................................................................................................................................................ 83

14.0 Quadrature Encoder Interface (QEI) Module ............................................................................................................................. 87

15.0 Motor Control PWM Module ....................................................................................................................................................... 93

16.0 SPI™ Module ........................................................................................................................................................................... 103

17.0 I2C Module............................................................................................................................................................................... 107

18.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 115

19.0 CAN Module............................................................................................................................................................................. 123

20.0 10-bit High-Speed Analog-to-Digital Converter (A/D) Module.................................................................................................. 133

21.0 System Integration ................................................................................................................................................................... 145

22.0 Instruction Set Summary .......................................................................................................................................................... 161

23.0 Development Support............................................................................................................................................................... 169

24.0 Electrical Characteristics .......................................................................................................................................................... 173

25.0 Packaging Information.............................................................................................................................................................. 217

Appendix A: Revision History............................................................................................................................................................. 221

Index ................................................................................................................................................................................................. 223

The Microchip Web Site..................................................................................................................................................................... 229

Customer Change Notification Service .............................................................................................................................................. 229

Customer Support .............................................................................................................................................................................. 229

Reader Response .............................................................................................................................................................................. 230

Product Identification System ............................................................................................................................................................ 231

TO OUR VALUED CUSTOMERS

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes features of this

group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the

Family Reference Manual

information on the device instruction set and programming, refer to the

Reference Manual

This document contains device specific information for the dsPIC30F5015 and dsPIC30F5016 devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture.

(DS70030).

(DS70046). For more

dsPIC30F Programmer’s

dsPIC30F

Figure 1-1 is a block diagram of the dsPIC30F5015 device. Following the block diagram, Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the dsPIC30F5015.

Figure 1-2 is a block diagram of the dsPIC30F5016 device. Following the block diagram, Table 1-2 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the dsPIC30F5016.

dsPIC30F5015/5016

FIGURE 1-1: dsPIC30F5015 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(66 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals to Various Blocks

OSC1/CLKIN

Instruction

Decode &

Control

Timing

Generation

MCLR

VDD, VSS

AVDD, AVSS

PSV & Table Data Access

Control Block

Y Data Bus

PCU

Program Counter

Stac k

Control

Logic

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

PCH PCL

Loop

Control

Logic

Decode

Y AGU

DSP

Engine

X Data Bus

Y Data

RAM

(1 Kbyte)

Address

Latch

Effective Address

Data LatchData Latch

X RAGU X WAGU

16 x 16

W Reg Array

Divide

ALU<16>

X Data

RAM

(1 Kbyte)

Address

Latch

Unit

PORTB

PORTC

PORTD

AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/CN6/RB4 AN5/QEB/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 AN9/RB9 AN10/RB10

AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/CN12/RB15

EMUD1/SOSCI/T4CK/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 IC5/CN13/RD4 IC6/CN14/RD5 CN15/RD6 UPDN/CN16/RD7 IC1/FLTA/INT1/RD8 IC2/FLTB/INT2/RD9 IC3/INT3/RD10 IC4/INT4/RD11

CAN1

SPI1, SPI2

10-bit ADC

Timers

Input

Capture

Module

QEI

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2

Output

Compare

Module

Motor Control

PWM

SCL/RG2

SDA/RG3

/CN11/RG9

I2C™

UART1

PORTG PORTF

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7

PORTE

C1RX/RF0 C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 CN17/RF4 CN18/RF5 EMUC3/SCK1/INT0/RF6

dsPIC30F5015/5016

Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the dsPIC30F5015 device. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015

Pin Name

AN0-AN15 I Analog Analog input channels.

DD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKIN CLKO

CN0-CN18 I ST Input change notification inputs.

C1RX C1TX

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3

IC1-IC4 I ST Capture inputs 1 through 4.

INDX QEA

QEB

UPDN

INT0 INT1 INT2 INT3 INT4

FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I/O I/O I/O I/O I/O I/O I/O I/O

I I

I I I I I

I O O O O O O O O

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

AN0 and AN1 are also used for device programming data and clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

—

ST ST ST ST ST ST ST ST

ST ST

CMOS

ST ST ST ST ST

ST ST

— — — — — — — —

CAN1 bus receive pin. CAN1 bus transmit pin.

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin.

Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. PWM 3 High output. PWM 4 Low output. PWM 4 High output.

Description

dsPIC30F5015/5016

TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015 (CONTINUED)

Pin Name

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-

OCFA OC1-OC4

OSC1

OSC2

PGD PGC

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC13-RC15 I/O ST PORTC is a bidirectional I/O port.

RD0-RD11 I/O ST PORTD is a bidirectional I/O port.

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF0-RF6 I/O ST PORTF is a bidirectional I/O port.

RG2-RG3 RG6-RG9

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL SDA

SOSCO SOSCI

T1CK T4CK

U1RX U1TX

DD P — Positive supply for logic and I/O pins.

SS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I/O

I/O I/O

I/O

I/O I/O

I I

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

low Reset to the device.

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST ST

— ST ST ST

— ST

ST ST

—

ST/CMOS

ST ST

—

Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare outputs 1 through 4.

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI™ #1. SPI #1 Data In. SPI #1 Data Out. SPI #1 Slave Synchronization. Synchronous serial clock input/output for SPI #2. SPI #2 Data In. SPI #2 Data Out. SPI #2 Slave Synchronization.

Synchronous serial clock input/output for I Synchronous serial data input/output for I

32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Timer1 external clock input. Timer4 external clock input.

UART1 Receive. UART1 Transmit.

Description

C™.

FIGURE 1-2: dsPIC30F5016 BLOCK DIAGRAM

dsPIC30F5015/5016

Interrupt

Controller

Address Latch

Program Memory

(66 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals to Various Blocks

OSC1/CLKIN

Instruction

Decode &

Control

Timing

Generation

MCLR

VDD, VSS

AVDD, AVSS

CAN1

SPI1, SPI2

PSV & Table Data Access

Control Block

10-bit ADC

Timers

Y Data Bus

PCH PCL

PCU

Program Counter

Stac k

Control

Logic

ROM Latch

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

Loop

Control

Logic

Input

Capture

Module

QEI

Decode

DSP Engine

Y Data

RAM

(1 Kbyte)

Address

Latch

Y AGU

Effective Address

Output

Compare

Module

Motor Control

PWM

X Data Bus

X RAGU X WAGU

16 x 16

W Reg Array

ALU<16>

Data LatchData Latch

X Data

RAM

(1 Kbyte)

Address

Latch

Divide

Unit

I2C™

UART1

PORTA

PORTB

PORTC

PORTD

PORTE

VREF-/RA9 VREF+/RA10 INT3/RA14 INT4/RA15

PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/CN6/RB4 AN5/QEB/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 AN9/RB9 AN10/RB10

AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/CN12/RB15

T2CK/RC1 T4CK/RC3 EMUD1/SOSCI/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 CN13/RD4 CN14/RD5 CN15/RD6 CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 RD12 CN19/RD13 CN20/RD14 CN21/RD15

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9

RG0 RG1

SCL/RG2

SDA/RG3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2

/CN11/RG9

PORTG PORTF

C1RX/RF0 C1TX/RF1 U1RX/RF2

U1TX/RF3 CN17/RF4 CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8

dsPIC30F5015/5016

Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the dsPIC30F5016. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-2: I/O PIN DESCRIPTIONS For dsPIC30F5016

Pin Name

AN0-AN15 I Analog Analog input channels.

DD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKIN CLKO

CN0-CN21 I ST Input change notification inputs.

C1RX C1TX

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3

IC1-IC4 I ST Capture inputs 1 through 8.

INDX QEA

QEB

UPDN

INT0 INT1 INT2 INT3 INT4

FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I/O I/O I/O I/O I/O I/O I/O I/O

I I

I I I I I

I O O O O O O O O

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

AN0 and AN1 are also used for device programming data and clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

—

ST ST ST ST ST ST ST ST

ST ST

CMOS

ST ST ST ST ST

ST ST

— — — — — — — —

CAN1 bus receive pin. CAN1 bus transmit pin.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. PWM 3 High output. PWM 4 Low output. PWM 4 High output.

Description

dsPIC30F5015/5016

TABLE 1-2: I/O PIN DESCRIPTIONS For dsPIC30F5016 (CONTINUED)

Pin Name

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-

OCFA OCFB OC1-OC4

OSC1

OSC2

PGD PGC

RA9-RA10 RA14-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1 RC3 RC13-RC15

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE9 I/O ST PORTE is a bidirectional I/O port.

RF0-RF8 I/O ST PORTF is a bidirectional I/O port.

RG0-RG3 RG6-RG9

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL SDA

SOSCO SOSCI

T1CK T2CK T4CK

U1RX U1TX

DD P — Positive supply for logic and I/O pins.

SS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I I

I/O

I/O I/O

I/O I/O I/O

I/O I/O

I/O

I/O I/O

I I I

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

low Reset to the device.

ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST ST

ST ST ST

ST ST

— ST ST ST

— ST

ST ST

—

ST/CMOS

ST ST ST

—

Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare Fault B input (for Compare channels 5, 6, 7 and 8). Compare outputs 1 through 4.

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for I Synchronous serial data input/output for I

32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Timer1 external clock input. Timer2 external clock input. Timer4 external clock input.

UART1 Receive. UART1 Transmit.

Description

C™.

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

2.0 CPU ARCHITECTURE OVERVIEW

Note: This data sheet summarizes features of this

group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the

Family Reference Manual

information on the device instruction set and programming, refer to the

Reference Manual

This document provides a summary of the dsPIC30F5015/5016 CPU and peripheral function. For a complete description of this functionality, please refer

dsPIC30F Family Reference Manual

to the

(DS70030).

(DS70046). For more

dsPIC30F Programmer’s

2.1 Core Overview

The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear (see Section 3.1 “Program Address Space”), and the Most Significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The working register array consists of 16x16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2 “Data Address Space”). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes.

dsPIC30F

(DS70046).

There are two methods of accessing data stored in program memory:

The upper 32 Kbytes of data space memory can be

• mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this

• Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 “Address Generator Units” for details on Modulo and Bit-Reversed Addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined addressing modes, depending upon their functional requirements.

For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 16 bits right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory, while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.

method.

dsPIC30F5015/5016

The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined ‘natural order’. Traps have fixed priorities, ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction

DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte-wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® DSC devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register (SR), the LSB of which is referred to as the SR Low Byte (SRL) and the MSB as the SR High Byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation Status flags (including the Z bit), as well as the CPU Interrupt Priority Level Status bits, IPL<2:0>, and the Repeat Active Status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value which is then stacked.

The upper byte of the SR register contains the DSP Adder/Subtractor Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

dsPIC30F5015/5016

FIGURE 2-1: dsPIC30F5015/5016 PROGRAMMER’S MODEL

D0D15

W0/WREG

DSP Operand Registers

DSP Address Registers

W13/DSP Write Back

W10

W11

W12/DSP Offset

W14/Frame Pointer

W15/Stack Pointer

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31

AccA

AccB

Data Table Page Address

DOSTART

SPLIM Stack Pointer Limit Register

PC0

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOEND

AD15

Program Counter

Repeat Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

STATUS Register

dsPIC30F5015/5016

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The divide instructions must be executed within a Repeat loop. Any other form of execution (e.g. a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value, and it must, therefore, be explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The Repeat loop count must be set up for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The divide flow is interruptible. However,

the user needs to save the context as appropriate.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.sw (or DIV.s) Signed divide: Wm/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.uw (or DIV.u) Unsigned divide: Wm/Wn → W0; Rem → W1

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter, and a 40-bit adder/subtractor (with two target accumulators, round and saturation logic).

The dsPIC30F devices have a single instruction flow which can execute either DSP or MCU instructions. Many of the hardware resources are shared between the DSP and MCU instructions. For example, the instruction set has both DSP and MCU multiply instructions which use the same hardware multiplier.

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1. Fractional or Integer DSP Multiply (IF).

2. Signed or Unsigned DSP Multiply (US).

3. Conventional or Convergent Rounding (RND).

4. Automatic Saturation On/Off for AccA (SATA).

5. Automatic Saturation On/Off for AccB (SATB).

6. Automatic Saturation On/Off for Writes to Data Memory (SATDW).

7. Accumulator Saturation mode Selection (ACCSAT).

Note: For CORCON layout, see Table 4-2.

A block diagram of the DSP engine is shown in Figure 2-2.

TABLE 2-2: DSP INSTRUCTION

SUMMARY

Instruction Algebraic Operation

CLR A = 0

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y)

MOVSAC No change in A

MPY A = x * y

MPY.N A = – x * y

MSC A = A – x * y

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

dsPIC30F5015/5016

S a

Round

Logic

Barrel Shifter

X Data Bus

Zero Backfill

Sign-Extend

Y Data Bus

17-bit

Multiplier/Scaler

To/From W Array

dsPIC30F5015/5016

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or unsigned operations and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value, which is signextended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2 range is -32768 (0x8000) to 32767 (0x7FFF), including

0. For a 32-bit integer, the data range is -2,147,483,648

(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 2 For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF), including 0 and has a precision of 3.01518x10 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661x10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

N-1

to 2

– 1. For a 16-bit integer, the data

-5

. In Fractional mode, a

-10

1-N

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTOR

The data accumulator consists of a 40-bit adder/ subtractor with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtractor, Overflow and Saturation

The adder/subtractor is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/borrow other input is complemented. The adder/subtractor generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register.

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated (bit 39 overflow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated (bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtractor. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active-high and the other input is

input is active-low and the

dsPIC30F5015/5016

The SA and SB bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The Overflow and Saturation Status bits can optionally be viewed in the STATUS register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators.

The device supports three Saturation and Overflow modes.

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13]+ = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LSb (bit 16 of the accumulator) of ACCxH is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory, via the X bus (subject to data saturation, see Section 2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

dsPIC30F5015/5016

2.4.2.4 Data Space Write Saturation

In addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly. For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of ‘0’ will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 15 for left shifts.

dsPIC30F5015/5016

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes features of this

group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the

Family Reference Manual

(DS70046). For more information on the device instruction set and programming, refer to the

Reference Manual

dsPIC30F Programmer’s

(DS70030).

3.1 Program Address Space

The program address space is 4M instruction words. It is addressable by the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space, as defined by Table 3-1. Note that the program space address is incremented by two between successive program words, in order to provide compatibility with data space addressing.

User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, read/write instructions, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear.

dsPIC30F

FIGURE 3-1:

Space

User Memory

PROGRAM SPACE MEMORY MAP FOR dsPIC30F5015/5016

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash Program Memory (22K instructions)

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

000000 000002 000004

Vector Tables

00007E 000080 000084 0000FE 000100

00AFFE 00B000

7FFBFE 7FFC00

7FFFFE 800000

Reserved

8005BE

Space

Configuration Memory

UNITID (32 instr.)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

8005C0

8005FE 800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FFFFFE

dsPIC30F5015/5016

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Access

Space

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User

TBLPAG<7:0> Data EA<15:0>

(TBLPAG<7> = 0)

TBLRD/TBLWT Configuration

TBLPAG<7:0> Data EA<15:0>

(TBLPAG<7> = 1)

Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using Program Counter

Program Space Address

0Program Counter

Select

Using Program Space Visibility

Using Table Instruction

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

1/0

User/ Configuration

Space Select

PSVPAG Reg

8 bits

TBLPAG Reg

8 bits

24-bit EA

15 bits

16 bits

Byte

Select

dsPIC30F5015/5016

3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.

There are two methods by which program space can be accessed; via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2 “Data

Access From Program Memory Using Program Space Visibility”). The TBLRDL and TBLWTL instruc-

tions offer a direct method of reading or writing the least significant word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant word, and TBLRDH and TBLWTH access the space which contains the MSB.

Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

A set of table instructions are provided to move byte or word-sized data to and from program space.

1. TBLRDL: Table Read Low

Word:

Read the least significant word of the program address; P<15:0> maps to D<15:0>.

Byte:

Read one of the LSBs of the program address; P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the destination byte when byte select = 1.

2. TBLWTL: Table Write Low (refer to Section 6.0 “Flash Program Memory” for details on Flash Programming).

3. TBLRDH: Table Read High

Word:

Read the most significant word of the program address; P<23:16> maps to D<7:0>; D<15:8> always be = 0.

Byte:

Read one of the MSBs of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1.

4. TBLWTH: Table Write High (refer to Section 6.0 “Flash Program Memory” for details on Flash Programming).

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

PC Address

0x000000 0x000002

0x000004

0x000006

Program Memory ‘Phantom’ Byte (Read as ‘0’).

00000000

TBLRDL.W

TBLRDL.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

dsPIC30F5015/5016

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB)

TBLRDH.W

PC Address

0x000000 0x000002 0x000004 0x000006

Program Memory ‘Phantom’ Byte (Read as ‘0’)

00000000

TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space, without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs if the MSb of the data space EA is set and program space visibility is enabled, by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 2.4 “DSP Engine”.

Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data.

Although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see Figure 3-5), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer

dsPIC30F Programmer’s Reference Manual

to the (DS70030) for details on instruction encoding.

TBLRDH.B (Wn<0> = 0)

Note that by incrementing the PC by 2 for each program memory word, the Least Significant 15 bits of data space addresses directly map to the Least Significant 15 bits in the corresponding program space addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG<7:0>, as shown in Figure 3-5.

Note: PSV access is temporarily disabled during

table reads/writes.

For instructions that use PSV which are executed outside a Repeat loop:

• The following instructions will require one instruction cycle in addition to the specified execution time:

- MAC class of instructions with data operand

pre-fetch

- MOV instructions

- MOV.D instructions

• All other instructions will require two instruction cycles in addition to the specified execution time of the instruction.

For instructions that use PSV which are executed inside a Repeat loop:

• The following instances will require two instruction cycles in addition to the specified execution time of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the Repeat loop will allow the instruction, accessing data using PSV, to execute in a single cycle.

dsPIC30F5015/5016

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space Program Space

0x0000

0x000100

EA<15> =

Data

Space

BSET CORCON,#2 ; PSV bit set MOV #0x00, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x9200, W0 ; Access program memory location

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

EA<15> = 1

Upper Half of Data Space is Mapped into Program Space

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

; using a data space access

0x8000

0xFFFF

PSVPAG

Address Concatenation

(1)

0x00

23 15 0

Data Read

0x001200

0x017FFE

3.2 Data Address Space

The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.

When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instructions extract the Y address space from data space and address it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions.

A data space memory map is shown in Figure 3-6.

Figure 3-7 shows a graphical summary of how X and Y data spaces are accessed for MCU and DSP instructions.

dsPIC30F5015/5016

FIGURE 3-6: dsPIC30F5015/5016 DATA SPACE MEMORY MAP

2 Kbyte SFR Space

2 Kbyte

SRAM Space

MSB

Address

0x0001

0x07FF

0x0801

0x0BFF

0x0C01

0x0FFF 0x0FFE

0x1FFF 0x1FFE

≈

0x8001

16 bits

LSBMSB

SFR Space

X Data RAM (X)

Y Data RAM (Y)

Unimplemented

0x0000

0x07FE 0x0800

0x0BFE 0x0C00

0x10000x1001

≈

0x8000

LSB

Address

8 Kbyte Near

Data Space

Optionally Mapped into Program Memory

0xFFFF

X Data

Unimplemented (X)

0xFFFE

+ 205 hidden pages

MICROCHIP dsPIC30F5015, dsPIC30F5016 Technical data

High-Performance Modified RISC CPU:

DSP Engine Features:

Peripheral Features:

Motor Control PWM Module Features:

Quadrature Encoder Interface Module Features:

Analog Features:

Special Microcontroller Features:

CMOS Technology:

dsPIC30F Motor Control and Power Conversion Family*

Pin Diagram

Pin Diagram

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC30F5015 BLOCK DIAGRAM

FIGURE 1-2: dsPIC30F5016 BLOCK DIAGRAM

2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

2.2 Programmer’s Model

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

2.2.2 STATUS REGISTER

2.2.3 PROGRAM COUNTER

FIGURE 2-1: dsPIC30F5015/5016 PROGRAMMER’S MODEL

2.3 Divide Support

TABLE 2-1: DIVIDE INSTRUCTIONS

2.4 DSP Engine

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

2.4.1 MULTIPLIER

2.4.3 BARREL SHIFTER

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB)

3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

3.2 Data Address Space

3.2.1 DATA SPACE MEMORY MAP

FIGURE 3-6: dsPIC30F5015/5016 DATA SPACE MEMORY MAP