MICROCHIP dsPIC30F5011, dsPIC30F5013 Technical data

dsPIC30F5011/5013

Data Sheet

High-Performance, 16-bit Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping devices, Serial

dsPIC30F5011/5013

dsPIC30F5011/5013 High-Performance

Digital Signal Controllers

Note: This data sheet summarizes features of this g roup of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more informat ion on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• 66 Kbytes on-chip Fla sh program space

• 4 Kbytes of on-chip data RAM

• 1 Kbyte of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• Up to 41 interrupt sources:

- 8 user selectable priority levels

- 5 external interrupt sources

- 4 processor traps

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25mA

• Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

• Data Converter Interface (DCI) supports common audio codec protocols, including I

• 3-wire SPI modules (supports 4 Frame modes)

•I

C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Two addressable UART modules with FIFO buffers

• Two CAN bus modules compliant with CAN 2.0B standard

S and AC’97

Analog Features:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 ksps conversion rate

- Up to 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:

DSP Features:

• Dual data fetch

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single cycle hardware fractional/ integer multiplier

• All DSP instructions are single cycle

- Multiply-Accumulate (MAC) operation

• Single cycle ±16 shift

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T) and Oscillator Start-up Timer (OST)

• Flexible Wa tchdog T im er (WDT) w ith on -chip l owpower RC oscillator for reliable operation

dsPIC30F5011/5013

Special Microcontroller Features (Cont.):

• Fail-Safe Clock Monitor operation:

- Detects clock failure and swit ches to on-chip low-power RC oscillator

• Programmable code protection

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

dsPIC30F5011/5013 Controller Family

Program Memory

Device Pins

Bytes Instructi ons

dsPIC30F5011 64 66K 22K 4096 1024 5 8 8 AC’97, I dsPIC30F5013 80 66K 22K 4096 1024 5 8 8 AC’97, I

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

Input

Cap

Output

Comp/Std

PWM

Codec

Interface

A/D 12-bit

200 ksps

S 16 ch 2 2 1 2

UART

C™

SPI

CAN

Pin Diagrams

64-Pin TQFP

dsPIC30F5011/5013

CSDO/RG13

CSDI/RG12

CSCK/RG14

C2TX/RG1

C1TX/RF1

C2RX/RG0

OC8/CN16/RD7

VDD

C1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

AN2/SS1

AN1/V

AN0/V

COFS/RG15

T2CK/RC1 T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

/LVDIN/CN4/RB2

MCLR

/CN11/RG9

SS2

AN3/CN5/RB3

REF-/CN3/RB1

REF+/CN2/RB0

VSS VDD

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AVSS

dsPIC30F5011

AN8/RB8

AN9/RB9

545352

VDD

AN11/RB11

AN10/RB10

AN12/RB12

504951

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/INT2/RD9

IC1/INT1/RD8

OSC2/CLKO/RC15

OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

AN13/RB13

AN14/RB14

U2TX/CN18/RF5

U2RX/CN17/RF4

AN15/OCFB/CN12/RB15

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

dsPIC30F5011/5013

Pin Diagrams (Continued)

80-Pin TQFP

CSCK/RG14

CSDO/RG13

CSDI/RG12

CN23/RA7

CN22/RA6

C2RX/RG0

C2TX/RG1

C1TX/RF1

VSS

C1RX/RF0

OC8/CN16/RD7

OC5/CN13/RD4

IC6/CN19/RD13

OC7/CN15/RD6

OC6/CN14/RD5

IC5/RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

COFS/RG15

T2CK/RC1 T3CK/RC2

T4CK/RC3 T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD INT1/RA12 INT2/RA13

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1 PGC/EMUC/AN1/CN3/RB1 PGD/EMUD/AN0/CN2/RB0

1 2

3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19

2324252627282930313233

AN7/RB7

REF-/RA9

AN6/OCFA/RB6

767877

AVSS

VREF+/RA10

727473

7170696867666564636261

dsPIC30F5013

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AN12/RB12

AN13/RB13

AN14/RB14

IC8/CN21/RD15

IC7/CN20/RD14

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15

INT3/RA14

V OSC2/CLKO/RC15

OSC1/CLKI

V SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3

U2TX/CN18/RF5

AN15/OCFB/CN12/RB15

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

dsPIC30F5011/5013

Table of Contents

1.0 Device Overview..........................................................................................................................................................................7

2.0 CPU Architecture Overview........................................................................................................................................................13

3.0 Memory Organization................................................................................................................................................................. 23

4.0 Address Generator Units............................................................................................................................................................ 35

5.0 Interrupts....................................................................................................................................................................................41

6.0 Flash Program Memory............................................................................. ................................................................................. 47

7.0 Data EEPROM Memory................... .......................................................................................................................................... 53

8.0 I/O Ports..................................................................................................................................................................................... 59

9.0 Timer1 Module ........................................................................................................................................................................... 65

10.0 Timer2/3 Module ............................................................................ .. .. ....... .. .. .. .... .. .. .. ..... ............................................................ 69

11.0 Timer4/5 Module ............................................................................... .. ....... .. .. .. .... .. .. ..... ............................................................ 75

12.0 Input Capture Module..................................................................... .. .... ....... .. .. .... .. .. .. ....... .......................................................... 79

13.0 Output Compare Module..................................................................................... ....................................................................... 83

14.0 SPI Module.................................................................................................................................................................................87

15.0 I2C Module................................................................................................................................................................................. 91

16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 99

17.0 CAN Module .............................................................................................................................................................................107

18.0 Data Converter Interface (DCI) Module....................................................................................................................................119

19.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 129

20.0 System Integration................................... ................................................................................................................................139

21.0 Instruction Set Summary..........................................................................................................................................................155

22.0 Development Support............................................................................................................................................................... 163

23.0 Electrical Characteristics..........................................................................................................................................................167

24.0 Packaging Information. ................................................................. ............................................................................................ 207

Index .................................................................................................................................................................................................. 213

The Microchip Web Site..................................................................................................................................................................... 219

Customer Change Notification Service .............................................................................................................................................. 219

Customer Support.............................................................................................................................................................................. 219

Reader Response.............................................................................................................................................................................. 220

Product Identification System............................................................................................................................................................ 221

dsPIC30F5011/5013

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

dsPIC30F5011/5013

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes features of this g roup

of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more informat ion on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual“ (DS70157).

This document contains specific information for the dsPIC30F5011/5013 Digital Signal Controller (DSC) devices. The dsPIC30F5011/5013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC 30F5011 and dsPIC30F5013, respectively.

dsPIC30F5011/5013

FIGURE 1-1: dsPIC30F5011 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(66 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

Generation

Instruction

Decode &

Control

Timing

MCLR

VDD, V

PSV & Table Data Access

Control Block

, AV

Y Data Bus

PCH PCL

PCU Program Counter

Stack

Control

Logic

Start-up Timer

Low-Voltage

ROM Latch

Power-up

Timer

Oscillator

POR/BOR

Reset

Watchdog

Timer

Detect

Control

Loop Logic

Decode

Y AGU

DSP Engine

X Data Bus

16 16

Y Data

RAM

(2 Kbytes)

Address

Latch

16 X RAGU

X WAGU

Effective Address

16 x 16

W Reg Array

ALU<16>

Data LatchData Latch

X Data

RAM

(2 Kbytes)

Address

Latch

Divide

Unit

PORTB

PORTC

PORTD

AN0/V

REF

+/CN2/RB0

AN1/V

REF

-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7

AN8/RB8 AN9/RB9

AN10/RB10 AN11/RB11 AN12/RB12

AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15

T2CK/RC1 T3CK/RC2 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/IC5/CN13/RD4 OC6/IC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/INT1/RD8 IC2/INT2/RD9 IC3/INT3/RD10 IC4/INT4/RD11

CAN1, CAN2

12-bit ADC

Timers

Input Capture Module

DCI

Output

Compare

Module

SPI1, SPI2

I2C™

UART1,

UART2

PORTF

PORTG

C1RX/RF0 C1TX/RF1

U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6

C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8

/CN11/RG9

SS2 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15

FIGURE 1-2: dsPIC30F5013 BLOCK DIAGRAM

dsPIC30F5011/5013

Interrupt

Controller

Address Latch

Program Memory

(66 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

Generation

Instruction

Decode &

Control

Timing

MCLR

VDD, V

, AV

PSV & Table Data Access Control Block

Stack

Control

Start-up Timer

Low-Voltage

Y Data Bus

PCH PCL

PCU Program Counter

Logic

Power-up

Oscillator

POR/BOR

Watchdog

ROM Latch

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

(2 Kbytes)

Y AGU

DSP Engine

X Data Bus

Y Data

RAM

Address

Latch

Effective Address

Data LatchData Latch

(2 Kbytes)

16 X RAGU

X WAGU

16 x 16

W Reg Array

Divide

Unit

ALU<16>

X Data

RAM

Address

Latch

PORTA

PORTB

PORTC

PORTD

CN22/RA6 CN23/RA7 V

REF

-/RA9

REF

+/RA10

INT1/RA12

INT2/RA13 INT3/RA14 INT4/RA15

PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 AN6/OCFA/RB6 AN7/RB7

AN8/RB8 AN9/RB9

AN10/RB10 AN11/RB11 AN12/RB12

AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15

T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 EMUD1/SOSCI/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15

CAN1, CAN2

12-bit ADC

Timers

Input Capture Module

DCI

Output

Compare

Module

SPI1, SPI2

I2C™

UART1,

UART2

PORTF

PORTG

C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8

C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8

/CN11/RG9

SS2 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15

dsPIC30F5011/5013

Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN15 I Analog A nalog input channels.

DD P P Positive supply for analog module . SS P P Ground reference for analog module.

AV CLKI

CLKO

CN0-CN23 I ST Input change notification inputs.

COFS CSCK CSDI CSDO

C1RX C1TX C2RX C2TX

EMUD EMUC EMUD1

EMUC1 EMUD2 EMUC2 EMUD3

EMUC3 IC1-IC8 I ST Capture inputs 1 through 8. INT0

INT1 INT2 INT3 INT4

LVDIN I Analog Low-Voltage Detect Reference Voltage input pin. MCLR

OCFA OCFB OC1-OC8

Type

I/O I/O

I/O I/O I/O

I/O I/O I/O I/O

I/O

I I I I I

I/P ST Master Clear (Reset) in put or programming voltage input . T his

I I

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

AN0 and AN1 are also used for device programming data and clock inputs, respectivel y.

ST/CMOS—External clock source i nput. Alway s associated wi th OSC1 pin

function. Oscillator crystal outp ut . Co nnects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always ass oc ia te d wi th O SC 2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ST ST ST

—

ST ST ST

ST ST ST ST

ST ST ST ST ST

ST ST

—

Data Converter Interface Fram e Synchronization pin. Data Converter Interface Se rial C l ock in put / output pin. Data Converter Interface Serial data inp ut pin. Data Converter Interface Serial data output pi n.

CAN1 Bus Receive pin. CAN1 Bus Transmit pin. CAN2 Bus Receive pin. CAN2 Bus Transmit pin

ICD Primary Communi cation Channel data input/ou tp ut pi n. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Comm unication Channel cloc k i nput/output pin. ICD T ertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Comm unication Channel clock in put / ou tp ut pi n.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

pin is an active low Reset to the device. Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8). Compare outputs 1 through 8.

Description

dsPIC30F5011/5013

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

OSC1

OSC2

PGD PGC

RA6-RA7 RA9-RA10 RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4

RC13-RC15 RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RF0-RF8 I/O ST PORTF is a bidirectional I/O port. RG0-RG3

RG6-RG9 RG12-RG15

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL SDA

SOSCO SOSCI

T1CK T2CK T3CK T4CK T5CK

U1RX U1TX U1ARX U1ATX U2RX U2TX

DD P — Positive supply for logic and I/O pins. SS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Type

I/O

I/O I/O I/O

I/O I/O

I/O I/O I/O

I/O

I/O I/O

I I I I I

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise. Oscillator crystal outp ut . Co nnects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

ST ST

ST ST ST

ST ST

ST ST ST

ST ST

— ST ST ST

— ST

ST ST

—

ST/CMOS

ST ST ST ST ST

— ST

—

In-Circuit Serial Programmi ng™ data input/output pin. In-Circuit Serial Programmi ng clock input pin.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Synchronous serial clock input/output for SPI2. SPI2 Data In. SPI2 Data Out. SPI2 Slave Synchronization.

Synchronous serial clock input/output for I Synchronous serial data inp ut / out put for I

32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; C M O S ot her w i se.

Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input.

UART1 Receive. UART1 Transmit. UART1 Al t ernate Receive. UART1 Al t ernate Transmit . UART2 Receive. UART2 Transmit.

Description

C™.

dsPIC30F5011/5013

NOTES:

dsPIC30F5011/5013

2.0 CPU ARCHITECTURE OVERVIEW

Note: This data sheet summarizes features of this g roup

2.1 Core Overview

This section contains a brief overview of the CPU architecture of the dsPIC30F. For additional hardware and programming information, please refer to the “dsPIC30F Family Reference Manual” (DS70046) and the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157), respectively.

The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear (refer to Section 3.1 “Program Address Space ”), and the Most Significant bit (MSb) is ignored during no rmal program exec ution, exce pt for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported usin g the DO and REPEAT instructions, both of which are interruptible at any point.

The working registe r array consis ts of 16 x 16-bit re gisters, each of which can act as data, address or offset registers. One working register (W15) operates as a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single unified data space. The Multiply-Accu mulate (MAC) class of dual s ource DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2 “Data Address Space”). The X and Y data space boundary is device specific and cannot be altered by the user . Each dat a word consis ts of 2 bytes, and most instruct ions can address data eith er as words or bytes.

There are two methods of accessing data stored in program memory:

• The upper 32 Kbytes of data space memory can be mapped into the lowe r hal f (us er space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVP AG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within program space is als o possibl e using any work ing register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports bit-reversed addressing on destination ef fect ive ad dresse s to great ly sim plify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 “Address Generator Units” for details on modulo and bit-reversed addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.

For most i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional b arre l s hi fter. Data in the accumulator or any wor kin g regi ste r can be sh ifted up to 15 bi ts right, or 16 bits left in a single cycle. The DSP instructions operate seamles sly with all other in struct ion s and have been desi gned for o ptimal re al-time p erformanc e. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transpar en t and fle xib le mann er, by dedicating certai n working registe rs to eac h address spac e for the MAC class of instructions.

dsPIC30F5011/5013

The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) a nd 54 int errup ts. Each interrupt is prioritized based on a use r assigned pr iority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temp orary holding reg ister and can transfer it s con ten ts to or from its host reg is ter upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register , only th e Least Significan t Byte (LSB) of th e targ et register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes (MSBs) can be manipulated through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® DSC devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine ca lls and return s. However , W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register (SR), the LSB of which is referred to as the SR Low byte (SRL) and the MSB as the SR High byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags (including the Z bit), as wel l as the CPU Inter rupt Pri ority Level status bits, IPL<2:0> and the Repeat Active Status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

dsPIC30F5011/5013

W0/WREG

W1 W2 W3 W4 W5

W6 W7

W8 W9 W10 W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31 AccA AccB

Data Table Page Address

DOSTART

SPLIM Stack Pointer Limit Register

PC0

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOEND

AD15

Program Counter

REPEAT Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

STATUS Register

dsPIC30F5011/5013

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed fractional divide ope rati on , as w ell as 32/16-bit and 16/ 16-bit signed an d unsigned intege r divide operati ons, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.sw - 16/16 signed divide

5. DIV.uw - 16/16 unsigned divide The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or sign-extended during the first iteration.

The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the REPEAT instruction as shown in T able 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The divide flow is interruptible. However,

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw or DIV.s

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.uw or DIV.u

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

the user needs to save the context as appropriate.

dsPIC30F5011/5013

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no ad ditional dat a. These instr uctions are ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concu rrently by the s ame instruction (e.g., ED, EDAC).

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y) Yes MAC A = A + x

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 3-3.

A block diagram of the DSP engine is shown in Figure 2-2.

No No

dsPIC30F5011/5013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

Round

Logic

S a

Y Data Bus

Sign-Extend

17-bit

Multiplier/Scaler

Barrel Shifter

X Data Bus

Zero Backfill

To/From W Array

dsPIC30F5011/5013

2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or unsigned operati on and can mul tiplex i ts ou tput usi ng a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-exten ded into the 17th bit of the mu ltiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s compleme nt in teger i s -2 For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the M SB is defined as a sign b it and the radix point is impl ied to lie just after the sign b it (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 2 16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10 multiply operation generates a 1.31 product which has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or word sized operands. By te opera nds wil l direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

-5

. In Fractional mode, the 16x16

-10

N-1

to 2

1-N

N-1

– 1.

). For a

2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or load ed ca n be optio nally sca led v ia th e barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one si de and e ither true , or comp leme nt data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/bo rrow other input is complemented. The adder/subtracter generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated (bit 39 overflow and s aturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated (bit 39 overflow and s aturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active high and the other input is

input is active low and the

dsPIC30F5011/5013

The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, th ey indicate th at the accumulator has overfl owed it s m aximum range (b it 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB defa ult to bit 3 9 overflow and thus in di ca te th at a c ata str o ph ic ov erf l ow h as occurred. If the COVT E bit in th e INTCO N1 regi ster is set, SA and SB bits wil l gene rate an arithmeti c warnin g trap when saturation is disabled.

The overflow and saturation status bits can optionally be viewed in the STATUS register (SR) as the lo gical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has s aturated. T his w ould be us eful for complex number arithmetic which typically uses both the accumulators.

The device supports three Saturation and Overflow modes:

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data, or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow: The bit 39 overflow Status bit from the adder is used to set the SA or SB bit which remain set until cleared by the user. No saturation operation is performed and the ac cumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 regis ter is set, a cat astrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instructio n into data spac e memory. The write is performed across the X bus into combined X and Y address space. The following Addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13]+=2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register . It generates a 16bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is no t indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and ad ds it to the AC CxH w ord (bi t s 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LSb (bit 16 of the accumulator) of ACCxH is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not modified. As sumi ng t hat bi t 16 is effe cti vely r and om in nature, this scheme w i ll re mo ve any rou ndi ng b ias th at may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the c ontents of the target ac cumu la tor to d ata memo ry via th e X bu s (subject to data saturation, see Section 2.4.2.4 “Data Space Write Saturation”). Note that for the MAC cl as s of instructions, the accumulator write back operation will function in the s ame mann er , a ddressing co mbine d MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

dsPIC30F5011/5013

2.4.2.4 Data Space Write Saturation

In addition to adder/subtrac ter saturation, writes to dat a space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tes te d for ove rflo w and adjusted accordingly, For input data greater than 0x007FFF, data written to memory is force d to the maximum positi ve 1. 15 val ue, 0x 7FFF. For input data less than 0xFF8000, da ta wr itten to me mory i s forced to th e maximum negative 1.1 5 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested.

If the SA TDW bi t in the CORCON regis ter is not set , the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single c ycle. The sou rce can be ei ther of th e two DSP accumul ators, or the X bus (t o support multi-bit shifts of register or memory data).

The shifter requi res a signed binary val ue to de term in e both the magnitude (num ber of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of ‘0’ will not modify the operand.

The barrel shifter is 40-bits wide, thereby obtaining a 40-bit result for DSP shift operati ons and a 16- bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shift s, and bit pos itions 0 to 16 for left shift s.

dsPIC30F5011/5013

NOTES:

dsPIC30F5011/5013

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes features of this g roup

3.1 Program Address Space

The program address space is 4M instruction words. It is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1. Note that the program space address i s incr ement ed by two betw een suc cessive program words in order to provide compatibility with data space addressing.

User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, Program Space Address Construction, bit23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear.

FIGURE 3-1: PROGRAM SPACE

MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

Space

User Memory

User Flash Program Memory (22K instructions)

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

000000 000002 000004

Vector Tables

00007E 000080 000084 0000FE 000100

00AFFE 00B000

7FFBFE 7FFC00

7FFFFE 800000

Reserved

8005BE

Space

Configuration Memory

UNITID (32 instr.)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

8005C0 8005FE

800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FFFFFE

dsPIC30F5011/5013

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User

TBLRD/TBLWT Configuration

Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

Access

Space

(TBLPAG<7> = 0)

(TBLPAG<7> = 1)

<23> <22:16> <15> <14:1> <0>

TBLPAG<7:0> Data EA<15:0>

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using Program Counter

Program Space Address

0Program Counter

Select

Using Program Space

Visibility

Using Table Instruction

User/ Configuration Space Select

Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory.

PSVPAG Reg

1/0

TBLPAG Reg

8 bits

24-bit EA

15 bits

16 bits

Byte

Select

dsPIC30F5011/5013

3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

This architecture fetc hes 24 -bi t w ide prog ram me mo ry. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.

There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16 K word program space p age in to the upper half o f da ta space (see Section 3.1.2 “Data

Access from Program Memory Using Program Space Visibility”). The TBLRDL and TBLWTL instruc-

tions offer a direct m ethod of reading or w riting the least significant word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits o f a pro gram s pa ce word can be acc esse d as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address sp ac es , res id ing sid e by si de, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH a nd TBLWTH ac cess the sp ace which contains the Most Significant data Byte.

Figure 3-2 shows how the EA is created for t a ble operations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

A set of table in st ruc tion s a re provided to move by te or word sized data to and from program space.

1. TBLRDL: Table Read Low Word: Read the lsw of the program address; P<15:0> maps to D<15:0>. Byte: Read one of the LSBs of the program address; P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the d estination b yte when byte select = 1.

2. TBLWTL: Table Write Low (ref er t o Section 6.0 “Flash Program Memory” for details on Flash Programming)

3. TBLRDH: Table Read High Word: Read th e most significa nt wor d of the program address; P<23:16> maps to D<7:0>; D<15:8> will always be = 0. Byte: Read one of the MSBs of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1.

4. TBLWTH: Table Wri te Hi gh (ref er to Section 6.0 “Flash Program Memory” for details on Flash Programming)

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

PC Address

0x000000 0x000002 0x000004 0x000006

Program Memory ‘Phantom’ Byte (read as ‘0’)

00000000

TBLRDL.W

TBLRDL.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

dsPIC30F5011/5013

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)

TBLRDH.W

PC Address

0x000000 0x000002 0x000004 0x000006

Program Memory ‘Phantom’ Byte (read as ‘0’)

00000000

TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instru cti ons).

Program space access through the data space occurs if the MSb of the data space EA is set and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 2.4, DSP Engine.

Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program sp ace mapp ing to acc ess this memory region , Y d at a space should ty pic al ly contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data.

Although each da ta sp ace addres s, 0x8000 and higher , maps directly into a corresponding program memory address (see Figure 3-5), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits shoul d be progra mmed to forc e an illeg al instruction to maintain machine robustness. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on instruction encoding.

TBLRDH.B (Wn<0> = 0)

Note that by incrementing the PC by 2 for each program memory word, the Least Significant 15 bits of data space addresses directly map to the Least Significant 15 bits in the corresponding program space addresses. The rem aining b its a re provid ed by th e Program Space Vis ibilit y Page regi ster, PSVPAG<7:0>, as shown in Figure 3-5.

Note: PSV access is temporarily disabled during

table reads/writes.

For instructions that use PSV which are executed outside a REPEAT loop:

• The following instructions will require one instruction cycle in addition to the specified execution time:

- MAC class of instructions with data operand

prefetch

- MOV instructions

- MOV.D instructions

• All other instructions will require two instruction cycles in addition to the specified execution time of the instruction.

For instructions that use PSV which are executed inside a REPEAT loop:

• The following inst ances wi ll require two ins truction cycles in addition to the specified execution time of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.

dsPIC30F5011/5013

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space Program Space

0x0000

0x000100

0x01

(1)

23 15 0

Data Read

0x008000

0x017FFF

EA<15> =

Data Space EA

EA<15> = 1

Upper Half of Data Space is Mapped into Program Space

BSET CORCON,#2 ; PSV bit set MOV #0x01, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x8000, W0 ; Access program memory location

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines

the page in program space to which the upper half of data space is being mapped).

; using a data space access

0x8000

0xFFFF

PSVPAG

Address

Concatenation

3.2 Data Address Space

The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (fo r MCU instructions). The dat a spaces are accessed using tw o Address Generation Units (AGUs) and separate data paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and Y data space. A key ele me nt of th is archi tec ture is th at Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.

dsPIC30F5011/5013

When executing any instruction other than one of the MAC class of instructio ns, the X block con sists of the 6 4Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instruc tions ext ract the Y address sp ace

FIGURE 3-6: DAT A SPACE MEMORY MAP

2 Kbyte SFR Space

4 Kbyte

SRAM Space

MSB

Address

0x0001

0x07FF 0x0801

0x0FFF 0x1001

0x17FF 0x17FE

16 bits

SFR Space

X Data RAM (X)

Y Data RAM (Y)

from data space and address it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 an d W9. Both addres s spaces a re concurrently accessed only with the MAC class instructions.

The data space memory map is shown in Figure 3-6. The X data space is used by all instructions and supports all Addressing modes, as shown in Figure 3-7.

LSB

Address

LSBMSB

0x0000

0x07FE 0x0800

0x0FFE 0x1000

0x18000x1801

8 Kbyte Near Data Space

Optionally Mapped into Program Memory

0x8001

0xFFFF

0x1FFE 0x1FFF

0x8000

X Data

Unimplemented (X)

0xFFFE

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