MICROCHIP dsPIC30F5011, dsPIC30F5013 Technical data

dsPIC30F5011, dsPIC30F5013

Data Sheet

High-Performance

Digital Signal Controllers

 2004 Microchip Technology Inc. Preliminary DS70116C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEEL

®

OQ

code hopping

DS70116C-page ii Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

dsPIC30F5011/5013 High Performance

Digital Signal Controllers

High Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• 66 Kbytes on-chip Flash program space

• 4 Kbytes of on-chip data RAM

• 1 Kbytes of non-volatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)

• Up to 41 interrupt sources:

- 8 user selectable priority levels

- 5 external interrupt sources

- 4 processor traps

DSP Features:

• Dual data fetch

• Modulo and Bit-reversed modes

• Two 40-bit wide accumulators with optional
saturation logic

• 17-bit x 17-bit single cycle hardware fractional/
integer multiplier

• All DSP instructins are single cycle

- Multiply-Accumulate (MAC) operation

• Single cycle ±16 shift

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

• Five 16-bit timers/counters; optionally pair up 16­bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions:

• Data Converter Interface (DCI) supports common
audio Codec protocols, including I

• 3-wire SPI™ modules (supports 4 Frame modes)

2

S and AC’97

•I2C™ module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing

• Two addressable UART modules with FIFO
buffers

• Two CAN bus modules compliant with CAN 2.0B
standard

Analog Features:

• 12-bit Analog-to-Digital Converter (A/D) with:

- 100 Ksps conversion rate

- Up to 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset
generation

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip

low power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low power, high speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

 2004 Microchip Technology Inc. Preliminary DS70116C-page 1

dsPIC30F5011/5013

dsPIC30F5011/5013 Controller Family

Program Memory

Device Pins

Bytes Instructions

SRAM
Bytes

EEPROM

Bytes

Timer
16-bit

Input

dsPIC30F5011 64 66K 22K 4096 1024 5 8 8 AC’97, I
dsPIC30F5013 80 66K 22K 4096 1024 5 8 8 AC’97, I

Pin Diagrams

64-Pin TQFP

SS

CSDO/RG13

CSDI/RG12

CSCK/RG14

C2TX/RG1

C1TX/RF1

C2RX/RG0

OC8/CN16/RD7

V

VDD

C1RX/RF0

OC7/CN15/RD6

Cap

OC6/IC6/CN14/RD5

Output

Comp/Std

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

PWM

EMUD2/OC2/RD1

Codec

Interface

A/D 12-bit

100 Ksps

2

S 16 ch 2 2 1 2

2

S 16 ch 2 2 1 2

UART

™

SPI

C™

2

I

CAN

AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4

AN2/SS1

AN1/V

AN0/V

COFS/RG15

T2CK/RC1
T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

/LVDIN/CN4/RB2

MCLR

/CN11/RG9

SS2

AN3/CN5/RB3

REF-/CN3/RB1

REF+/CN2/RB0

VSS
VDD

646362616059585756

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

171819202122232425

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

DD

AV

AVSS

dsPIC30F5011

AN8/RB8

AN9/RB9

545352

55

27

26

SS

V

VDD

AN11/RB11

AN10/RB10

AN12/RB12

504951

48

EMUC1/SOSCO/T1CK/CN0/RC14

47

EMUD1/SOSCI/T4CK/CN1/RC13

46

EMUC2/OC1/RD0
IC4/INT4/RD11

45
44

IC3/INT3/RD10

IC2/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKI

38

V

DD

37

SCL/RG2

36

SDA/RG3

35

EMUC3/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

EMUD3/U1TX/SDO1/RF3

32

31

30

29

28

AN13/RB13

AN14/RB14

U2TX/CN18/RF5

U2RX/CN17/RF4

AN15/OCFB/CN12/RB15

Note: Pinout subject to change.

Note: For descriptions of individual pins, see Section 1.0.

DS70116C-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

dsPIC30F5011/5013

DD

CSCK/RG14

CSDO/RG13

CSDI/RG12

CN23/RA7

CN22/RA6

C2RX/RG0

C2TX/RG1

C1TX/RF1

VSS

C1RX/RF0

OC8/CN16/RD7

V

OC5/CN13/RD4

IC6/CN19/RD13

OC7/CN15/RD6

OC6/CN14/RD5

IC5/RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

COFS/RG15

T2CK/RC1
T3CK/RC2

T4CK/RC3
T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

V

VDD
INT1/RA12
INT2/RA13

AN5/CN7/RB5
AN4/CN6/RB4

AN3/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0

80

79

1
2

3
4
5
6
7
8
9

10

SS

11
12
13
14
15
16
17
18
19

20

21

22

2324252627282930313233

REF-/RA9

AN7/RB7

V

AN6/OCFA/RB6

75

767877

DD

AVSS

AV

VREF+/RA10

727473

7170696867666564636261

dsPIC30F5013

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

DD

V

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

39

38

37

36

35

34

AN12/RB12

AN13/RB13

AN14/RB14

IC8/CN21/RD15

IC7/CN20/RD14

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15

INT3/RA14

SS

V
OSC2/CLKO/RC15

OSC1/CLKI

DD

V
SCL/RG2
SDA/RG3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
U1RX/RF2
U1TX/RF3

40

U2TX/CN18/RF5

AN15/OCFB/CN12/RB15

Note: Pinout subject to change.

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 3

dsPIC30F5011/5013

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 CPU Architecture Overview........................................................................................................................................................ 11

3.0 Memory Organization ................................................................................................................................................................. 21

4.0 Address Generator Units............................................................................................................................................................ 33

5.0 Interrupts .................................................................................................................................................................................... 39

6.0 Flash Program Memory.............................................................................................................................................................. 45

7.0 Data EEPROM Memory ............................................................................................................................................................. 51

8.0 I/O Ports ..................................................................................................................................................................................... 57

9.0 Timer1 Module ........................................................................................................................................................................... 63

10.0 Timer2/3 Module ........................................................................................................................................................................ 67

11.0 Timer4/5 Module ........................................................................................................................................................................ 73

12.0 Input Capture Module ................................................................................................................................................................. 77

13.0 Output Compare Module............................................................................................................................................................ 81

14.0 SPI Module................................................................................................................................................................................. 85

15.0 I2C Module................................................................................................................................................................................. 89

16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 97

17.0 CAN Module............................................................................................................................................................................. 105

18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 117

19.0 12-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 127

20.0 System Integration ................................................................................................................................................................... 135

21.0 Instruction Set Summary .......................................................................................................................................................... 151

22.0 Development Support............................................................................................................................................................... 159

23.0 Electrical Characteristics .......................................................................................................................................................... 165

24.0 Packaging Information.............................................................................................................................................................. 205

Index .................................................................................................................................................................................................. 209

On-Line Support................................................................................................................................................................................. 215

Systems Information and Upgrade Hot Line ...................................................................................................................................... 215

Reader Response .............................................................................................................................................................................. 216

Product Identification System............................................................................................................................................................. 217

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DS70116C-page 4 Preliminary  2004 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

This document contains specific information for the
dsPIC30F5011/5013 Digital Signal Controller (DSC)
devices. The dsPIC30F5011/5013 devices contain
extensive Digital Signal Processor (DSP) functionality
within a high performance 16-bit microcontroller (MCU)
architecture. Figure 1-1 and Figure 1-2 show device
block diagrams for dsPIC30F5011 and dsPIC30F5013
respectively.

dsPIC30F5011/5013

 2004 Microchip Technology Inc. Preliminary DS70116C-page 5

dsPIC30F5011/5013

FIGURE 1-1: dsPIC30F5011 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(144 Kbytes)

Data EEPROM

(4 Kbytes)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

24

Generation

24

24

16

Instruction

Decode &

Control

Timing

MCLR

VDD, V

DD

, AV

AV

PSV & Table

Data Access

Control Block

Control

16

24

Start-up Timer

Low Voltage

SS

SS

Y Data Bus

8

16

PCH PCL

PCU
Program Counter

Stack

Logic

Power-up

Oscillator

POR/BOR

Watchdog

ROM Latch

IR

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

16

Y AGU

DSP
Engine

16

X Data Bus

16 16

16

Y Data

RAM

(4 Kbytes)

Address

Latch

16

16

X RAGU
X WAGU

Effective Address

16

16 x 16

W Reg Array

16

16

ALU<16>

16

Data LatchData Latch

X Data

RAM

(4 Kbytes)

Address

Latch

16

16

Divide

Unit

16

PORTB

PORTC

PORTD

AN0/CN2/RB0
AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7

AN8/RB8
AN9/RB9

AN10/RB10
AN11/RB11
AN12/RB12

AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15

T2CK/RC1
T3CK/RC2
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15

EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11

CAN1,
CAN2

12-bit ADC

Timers

Input
Capture
Module

DCI

Output

Compare

Module

SPI1,
SPI2

I2C™

UART1,

UART2

PORTF

PORTG

C1RX/RF0
C1TX/RF1

U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6

C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8

/CN11/RG9

SS2
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15

DS70116C-page 6 Preliminary  2004 Microchip Technology Inc.

FIGURE 1-2: dsPIC30F5013 BLOCK DIAGRAM

dsPIC30F5011/5013

Interrupt

Controller

Address Latch

Program Memory

(144 Kbytes)

Data EEPROM

(4 Kbytes)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

24

Generation

24

24

16

Instruction

Decode &

Control

Timing

MCLR

VDD, V

DD

, AV

AV

PSV & Table
Data Access

Control Block

Stack

Control

16

24

Start-up Timer

Low Voltage

SS

SS

Y Data Bus

8

16

PCH PCL

PCU
Program Counter

Logic

Power-up

Oscillator

POR/BOR

Watchdog

ROM Latch

IR

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

16

Y AGU

DSP
Engine

16

X Data Bus

16

16

Y Data

RAM

(4 Kbytes)

Address

Latch

16

16
X RAGU

X WAGU

Effective Address

16

16 x 16

W Reg Array

16

16

ALU<16>

16

16

Data LatchData Latch

X Data

RAM

(4 Kbytes)

Address

Latch

16

16

Divide

Unit

16

PORTA

PORTB

PORTC

PORTD

CN22/RA6

CN23/RA7
V

REF

-/RA9

V

REF

+/RA10

INT1/RA12

INT2/RA13
INT3/RA14
INT4/RA15

AN0/CN2/RB0

AN1/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11
AN12/RB12

AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15

T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15

EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15

CAN1,
CAN2

12-bit ADC

Timers

Input
Capture
Module

DCI

Output

Compare

Module

SPI1,
SPI2

I2C

UART1,

UART2

PORTF

PORTG

C1RX/RF0
C1TX/RF1
U1RX/RF2

U1TX/RF3
U2RX/CN17/RF4

U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

/CN11/RG9

SS2

CSDI/RG12

CSDO/RG13

CSCK/RG14

COFS/RG15

 2004 Microchip Technology Inc. Preliminary DS70116C-page 7

dsPIC30F5011/5013

Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN15 I Analog Analog input channels.

AV

DD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.
CLKI

CLKO

CN0-CN23 I ST Input change notification inputs.

COFS
CSCK
CSDI
CSDO

C1RX
C1TX
C2RX
C2TX

EMUD
EMUC
EMUD1

EMUC1
EMUD2
EMUC2
EMUD3

EMUC3
IC1-IC8 I ST Capture inputs 1 through 8.
INT0

INT1
INT2
INT3
INT4

LVDIN I Analog Low Voltage Detect Reference Voltage input pin.
MCLR

OCFA
OCFB
OC1-OC8

Pin

Typ e

I

O

I/O
I/O

I

O

I

O

I

O

I/O
I/O
I/O

I/O
I/O
I/O
I/O

I/O

I
I
I
I
I

I/P ST Master Clear (Reset) input or programming voltage input. This

I
I

O

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

Buffer

Typ e

AN0 and AN1 are also used for device programming data and
clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin

function.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with OSC2 pin
function.

Can be software programmed for internal weak pull-ups on all
inputs.

ST
ST
ST

—

ST

—

ST

—

ST
ST
ST

ST
ST
ST
ST

ST

ST
ST
ST
ST
ST

ST
ST

—

Data Converter Interface Frame Synchronization pin.
Data Converter Interface Serial Clock input/output pin.
Data Converter Interface Serial data input pin.
Data Converter Interface Serial data output pin.

CAN1 Bus Receive pin.
CAN1 Bus Transmit pin.
CAN2 Bus Receive pin.
CAN2 Bus Transmit pin

ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data
input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data
input/output pin.
ICD Quaternary Communication Channel clock input/output pin.

External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.

pin is an active low Reset to the device.
Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.

Description

DS70116C-page 8 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

OSC1

OSC2

PGD
PGC

RA6-RA7
RA9-RA10
RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC1-RC4

RC13-RC15
RD0-RD15 I/O ST PORTD is a bidirectional I/O port.
RF0-RF8 I/O ST PORTF is a bidirectional I/O port.
RG0-RG3

RG6-RG9
RG12-RG15

SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2

SCL
SDA

SOSCO
SOSCI

T1CK
T2CK
T3CK
T4CK
T5CK

U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX

V

DD P — Positive supply for logic and I/O pins.
SS P — Ground reference for logic and I/O pins.

V
VREF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

V

Pin

Typ e

I

I/O

I/O

I

I/O
I/O
I/O

I/O
I/O

I/O
I/O
I/O

I/O

I

O

I

I/O

I

O

I

I/O
I/O

O

I

I
I
I
I
I

I

O

I

O

I

O

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

Buffer

Typ e

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes.

ST
ST

ST
ST
ST

ST
ST

ST
ST
ST

ST
ST

—
ST
ST
ST

—
ST

ST
ST

—

ST/CMOS

ST
ST
ST
ST
ST

ST

—
ST

—
ST

—

In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.

Synchronous serial clock input/output for I
Synchronous serial data input/output for I

32 kHz low power oscillator crystal output.
32 kHz low power oscillator crystal input. ST buffer when config­ured in RC mode; CMOS otherwise.

Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.

UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
UART2 Transmit.

Description

2

C.

2

C.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 9

dsPIC30F5011/5013

NOTES:

DS70116C-page 10 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

This section contains a brief overview of the CPU
architecture of the dsPIC30F. For additional hard­ware and programming information, please refer to

dsPIC30F Family Reference Manual

the
the

dsPIC30F Programmer’s Reference Manual

respectively.
The core has a 24-bit instruction word. The Program

Counter (PC) is 23-bits wide with the Least Significant
(LS) bit always clear (refer to Section 3.1), and the
Most Significant (MS) bit is ignored during normal pro­gram execution, except for certain specialized instruc­tions. Thus, the PC can address up to 4M instruction
words of user program space. An instruction pre-fetch
mechanism is used to help maintain throughput. Pro­gram loop constructs, free from loop count manage­ment overhead, are supported using the DO and
REPEAT instructions, both of which are interruptible at
any point.

The working register array consists of 16 x 16-bit regis­ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera­tion Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user. Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.

There are two methods of accessing data stored in
program memory:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of pro­gram space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an addi­tional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.

• Linear indirect access of 32K word pages within

program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.

and

Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.

The X AGU also supports bit-reversed addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 for details on modulo and
bit-reversed addressing.

The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
Addressing modes, depending upon their functional
requirements.

For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg­ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula­tor or any working register can be shifted up to 15 bits
right, or 16 bits left in a single cycle. The DSP instruc­tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by ded­icating certain working registers to each address space
for the MAC class of instructions.

The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.

The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 11

dsPIC30F5011/5013

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.

Some of these registers have a shadow register asso­ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.

• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.

When a byte operation is performed on a working reg­ister, only the Least Significant Byte of the target regis­ter is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Sig­nificant Bytes can be manipulated through byte wide
data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/
FRAME POINTER

The dsPIC® devices contain a software stack. W15 is
the dedicated software Stack Pointer (SP), and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be ref­erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.

W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC core has a 16-bit STATUS register (SR), the
LS Byte of which is referred to as the SR Low byte
(SRL) and the MS Byte as the SR High byte (SRH).
See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior­ity Level status bits, IPL<2:0> and the Repeat Active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.

The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.

2.2.3 PROGRAM COUNTER

The program counter is 23-bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.

DS70116C-page 12 Preliminary  2004 Microchip Technology Inc.

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand
Registers

DSP Address
Registers

dsPIC30F5011/5013

W0/WREG

W1
W2
W3
W4
W5

W6
W7

W8
W9
W10
W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP
Accumulators

PC22

7

TABPAG

TBLPAG

7

22

22

PSVPAG

PSVPAG

AD39 AD0AD31
AccA
AccB

0

Data Table Page Address

0

DOSTART

SPLIM Stack Pointer Limit Register

PC0

Program Space Visibility Page Address

15

RCOUNT

15

DCOUNT

DOEND

AD15

Program Counter

0

0

REPEAT Loop Counter

0

DO Loop Counter

0

DO Loop Start Address

DO Loop End Address

15

CORCON

OA OB SA SB

 2004 Microchip Technology Inc. Preliminary DS70116C-page 13

OAB SAB

SRH

DA DC

IPL2 IPL1

RA

IPL0 OV

SRL

N

0

Core Configuration Register

C

Z

Status Register

dsPIC30F5011/5013

2.3 Divide Support

The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.sw - 16/16 signed divide

5. DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.

The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc­tion as shown in Table 2-1 (REPEAT will execute the tar­get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.

Note: The divide flow is interruptible. However,

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF
DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.sw or

DIV.s
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.uw or

DIV.u

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

the user needs to save the context as
appropriate.

DS70116C-page 14 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).

The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations,
which require no additional data. These instructions are
ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow archi­tecture, threfore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC).

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y) Yes
MAC A = A + x

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data
memory (SATDW).

7. Accumulator Saturation mode selection
(ACCSAT).

Note: For CORCON layout, see Table 4-2.

A block diagram of the DSP engine is shown in
Figure 2-2.

2

2

2

No
No

No

 2004 Microchip Technology Inc. Preliminary DS70116C-page 15

dsPIC30F5011/5013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

40

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A
40-bit Accumulator B

Saturate

Adder

Negate

40

Round

Logic

S
a

16

t

u

r

a

t

e

Y Data Bus

40

Sign-Extend

33

17-bit

Multiplier/Scaler

16

40

40

16

Barrel
Shifter

32

32

40

16

X Data Bus

16

Zero Backfill

To/From W Array

DS70116C-page 16 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the mul­tiplier input value. The output of the 17 x 17-bit multi­plier/scaler is a 33-bit value which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two’s complement integer is -2
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF) including ‘0’. For a 32-bit integer,
the data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multipli­cation, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX for­mat). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1 – 2
16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a preci­sion of 3.01518x10
multiply operation generates a 1.31 product which has
a precision of 4.65661 x 10

The same multiplier is used to support the MCU multi­ply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.

-5

. In Fractional mode, the 16x16

-10

.

N-1

to 2

1-N

N-1

– 1.

). For a

2.4.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre­accumulation source and post-accumulation destina­tion. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and
Saturation

The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true, or complement
data into the other input. In the case of addition, the
carry/borrow
true data (not complemented), whereas in the case of
subtraction, the carry/borrow
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is
destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all
the guard bits bits are not identical to each other.

The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.

Six Status register bits have been provided to support
saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

or

AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

or

AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond­ing overflow trap flag enable bit (OVATEN, OVBTEN) in
the INTCON1 register (refer to Section 5.0) is set. This
allows the user to take immediate action, for example,
to correct system gain.

input is active high and the other input is

input is active low and the

 2004 Microchip Technology Inc. Preliminary DS70116C-page 17

dsPIC30F5011/5013

The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation, or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When satu­ration is not enabled, SA and SB default to bit 39 over­flow and thus indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.

The overflow and saturation status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.

The device supports three saturation and overflow
modes:

1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumula­tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro­neous data, or unexpected algorithm problems
(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally posi­tive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).

3. Bit 39 Catastrophic Overflow:
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following Addressing modes are supported:

1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.

2. [W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu­lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which per­forms a conventional (biased) or convergent (unbi­ased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16­bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the LS Word is simply discarded.

Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algo­rithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.

Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LS bit
(bit 16 of the accumulator) of ACCxH is examined. If it
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.

The SAC and SAC.R instructions store either a trun­cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4). Note
that for the MAC class of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.

DS70116C-page 18 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data
space may also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac­tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.

If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly, For input data greater than
0x007FFF, data written to memory is forced to the max­imum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MS bit of
the source (bit 39) is used to determine the sign of the
operand being tested.

If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).

The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.

The barrel shifter is 40-bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is pre­sented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 16 for left shifts.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 19

dsPIC30F5011/5013

NOTES:

DS70116C-page 20 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
space address is incremented by two between succes­sive program words in order to provide compatibility
with data space addressing.

User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura­tion space access. In Table 3-1, Program Space
Address Construction, bit 23 allows access to the
Device ID, the User ID and the configuration bits.
Otherwise, bit 23 is always clear.

FIGURE 3-1: PROGRAM SPACE

MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

Space

User Memory

User Flash
Program Memory
(22K instructions)

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

000000
000002
000004

Vector Tables

00007E
000080
000084
0000FE
000100

00AFFE
00B000

7FFBFE
7FFC00

7FFFFE
800000

Reserved

8005BE

Space

Configuration Memory

UNITID (32 instr.)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

8005C0
8005FE

800600

F7FFFE
F80000

F8000E
F80010

FEFFFE
FF0000
FFFFFE

 2004 Microchip Technology Inc. Preliminary DS70116C-page 21

dsPIC30F5011/5013

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access User 0 PC<22:1> 0
TBLRD/TBLWT User

TBLRD/TBLWT Configuration

Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

Access

Space

(TBLPAG<7> = 0)

(TBLPAG<7> = 1)

<23> <22:16> <15> <14:1> <0>

TBLPAG<7:0> Data EA<15:0>

TBLPAG<7:0> Data EA<15:0>

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using
Program
Counter

0

Program Space Address

0Program Counter

Select

Using
Program
Space

Visibility

Using
Table
Instruction

User/
Configuration
Space
Select

Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory.

0

1/0

PSVPAG Reg

8 bits

TBLPAG Reg

8 bits

1

24-bit EA

EA

15 bits

EA

16 bits

Byte

Select

DS70116C-page 22 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

3.1.1 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS

This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.

There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2). The
TBLRDL and TBLWTL instructions offer a direct method
of reading or writing the LS Word of any address within
program space, without going through data space. The
TBLRDH and TBLWTH instructions are the only method
whereby the upper 8 bits of a program space word can
be accessed as data.

The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the LS Data Word,
and TBLRDH and TBLWTH access the space which
contains the MS Data Byte.

Figure 3-2 shows how the EA is created for table oper­ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.

A set of table instructions are provided to move byte or
word sized data to and from program space.

1. TBLRDL: Table Read Low

Word:

Read the LS Word of the program address;

P<15:0> maps to D<15:0>.

Byte:

Read one of the LS Bytes of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.

2. TBLWTL: Table Write Low (refer to Section 6.0
for details on Flash Programming)

3. TBLRDH: Table Read High

Word:

Read the MS Word of the program address;
P<23:16> maps to D<7:0>; D<15:8> will always
be = 0.

Byte:

Read one of the MS Bytes of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.

4. TBLWTH: Table Write High (refer to Section 6.0
for details on Flash Programming)

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LS WORD)

PC Address

0x000000
0x000002
0x000004
0x000006

Program Memory
‘Phantom’ Byte
(read as ‘0’)

00000000
00000000

00000000
00000000

23

TBLRDL.W

16

TBLRDL.B (Wn<0> = 1)

8

TBLRDL.B (Wn<0> = 0)

0

 2004 Microchip Technology Inc. Preliminary DS70116C-page 23

dsPIC30F5011/5013

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MS BYTE)

TBLRDH.W

PC Address

0x000000
0x000002
0x000004
0x000006

Program Memory
‘Phantom’ Byte
(read as ‘0’)

00000000
00000000

00000000
00000000

23

TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs
if the MS bit of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4, DSP Engine.

Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.

Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically con­tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.

Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the Programmer’s Reference Manual (DS70030) for
details on instruction encoding.

16

TBLRDH.B (Wn<0> = 0)

Note that by incrementing the PC by 2 for each
program memory word, the LS 15 bits of data space
addresses directly map to the LS 15 bits in the corre­sponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG<7:0>, as shown in Figure 3-5.

Note: PSV access is temporarily disabled during

table reads/writes.

For instructions that use PSV which are executed
outside a REPEAT loop:

• The following instructions will require one
instruction cycle in addition to the specified
execution time:

- MAC class of instructions with data operand

pre-fetch

- MOV instructions

- MOV.D instructions

• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.

For instructions that use PSV which are executed
inside a REPEAT loop:

• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop will allow
the instruction accessing data, using PSV, to
execute in a single cycle.

8

0

DS70116C-page 24 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Program Space

Data Space

0x0000

0x21

(1)

8

23 15 0

23

Data Read

0x108000

0x108200

0x10FFFF

EA<15> =

16

Data
Space
EA

EA<15> = 1

Upper Half of Data
Space is Mapped
into Program Space

BSET CORCON,#2 ; PSV bit set
MOV #0x21, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x8200, W0 ; Access program memory location

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines

the page in program space to which the upper half of data space is being mapped).

15

0

15

; using a data space access

0x8000

15

0xFFFF

PSVPAG

Address

Concatenation

3.2 Data Address Space

The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc­tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 25

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.

dsPIC30F5011/5013

When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64­Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64-Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.

FIGURE 3-6: DATA SPACE MEMORY MAP

2 Kbyte
SFR Space

4 Kbyte
SRAM Space

MS Byte

Address

0x0001

0x07FF
0x0801

0x0FFF
0x1001

0x17FF 0x17FE

16 bits

SFR Space

X Data RAM (X)

Y Data RAM (Y)

The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.

The data space memory map is shown in Figure 3-6.

LS Byte

Address

LSBMSB

0x0000

0x07FE
0x0800

0x0FFE
0x1000

0x18000x1801

8 Kbyte
Near
Data
Space

Optionally
Mapped
into Program
Memory

0x8001

0xFFFF

0x1FFE 0x1FFF

0x8000

X Data

Unimplemented (X)

0xFFFE

DS70116C-page 26 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

UNUSED

(Y SPACE)

X SPACE

Non-MAC Class Ops (Read/Write) MAC Class Ops (Read)

MAC Class Ops (Write)

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

Y SPACE

UNUSED

SFR SPACE

UNUSED

X SPACE

X SPACE

 2004 Microchip Technology Inc. Preliminary DS70116C-page 27

dsPIC30F5011/5013

3.2.2 DATA SPACES

The X data space is used by all instructions and sup­ports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.

The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restric­tions. Bit-reversed addressing is only supported for
writes to X data space.

The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedi­cates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.

The Y data space can only be used for the data pre­fetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instruc­tions can access the Y data address space through the
X data path as part of the composite linear space.

The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro­grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys­ical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) will return
0x0000.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALIGNMENT

To help maintain backward compatibility with
PICmicro
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS Byte of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.

As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws+1 for byte operations
and Ws+2 for word operations.

All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word opera­tions, or translating from 8-bit MCU code. Should a mis­aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam­ine the machine state prior to execution of the address
fault.

®

devices and improve data space memory

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

Attempted Operation Data Returned

EA = an unimplemented address 0x0000
W8 or W9 used to access Y data

space in a MAC instruction
W10 or W11 used to access X

data space in a MAC instruction

All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.

DS70116C-page 28 Preliminary  2004 Microchip Technology Inc.

0x0000

0x0000

FIGURE 3-8: DATA ALIGNMENT

15 8 7 0

0001

0003

0005

Byte1 Byte 0

Byte3 Byte 2

Byte5 Byte 4

LS ByteMS Byte

0000

0002

0004

dsPIC30F5011/5013

All byte loads into any W register are loaded into the
LS Byte. The MSB is not modified.

A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.

Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.

3.2.5 NEAR DATA SPACE

An 8-Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.

3.2.6 SOFTWARE STACK

The dsPIC devices contain a software stack. W15 is
used as the stack pointer.

The stack pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.

Note: A PC push during exception processing

will concatenate the SRL register to the
MSB of the PC prior to the push.

There is a Stack Pointer Limit register (SPLIM) associ­ated with the stack pointer. SPLIM is uninitialized at
Reset. As is the case for the stack pointer, SPLIM<0>
is forced to ‘0’ because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a Stack Error Trap will not
occur. The Stack Error Trap will occur on a subsequent
push operation. Thus, for example, if it is desirable to
cause a Stack Error Trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.

Similarly, a stack pointer underflow (stack error) trap is
generated when the stack pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.

A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.

FIGURE 3-9: CALL STACK FRAME

0x0000

Stack Grows Towards

000000000

Higher Address

PC<15:0>

PC<22:16>

<Free Word>

015

W15 (before CALL)

W15 (after CALL)

POP : [--W15]
PUSH : [W15++]

 2004 Microchip Technology Inc. Preliminary DS70116C-page 29

dsPIC30F5011/5013

uuuu uuuu uuuu uuu0

0

— — — — — — — — —PCH0000 0000 0000 0000

— — — — — — — —TBLPAG0000 0000 0000 0000

Address

TABLE 3-3: CORE REGISTER MAP

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR Name

— — — — — — — — PSVPAG 0000 0000 0000 0000

(Home)

W0 0000 W0 / WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PSVPAG 0034

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

TBLPAG 0032

PCH 0030

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0

— — — — — — — — —DOSTARTH0000 0000 0uuu uuuu

DOSTARTH 003C

DOENDL 003E DOENDL

— — — — — — — — — DOENDH 0000 0000 0uuu uuuu

DOENDH 0040

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

Legend: u = uninitialized bit

DS70116C-page 30 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

— — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

— — DISICNT<13:0> 0000 0000 0000 0000

DISICNT 0052

Legend: u = uninitialized bit

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

(Home)

Address

SFR Name

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

MODCON 0046 XMODEN YMODEN

XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

 2004 Microchip Technology Inc. Preliminary DS70116C-page 31

YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0

dsPIC30F5011/5013

NOTES:

DS70116C-page 32 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

4.0 ADDRESS GENERATOR UNITS

The dsPIC core contains two independent address
generator units: the X AGU and Y AGU. The Y AGU
supports word sized data reads for the DSP MAC class
of instructions only. The dsPIC AGUs support three
types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-reversed
addressing is only applicable to data space addresses.

4.1 Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the File register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

4.1.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the
addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

Note: Not all instructions support all the address-

ing modes given above. Individual
instructions may support different subsets
of these addressing modes.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 33

dsPIC30F5011/5013

4.1.3 MOVE AND ACCUMULATOR
INSTRUCTIONS

Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instruc­tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).

In summary, the following addressing modes are
supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note: Not all instructions support all the address-

ing modes given above. Individual
instructions may support different subsets
of these addressing modes.

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.

The 2 source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.

In summary, the following addressing modes are
supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.

4.2 Modulo Addressing

Modulo addressing is a method of providing an auto­mated means to support circular data buffers using
hardware. The objective is to remove the need for soft­ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.

Modulo addressing can operate in either data or pro­gram space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Mod­ulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for mod­ulo addressing since these two registers are used as
the stack frame pointer and stack pointer, respectively.

In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer­tain restrictions on the buffer start address (for incre­menting buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for buff­ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks will be performed on both the lower and upper
address boundaries).

Note: Register indirect with register offset

addressing is only available for W9 (in X
space) and W11 (in Y space).

DS70116C-page 34 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

4.2.1 START AND END ADDRESS

The modulo addressing scheme requires that a starting
and an ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).

Note: Y space modulo addressing EA calcula-

tions assume word sized data (LS bit of
every EA is always clear).

The length of a circular buffer is not directly specified. It
is determined by the difference between the corre­sponding start and end addresses. The maximum pos­sible length of the circular buffer is 32K words
(64 Kbytes).

4.2.2 W ADDRESS REGISTER
SELECTION

The Modulo and Bit-Reversed Addressing Control reg­ister MODCON<15:0> contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X
RAGU and X WAGU modulo addressing is disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.

The X Address Space Pointer W register (XWM), to
which modulo addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.

The Y Address Space Pointer W register (YWM), to
which modulo addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Byte
Address

0x1100

MOV #0x1100,W0
MOV W0,XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo

0x1163

Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0,[W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value

 2004 Microchip Technology Inc. Preliminary DS70116C-page 35

dsPIC30F5011/5013

4.2.3 MODULO ADDRESSING
APPLICABILITY

Modulo addressing can be applied to the effective
address (EA) calculation associated with any W regis­ter. It is important to realize that the address bound­aries check for addresses less than, or greater than the
upper (for incrementing buffers), and lower (for decre­menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.

Note: The modulo corrected effective address is

written back to the register only when Pre­Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2]) is
used, modulo address correction is per­formed but the contents of the register
remain unchanged.

4.3 Bit-Reversed Addressing

Bit-reversed addressing is intended to simplify data re­ordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.

The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.

4.3.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION

Bit-reversed addressing is enabled when:

1. BWM (W register selection) in the MODCON

register is any value other than ‘15’ (the stack
cannot be accessed using bit-reversed
addressing) and

2. the BREN bit is set in the XBREV register and

3. the addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

N

If the length of a bit-reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.

Note: All bit-reversed EA calculations assume

word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.

When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses will be gener­ated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and always clear).

Note: Modulo addressing and bit-reversed

addressing should not be enabled together.
In the event that the user attempts to do
this, bit-reversed addressing will assume
priority when active for the X WAGU, and X
WAGU modulo addressing will be disabled.
However, modulo addressing will continue
to function in the X RAGU.

If bit-reversed addressing has already been enabled by
setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.

bytes,

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Sequential Address

b15 b14 b13 b12

b15 b14 b13 b12

DS70116C-page 36 Preliminary  2004 Microchip Technology Inc.

b11 b10 b9 b8

b7 b6 b5 b4b11 b10 b9 b8

b7 b6 b5 b1

Pivot Point

b3 b2 b1 0

Bit Locations Swapped Left-to-Right
Around Center of Binary Value

b2 b3 b4 0

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

dsPIC30F5011/5013

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 0 0000 0
0001 1 1000 8
0010 2 0100 4
0011 3 1100 12
0100 4 0010 2
0101 5 1010 10
0110 6 0110 6
0111 7 1110 14
1000 8 0001 1
1001 9 1001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value

32768 0x4000
16384 0x2000

8192 0x1000
4096 0x0800
2048 0x0400
1024 0x0200

512 0x0100
256 0x0080
128 0x0040

64 0x0020
32 0x0010
16 0x0008

8 0x0004
4 0x0002
2 0x0001

 2004 Microchip Technology Inc. Preliminary DS70116C-page 37

dsPIC30F5011/5013

NOTES:

DS70116C-page 38 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

5.0 INTERRUPTS

The dsPIC30F Sensor and General Purpose Family
has up to 41 interrupt sources and 4 processor excep­tions (traps) which must be arbitrated based on a
priority scheme.

The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The inter­rupt vector is transferred from the program data bus
into the program counter via a 24-bit wide multiplexer
on the input of the program counter.

The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.

The interrupt controller is responsible for pre­processing the interrupts and processor exceptions
prior to them being presented to the processor core.
The peripheral interrupts and traps are enabled, priori­tized and controlled using centralized Special Function
Registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec­tive peripherals or external signals, and they are
cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.

• IPC0<15:0>... IPC10<7:0>
The user assignable priority level associated with
each of these 41 interrupts is held centrally in
these twelve registers.

• IPL<3:0>
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.

• INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con­trol and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.

Note: Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit. User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers. Each
interrupt source is associated with an interrupt vector,
as shown in Table 5-1. Levels 7 and 1 represent the
highest and lowest maskable priorities, respectively.

Note: Assigning a priority level of ‘0’ to an inter-

rupt source is equivalent to disabling that
interrupt.

If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is pre­vented even if the new interrupt is of higher priority than
the one currently being serviced.

Note: The IPL bits become read only whenever

the NSTDIS bit has been set to ‘1’.

Certain interrupts have specialized control bits for fea­tures like edge or level triggered interrupts, interrupt­on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.

The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program mem­ory that corresponds to the interrupt. There are 63 dif­ferent vectors within the IVT (refer to Table 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Table 5-1).
These locations contain 24-bit addresses and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu­tion of random data as a result of accidentally decre­menting a PC into vector space, accidentally mapping
a data space address into vector space, or the PC roll­ing over to 0x000000 after reaching the end of imple­mented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 39

dsPIC30F5011/5013

5.1 Interrupt Priority

The user assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the LS
3 bits of each nibble within the IPCx register(s). Bit 3 of
each nibble is not used and is read as a ‘0’. These bits
define the priority level assigned to a particular interrupt
by the user.

Note: The user selectable priority levels start at

0 as the lowest priority and level 7 as the
highest priority.

Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.

Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC device and their associated
vector numbers.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the
lowest priority.

2: The natural order priority number is the

same as the INT number.

The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low
Voltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.

TABLE 5-1: INTERRUPT VECTOR TABLE

INT

Number

Highest Natural Order Priority

0 8 INT0 - External Interrupt 0
1 9 IC1 - Input Capture 1
2 10 OC1 - Output Compare 1
3 11 T1 - Timer 1
4 12 IC2 - Input Capture 2
5 13 OC2 - Output Compare 2
6 14 T2 - Timer 2
7 15 T3 - Timer 3
816SPI1

9 17 U1RX - UART1 Receiver
10 18 U1TX - UART1 Transmitter
11 19 ADC - ADC Convert Done
12 20 NVM - NVM Write Complete
13 21 SI2C - I
14 22 MI2C - I2C Master Interrupt
15 23 Input Change Interrupt
16 24 INT1 - External Interrupt 1
17 25 IC7 - Input Capture 7
18 26 IC8 - Input Capture 8
19 27 OC3 - Output Compare 3
20 28 OC4 - Output Compare 4
21 29 T4 - Timer 4
22 30 T5 - Timer 5
23 31 INT2 - External Interrupt 2
24 32 U2RX - UART2 Receiver
25 33 U2TX - UART2 Transmitter
26 34 SPI2
27 35 C1 - Combined IRQ for CAN1
28 36 IC3 - Input Capture 3
29 37 IC4 - Input Capture 4
30 38 IC5 - Input Capture 5
31 39 IC6 - Input Capture 6
32 40 OC5 - Output Compare 5
33 41 OC6 - Output Compare 6
34 42 OC7 - Output Compare 7
35 43 OC8 - Output Compare 8
36 44 INT3 - External Interrupt 3
37 45 INT4 - External Interrupt 4
38 46 C2 - Combined IRQ for CAN2

39-40 47-48 Reserved

41 49 DCI - Codec Transfer Done
42 50 LVD - Low Voltage Detect

43-53 51-61 Reserved

Lowest Natural Order Priority

Vector

Number

Interrupt Source

2

C Slave Interrupt

DS70116C-page 40 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

5.2 Reset Sequence

A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro­cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca­tion immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.

5.2.1 RESET SOURCES

In addition to external Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.

• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.

• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.

• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.

• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.

• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.

5.3 Traps

Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.

Note: If the user does not intend to take correc-

tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.

Note that many of these trap conditions can only be
detected when they occur. Consequently, the question­able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.

If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing prior­ity. However, since all traps can be nested, priority has
little effect.

Math Error Trap:

The Math Error trap executes under the following three
circumstances:

1. Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.

2. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.

3. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.

4. If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 41

dsPIC30F5011/5013

Address Error Trap:

This trap is initiated when any of the following
circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data
memory location is attempted.

3. A data access of an unimplemented program
memory location is attempted.

4. An instruction fetch from vector space is
attempted.

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.

5. Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.

6. Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The stack pointer is loaded with a value which is
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow).

2. The stack pointer is loaded with a value which is
less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.

‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.

Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.

The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.

FIGURE 5-1: TRAP VECTORS

Reset - GOTO Instruction

Reset - GOTO Address

Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector

Stack Error Trap Vector
Math Error Trap Vector

IVT

Priority

Decreasing

AIVT

Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector

—
—

—
Interrupt 52 Vector
Interrupt 53 Vector

Reserved
Reserved
Reserved

Oscillator Fail Trap Vector

Stack Error Trap Vector

Address Error Trap Vector

Math Error Trap Vector

Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector

—

—

—
Interrupt 52 Vector

Interrupt 53 Vector

0x000000
0x000002

0x000004

0x000014

0x00007E

0x000080
0x000082
0x000084

0x000094

0x0000FE

DS70116C-page 42 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

5.4 Interrupt Sequence

All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the Interrupt
Enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.

If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.

The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 5-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this inter­rupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.

FIGURE 5-2: INTERRUPT STACK

FRAME

0x0000

Stack Grows Towards

PC<15:0>
SRL IPL3 PC<22:16>

<Free Word>

Higher Address

015

W15 (before CALL)

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

5.5 Alternate Vector Table

In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the alternate vector
table is provided by the ALTIVT bit in the INTCON2 reg­ister. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors. The AIVT sup­ports emulation and debugging efforts by providing a
means to switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.

If the AIVT is not required, the program memory allo­cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow reg­isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.

When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc­tions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.

5.7 External Interrupt Requests

The interrupt controller supports up to five external

Note 1: The user can always lower the priority

level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro­cessed. It is set only during execution of
traps.

The RETFIE (return from interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 43

interrupt request signals, INT0-INT4. These inputs are
edge sensitive; they require a low-to-high or a high-to­low transition to generate an interrupt request. The
INTCON2 register has five bits, INT0EP-INT4EP, that
select the polarity of the edge detection circuitry.

5.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.

dsPIC30F5011/5013

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0100 0100 0100 0100

0100 0100 0100 0100

0100 0100 0100 0100

0000 0000 0000 0000

0000 0000 0000 0000

0100 0100 0100 0100

0100 0100 0100 0100

0100 0100 0100 0100

0100 0100 0100 0100

0100 0100 0100 0100

0100 0100 0100 0100

0000 0100 0100 0100

0000 0100 0100 0000

— — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —

— — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

— — — — — LVDIF DCIIF — — C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF

ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

INTCON2 0082 ALTIVT

INTCON1 0080 NSTDIS

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF

IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP

IFS2 0088

— — — — — LVDIE DCIIE — — C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE

— T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0>

— T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0>

—ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0>

— CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0>

—OC3IP<2:0>—IC8IP<2:0>— IC7IP<2:0> — INT1IP<2:0>

— INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0>

— C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0>

— IC6IP<2:0> —IC5IP<2:0>— IC4IP<2:0> — IC3IP<2:0>

—OC8IP<2:0>—OC7IP<2:0>— OC6IP<2:0> — OC5IP<2:0>

— — — — — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0>

— — — — — LVDIP<2:0> — DCIIP<2:0> — — — —

IPC1 0096

IPC2 0098

IPC3 009A

IPC4 009C

IPC5 009E

IPC6 00A0

IPC7 00A2

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE

IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE

IEC2 0090

IPC0 0094

IPC8 00A4

Legend: u = uninitialized bit

IPC9 00A6

IPC10 00A8

DS70116C-page 44 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

6.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal pro­gram Flash memory for executing user code. There are
two methods by which the user can program this
memory:

1. Run-Time Self-Programming (RTSP)

2. In-Circuit Serial Programming™ (ICSP™)

6.1 In-Circuit Serial Programming (ICSP)

dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (V
Master Clear (MCLR

). this allows customers to manu­facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.

DD), Ground (VSS) and

6.2 Run-Time Self-Programming (RTSP)

RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.

With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 32 instructions (96 bytes) at a time.

6.3 Table Instruction Operation Summary

The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.

The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.

A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the effective
address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.

FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Using
Program
Counter

Using
NVMADR
Addressing

Using
Table
Instruction

User/Configuration
Space Select

0

1/0

NVMADRU Reg

1/0

TBLPAG Reg

24 bits

Program Counter

NVMADR Reg EA

8 bits 16 bits

Working Reg EA

8 bits

24-bit EA

16 bits

0

Byte
Select

 2004 Microchip Technology Inc. Preliminary DS70116C-page 45

dsPIC30F5011/5013

6.4 RTSP Operation

The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc­tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.

Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a group of 32 boundary.

The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.

All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.

The Flash Program Memory is readable, writable and
erasable during normal operation over the entire V
range.

DD

6.5 Control Registers

The four SFRs used to read and write the program
Flash memory are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

6.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.

6.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.

6.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap­tures the EA<23:16> of the last table instruction that
has been executed.

6.5.4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6 for
further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.

DS70116C-page 46 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

6.6 Programming Operations

A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the oper­ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.

6.6.1 PROGRAMMING ALGORITHM FOR
PROGRAM FLASH

The user can erase or program one row of program
Flash memory at a time. The general process is:

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data
“image”.

2. Update the data image with the desired new

data.

3. Erase program Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.
c) Write ‘55’ to NVMKEY.
d) Write ‘AA’ to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase

cycle.
g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.

5. Program 32 instruction words into program
Flash.

a) Setup NVMCON register for multi-word,

program Flash, program, and set WREN

bit.
b) Write ‘55’ to NVMKEY.
c) Write ‘AA’ to NVMKEY.
d) Set the WR bit. This will begin program

cycle.
e) CPU will stall for duration of the program

cycle.
f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.

6.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.

EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled

; Init pointer to row to be ERASED

MOV #0x4041,W0 ;
MOV W0

MOV #tblpage(PROG_ADDR),W0 ;
MOV W0
MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer
MOV W0, NVMADR ; Initialize NVMADR SFR
DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0
MOV W0
MOV #0xAA,W1 ;
MOV W1
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

NVMCON ; Init NVMCON SFR

,

NVMADRU ; Initialize PM Page Boundary SFR

,

; next 5 instructions

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

 2004 Microchip Technology Inc. Preliminary DS70116C-page 47

dsPIC30F5011/5013

6.6.3 LOADING WRITE LATCHES

Example 6-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches. 32
TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the table pointer.

EXAMPLE 6-2: LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled

; Perform the TBLWT instructions to write the latches
; 0th_program_word

; 1st_program_word

; 2nd_program_word

; 31st_program_word

MOV #0x0000,W0 ;
MOV W0
MOV #0x6000,W0 ; An example program memory address

MOV #LOW_WORD_0,W2 ;
MOV #HIGH_BYTE_0,W3 ;
TBLWTL W2
TBLWTH W3

MOV #LOW_WORD_1,W2 ;
MOV #HIGH_BYTE_1,W3 ;
TBLWTL W2
TBLWTH W3

MOV #LOW_WORD_2,W2 ;
MOV #HIGH_BYTE_2,W3 ;
TBLWTL W2
TBLWTH W3

•

•

•

MOV #LOW_WORD_31,W2 ;
MOV #HIGH_BYTE_31,W3 ;
TBLWTL W2
TBLWTH W3

TBLPAG ; Initialize PM Page Boundary SFR

,

[W0] ; Write PM low word into program latch

,

[W0++] ; Write PM high byte into program latch

,

[W0] ; Write PM low word into program latch

,

[W0++] ; Write PM high byte into program latch

,

[W0] ; Write PM low word into program latch

,

[W0++] ; Write PM high byte into program latch

,

[W0] ; Write PM low word into program latch

,

[W0++] ; Write PM high byte into program latch

,

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

6.6.4 INITIATING THE PROGRAMMING
SEQUENCE

For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions fol­lowing the start of the programming sequence should
be NOPs.

EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0 ;
MOV W0
MOV #0xAA,W1 ;
MOV W1
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

; next 5 instructions

DS70116C-page 48 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

— — — —TWRI — PROGOP<6:0> 0000 0000 0000 0000

— — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

— — — — — — — — KEY<7:0> 0000 0000 0000 0000

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764

NVMCON 0760 WR WREN WRERR

TABLE 6-1: NVM REGISTER MAP

 2004 Microchip Technology Inc. Preliminary DS70116C-page 49

NVMKEY 0766

Legend: u = uninitialized bit

dsPIC30F5011/5013

NOTES:

DS70116C-page 50 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

7.0 DATA EEPROM MEMORY

The Data EEPROM Memory is readable and writable
during normal operation over the entire V
data EEPROM memory is directly mapped in the
program memory address space.

The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.5, these
registers are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY
The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
NVMADRU register are used to address the EEPROM
location being accessed. TBLRDL and TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F devices have up to 8 Kbytes (4K
words) of data EEPROM with an address range from
0x7FF000 to 0x7FFFFE.

A word write operation should be preceded by an erase
of the corresponding memory location(s). The write typ­ically requires 2 ms to complete but the write time will
vary with voltage and temperature.

A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon­sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.

DD range. The

Control bit WR initiates write operations similar to pro­gram Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the com­pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.

The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera­tion. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.

Note: Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be
cleared in software.

7.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current pro­gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 7-1.

EXAMPLE 7-1: DATA EEPROM READ

MOV #LOW_ADDR_WORD,W0 ; Init Pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1
TBLRDL [ W0 ], W4 ; read data EEPROM

TBLPAG

,

 2004 Microchip Technology Inc. Preliminary DS70116C-page 51

dsPIC30F5011/5013

7.2 Erasing Data EEPROM

7.2.1 ERASING A BLOCK OF DATA
EEPROM

In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially point
to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM, and
set the ERASE and WREN bits in the NVMCON
register. Setting the WR bit initiates the erase as
shown in Example 7-2.

EXAMPLE 7-2: DATA EEPROM BLOCK ERASE

; Select data EEPROM block, ERASE, WREN bits

MOV #4045,W0
MOV W0

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0 ;
MOV W0
MOV #0xAA,W1 ;
MOV W1

BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

NVMCON ; Initialize NVMCON SFR

,

; next 5 instructions

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

7.2.2 ERASING A WORD OF DATA
EEPROM

The TBLPAG and NVMADR registers must point to the
block. Select erase a block of data Flash, and set the
ERASE and WREN bits in the NVMCON register. Set­ting the WR bit initiates the erase as shown in
Example 7-3.

EXAMPLE 7-3: DATA EEPROM WORD ERASE

; Select data EEPROM word, ERASE, WREN bits

MOV #4044,W0
MOV W0

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0 ;
MOV W0

MOV #0xAA,W1 ;

MOV W1
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

NVMCON

,

; next 5 instructions

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

DS70116C-page 52 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

7.3 Writing to the Data EEPROM

To write an EEPROM data location, the following
sequence must be followed:

1. Erase data EEPROM word.
a) Select word, data EEPROM erase, and set

WREN bit in NVMCON register.

b) Write address of word to be erased into

NVMADR.
c) Enable NVM interrupt (optional).
d) Write ‘55’ to NVMKEY.
e) Write ‘AA’ to NVMKEY.
f) Set the WR bit. This will begin erase cycle.
g) Either poll NVMIF bit or wait for NVMIF

interrupt.
h) The WR bit is cleared when the erase cycle

ends.

2. Write data word into data EEPROM write
latches.

3. Program 1 data word into data EEPROM.
a) Select word, data EEPROM program, and

set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional).
c) Write ‘55’ to NVMKEY.
d) Write ‘AA’ to NVMKEY.
e) Set the WR bit. This will begin program

cycle.
f) Either poll NVMIF bit or wait for NVM

interrupt.
g) The WR bit is cleared when the write cycle

ends.

The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.

Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe­cution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.

After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc­tion. Both WR and WREN cannot be set with the same
instruction.

At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt or poll this bit.
NVMIF must be cleared by software.

7.3.1 WRITING A WORD OF DATA
EEPROM

Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 7-4.

EXAMPLE 7-4: DATA EEPROM WORD WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1
MOV #LOW(WORD),W2 ; Get data

TBLWTL W2
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0

MOV W0

MOV #0xAA,W1

MOV W1

BSET NVMCON,#WR ; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

 2004 Microchip Technology Inc. Preliminary DS70116C-page 53

TBLPAG

,

[ W0] ; Write data

,

NVMCON

,

; next 5 instructions

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

dsPIC30F5011/5013

7.3.2 WRITING A BLOCK OF DATA
EEPROM

To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.

EXAMPLE 7-5: DATA EEPROM BLOCK WRITE

MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1
MOV #data1,W2 ; Get 1st data
TBLWTL W2
MOV #data2,W2 ; Get 2nd data
TBLWTL W2
MOV #data3,W2 ; Get 3rd data
TBLWTL W2
MOV #data4,W2 ; Get 4th data
TBLWTL W2
MOV #data5,W2 ; Get 5th data
TBLWTL W2
MOV #data6,W2 ; Get 6th data
TBLWTL W2
MOV #data7,W2 ; Get 7th data
TBLWTL W2
MOV #data8,W2 ; Get 8th data
TBLWTL W2
MOV #data9,W2 ; Get 9th data
TBLWTL W2
MOV #data10,W2 ; Get 10th data
TBLWTL W2
MOV #data11,W2 ; Get 11th data
TBLWTL W2
MOV #data12,W2 ; Get 12th data
TBLWTL W2
MOV #data13,W2 ; Get 13th data
TBLWTL W2
MOV #data14,W2 ; Get 14th data
TBLWTL W2
MOV #data15,W2 ; Get 15th data
TBLWTL W2
MOV #data16,W2 ; Get 16th data
TBLWTL W2
MOV #0x400A,W0 ; Select data EEPROM for multi word op
MOV W0

DISI #5 ; Block all interrupts with priority <7 for

MOV #0x55,W0
MOV W0
MOV #0xAA,W1
MOV W1
BSET NVMCON,#WR ; Start write cycle
NOP
NOP

TBLPAG

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data

,

[ W0]++ ; write data. The NVMADR captures last table access address.

,

NVMCON ; Operate Key to allow program operation

,

; next 5 instructions

NVMKEY ; Write the 0x55 key

,

NVMKEY ; Write the 0xAA key

,

DS70116C-page 54 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

7.4 Write Verify

Depending on the application, good programming
practice may dictate that the value written to the mem­ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.

7.5 Protection Against Spurious Write

There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 55

dsPIC30F5011/5013

NOTES:

DS70116C-page 56 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

8.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.

8.1 Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read but the output driver for the parallel port bit
will be disabled. If a peripheral is enabled but the
peripheral is not actively driving a pin, that pin may be
driven by a port.

All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
port pins, write the latch (LATx).

Any bit and its associated data and control registers
that are not valid for a particular device will be dis­abled. That means the corresponding LATx and TRISx
registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func­tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.

The format of the registers for PORTA are shown in
Table 8-1.

The TRISA (Data Direction Control) register controls
the direction of the RA<7:0> pins, as well as the INTx
pins and the V

REF pins. The LATA register supplies

data to the outputs and is readable/writable. Reading
the PORTA register yields the state of the input pins,
while writing the PORTA register modifies the contents
of the LATA register.

A parallel I/O (PIO) port that shares a pin with a periph­eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-2 shows how ports are shared
with other peripherals and the associated I/O cell (pad)
to which they are connected. Table 8-2 through
Table 8-9 show the formats of the registers for the
shared ports, PORTB through PORTG.

Note: The actual bits in use vary between

devices.

FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module

Data Bus

WR TRIS

WR LAT +
WR Port

Read LAT

Read Port

Read TRIS

TRIS Latch

QD

CK

Data Latch

QD

CK

I/O Cell

I/O Pad

 2004 Microchip Technology Inc. Preliminary DS70116C-page 57

dsPIC30F5011/5013

FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Data Bus

WR TRIS

WR LAT +
WR Port

Peripheral Module

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

PIO Module

Read TRIS

QD

CK

TRIS Latch

QD

CK

Data Latch

Read LAT

Output Multiplexers

1

Output Enable

0

1

Output Data

0

I/O Cell

I/O Pad

Input Data

Read Port

8.2 Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond­ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.

When reading the Port register, all pins configured as
analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an ana­log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.

8.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.

EXAMPLE 8-1: PORT WRITE/READ

EXAMPLE

MOV 0xFF00, W0 ; Configure PORTB<15:8>

; as inputs
MOV W0, TRISB ; and PORTB<7:0> as outputs
NOP ; additional instruction

cylcle

btss PORTB, #13 ; bit test RB13 and skip if

set

DS70116C-page 58 Preliminary  2004 Microchip Technology Inc.

1111 0110 1100 0000

0000 0000 0000 0000

dsPIC30F5011/5013

0000 0000 0000 0000

— TRISA10 TRISA9 — TRISA7 TRISA6 — — — — — —

— RA10 RA9 —RA7 RA6 — — — — — —

— LATA10 LATA9 —LATA7LATA6 — — — — — —

— — — — — — — — — — TRISC2 TRISC1 — 1110 0000 0000 0110

— — — — — — — — — — RC2 RC1 — 0000 0000 0000 0000

TABLE 8-1: PORTA REGISTER MAP FOR dsPIC30F5013

— — — — — — — — — —LATC2LATC1— 0000 0000 0000 0000

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISA 02C0 TRISA15 TRISA14 TRISA13 TRISA12

PORTA 02C2 RA15 RA14 RA13 RA12

LATA 02C4 LATA15 LATA14 LATA13 LATA12

Legend: u = uninitialized bit

Note: PORTA is not implemented in the dsPIC30F5011 device.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

TABLE 8-2: PORTB REGISTER MAP FOR dsPIC30F5011/5013

Legend: u = uninitialized bit

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

PORTC 02CE RC15 RC14 RC13

LATC 02D0 LATC15 LATC14 LATC13

TABLE 8-3: PORTC REGISTER MAP FOR dsPIC30F5011

TRISC 02CC TRISC15 TRISC14 TRISC13

Legend: u = uninitialized bit

TABLE 8-4: PORTC REGISTER MAP FOR dsPIC30F5013

— — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — 1110 0000 0001 1110

— — — — — — — — RC4 RC3 RC2 RC1 — 0000 0000 0000 0000

— — — — — — — — LATC4 LATC3 LATC2 LATC1 — 0000 0000 0000 0000

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

PORTC 02CE RC15 RC14 RC13

LATC 02D0 LATC15 LATC14 LATC13

TRISC 02CC TRISC15 TRISC14 TRISC13

Legend: u = uninitialized bit

 2004 Microchip Technology Inc. Preliminary DS70116C-page 59

dsPIC30F5011/5013

— — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 1111 0011 1100 1111

— — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 0000 0000 0000 0000

— — L ATG 9 L ATG 8 L ATG7 L ATG6 — — LATG3 LATG2 LATG1 LATG0 0000 0000 0000 0000

— — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111

— — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000

— — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0000 1111 1111 1111

— — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000

— — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TABLE 8-7: PORTF REGISTER MAP FOR dsPIC30F5011

TABLE 8-6: PORTD REGISTER MAP FOR dsPIC30F5013

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000

LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000

Legend: u = uninitialized bit

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

PORTD 02D4

LATD 02D6

TABLE 8-5: PORTD REGISTER MAP FOR dsPIC30F5011

TRISD 02D2

Legend: u = uninitialized bit

— — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000

PORTF 02E0

LATF 02E2

TRISF 02DE

Legend: u = uninitialized bit

TABLE 8-8: PORTF REGISTER MAP FOR dsPIC30F5013

— — — — — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0001 1111 1111

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISF 02DE

— — — — — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000

— — — — — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000

LATF 02E2

Legend: u = uninitialized bit

PORTF 02E0

TABLE 8-9: PORTG REGISTER MAPFOR dsPIC30F5011/5013

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12

LATG 02E8 LATG15 LATG14 LATG13 LATG12

PORTG 02E6 RG15 RG14 RG13 RG12

DS70116C-page 60 Preliminary  2004 Microchip Technology Inc.

Legend: u = uninitialized bit

dsPIC30F5011/5013

8.3 Input Change Notification Module

The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor, in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in Sleep mode,
when the clocks are disabled. There are up to 24 exter­nal signals (CN0 through CN23) that may be selected
(enabled) for generating an interrupt request on a
change of state.

TABLE 8-10: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 15-8)

SFR

Name

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6
Legend: u = uninitialized bit

TABLE 8-11: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 7-0)

SFR

Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6
Legend: u = uninitialized bit

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State

— — — — — — — — 0000 0000 0000 0000

— — — — — — — — 0000 0000 0000 0000

Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

— — — — — CN18IE CN17IE CN16IE 0000 0000 0000 0000

— — — — — CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000

TABLE 8-12: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 15-8)

SFR

Name

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6
Legend: u = uninitialized bit

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State

— — — — — — — — 0000 0000 0000 0000

— — — — — — — — 0000 0000 0000 0000

TABLE 8-13: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 7-0)

SFR

Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: u = uninitialized bit

Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

 2004 Microchip Technology Inc. Preliminary DS70116C-page 61

dsPIC30F5011/5013

NOTES:

DS70116C-page 62 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

9.0 TIMER1 MODULE

This section describes the 16-bit General Purpose
(GP) Timer1 module and associated Operational
modes. Figure 9-1 depicts the simplified block diagram
of the 16-bit Timer1 module.

The following sections provide a detailed description
including setup and control registers, along with asso­ciated block diagrams for the Operational modes of the
timers.

The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free-running interval timer/counter. The 16-bit timer has
the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter
Further, the following operational characteristics are

supported:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep
modes

• Interrupt on 16-bit Period register match or falling
edge of external gate signal

These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.

16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value preloaded into the Period register PR1, then
resets to ‘0’ and continues to count.

When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.

16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.

When the CPU goes into the Idle mode, the timer will
stop incrementing unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.

16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.

When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer will stop incrementing if TSIDL = 1.

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

T1IF

Event Flag

SOSCO/

T1CK

SOSCI

TGATE

Equal

Reset

0

1

LPOSCEN

PR1

Comparator x 16

TMR1

QD

Q

CK

Gate
Sync

T

CY

TGATE

TCS

1 x

0 1

0 0

TGATE

TON

TSYNC

1

0

Sync

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

 2004 Microchip Technology Inc. Preliminary DS70116C-page 63

dsPIC30F5011/5013

9.1 Timer Gate Operation

The 16-bit timer can be placed in the Gated Time Accu­mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig­nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).

When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.

CY to

9.2 Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:

• a write to the TMR1 register

• a write to the T1CON register

• device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler
clock is halted.

TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.

9.3 Timer Operation During Sleep Mode

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock source is selected as external

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asserted to a logic

‘0’ which defines the external clock source as
asynchronous.

When all three conditions are true, the timer will con­tinue to count up to the Period register and be reset to
0x0000.

When a match between the timer and the Period regis­ter occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.

9.4 Timer Interrupt

The 16-bit timer has the ability to generate an interrupt on
period match. When the timer count matches the Period
register, the T1IF bit is asserted and an interrupt will be
generated if enabled. The T1IF bit must be cleared in
software. The timer interrupt flag, T1IF, is located in the
IFS0 Control register in the interrupt controller.

When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec­tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.

9.5 Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

•Low power

• Real-Time Clock interrupts
These operating modes are determined by setting the

appropriate bit(s) in the T1CON Control register.

FIGURE 9-2: RECOMMENDED

COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC

C1

SOSCI

32.768 kHz
XTAL

C2

C1 = C2 = 18 pF; R = 100K

R

dsPIC30FXXXX

SOSCO

DS70116C-page 64 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

9.5.1 RTC OSCILLATOR OPERATION

When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla­tor output signal, up to the value specified in the Period
register and is then reset to ‘0’.

The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.

Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.

When the CPU enters Sleep mode, the RTC will con­tinue to operate provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.

9.5.2 RTC INTERRUPTS

When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt will be generated
if enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 Status register in the interrupt controller.

Enabling an interrupt is accomplished via the respec­tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 65

dsPIC30F5011/5013

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 —TSYNCTCS — 0000 0000 0000 0000

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 9-1: TIMER1 REGISTER MAP

DS70116C-page 66 Preliminary  2004 Microchip Technology Inc.

T1CON 0104 TON

TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu

Legend: u = uninitialized bit

PR1 0102 Period Register 1 1111 1111 1111 1111

dsPIC30F5011/5013

10.0 TIMER2/3 MODULE

This section describes the 32-bit General Purpose
(GP) Timer module (Timer2/3) and associated Opera­tional modes. Figure 10-1 depicts the simplified block
diagram of the 32-bit Timer2/3 module. Figure 10-2
and Figure 10-3 show Timer2/3 configured as two
independent 16-bit timers, Timer2 and Timer3,
respectively.

The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable
Operating modes. These timers are utilized by other
peripheral modules, such as:

• Input Capture

• Output Compare/Simple PWM
The following sections provide a detailed description,

including setup and control registers, along with asso­ciated block diagrams for the Operational modes of the
timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit Operating modes (except
Asynchronous Counter mode)

• Single 32-bit timer operation

• Single 32-bit synchronous counter

Further, the following operational characteristics are
supported:

• ADC event trigger

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.

For 32-bit timer/counter operation, Timer2 is the LS
Word and Timer3 is the MS Word of the 32-bit timer.

16-bit Timer Mode: In the 16-bit mode, Timer2 and
Timer3 can be configured as two independent 16-bit
timers. Each timer can be set up in either 16-bit Timer
mode or 16-bit Synchronous Counter mode. See
Section 9.0, Timer1 Module for details on these two
Operating modes.

The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high frequency
external clock inputs.

32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle, up to a match
value preloaded into the combined 32-bit Period
register PR3/PR2, then resets to ‘0’ and continues to
count.

For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the LS Word (TMR2 register) will cause
the MS word to be read and latched into a 16-bit
holding register, termed TMR3HLD.

For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to ‘0’ and continues.

When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits
are used for setup and control. Timer2
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is gen­erated with the Timer3 interrupt flag (T3IF)
and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).

 2004 Microchip Technology Inc. Preliminary DS70116C-page 67

dsPIC30F5011/5013

FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>

Write TMR2

Read TMR2

ADC Event Trigger

T3IF
Event Flag

TGATE

(T2CON<6>)

T2CK

TMR3HLD

16

16

Reset

Equal

0

1

TMR3 TMR2

Comparator x 32

PR3 PR2

16

LSB MSB

QD

CK

Q

TGATE (T2CON<6>)

1 x

Sync

TCS

TGATE

TON

TCKPS<1:0>

2

Gate
Sync

T

Note: Timer configuration bit T32 (T2CON<3>) must be set to ‘

bits are respective to the T2CON register.

CY

Prescaler

0 1

0 0

1, 8, 64, 256

1’ for a 32-bit timer/counter operation. All control

DS70116C-page 68 Preliminary  2004 Microchip Technology Inc.

FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM

dsPIC30F5011/5013

T2IF
Event Flag

T2CK

0

1

TGATE

Equal

Reset

PR2

Comparator x 16

TMR2

Q

Q

D

CK

Gate

Sync

CY

T

FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM

TGATE

TCS

1 x

0 1

0 0

TGATE

TON

Sync

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

ADC Event Trigger

T3IF
Event Flag

TGATE

T3CK

Equal

Reset

0

1

PR3

Comparator x 16

TMR3

QD

CK

Q

Sync

T

CY

TGATE

TCS

1 x

0 1

0 0

TGATE

TON

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

 2004 Microchip Technology Inc. Preliminary DS70116C-page 69

dsPIC30F5011/5013

10.1 Timer Gate Operation

The 32-bit timer can be placed in the Gated Time Accu­mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig­nal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).

The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.

CY to

10.2 ADC Event Trigger

When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler oper­ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:

• a write to the TMR2/TMR3 register

• a write to the T2CON/T3CON register

• device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset since the prescaler
clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is
written.

10.4 Timer Operation During Sleep Mode

During CPU Sleep mode, the timer will not operate
because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an interrupt on
period match or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener­ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.

Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).

DS70116C-page 70 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

—TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS — 0000 0000 0000 0000

—TSIDL— — — — — — TGATE TCKPS1 TCKPS0 — —TCS — 0000 0000 0000 0000

T2CON 0110 TON

PR3 010E Period Register 3 1111 1111 1111 1111

PR2 010C Period Register 2 1111 1111 1111 1111

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 10-1: TIMER2/3 REGISTER MAP

 2004 Microchip Technology Inc. Preliminary DS70116C-page 71

TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

T3CON 0112 TON

Legend: u = uninitialized bit

dsPIC30F5011/5013

NOTES:

DS70116C-page 72 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

11.0 TIMER4/5 MODULE

This section describes the second 32-bit General Pur­pose (GP) Timer module (Timer4/5) and associated
Operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 module.
Figure 11-2 and Figure 11-3 show Timer4/5 configured
as two independent 16-bit timers, Timer4 and Timer5,
respectively.

The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some differences
which are listed below:

• The Timer4/5 module does not support the ADC
event trigger feature

• Timer4/5 can not be utilized by other peripheral
modules, such as input capture and
output compare

FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM

Data Bus<15:0>

Write TMR4

Read TMR4

TMR5HLD

16

16

The Operating modes of the Timer4/5 module are
determined by setting the appropriate bit(s) in the
16-bit T4CON and T5CON SFRs.

For 32-bit timer/counter operation, Timer4 is the LS
Word and Timer5 is the MS Word of the 32-bit timer.

Note: For 32-bit timer operation, T5CON control

bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is gen­erated with the Timer5 interrupt flag (T5IF)
and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).

T5IF
Event Flag

T4CK

0

1

TGATE

(T4CON<6>)

Reset

Equal

16

TMR5

MSB

TMR4

LSB

Comparator x 32

PR5 PR4

QD

CK

Q

TGATE (T4CON<6>)

Gate
Sync

T

CY

TCS

1 x

0 1

0 0

Sync

TGATE

TON

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘

bits are respective to the T4CON register.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 73

1’ for a 32-bit timer/counter operation. All control

dsPIC30F5011/5013

FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM

T4IF
Event Flag

T4CK

0

1

TGATE

Equal

Reset

PR4

Comparator x 16

TMR4

Q

Q

D

CK

Gate
Sync

T

CY

FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM

TGATE

TCS

1 x

0 1

0 0

TGATE

TON

Sync

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

PR5

ADC Event Trigger

T5IF
Event Flag

TGATE

T5CK

Note: In the dsPIC30F5011 device, there is no T5CK pin. Therefore, in this device the following modes should

not be used for Timer5:

1: TCS = 1 (16-bit counter)
2: TCS = 0, TGATE = 1 (gated time accumulation)

Equal

Reset

0

1

Comparator x 16

TMR5

QD

CK

Q

Sync

T

CY

TGATE

TCS

1 x

0 1

0 0

TGATE

TON

TCKPS<1:0>

2

Prescaler

1, 8, 64, 256

DS70116C-page 74 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 —TCS — 0000 0000 0000 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — —TCS — 0000 0000 0000 0000

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR4 0114 Timer 4 Register uuuu uuuu uuuu uuuu

TMR5HLD 0116 Timer 5 Holding Register (for 32-bit operations only) uuuu uuuu uuuu uuuu

TMR5 0118 Timer 5 Register uuuu uuuu uuuu uuuu

PR4 011A Period Register 4 1111 1111 1111 1111

PR5 011C Period Register 5 1111 1111 1111 1111

T4CON 011E TON

T5CON 0120 TON

TABLE 11-1: TIMER4/5 REGISTER MAP

 2004 Microchip Technology Inc. Preliminary DS70116C-page 75

Legend: u = uninitialized

dsPIC30F5011/5013

NOTES:

DS70116C-page 76 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

12.0 INPUT CAPTURE MODULE

The key operational features of the input capture
module are:

This section describes the input capture module and
associated Operational modes. The features provided
by this module are useful in applications requiring fre­quency (period) and pulse measurement. Figure 12-1
depicts a block diagram of the input capture module.
Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event
These Operating modes are determined by setting the

appropriate bits in the ICxCON register (where
x = 1,2,...,N). The dsPIC devices contain up to 8
capture channels (i.e., the maximum value of N is 8).

FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module

ICx pin

Prescaler

1, 4, 16

3

Clock

Synchronizer

ICM<2:0>

Mode Select

ICBNE, ICOV

Edge

Detection

Logic

FIFO

R/W

Logic

T2_CNT

T3_CNT

16 16

10

ICxBUF

ICTMR

ICI<1:0>

ICxCON

Data Bus

Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channels 1 through N.

12.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product
family are:

• Capture every falling edge

• Capture every rising edge

Interrupt

Logic

Set Flag

Set Flag
ICxIF

ICxIF

12.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings speci­fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).

 2004 Microchip Technology Inc. Preliminary DS70116C-page 77

dsPIC30F5011/5013

12.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer
which is four 16-bit words deep. There are two status
flags which provide status on the FIFO buffer:

• ICBFNE - Input Capture Buffer Not Empty

• ICOV - Input Capture Overflow
The ICBFNE will be set on the first input capture event

and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.

In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured until all four events have been
read from the buffer.

If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.

12.1.3 TIMER2 AND TIMER3 SELECTION
MODE

The input capture module consists of up to 8 input cap­ture channels. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.

12.1.4 HALL SENSOR MODE

When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the fol­lowing operations are performed by the input capture
logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored since every capture
generates an interrupt.

• A capture overflow condition is not generated in

this mode.

12.2 Input Capture Operation During Sleep and Idle Modes

An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.

Independent of the timer being enabled, the input cap­ture module will wake-up from the CPU Sleep or Idle
mode when a capture event occurs if ICM<2:0> = 111
and the interrupt enable bit is asserted. The same wake­up can generate an interrupt if the conditions for pro­cessing the interrupt have been satisfied. The wake-up
feature is useful as a method of adding extra external pin
interrupts.

12.2.1 INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera­tion with reduced functionality. In the CPU Sleep mode,
the ICI<1:0> bits are not applicable and the input cap­ture module can only function as an external interrupt
source.

The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.

12.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Inter­rupt mode selected by the ICI<1:0> bits is applicable,
as well as the 4:1 and 16:1 capture prescale settings
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover,
the ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.

12.3 Input Capture Interrupts

The input capture channels have the ability to generate
an interrupt based upon the selected number of cap­ture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.

Enabling an interrupt is accomplished via the respec­tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.

DS70116C-page 78 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

— —ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 12-1: INPUT CAPTURE REGISTER MAP

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146

IC1CON 0142

IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu

IC3CON 014A

IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu

IC4CON 014E

IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu

IC5CON 0152

IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu

IC6CON 0156

IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu

IC7CON 015A

IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu

IC8CON 015E

Legend: u = uninitialized bit

 2004 Microchip Technology Inc. Preliminary DS70116C-page 79

dsPIC30F5011/5013

NOTES:

DS70116C-page 80 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

13.0 OUTPUT COMPARE MODULE

These Operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where

This section describes the output compare module and
associated Operational modes. The features provided
by this module are useful in applications requiring
Operational modes, such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

x = 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels (i.e., the maximum value of N is 8).

OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.

Figure 13-1 depicts a block diagram of the output
compare module.

The key operational features of the output compare
module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR

Comparator

01

From GP
Timer Module

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 through N.

OCTSEL

01

T2P2_MATCHTMR2<15:0 TMR3<15:0> T3P3_MATCH

Output

Logic

3

OCM<2:0>

Mode Select

QS

R

Output

Enable

OCx

OCFA

(for x = 1, 2, 3 or 4)

or OCFB

(for x = 5, 6, 7 or 8)

 2004 Microchip Technology Inc. Preliminary DS70116C-page 81

dsPIC30F5011/5013

13.1 Timer2 and Timer3 Selection Mode

Each output compare channel can select between one
of two 16-bit timers, Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.

13.2 Simple Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is

configured for one of three simple Output Compare
Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.

13.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config­ured for one of two Dual Output Compare modes,
which are:

• Single Output Pulse mode

• Continuous Output Pulse mode

13.3.1 SINGLE PULSE MODE

For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):

• Determine instruction cycle time T

• Calculate desired pulse width value based on T

• Calculate time to start pulse from timer start value

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS Compare registers (x denotes
channel 1, 2, ...,N).

• Set Timer Period register to value equal to, or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

To initiate another single pulse, issue another write to
set OCM<2:0> = 100.

CY.

CY.

13.3.2 CONTINUOUS PULSE MODE

For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:

• Determine instruction cycle time T

• Calculate desired pulse value based on TCY.

• Calculate timer to start pulse width from timer start
value of 0x0000.

• Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
Compare registers, respectively.

• Set Timer Period register to value equal to, or
greater than value in OCxRS Compare register.

• Set OCM<2:0> = 101.

• Enable timer, TON (TxCON<15>) = 1.

CY.

13.4 Simple PWM Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config­ured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the main latch
(read only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.

The user must perform the following steps in order to
configure the output compare module for PWM
operation:

1. Set the PWM period by writing to the appropriate

period register.

2. Set the PWM duty cycle by writing to the OCxRS

register.

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON (TxCON<15>) = 1.

13.4.1 INPUT PIN FAULT PROTECTION

FOR PWM

When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config­ured for the PWM mode of operation with the additional
feature of input FAULT protection. While in this mode,
if a logic ‘0’ is detected on the OCFA/B pin, the respec­tive PWM output pin is placed in the high impedance
input state. The OCFLT bit (OCxCON<4>) indicates
whether a FAULT condition has occurred. This state will
be maintained until both of the following events have
occurred:

• The external FAULT condition has been removed.

• The PWM mode has been re-enabled by writing
to the appropriate control bits.

DS70116C-page 82 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

13.4.2 PWM PERIOD

The PWM period is specified by writing to the PRx
register. The PWM period can be calculated using
Equation 13-1.

EQUATION 13-1:

PWM period = [(PRx) + 1] • 4 • T

(TMRx prescale value)

PWM frequency is defined as 1 / [PWM period].

OSC •

FIGURE 13-2: PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle

(OCxR)

When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.

- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.

• The PWM duty cycle is latched from OCxRS into
OCxR.

• The corresponding timer interrupt flag is set.

See Figure 13-2 for key PWM period comparisons.
Timer3 is referred to in Figure 13-2 for clarity.

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle

(OCxR)

13.5 Output Compare Operation During CPU Sleep Mode

When the CPU enters Sleep mode, all internal clocks
are stopped. Therefore, when the CPU enters the
Sleep state, the output compare channel will drive the
pin to the active state that was observed prior to
entering the CPU Sleep state.

For example, if the pin was high when the CPU entered
the Sleep state, the pin will remain high. Likewise, if the
pin was low when the CPU entered the Sleep state, the
pin will remain low. In either case, the output compare
module will resume operation when the device wakes
up.

13.6 Output Compare Operation During CPU Idle Mode

When the CPU enters the Idle mode, the output
compare module can operate with full functionality.

The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is set
to logic ‘0’.

13.7 Output Compare Interrupts

The output compare channels have the ability to gener­ate an interrupt on a compare match, for whichever
Match mode has been selected.

For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated if enabled.
The OCxIF bit is located in the corresponding IFS
Status register and must be cleared in software. The
interrupt is enabled via the respective compare inter­rupt enable (OCxIE) bit located in the corresponding
IEC Control register.

For the PWM mode, when an event occurs, the respec­tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated if enabled. The IF bit is
located in the IFS0 Status register and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE) located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 83

dsPIC30F5011/5013

0000 0000 0000 0000

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 13-1: OUTPUT COMPARE REGISTER MAP

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000

OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000

OC1CON 0184

— —OCSIDL— — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000

OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000

OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000

OC2CON 018A

OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000

OC3CON 0190

OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000

OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC4CON 0196

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC5RS 0198 Output Compare 5 Secondary Register 0000 0000 0000 0000

OC5R 019A Output Compare 5 Main Register 0000 0000 0000 0000

OC5CON 019C

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC6RS 019E Output Compare 6 Secondary Register 0000 0000 0000 0000

OC6R 01A0 Output Compare 6 Main Register 0000 0000 0000 0000

OC6CON 01A2

OC7RS 01A4 Output Compare 7 Secondary Register 0000 0000 0000 0000

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC7R 01A6 Output Compare 7 Main Register 0000 0000 0000 0000

OC7CON 01A8

OC8RS 01AA Output Compare 8 Secondary Register 0000 0000 0000 0000

OC8R 01AC Output Compare 8 Main Register 0000 0000 0000 0000

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0>

OC8CON 01AE

Legend: u = uninitialized bit

DS70116C-page 84 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

14.0 SPI MODULE

The Serial Peripheral Interface (SPI) module is a syn­chronous serial interface. It is useful for communicating
with other peripheral devices, such as EEPROMs, shift
registers, display drivers and A/D converters, or other
microcontrollers. It is compatible with Motorola's SPI
and SIOP interfaces.

14.1 Operating Function Description

Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions.

The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock
input or output), and SSx

In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPIxSR to SDOx pin and simulta­neously shift in data from SDIx pin. An interrupt is gen­erated when the transfer is complete and the
corresponding interrupt flag bit (SPI1IF or SPI2IF) is
set. This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE).

The receive operation is double-buffered. When a com­plete byte is received, it is transferred from SPIxSR to
SPIxBUF.

If the receive buffer is full when new data is being trans­ferred from SPIxSR to SPIxBUF, the module will set the
SPIROV bit indicating an overflow condition. The trans­fer of the data from SPIxSR to SPIxBUF will not be
completed and the new data will be lost. The module
will not respond to SCL transitions while SPIROV is ‘1’,
effectively disabling the module until SPIxBUF is read
by user software.

Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the contents of the shift register (SPIxSR)
are moved to the receive buffer. If any transmit data has
been written to the buffer register, the contents of the
transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.

Note: Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.

In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPIxBUF. The interrupt is generated
at the middle of the transfer of the last bit.

(active low slave select).

In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the inter­rupt is generated when the last bit is latched. If SSx
control is enabled, then transmission and reception are
enabled only when SSx
disabled in SSx

The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi­tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.

mode with SSx high.

= low. The SDOx output will be

OSC/4). This

14.1.1 WORD AND BYTE
COMMUNICATION

A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.

14.1.2 SDOx DISABLE

A control bit, DISSDO, is provided to the SPIxCON reg­ister to allow the SDOx output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.

14.2 Framed SPI Support

The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 85

dsPIC30F5011/5013

FIGURE 14-1: SPI BLOCK DIAGRAM

Read Write

Internal

Data Bus

Shift

Clock

Clock

Control

SPIxBUF

Transmit

Edge

Select

SDIx

SDOx

SSx

SCKx

Note: x = 1 or 2.

SPIxBUF

Receive

SPIxSR

bit 0

SS & FSYNC

Control

FIGURE 14-2: SPI MASTER/SLAVE CONNECTION

SPI™ Master

SDOx

Secondary

Prescaler

1, 2, 4, 6, 8

Enable Master Clock

SDIy

Prescaler

1, 4, 16, 64

SPI™ Slave

Primary

CY

F

Serial Input Buffer

(SPIxBUF)

Shift Register

(SPIxSR)

MSb

PROCESSOR 1

Note: x = 1 or 2, y = 1 or 2.

LSb

SDIx

SCKx

Serial Clock

SDOy

SCKy

Serial Input Buffer

(SPIyBUF)

Shift Register

(SPIySR)

MSb

PROCESSOR 2

LSb

DS70116C-page 86 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

14.3 Slave Select Synchronization

The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx
control enabled (SSEN = 1). When the SSx
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is re­synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx
again, transmission/reception will begin at the MS bit
even if SSx had been de-asserted in the middle of a
transmit/receive.

pin is asserted low

pin

pin is low,

14.4 SPI Operation During CPU Sleep Mode

During Sleep mode, the SPI module is shutdown. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.

The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.

14.5 SPI Operation During CPU Idle Mode

When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 87

dsPIC30F5011/5013

— SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000

— FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

SPI1CON 0222

SPI1STAT 0220 SPIEN

SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000

TABLE 14-1: SPI1 REGISTER MAP

DS70116C-page 88 Preliminary  2004 Microchip Technology Inc.

Legend: u = uninitialized bit

— SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SPI2STAT 0226 SPIEN

TABLE 14-2: SPI2 REGISTER MAP

— FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000

SPI2BUF 022A Transmit and Receive Buffer 0000 0000 0000 0000

Legend: u = uninitialized bit

SPI2CON 0228

dsPIC30F5011/5013

15.0 I2C MODULE

The Inter-Integrated Circuit (I2CTM) module provides
complete hardware support for both Slave and Multi­Master modes of the I2C serial communication
standard, with a 16-bit interface.

This module offers the following key features:

2

C interface supporting both master and slave

•I
operation.

2

•I

C Slave mode supports 7 and 10-bit address.

•I2C Master mode supports 7 and 10-bit address.

•I2C port allows bidirectional transfers between
master and slaves.

• Serial clock synchronization for I
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).

2

C supports multi-master operation; detects bus

•I
collision and will arbitrate accordingly.

FIGURE 15-1: PROGRAMMER’S MODEL

Bit 15

Bit 15

2

C port can be

Bit 9

Bit 7

Bit 7

Bit 8

15.1 Operating Function Description

The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.

2

Thus, the I
a master on an I

C module can operate either as a slave or

15.1.1 VARIOUS I2C MODES

The following types of I2C operation are supported:

2

C slave operation with 7-bit address

•I

2

•I

C slave operation with 10-bit address

•I2C master operation with 7 or 10-bit address

2

See the I

C programmer’s model in Figure 15-1.

Bit 0

Bit 0

Bit 0

Bit 0

Bit 0

Bit 0

2

C Standard and Fast mode

2

C bus.

I2CRCV (8 bits)

I2CTRN (8 bits)

I2CBRG (9 bits)

I2CCON (16 bits)

I2CSTAT (16 bits)

I2CADD (10 bits)

2

15.1.2 PIN CONFIGURATION IN I

I2C has a 2-pin interface: the SCL pin is clock and the
SDA pin is data.

C MODE

15.1.3 I2C REGISTERS

I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ­able. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in Figure 15-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 15-2.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 89

The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the baud rate generator reload value.

In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.

Note: Following a RESTART condition in 10-bit

mode, the user only needs to match the
first 7-bit address.

dsPIC30F5011/5013

FIGURE 15-2: I2C BLOCK DIAGRAM

Internal

Data Bus

SCL

SDA

Shift
Clock

Start, RESTART,

Stop bit Generate

I2CRCV

I2CRSR

Match Detect

I2CADD

Start and

Stop bit Detect

Collision

Detect

LSB

Addr_Match

Control Logic

Read

Write

Read

Write

I2CSTAT

Read

Write

Shift
Clock

Acknowledge

Generation

Clock

Stretching

I2CTRN

Reload

Control

BRG Down

Counter

LSB

FCY

I2CBRG

I2CCON

Read

Write

Read

Write

Read

DS70116C-page 90 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

15.2 I2C Module Addresses

The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.

If the A10M bit (I2CCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LS bits of
the I2CADD register.

If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value ‘11110 A9 A8’ (where
A9 and A8 are two Most Significant bits of I2CADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
in the 10-bit addressing protocol.

2

C Slave Addresses supported by dsPIC30F:

7-bit I

0x00 General call address or start byte
0x01-0x03 Reserved
0x04-0x77 Valid 7-bit addresses
0x78-0x7b Valid 10-bit addresses (lower 7

bits)

0x7c-0x7f Reserved

15.3 I2C 7-bit Slave Mode Operation

Once enabled (I2CEN = 1), the slave module will wait
for a Start bit to occur (i.e., the I
lowing the detection of a Start bit, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the ris­ing edge of SCL.

If an address match occurs, an Acknowledgement will
be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.

15.3.1 SLAVE TRANSMISSION

If the R_W bit received is a ‘1’, then the serial port will
go into Transmit mode. It will send ACK
and then hold SCL to ‘0’ until the CPU responds by writ­ing to I2CTRN. SCL is released by setting the SCLREL
bit, and 8 bits of data are shifted out. Data bits are
shifted out on the falling edge of SCL, such that SDA is
valid during SCL high. The interrupt pulse is sent on the
falling edge of the ninth clock pulse, regardless of the
status of the ACK

received from the master.

15.3.2 SLAVE RECEPTION

If the R_W bit received is a ‘0’ during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are

2

C module is ‘Idle’). Fol-

) bit. The

on the ninth bit

received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK
ninth clock.

If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then

is not sent; however, the interrupt pulse is gener-

ACK
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.

Note: The I2CRCV will be loaded if the I2COV

bit = 1 and the RBF flag = 0. In this case,
a read of the I2CRCV was performed but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The Acknowledgement is not
sent (ACK
updated.

= 1) and the I2CRCV is

is sent on the

15.4 I2C 10-bit Slave Mode Operation

In 10-bit mode, the basic receive and transmit opera­tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.

2

C specification dictates that a slave must be

The I
addressed for a write operation with two address bytes
following a Start bit.

The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.

I2CADD holds the entire 10-bit address. Upon receiv­ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.

The low byte of the address is then received and com­pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.

15.4.1 10-BIT MODE SLAVE
TRANSMISSION

Once a slave is addressed in this fashion with the full
10-bit address (we will refer to this state as
“PRIOR_ADDR_MATCH”), the master can begin
sending data bytes for a slave reception operation.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 91

dsPIC30F5011/5013

15.4.2 10-BIT MODE SLAVE RECEPTION

Once addressed, the master can generate a Repeated
Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation.

15.5 Automatic Clock Stretch

In the Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.

15.5.1 TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared, indicat­ing the buffer is empty.

In Slave Transmit modes, clock stretching is always
performed irrespective of the STREN bit.

Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK
TBF bit is still clear, then the SCLREL bit is automati­cally cleared. The SCLREL being cleared to ‘0’ will
assert the SCL line low. The user’s ISR must set the
SCLREL bit before transmission is allowed to continue.
By holding the SCL line low, the user has time to ser­vice the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit
sequence.

15.5.2 RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at the
end of each data receive sequence.

15.5.3 CLOCK STRETCHING DURING

When the STREN bit is set in Slave Receive mode, the
SCL line is held low when the buffer register is full. The
method for stretching the SCL output is the same for
both 7 and 10-bit Addressing modes.

Clock stretching takes place following the ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing
the SCL output to be held low. The user’s ISR must set
the SCLREL bit before reception is allowed to continue.
By holding the SCL line low, the user has time to ser-

on the falling edge of the ninth clock and if the

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not
be cleared and clock stretching will not
occur.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

7-BIT ADDRESSING (STREN = 1)

2

vice the ISR and read the contents of the I
before the master device can initiate another receive
sequence. This will prevent buffer overruns from
occurring.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
stretching will not occur.

2: The SCLREL bit can be set in software

regardless of the state of the RBF bit. The
user should be careful to clear the RBF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.

CRCV

15.5.4 CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching
will occur on each data receive or transmit sequence as
was described earlier.

15.6 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to the
SCLREL bit with the SCL clock. Clearing the SCLREL
bit will not assert the SCL output until the module
detects a falling edge on the SCL output and SCL is
sampled low. If the SCLREL bit is cleared by the user
while the SCL line has been sampled low, the SCL out­put will be asserted (held low). The SCL output will
remain low until the SCLREL bit is set, and all other
devices on the I
ensures that a write to the SCLREL bit will not violate
the minimum high time requirement for SCL.

If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.

2

C bus have de-asserted SCL. This

15.7 Interrupts

The I2C module generates two interrupt flags, MI2CIF

2

(I

C Master Interrupt Flag) and SI2CIF (I2C Slave Inter­rupt Flag). The MI2CIF interrupt flag is activated on
completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message
directed to the slave.

DS70116C-page 92 Preliminary  2004 Microchip Technology Inc.

dsPIC30F5011/5013

15.8 Slope Control

The I2C standard requires slope control on the SDA
and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate con­trol if desired. It is necessary to disable the slew rate
control for 1 MHz mode.

15.9 IPMI Support

The control bit, IPMIEN, enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.

15.10 General Call Address Support

The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.

The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R_W = 0.

The general call address is recognized when the Gen­eral Call Enable (GCEN) bit is set (I2CCON<15> = 1).
Following a Start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.

If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set and on the falling edge of the ninth bit

bit), the master event interrupt flag (MI2CIF) is

(ACK
set.

When the interrupt is serviced, the source for the inter­rupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific or a general call address.

2

C protocol. It

15.11 I2C Master Support

15.12 I2C Master Operation

The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
not be released.

In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic ‘0’. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK
ditions are output to indicate the beginning and the end
of a serial transfer.

In Master Receive mode, the first byte transmitted con­tains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic ‘1’. Thus, the first byte trans­mitted is a 7-bit slave address, followed by a ‘1’ to indi­cate receive bit. Serial data is received via SDA while
SCL outputs the serial clock. Serial data is received
8 bits at a time. After each byte is received, an ACK
is transmitted. Start and Stop conditions indicate the
beginning and end of transmission.

bit is received. Start and Stop con-

15.12.1 I2C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address, or the sec­ond half of a 10-bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the baud rate generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.

2

C bus will

bit

As a master device, six operations are supported:

• Assert a Start condition on SDA and SCL.

• Assert a RESTART condition on SDA and SCL.

• Write to the I2CTRN register initiating
transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Configure the I

• Generate an ACK condition at the end of a
received byte of data.

 2004 Microchip Technology Inc. Preliminary DS70116C-page 93

2

C port to receive data.

15.12.2 I2C MASTER RECEPTION

Master mode reception is enabled by programming the
Receive Enable bit, RCEN (I2CCON<11>). The I
module must be Idle before the RCEN bit is set, other­wise the RCEN bit will be disregarded. The baud rate
generator begins counting and on each rollover, the
state of the SCL pin ACK
I2CRSR on the rising edge of each clock.

and data are shifted into the

2

C

dsPIC30F5011/5013

15.12.3 BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock arbi­tration is taking place, for instance, the BRG is reloaded
when the SCL pin is sampled high.

2

As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

C standard, FSCK may be 100 kHz or

EQUATION 15-1: SERIAL CLOCK RATE

FSCK = F

CY / I2CBRG

15.12.4 CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive, transmit, or RESTART/Stop condition. When
the SCL pin is allowed to float high, the baud rate gen­erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam­pled high, the baud rate generator is reloaded with the
contents of I2CBRG and begins counting. This ensures
that the SCL high time will always be at least one BRG
rollover count in the event that the clock is held low by
an external device.

15.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION

Multi-master operation support is achieved by bus arbi­tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I

If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted and a
value can now be written to I2CTRN. When the user
services the I
tine, if the I
can resume communication by asserting a Start
condition.

2

C port to its Idle state.

2

C master event Interrupt Service Rou-

2

C bus is free (i.e., the P bit is set), the user

If a Start, RESTART, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are de­asserted, and the respective control bits in the I2CCON
register are cleared to ‘0’. When the user services the
bus collision Interrupt Service Routine, and if the I
bus is free, the user can resume communication by
asserting a Start condition.

The master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.

A write to the I2CTRN will start the transmission of data
at the first data bit regardless of where the transmitter
left off when bus collision occurred.

In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.

2

2

15.13 I2C Module Operation During CPU Sleep and Idle Modes

15.13.1 I2C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.

15.13.2 I2C OPERATION DURING CPU IDLE

MODE

For the I2C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.

C

C

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dsPIC30F5011/5013

— — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000

— I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000

— — — — — — — — Receive Register 0000 0000 0000 0000

— — — — — — — — Transmit Register 0000 0000 1111 1111

C REGISTER MAP

2

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 15-1: I

 2004 Microchip Technology Inc. Preliminary DS70116C-page 95

— — — — — — — Baud Rate Generator 0000 0000 0000 0000

I2CRCV 0200

I2CTRN 0202

I2CBRG 0204

— — — — — — Address Register 0000 0000 0000 0000

I2CADD 020A

I2CCON 0206 I2CEN

I2CSTAT 0208 ACKSTAT TRSTAT

Legend: u = uninitialized bit

dsPIC30F5011/5013

NOTES:

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16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE

This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.

• Fully integrated baud rate generator with 16-bit
prescaler

• Baud rates range from 38 bps to 1.875 Mbps at a
30 MHz instruction rate

• 4-word deep transmit data buffer

• 4-word deep receive data buffer

• Parity, framing and buffer overrun error detection

16.1 UART Module Overview

The key features of the UART module are:

• Full-duplex, 8 or 9-bit data communication

• Even, odd or no parity options (for 8-bit data)

• Support for interrupt only on address detect
(9th bit = 1)

• Separate transmit and receive interrupts

• Loopback mode for diagnostic support

• One or two Stop bits

FIGURE 16-1: UART TRANSMITTER BLOCK DIAGRAM

Internal Data Bus

Write

UxTXREG Low Byte

UTX8

Control and Status bits

Write

Transmit Control

– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt

UxTX

Note: x = 1 or 2.

UTXBRK

Data

Parity

0’ (Start)

‘

‘

1’ (Stop)

Transmit Shift Register (UxTSR)

Parity

Generator

Load TSR

16 Divider

Control
Signals

UxTXIF

16x Baud Clock
from Baud Rate

Generator

 2004 Microchip Technology Inc. Preliminary DS70116C-page 97

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FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM

From UxTX

UxRX

LPBACK

1

0

Internal Data Bus

Read

UxRXREG Low Byte

URX8

Receive Shift Register

8-9

(UxRSR)

Load RSR

to Buffer

16

Write

UxMODE

Receive Buffer Control

– Generate Flags
– Generate Interrupt
– Shift Data Characters

Control
Signals

Read Read

UxSTA

PERR

Write

FERR

· Start bit Detect

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

16 Divider

16x Baud Clock from
Baud Rate Generator

UxRXIF

DS70116C-page 98 Preliminary  2004 Microchip Technology Inc.