MICROCHIP dsPIC30F3014, dsPIC30F4013 Technical data

dsPIC30F3014, dsPIC30F4013

Data Sheet

High-Performance

Digital Signal Controllers

 2004 Microchip Technology Inc. Advance Information DS70138C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

DS70138C-page ii Advance Information  2004 Microchip Technology Inc.

dsPIC30F3014/4013

dsPIC30F3014/4013 High-Performance

Digital Signal Controllers

Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030).

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 48 Kbytes on-chip Flash program space

• 2 Kbytes of on-chip data RAM

• 1 Kbyte of non-volatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• Up to 33 interrupt sources:

- 8 user selectable priority levels

- 3 external interrupt sources

- 4 processor traps

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

• Up to five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• Up to four 16-bit Capture input functions

• Up to four 16-bit Compare/PWM output functions

• Data Converter Interface (DCI) supports common audio Codec protocols, including I

• 3-wire SPI™ module (supports 4 Frame modes)

•I

C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Up to two addressable UART modules with FIFO buffers

• CAN bus module compliant with CAN 2.0B standard

S and AC’97

Analog Features:

• 12-bit Analog-to-Digital Converter (A/D) with:

- 100 Ksps conversion rate

- Up to 13 input channels

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:

DSP Features:

• Dual data fetch

• Modulo and Bit-reversed modes

• Two 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single cycle hardware fractional/ integer multiplier

• All DSP instructins are single cycle

- Multiply-Accumulate (MAC) operation

• Single cycle ±16 shift

 2004 Microchip Technology Inc. Advance Information DS70138C-page 1

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip

low power RC oscillator

dsPIC30F3014/4013

Special Microcontroller Features (Cont.):

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low power, high speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F3014/4013 Controller Family

Program Memory

Device Pins

Bytes Instructions

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

dsPIC30F3014 40/44 24K 8K 2048 1024 3 2 2 - 13 ch 2 1 1 0

dsPIC30F4013 40/44 48K 16K 2048 1024 5 4 4 AC’97, I

Pin Diagrams

40-Pin PDIP

AN0/V

AN1/V

AN2/SS1/LVDIN/CN4/RB2

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

MCLR

REF+/CN2/RB0

REF-/CN3/RB1

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

AN8/RB8

OSC1/CLKIN

INT0/RA11

IC2/INT2/RD9

VDD

Vss

RD3

Vss

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

dsPIC30F3014

Input

Cap

Output

Comp/Std

PWM

AVs s

AN9/RB9

AN10/RB10

AN11/RB11

AN12/RB12

EMUC2/OC1/RD0

EMUD2/OC2/RD1

32 31

Vss

RF0

RF1

U2RX/CN17/RF4

U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/INT1/RD8

RD2

Codec

Interface

A/D 12-bit

100 Ksps

S 13 ch 2 1 1 1

UART

™

SPI

C™

CAN

DS70138C-page 2 Advance Information  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

dsPIC30F3014/4013

EMUC3/SCK1/RF6

IC1/NT1/RD8

RD2

VSSRD3

IC2/INT2/RD9

dsPIC30F3014

1819202122

AVSS

AN9/RB9

AN10/RB10

MCLR

REF+/CN2/RB0

AN0/V

INT0/RA11

363435

REF-/CN3/RB1

AN1/V

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUD2/OC2/RD1 EMUC2/OC1/RD0

RF1 RF0 VSS V

AN12/RB12

AN11/RB11

EMUD3/U1TX/SDO1/SCL/RF3

4443424140

1 2 3 4 5 6 7 8 9 10 11

121314

Note: For descriptions of individual pins, see Section 1.0.

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKIN

VSS

28 27 26 25

24 23

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/CN7/RB5 AN4/CN6/RB4

 2004 Microchip Technology Inc. Advance Information DS70138C-page 3

dsPIC30F3014/4013

Pin Diagrams (Continued)

44-Pin QFN

EMUC3/SCK1/RF6

IC1/INT1/RD8

RD2

VSSRD3

IC2/INT2/RD9

INT0/RA11

434241403938373635

dsPIC30F3014

AVSS

AN9/RB9

AN10/RB10

MCLR

REF-/CN3/RB1

REF+/CN2/RB0

AN1/V

AN0/V

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUD2/OC2/RD1 EMUC2/OC1/RD0

RF1 RF0

VSS VDD

AN12/RB12

EMUD3/U1TX/SDO1/SCL/RF3

1 2 32 3 4 5 6 7 8 9

121314151617181920

AN11/RB11

Note: For descriptions of individual pins, see Section 1.0.

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKIN VSS

VSS

VDD

AN8/RB8

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

DS70138C-page 4 Advance Information  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

40-Pin PDIP

dsPIC30F3014/4013

44-Pin TQFP

AN0/V

AN1/V

AN2/SS1/LVDIN/CN4/RB2

AN4/IC7/CN6/RB4

PGC/EMUC/AN6/OCFA/RB6

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

AN5/IC8/CN7/RB5

PGD/EMUD/AN7/RB7

OSC2/CLKO/RC15

MCLR

REF+/CN2/RB0

REF-/CN3/RB1

AN3/CN5/RB3

AN8/RB8

VDD VSS

OSC1/CLKIN

INT0/RA11

IC2/INT2/RD9

OC4/RD3

1 2 3 4 5 6

dsPIC30F4013

7 8 9 10 11 12 13 14 15 16 17 18 19 20

AVSS

AN9/CSCK/RB9

38 37

AN10/CSDI/RB10

AN11/CSDO/RB11

AN12/COFS/RB12

EMUC2/OC1/RD0

EMUD2/OC2/RD1

VDD

C1RX/RF0

C1TX/RF1

U2RX/CN17/RF4

U2TX/CN18/RF5 U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/INT1/RD8

OC3/RD2

EMUC3/SCK1/RF6

IC1/INT1/RD8

OC3/RD2

VSSOC4/RD3

IC2/INT2/RD9

dsPIC30F4013

1819202122

AVSS

MCLR

AN9/CSCK/RB9

AN10/CSDI/RB10

REF+/CN2/RB0

AN0/V

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

INT0/RA11

363435

REF-/CN3/RB1

AN1/V

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5 U2RX/CN17/RF4

CTX1/RF1 CRX1/RF0

VSS V

EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/COFS/RB12

AN11/CSDO/RB11

EMUD3/U1TX/SDO1/SCL/RF3

4443424140

1 2 3 4 5 6 7 8 9 10 11

121314

AN2/SS1/LVDIN/CN4/RB2

Note: For descriptions of individual pins, see Section 1.0.

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKIN

VSS

29 28

27 26 25

24 23

V AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

AN3/CN5/RB3

 2004 Microchip Technology Inc. Advance Information DS70138C-page 5

dsPIC30F3014/4013

Pin Diagrams (Continued)

44-Pin QFN

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/NT1/RD8

444342414039383736

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

CTX1/RF1

CRX1/RF0

EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/COFS/RB12

1 2 32 3 4 5 6

VSS VDD

10 11

dsPIC30F4013

7 8 9

121314151617181920

AN10/CSDI/RB10

AN11/CSDO/RB11

For descriptions of individual pins, see Section 1.0.

OC3/RD2

VSSOC4/RD3

IC2/INT2/RD9

AVSS

MCLR

AN9/CSCK/RB9

REF+/CN2/RB0

AN0/V

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

INT0/RA11

OSC2/CLKO/RC15 OSC1/CLKIN

VSS

VDD V

AN8/RB8

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

REF-/CN3/RB1

AN3/CN5/RB3

AN1/V

AN2/SS1/LVDIN/CN4/RB2

DS70138C-page 6 Advance Information  2004 Microchip Technology Inc.

dsPIC30F3014/4013

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 CPU Architecture Overview........................................................................................................................................................ 13

3.0 Memory Organization................................................................................................................................................................. 23

4.0 Address Generator Units............................................................................................................................................................ 35

5.0 Flash Program Memory.............................................................................................................................................................. 41

6.0 Data EEPROM Memory ............................................................................................................................................................. 47

7.0 I/O Ports ..................................................................................................................................................................................... 51

8.0 Interrupts .................................................................................................................................................................................... 55

9.0 Timer1 Module ........................................................................................................................................................................... 63

10.0 Timer2/3 Module ........................................................................................................................................................................ 67

11.0 Timer4/5 Module ....................................................................................................................................................................... 73

12.0 Input Capture Module................................................................................................................................................................. 77

13.0 Output Compare Module ............................................................................................................................................................ 81

14.0 SPI Module................................................................................................................................................................................. 85

15.0 I2C Module ................................................................................................................................................................................. 89

16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 97

17.0 CAN Module ............................................................................................................................................................................. 105

18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 115

19.0 12-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 125

20.0 System Integration ................................................................................................................................................................... 131

21.0 Instruction Set Summary .......................................................................................................................................................... 149

22.0 Development Support............................................................................................................................................................... 157

23.0 Electrical Characteristics .......................................................................................................................................................... 163

24.0 Packaging Information.............................................................................................................................................................. 205

Index .................................................................................................................................................................................................. 209

On-Line Support................................................................................................................................................................................. 215

Systems Information and Upgrade Hot Line ...................................................................................................................................... 215

Reader Response .............................................................................................................................................................................. 216

Product Identification System ............................................................................................................................................................ 217

TO OUR VALUED CUSTOMERS

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2004 Microchip Technology Inc. Advance Information DS70138C-page 7

dsPIC30F3014/4013

NOTES:

DS70138C-page 8 Advance Information  2004 Microchip Technology Inc.

dsPIC30F3014/4013

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC30F3014 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(24 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

Decode and

Generation

Instruction

Control

Timing

MCLR

VDD, V

, AV

PSV & Table Data Access

Control Block

Control

Start-up Timer

Low Voltage

Y Data Bus

PCH PCL

PCU Program Counter

Stac k

Logic

Power-up

Oscillator

POR/BOR

Watchdog

ROM Latch

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

Y Data

(1 Kbyte)

Address

Y AGU

Effective Address

DSP

Engine

Latch

RAM

16 x 16

W Reg Array

ALU<16>

X Data Bus

X RAGU X WAGU

This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013 respectively.

Data LatchData Latch

X Data

RAM

(1 Kbyte)

Address

Latch

Divide

Unit

PORTA

PORTB

PORTC

PORTD

INT0/RA11

AN0/CN2/RB0 AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 AN12/RB12

EMUD1/SOSCI/T2CK/U1ATX/ CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/ CN0/RC14

OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 RD2 RD3 IC1/INT1/RD8 IC2/INT2/RD9

RF0 RF1 U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4

U2TX/CN18/RF5 EMUC3/SCK1/RF6

12-bit ADC

Timers

Input

Capture

Module

DCI

Output

Compare

Module

SPI1

I2C™

UART1,

UART2

PORTF

 2004 Microchip Technology Inc. Advance Information DS70138C-page 9

dsPIC30F3014/4013

FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(48 Kbytes)

Data EEPROM

(1 Kbyte)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

Generation

Instruction

Decode &

Control

Timing

MCLR

VDD, V

PSV & Table Data Access

Control Block

, AV

Y Data Bus

PCH PCL

PCU Program Counter

Stac k

Control

Logic

Power-up

Oscillator

Start-up Timer

POR/BOR

Watchdog

Low Voltage

ROM Latch

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

DSP

Y AGU

Engine

X Data Bus

Y Data

RAM

(1 Kbyte)

Address

Latch

X RAGU X WAGU

Effective Address

16 x 16

W Reg Array

ALU<16>

Data LatchData Latch

X Data

RAM

(1 Kbyte)

Address

Latch

Divide

Unit

PORTA

PORTB

PORTC

PORTD

INT0/RA11

AN0/CN2/RB0 AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7

AN8/RB8 AN9/CSCK/RB9

AN10/CSDI/RB10 AN11/CSDO/RB11 AN12/COFS/RB12

EMUD1/SOSCI/T2CK/U1ATX/ CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/ CN0/RC14

OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3

IC1/INT1/RD8 IC2/INT2/RD9

CAN1

12-bit ADC

Timers

Input

Capture

Module

DCI

Output

Compare

Module

SPI1

I2C™

UART1,

UART2

PORTF

C1RX/RF0 C1TX/RF1 U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4

U2TX/CN18/RF5 EMUC3/SCK1/RF6

DS70138C-page 10 Advance Information  2004 Microchip Technology Inc.

dsPIC30F3014/4013

Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN12 I Analog Analog input channels.

DD P P Positive supply for analog module.

SS P P Ground reference for analog module.

CLKI

CLKO

CN0-CN7, CN17-CN18 I ST Input change notification inputs.

COFS CSCK CSDI CSDO

C1RX C1TX

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3

IC1, IC2, IC7, IC8 I ST Capture inputs 1,2, 7 and 8.

INT0 INT1 INT2

LVDIN I Analog Low Voltage Detect Reference Voltage input pin.

MCLR

OCFA OC1-OC4

OSC1

OSC2

PGD PGC

Typ e

I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O

I I I

I/P ST Master Clear (Reset) input or programming voltage input. This

I/O

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

AN6 and AN7 are also used for device programming data and clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin

function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ST ST ST

—

ST ST ST ST ST ST ST ST

ST ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

ST ST

Data Converter Interface Frame Synchronization pin. Data Converter Interface Serial Clock input/output pin. Data Converter Interface Serial data input pin. Data Converter Interface Serial data output pin.

CAN1 Bus Receive pin. CAN1 Bus Transmit pin.

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin.

External interrupt 0. External interrupt 1. External interrupt 2.

pin is an active low Reset to the device.

Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare outputs 1 through 4.

CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin.

Description

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dsPIC30F3014/4013

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RA11 I/O ST PORTA is a bidirectional I/O port.

RB0-RB12 I/O ST PORTB is a bidirectional I/O port.

RC13-RC15 I/O ST PORTC is a bidirectional I/O port.

RD0-RD3, RD8, RD9 I/O ST PORTD is a bidirectional I/O port.

RF0-RF5 I/O ST PORTF is a bidirectional I/O port.

SCK1 SDI1 SDO1 SS1

SCL SDA

SOSCO SOSCI

T1CK T2CK

U1RX U1TX U1ARX U1ATX

DD P — Positive supply for logic and I/O pins.

SS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Typ e

I/O

I/O I/O

I I

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

ST ST

—

ST ST

—

ST/CMOS

ST ST

—

Description

Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization.

Synchronous serial clock input/output for I Synchronous serial data input/output for I

32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Timer1 external clock input. Timer2 external clock input.

UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit.

DS70138C-page 12 Advance Information  2004 Microchip Technology Inc.

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2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

This section contains a brief overview of the CPU architecture of the dsPIC30F.

The core has a 24-bit instruction word. The Program Counter (PC) is 23-bits wide with the Least Significant (LS) bit always clear (refer to Section 3.1), and the Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes.

There are two methods of accessing data stored in program memory:

• The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.

For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.

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The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC core has a 16-bit STATUS register (SR), the LS Byte of which is referred to as the SR Low byte (SRL) and the MS Byte as the SR High byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit.

2.2.3 PROGRAM COUNTER

The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

DS70138C-page 14 Advance Information  2004 Microchip Technology Inc.

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

W13/DSP Write Back

dsPIC30F3014/4013

W0/WREG

W10

W11

W12/DSP Offset

W14/Frame Pointer

W15/Stack Pointer

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31

AccA

AccB

Data Table Page Address

DOSTART

SPLIM

PC0

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOEND

Stack Pointer Limit Register

AD15

Program Counter

REPEAT Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

 2004 Microchip Technology Inc. Advance Information DS70138C-page 15

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

Status Register

dsPIC30F3014/4013

2.3 Divide Support

The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.sw - 16/16 signed divide

5. DIV.uw - 16/16 unsigned divide

The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration.

The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the REPEAT instruction as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The divide flow is interruptible. However,

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw or DIV.s

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.uw or DIV.u

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

the user needs to save the context as appropriate.

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2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow architecture, threfore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED, EDAC).

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y) Yes

MAC A = A + x

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 4-2.

A block diagram of the DSP engine is shown in Figure 2-2.

 2004 Microchip Technology Inc. Advance Information DS70138C-page 17

dsPIC30F3014/4013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

Round

Logic

S a

Y Data Bus

Sign-Extend

17-bit

Multiplier/Scaler

Barrel Shifter

X Data Bus

Zero Backfill

To/From W Array

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2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2 For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 2 16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10 multiply operation generates a 1.31 product which has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

-5

. In Fractional mode, the 16x16

-10

N-1

to 2

1-N

N-1

– 1.

). For a

2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/borrow other input is complemented. The adder/subtracter generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits bits are not identical to each other.

The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six Status register bits have been provided to support saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated (bit 39 overflow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated (bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 8.0) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active high and the other input is

input is active low and the

 2004 Microchip Technology Inc. Advance Information DS70138C-page 19

dsPIC30F3014/4013

The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The overflow and saturation status bits can optionally be viewed in the STATUS register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators.

The device supports three saturation and overflow modes:

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data, or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow: The bit 39 overflow status bit from the adder is used to set the SA or SB bit which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following Addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13]+=2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the LS Word is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LS bit (bit 16 of the accumulator) of ACCxH is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus (subject to data saturation, see Section 2.4.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

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2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly, For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MS bit of the source (bit 39) is used to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators, or the X bus (to support multi-bit shifts of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of ‘0’ will not modify the operand.

The barrel shifter is 40-bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 16 for left shifts.

 2004 Microchip Technology Inc. Advance Information DS70138C-page 21

dsPIC30F3014/4013

NOTES:

DS70138C-page 22 Advance Information  2004 Microchip Technology Inc.

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3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1. Note that the program space address is incremented by two between successive program words in order to provide compatibility with data space addressing.

FIGURE 3-1: dsPIC30F3014 PROGRAM

SPACE MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Alternate Vector Table

Program Memory

Space

User Memory

UNITID (32 instr.)

Device Configuration

Spac e

Configuration Memory

Reserved

User Flash

(8K instructions)

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

Reserved

Registers

Reserved

DEVID (2)

000000 000002 000004

00007E 000080

000084

0000FE 000100

003FFE 004000

7FFBFE 7FFC00

7FFFFE 800000

8005BE 8005C0

8005FE 800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FF0002

Vector Tables

User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear.

FIGURE 3-2: dsPIC30F4013 PROGRAM

SPACE MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Alternate Vector Table

Program Memory (16K instructions)

Space

User Memory

UNITID (32 instr.)

Spac e

Configuration Memory

Device Configuration

Reserved

User Flash

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

Reserved

Registers

Reserved

DEVID (2)

000000 000002 000004

00007E 000080

000084

0000FE 000100

007FFE 004000

7FFBFE 7FFC00

7FFFFE 800000

8005BE 8005C0

8005FE 800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FF0002

Vector Tables

 2004 Microchip Technology Inc. Advance Information DS70138C-page 23

dsPIC30F3014/4013

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access User 0 PC<22:1> 0

TBLRD/TBLWT User

TBLRD/TBLWT Configuration

Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

Access

Space

(TBLPAG<7> = 0)

(TBLPAG<7> = 1)

<23> <22:16> <15> <14:1> <0>

TBLPAG<7:0> Data EA<15:0>

FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using Program Counter

Program Space Address

0Program Counter

Select

Using Program Space

Visibility

Using Table Instruction

User/ Configuration Space Select

Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory.

PSVPAG Reg

1/0

TBLPAG Reg

8 bits

24-bit EA

15 bits

16 bits

Byte

Select

DS70138C-page 24 Advance Information  2004 Microchip Technology Inc.

dsPIC30F3014/4013

3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.

There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LS Word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the LS Data Word, and TBLRDH and TBLWTH access the space which contains the MS Data Byte.

Figure 3-3 shows how the EA is created for table operations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

A set of table instructions are provided to move byte or word sized data to and from program space.

1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; P<15:0> maps to D<15:0>. Byte: Read one of the LS Bytes of the program address; P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the destination byte when byte select = 1.

2. TBLWTL: Table Write Low (refer to Section 5.0 for details on Flash Programming)

3. TBLRDH: Table Read High Word: Read the MS Word of the program address; P<23:16> maps to D<7:0>; D<15:8> will always be = 0. Byte: Read one of the MS Bytes of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1.

4. TBLWTH: Table Write High (refer to Section 5.0 for details on Flash Programming)

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LS WORD)

PC Address

0x000000 0x000002

0x000004 0x000006

Program Memory ‘Phantom’ Byte (read as ‘0’)

00000000

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

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FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MS BYTE)

TBLRDH.W

PC Address

0x000000 0x000002

0x000004 0x000006

Program Memory ‘Phantom’ Byte (read as ‘0’)

00000000

TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs if the MS bit of the data space EA is set and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 2.4, DSP Engine.

Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data.

Although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see Figure 3-6), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the Programmer’s Reference Manual (DS70030) for details on instruction encoding.

TBLRDH.B (Wn<0> = 0)

Note that by incrementing the PC by 2 for each program memory word, the LS 15 bits of data space addresses directly map to the LS 15 bits in the corresponding program space addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG<7:0>, as shown in Figure 3-6.

Note: PSV access is temporarily disabled during

table reads/writes.

For instructions that use PSV which are executed outside a REPEAT loop:

• The following instructions will require one instruction cycle in addition to the specified execution time:

- MAC class of instructions with data operand

pre-fetch

- MOV instructions

- MOV.D instructions

• All other instructions will require two instruction cycles in addition to the specified execution time of the instruction.

For instructions that use PSV which are executed inside a REPEAT loop:

• The following instances will require two instruction cycles in addition to the specified execution time of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.

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FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space Program Space

0x0000

0x000100

0x00

(1)

23 15 0

Data Read

0x000200

0x007FFF

EA<15> =

Data Space EA

EA<15> = 1

Upper Half of Data Space is Mapped into Program Space

BSET CORCON,#2 ; PSV bit set MOV #0x00, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x8200, W0 ; Access program memory location

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines

the page in program space to which the upper half of data space is being mapped). The memory map shown here is for a dsPIC30F4013 device.

; using a data space access

0x8000

0xFFFF

PSVPAG

Address

Concatenation

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3.2 Data Address Space

The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.

When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64-Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instructions extract the Y address space from data space and address it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions.

The data space memory map is shown in Figure 3-7.

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