MICROCHIP dsPIC30F2011, dsPIC30F2012, dsPIC30F3012, dsPIC30F3013 Technical data

dsPIC30F2011/2012/3012/3013

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PIC, PICSTART ,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC 8-bit MCUs, KEELOQ microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

code hopping devices, Serial EEPROMs,

dsPIC30F2011/2012/3012/3013

dsPIC30F201 1/2012/3012/3013 High-Performance

Digital Signal Controllers

Note: This data sheet summarizes features of this g roup of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more informat ion on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 24 Kbytes on-chip Flash program space

• Up to 2 Kbytes of on-chip data RAM

• Up to 1 Kbytes of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz - 10 MHz oscillator input with PLL active (4x, 8x, 16x)

• Up to 21 interrupt sources:

- 8 user-selectable priority levels

- 3 external interrupt sources

- 4 proce ssor trap sources

DSP Features:

• Dual data fetch

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single-cycle hardw are frac tio nal / integer multiplier

• All DSP instructions are single cycle

- Multiply-Accumulate (MAC) operation

• single-cycle ±16 shift

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25mA

• Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

• 3-wire SPI modules (supports four Frame modes)

•I

C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Up to two addressable UART modules with FIFO buffers

Analog Features:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 ksps conversion rate

- Up to 10 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Reset

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip lowpower RC oscillator for reliable operation

• Fail-Safe Clock Monitor opera t ion :

- Detects clock failure and switches to on-chip

low-power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low-power consumption

dsPIC30F2011/2012/3012/3013

dsPIC30F2011/2012/3012/3013 Sensor Family

Program Memory

Device Pins

Bytes Instructions

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

Input

Cap

dsPIC30F2011 18 12K 4K 1024 – 3 2 2 8 ch 1 1 1 dsPIC30F3012 18 24K 8K 2048 1024 3 2 2 8 ch 1 1 1 dsPIC30F2012 28 12K 4K 1024 – 3 2 2 10 ch 1 1 1 dsPIC30F3013 28 24K 8K 2048 1024 3 2 2 10 ch 2 1 1

Pin Diagrams

18-Pin PDIP and SOIC

Output

Comp/Std

PWM

A/D 12-bit

200 Ksps

UART

SPI

C™

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

28-Pin PDIP and SOIC

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

28-Pin SPDIP and SOIC

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

MCLR

AN2/SS1

/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC1/CLKI

OSC2/CLKO/RC15

MCLR

AN2/SS1/LVDIN/CN4/RB2

REF-/CN3/RB1

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

IC2/INT2/RD9 EMUC2/IC1/INT1/RD8

REF-/CN3/RB1

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

OSC2/CLKO/RC15

IC2/INT2/RD9

VSS

OSC1/CLKI V

VDD

MCLR

VSS

OSC1/CLKI

VDD

dsPIC30F3012

dsPIC30F2012

dsPIC30F3013

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

12 11

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 EMUC2/OC1/IC1/INT1/RD0

dsPIC30F2011

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

CN17/RF4

CN18/RF5

SSOSC2/CLKO/RC15

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

16 15

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

U2RX/CN17/RF4

U2TX/CN18/RF5

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7

8 9 10 11 12 13 14

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

Pin Diagrams

28-Pin QFN

dsPIC30F2011/2012/3012/3013

REF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AVDD

AVSS

AN6/SCK1/INT0/OCFA/RB6

EMUD3/AN0/V

MCLR

EMUD2/AN7/OC2/IC2/INT2/RB7

111213

EMUC2/OC1/IC1/INT1/RD0

21 20

NC NC

VDD

VSS

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

/LVDIN/CN4/RB2

AN2/SS1

OSC2/CLKO/RC15

AN3/CN5/RB3

NC NC

OSC1/CLKI

1 2 3 4

5 6 7

2827262524

dsPIC30F2011

8910

EMUD1/SOSC1/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

dsPIC30F2011/2012/3012/3013

Pin Diagrams

28-Pin QFN

REF-/CN3/RB1

AVDD

AVSS

AN6/OCFA/RB6

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

OSC1/CLKI

OSC2/CLKO/RC15

1 2 3

dsPIC30F2012

5 6 7

MCLR

EMUC3/AN1/V

EMUD3/AN0/VREF+/CN2/RB0

121314

EMUD2/AN7/RB7

AN8/OC1/RB8 AN9/OC2/RB9

CN17/RF4

CN18/RF5

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

IC2/INT2/RD9

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

PGD/EMUD/U1TX/SDO1/SCL/RF3

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

Note: For descriptions of individual pin s, see Section 1.0 “Device Overview”.

Pin Diagram

44-Pin QFN

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

dsPIC30F2011/2012/3012/3013

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

NCNCV

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4NCEMUC2/OC1/IC1/INT1/RD0NCNC

4443 424140 393837 3635

1 2 32

NC NC NC NC NC NC NC

6 7 8

9 10 11

dsPIC30F3012

1213 141516 171819 2021

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI VSS

31 30

NC NC

AN3/CN5/RB3

25 24

AN2/SS1/LVDIN/CN4/RB2

AVSS

AVDD

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

MCLR

REF-/CN3/RB1

REF+/CN2/RB0

EMUC3/AN1/V

EMUD3/AN0/V

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

dsPIC30F2011/2012/3012/3013

Pin Diagrams

44-Pin QFN

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

IC2/INT2/RD9

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8NCNC

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

PGC/EMUC/U1RX/SDI1/SDA/RF2

NC NC

U2TX/CN18/RF5

U2RX/CN17/RF4

AN9/OC2/RB9 AN8/OC1/RB8

444342414039383736

1 2 32

3 4

5 6

dsPIC30F3013

7 8

9 10 11

121314151617181920

AVSS

AVDD

AN6/OCFA/RB6

EMUD2/AN7/RB7

OSC2/CLKO/RC15

OSC1/CLKI VSS

30 29

NC NC

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

MCLR

REF-/CN3/RB1

REF+/CN2/RB0

EMUC3/AN1/V

EMUD3/AN0/V

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

dsPIC30F2011/2012/3012/3013

1.0 Device Overview.......................................................................................................................................................................... 9

2.0 CPU Architecture Overview........................................................................................................................................................ 17

3.0 Memory Organization................................................................................................................................................................. 27

4.0 Address Generator Units............................................................................................................................................................ 41

5.0 Flash Program Memory............ ............................................................................. ..................................................................... 47

6.0 Data EEPROM Memory............................................................................................... ..............................................................53

7.0 I/O Ports.................. ................................................................................................................................................................... 57

8.0 Interrupts....................................................................................................................................................................................63

9.0 Timer1 Module ........................................................................................................................................................................... 71

10.0 Timer2/3 Module ........................ .. .... .. .. .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. .. .... .. ..... .... .. .. .. .. .... ..... ............................................................ 75

11.0 Input Capture Module..................................................................... .. .... ....... .. .. .... .. .. .. ....... .......................................................... 81

12.0 Output Compare Module..................................................................................... ....................................................................... 85

13.0 SPI Module.................................................................................................................................................................................89

14.0 I2C Module................................................................................................................................................................................. 93

15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 101

16.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 109

17.0 System Integration................................... ................................................................................................................................119

18.0 Instruction Set Summary..........................................................................................................................................................133

19.0 Development Support............................................................................................................................................................... 141

20.0 Electrical Characteristics..........................................................................................................................................................145

21.0 Packaging Information. .............................................................................. ............................................................................... 183

Index ..................................................................................................................................................................................................193

The Microchip Web Site..................................................................................................................................................................... 199

Customer Change Notification Service ..............................................................................................................................................199

Customer Support.............................................................................................................................................................................. 199

Reader Response.............................................................................................................................................................................. 200

Product Identification System............................................................................................................................................................201

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more informat ion on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual“ (DS70157).

This data sheet contains information specific to the dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and dsPIC30F3013 Digit al Signal Controll ers (DSC). These devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture.

The following block di agrams depict the archi tecture for these devices:

• Figure 1-1 illustrates the dsPIC30F2011

• Figure 1-2 illustrates the dsPIC30F2012

• Figure 1-3 illustrates the dsPIC30F3012

• Figure 1-4 illustrates the dsPIC30F3013 Following the block d iag ram s, Table 1-1 relates the I/O

functions to pinout information.

dsPIC30F2011/2012/3012/3013

FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(12 Kbytes)

Data Latch

Control Block

Instruction

Decode &

Control

PSV & Table Data Access

Control

Y Data Bus

PCH PCL

PCU Program Counter

Stack

Logic

ROM Latch

Loop

Control

Logic

Decode

Y Data

RAM

(512 bytes)

Address

Latch

Y AGU

Effective Address

X Data Bus

Data LatchData Latch

(512 bytes)

Address

X RAGU X WAGU

16 x 16

W Reg Array

X Data

RAM

Latch

PORTB

PORTC

EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/R AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15

REF

+/CN2/RB0

REF

-/CN3/RB1

OSC1/CLKI

Timing

Generation

MCLR

VDD, V

AVDD, AV

12-bit ADC

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

Input

Capture

Module

Timers

DSP Engine

Compare

Module

SPI1

Output

Divide

Unit

ALU<16>

UART1

EMUC2/OC1/IC1/INT1/RD0

PORTD

I2C™

dsPIC30F2011/2012/3012/3013

FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(12 Kbytes)

Data Latch

PSV & Table Data Access

Control Block

Instruction Decode &

Control

Y Data Bus

PCH PCL

PCU Program Counter

Stack

Control

Logic

ROM Latch

Loop

Control

Logic

Decode

Y Data

(512 bytes)

Address

Latch

Y AGU

Effective Address

X Data Bus

16 16

Data LatchData Latch

RAM

(512 bytes)

X RAGU X WAGU

16 x 16

W Reg Array

X Data

RAM

Address

Latch

PORTB

PORTC

REF

EMUD3/AN0/V EMUC3/AN1/V

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4 AN5/CN7/RB5 AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

+/CN2/RB0

REF

-/CN3/RB1

OSC1/CLKI

Timing

Generation

MCLR

VDD, V

, AV

12-bit ADC

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

Input Capture Module

Timers

DSP

Engine

Compare

Module

Output

SPI1

Divide Unit

ALU<16>

UART1

I2C™

PORTD

PORTF

EMUC2/IC1/INT1/RD8 IC2/INT2/RD9

PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 CN17/RF4 CN18/RF5 SCK1/INT0/RF6

dsPIC30F2011/2012/3012/3013

FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(24 Kbytes)

Data EEPROM

(1 Kbytes)

Data Latch

Control Block

Instruction

Decode &

Control

PSV & Table Data Access

Control

Y Data Bus

PCH PCL

PCU Program Counter

Stack

Logic

ROM Latch

Loop

Control

Logic

Decode

Y Data

RAM

(1 Kbytes)

Address

Latch

Y AGU

Effective Address

X Data Bus

Data LatchData Latch

X Data

(1 Kbytes)

Address

Latch

X RAGU X WAGU

16 x 16

W Reg Array

RAM

PORTB

PORTC

EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/R AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15

REF

+/CN2/RB0

REF

-/CN3/RB1

OSC1/CLKI

Timing

Generation

MCLR

VDD, V

AVDD, AV

12-bit ADC

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

Input

Capture

Module

Timers

DSP Engine

Compare

Module

SPI1

Output

Divide

Unit

ALU<16>

UART1

EMUC2/OC1/IC1/INT1/RD0

PORTD

I2C™

dsPIC30F2011/2012/3012/3013

FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(24 Kbytes)

Data EEPROM

(1 Kbytes)

Data Latch

Data Access

Control Block

Instruction

Decode &

Control

PSV & Table

Control

Y Data Bus

PCH PCL

PCU Program Counter

Stack Logic

ROM Latch

Loop

Control

Logic

Decode

Y Data

RAM

(1 Kbytes)

Address

Latch

Y AGU

Effective Address

X Data Bus

Data LatchData Latch

X Data

(1 Kbytes)

Address

16 X RAGU

X WAGU

16 x 16

W Reg Array

RAM

Latch

PORTB

PORTC

EMUD3/AN0/V EMUC3/AN1/V

AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15

REF

+/CN2/RB0

REF

-/CN3/RB1

OSC1/CLKI

Timing

Generation

MCLR

VDD, V

, AV

12-bit ADC

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Low-Voltage

Detect

Input

Capture

Module

Timers

DSP Engine

Output

Compare

Module

SPI1

Divide

Unit

EMUC2/IC1/INT1/RD8 IC2/INT2/RD9

ALU<16>

I2C™

UART1,

UART2

PORTD

PORTF

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4

U2TX/CN18/RF5 SCK1/INT0/RF6

dsPIC30F2011/2012/3012/3013

Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0 - AN9 I Analog Analog input channels. AV

DD P P Positive supply for analog module. SS P P Ground reference fo r an al og module.

AV CLKI

CLKO

CN0 - CN7 I ST Input ch ange notification inputs.

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3

IC1 - IC2 I ST Capture in puts 1 thr ou gh 2. INT0

INT1 INT2

LVDIN I Analog Low-Voltage Detect Reference Voltage Input pin. MCLR

OC1-OC2 OCFA

OSC1

OSC2

PGD PGC

RB0 - RB9 I/O ST PORTB is a bidirectional I/O port. RC13 - RC15 I/O ST PORTC is a bidirectional I/O port. RD0, RD8 - RD9 I/O ST PORTD is a bidirectional I/O port. RF2 - RF5 I/O ST PORTF is a bidirectional I/O port. SCK1

SDI1 SDO1

Type

I/O I/O I/O I/O I/O I/O I/O I/O

I I I

I/P ST Maste r Cl ear (Reset) input or programm i ng voltage input. This

I I

I/O

Legend: CMOS = CMOS compatible input or out put Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

ST/CMOS—External clock source i nput. Alway s associated with OSC1 pin

function. Oscillator crystal outp ut . Co nnects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always ass ociated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ST ST ST ST ST ST ST ST

ST ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

ST ST

—

ICD Primary Communi cation Channel data input/ou tp ut pi n. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Comm unication Channel cloc k i nput/output pin. ICD T ertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Comm unication Channel data input /o utput pin. ICD Quaternary Comm unication Channel clock in put / ou tp ut pi n.

External interrupt 0. External interrupt 1. External interrupt 2.

pin is an active-low Reset to the device. Compare outputs 1 through 2.

Compare Fault A input.

CMOS otherwise. Oscillator crystal outp ut . Co nnects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

In-Circuit Serial Programmi ng™ data input/output pin. In-Circuit Serial Programmi ng clock input pin.

Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization.

Description

dsPIC30F2011/2012/3012/3013

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

SCL SDA

SOSCO SOSCI

T1CK T2CK

U1RX U1TX U1ARX U1ATX U2RX U2TX

DD P — Positive supply for logic and I/O pins.

V VSS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog Voltage Reference (High) input.

V VREF- I Analog Analog Voltage Reference (Low) input.

Type

I/O I/O

I I

Legend: CMOS = CMOS compatible input or out put Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

ST ST

—

ST/CMOS

ST ST

—

Description

Synchronous serial clock input/output for I2C™. Synchronous serial data inp ut / out put for I

32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; C M O S ot her w i se.

Timer1 external clock input. Timer2 external clock input.

UART1 Receive. UART1 Transmit. UART1 Al t ernate Receive. UART1 Al t ernate Transmit . UART2 Receive. UART2 Transmit.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

2.0 CPU ARCHITECTURE OVERVIEW

Note: This data sheet summarizes features of this group

This section is an overview of the CPU architecture of the dsPIC30F. The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear (see Section 3.1 “Program Address Space”). The Most Significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program spac e. An instruction prefetch m e ch anism helps maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

2.1 Core Overview

The working registe r array consis ts of 16 x 16-bit re gisters, each of which can act as data, address or offset registers. One working register (W15) operates as a Software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single unified data space. The Multiply-Accu mulate (MAC) class of dual s ource DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2 “Data Address Space”). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes and most instruction s can address da ta either as words or bytes.

Two ways to access data in program memory are:

• The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. Thus any instruction can access program space as if it were data space, with a limitation that the access requires an additional cycle. On ly the low er 16 bit s of ea ch instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within program space is als o possibl e using any work ing register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also support s Bit-Reverse d Addressi ng on destination ef fective addresses to great ly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 “Address Generator Units” for details on Modulo and Bit-Reversed Addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with pre-defined addressing modes, depending upon their functional requirements.

For most i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3 operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional b arre l s hi fter. Data in the accumulator or any wor kin g regi ste r can be sh ifted up to 15 bi ts right, or 16 bits left in a single cycle. The DSP instructions operate seamles sly with all other in struct ion s and have been desi gned for o ptimal re al-time p erformanc e. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear is for all others. This has been achieved in a transpar en t and fle xib le mann er, by dedicating certai n working registe rs to eac h address spac e for the MAC class of instructions.

dsPIC30F2011/2012/3012/3013

The core does not support a multi-stage instruction pipeline. However, a single-stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) a nd 54 int errup ts. Each interrupt is prioritized based on a us er-assigned priori ty between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temp orary holding reg ister and can transfer it s con ten ts to or from its host reg is ter upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start and popped on loop end.

When a byte operation is performed on a working register , only th e Least Significan t Byte (LSB) of th e targ et register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes (MSB) can be manipulated through byte-wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® DSC devices contain a software stack. W15 is the dedicated Software Stack Pointer (SP), which is autom atical ly modifi ed by exce ption pr ocessing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W register s. This simpli fies the read ing, writing and mani pulati on of the Stack Pointe r (e.g., cr eating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedica ted as a Stack Frame Po int er, as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register (SR), the LSB of which is referred to as the SR Low byte (SRL) and the MSB as the SR High byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation Status flags (including the Z bit), as wel l as the CPU Inter rupt Pri ority Level Status bits, IPL<2:0>, and the Repeat Active Status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

dsPIC30F2011/2012/3012/3013

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

W13/DSP Write-Back

W0/WREG

W1 W2 W3 W4 W5

W6 W7

W8 W9 W10 W11

W12/DSP Offset

W14/Frame Pointer

W15/Stack Pointer

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31 ACCA ACCB

Data Table Page Address

SPLIM Stack Pointer Limit Register

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOSTART

DOEND

PC0

AD15

Program Counter

REPEAT Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

STATUS register

dsPIC30F2011/2012/3012/3013

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed fractional divide ope rati on , as w ell as 32/16-bit and 16/ 16-bit signed an d unsigned intege r divide operati ons, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.s - 16/16 signed divide

5. DIV.u - 16/16 unsigned divide The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or sign-extended during the first iteration.

The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT . Th e divide instructi on does not automatica lly set up the RCOUNT value and it must, therefore, be explicitly and correctl y specifi ed in the REPEAT instruction, as shown in Table 2-1 (REPEAT executes the target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The divide flow is interruptible. However,

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.s Signed divide: Wm/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1

Signed fractional divide: Wm/Wn → W0; Rem → W1

the user needs to save the context as appropriate.

dsPIC30F2011/2012/3012/3013

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no ad ditional dat a. These instr uctions are ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow architecture, therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concu rrently by the s ame instruction (e.g., ED, EDAC). See Table 2-2.

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y) Yes MAC A = A + x

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 3-3.

A block diagram of the DSP engine is shown in Figure 2-2.

No No

dsPIC30F2011/2012/3012/3013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

Round

Logic

S a

Y Data Bus

Sign-Extend

17-bit

Multiplier/Scaler

Barrel Shifter

X Data Bus

Zero Backfill

To/From W Array

dsPIC30F2011/2012/3012/3013

2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or unsigned operati on and can mul tiplex i ts ou tput usi ng a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-exten ded into the 17th bit of the mu ltiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s compleme nt in teger i s -2 For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the M SB is defined as a sign b it and the radix point is impl ied to lie just after the sign b it (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 2 16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10 multiply operation genera tes a 1.3 1 produ ct, whi ch ha s a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit result. Word op erands direct a 32-bi t result to the s pecified register(s) in the W array.

-5

. In Fractional mode, the 16x16

-10

N-1

to 2

1-N

N-1

– 1.

). For a

2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or load ed ca n be optio nally sca led v ia th e barrel shifter prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/bo rrow other input is complemented. The adder/subtracter generates overflow Status bits SA/SB and OA/OB, which are latched and refle cted in the ST A T US register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block which controls accumulat or data satu ration if selected . It uses the result of the adder, the overflow Status bits described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow. They are:

1. OA:

ACCA overflowed into guard bits

2. OB:

ACCB overflowed into guard bits

3. SA:

ACCA saturated (bit 31 overflow and sa turation)

ACCA overflowed into guard bits and saturated (bit 39 overflow and s aturation)

4. SB:

ACCB saturated (bit 31 overflow and sa turation)

ACCB overflowed into guard bits and saturated (bit 39 overflow and s aturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 8.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active high and the other input is

input is active low and the

dsPIC30F2011/2012/3012/3013

The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, th ey indicate th at the accumulator has overfl owed it s m aximum range (b it 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVT E bit in th e INTCO N1 regi ster is set, SA and SB bits ge nerate an arithmet ic warning trap when saturation is disabled.

The overflow and saturation Status bits can optionally be viewed in the STATUS register (SR) as the lo gical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has s aturated. T his w ould be us eful for complex number arithmetic which typically uses both the accumulators.

The device supports three saturation and overflow modes:

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set.

3. Bit 39 Catastrophic Overflow: The bit 39 overflow Status bit from the adder is used to set the SA or SB bit which remains set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying it s sign). If the C OVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write-Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instructio n into data spac e memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13]+=2, Register Indirect with Post-Increment: The rounded conten ts of the non- target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register . It generates a 16bit, 1.15 data value, which is passed to the data space write saturation logic. If rounding is no t indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and ad ds it to the AC CxH w ord (bi t s 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCx L is between 0x000 0 and 0x7FFF, ACCxH is left unchanged. A conse que nc e of thi s alg orithm is that over a succession of random rounding operations, the value tends to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LSb (bit 16 of the accumulator) of ACCxH is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not modified. As sumi ng t hat bi t 16 is effe cti vely r and om in nature, this scheme w i ll re mo ve any rou ndi ng b ias th at may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the c ontents of the target ac cumu la tor to d ata memo ry via th e X bu s (subject to data saturation, see Section 2.4.2.4 “Data Space Write Saturation”). Note that for the MAC cl as s of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

dsPIC30F2011/2012/3012/3013

2.4.2.4 Data Space Write Saturation

In addition to adder/subtrac ter saturation, writes to dat a space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tes te d for ove rflo w and adjusted accordingly. For input data greater than 0x007FFF, data written to memory is force d to the maximum positi ve 1. 15 val ue, 0x 7FFF. For input data less than 0xFF8000, da ta wr itten to me mory i s forced to th e maximum negative 1.1 5 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested.

If the SA TDW bi t in the CORCON regis ter is not set , the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single c ycle. The sou rce can be ei ther of th e two DSP accumul ators, or the X bus (t o support multi-bit shifts of register or memory data).

The shifter requi res a signed binary val ue to de term in e both the magnitude (num ber of bits) and direction of the shift operation. A po sitive value shift s the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operati ons and a 16- bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shift s, and bit pos itions 0 to 16 for left shift s.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes features of this group

3.1 Program Address Space

The program address space is 4M instruction words. The program sp ace mem ory map fo r the dsPI30 F2011/ 2012 is shown in Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2.

Program memory is addres sable by a 24 -bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1. Note that the program space address is incremented by two between successiv e progr am w ords in o rder to prov ide compatibility with data space addressing.

User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which uses TBLPAG<7> to determine user or configuration space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear.

dsPIC30F2011/2012/3012/3013

FIGURE 3-1: dsPIC30F2011/2012

PROGRAM SPACE MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

Space

User Memory

User Flash

Program Memory

(4K instructions)

Reserved

(Read ‘0’s)

000000 000002 000004

Vector Tables

00007E 000080 000084

0000FE 000100

001FFE 002000

7FFFFE 800000

FIGURE 3-2: dsPIC30F3012/3013

PROGRAM SPACE MEMORY MAP

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

Space

User Memory

User Flash

Program Memory

(8K instructions)

Reserved

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

000000 000002 000004

Vector Tables

00007E 000080

000084 0000FE 000100

003FFE 004000

7FFBFE 7FFC00

7FFFFE 800000

Reserved

8005BE

Space

Configuration Memory

UNITID (32 instr.)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

8005C0 8005FE

800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FFFFFE

Space

Configuration Memory

Reserved

UNITID (32 instr.)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

8005BE 8005C0

8005FE 800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FFFFFE

+ 175 hidden pages

MICROCHIP dsPIC30F2011, dsPIC30F2012, dsPIC30F3012, dsPIC30F3013 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance Modified RISC CPU:

DSP Features:

Peripheral Features:

Analog Features:

Special Microcontroller Features:

CMOS Technology:

dsPIC30F2011/2012/3012/3013 Sensor Family

Pin Diagrams

Pin Diagrams

Pin Diagrams

Pin Diagram

Pin Diagrams

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM

FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM

FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM

FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM

2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

2.2 Programmer’s Model

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

2.2.2 STATUS REGISTER

2.2.3 PROGRAM COUNTER

FIGURE 2-1: PROGRAMMER’S MODEL

2.3 Divide Support

TABLE 2-1: DIVIDE INSTRUCTIONS

2.4 DSP Engine

TABLE 2-2: DSP INSTRUCTION SUMMARY

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

2.4.1 MULTIPLIER

2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

2.4.3 BARREL SHIFTER

3.0 MEMORY ORGANIZATION

3.1 Program Address Space