MICROCHIP dsPIC30F1010, dsPIC30F202X Technical data

dsPIC30F1010/202X

Data Sheet

28/44-Pin High-Performance

Switch Mode Power Supply

Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartT el, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology I ncorporat ed in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC 8-bit MCUs, KEELOQ microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

code hopping devices, Serial EEPROMs,

®

dsPIC30F1010/202X

28/44-Pin dsPIC30F1010/202X Enhanced Flash

SMPS 16-Bit Digital Signal Controller

Note: This data sheet summarizes features of this g roup of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more informat ion on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• 83 base instructions with flexible addressing

modes

• 24-bit wide instructions, 16-bit wide data path

• 12 Kbytes on-chip Fla sh program space

• 512 bytes on-chip data RAM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- Dual Internal RC

- 9.7 and 14.55 MHz (±1%) Industrial Temp

- 6.4 and 9.7 MHz (±1%) Extended Temp

- 32X PLL with 480 MHz VCO

- PLL inputs ±3%

- External EC clock 6.0 to 14.55 MHz

- HS Crystal mode 6.0 to 14.55 MHz

• 32 interrupt sources

• Three external interrupt sources

• 8 user-selectable priority levels for each interrupt

• 4 processor exceptions and software traps

DSP Engine Features:

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturation logic

• 17-bit x 17-bit single-cycle hardw are frac tio nal /

integer multiplier

• Single-cycle Multiply-Accumulate (MAC)

operation

• 40-stage Barrel Shifte r

• Dual data fetch

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25 mA

• Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• One 16-bit Capture input functions

• Two 16-bit Compare/PWM output functions

- Dual Compare mode available

• 3-wire SPI modules (supports 4 Frame modes)

2

•I

CTM module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• UART Module:

- Supports RS-232, RS-485 and LIN 1.2

- Supports IrDA

- Auto wake-up on Start bit

- Auto-Baud Detect

- 4-level FIFO buffer

®

with on-chip hardware endec

Power Supply PWM Module Features:

• Four PWM generators with 8 outputs

• Each PWM generator h as ind ependent time base and duty cycle

• Duty cycle resolution of 1.1 ns at 30 MIPS

• Individual dead time for each PWM generator:

- Dead-time resolution 4.2 ns at 30 MIPS

- Dead time for rising and falling edges

• Phase-shift resolution of 4.2 ns @ 30 MIPS

• Frequency resolution of 8.4 ns @ 30 MIPS

• PWM modes supported:

- Complementary

-Push-Pull

- Multi-Phase

- Variable Phase

- Current Reset

- Current-Limit

• Independent Current-Limit and Fault Inputs

• Output Override Control

• Special Event Trigger

• PWM generated ADC Trigger

dsPIC30F1010/202X

Analog Features:

ADC

• 10-bit resolution

• 2000 Ksps conversi on rate

• Up to 12 input channels

• “Conversion pairing” allows simultaneous conversion of two inputs (i.e., cu rrent and volt age) w ith a single trigger

• PWM control loop:

- Up to six conversion pairs available

- Each conversion pair has up to four PWM

and seven other selectable trigger sources

• Interrupt hardware supports up to 1M interrupts per second

COMPARATOR

• Four Analog Comparators:

- 20 ns response time

- 10-bit DAC reference generator

- Programmable output polarity

- Selectable input s ource

- ADC sample and convert capable

• PWM module interface

- PWM Duty Cycle Control

- PWM Period Control

- PWM Fault Detect

• Special Event Trigger

• PWM-generated ADC Trigger

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for industrial temperature range, 100k (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation

• Fail-Safe clock monitor operation

• Detects clock failure and switches to on-chip low power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• 3.3V and 5.0V operation (±10% )

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F SWITCH MODE POWER SUPPLY FAMILY

Product

dsPIC30F101028SDIP 6K 2562011112x2136 ch2 21 dsPIC30F101028SOIC6K 2562011112x2136 ch2 21 dsPIC30F1010 28 dsPIC30F202028SDIP12K5123121114x2158 ch4 21 dsPIC30F202028SOIC12K5123121114x2158 ch 4 21 dsPIC30F2020 28 dsPIC30F202344QFN12K5123121114x21512 ch4 35 dsPIC30F202344TQFP12K5123121114x21512 ch4 35

Pins

Packaging

QFN-S

(Bytes)

Data SRAM

Timers

Capture

(Bytes)

Memory

Program

6K 2562011112x2136 ch 2 21

12K5123121114x2158 ch4 21

UART

Compare

SPI

C™

2

I

PWM

ADCs

S & H

A/D

Inputs

Analog

Comparators

GPIO

Pin Diagrams

28-Pin SDIP and SOIC

dsPIC30F1010/202X

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3

AN4/CMP2C/CN6/RB4

AN5/CMP2D/CN7/RB5

OSC1/CLKI/RB6 V

OSC2/CLKO/RB7

PGD1/EMUD1/T2CK/U1ATX/CN1/RE7

PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6

PGD2/EMUD2/SCK1/SFLT3/INT2/RF6

MCLR

V

DD

28-Pin QFN-S

1 2 3 4 5 6 7

SS

8 9 10 11 12 13 14

dsPIC30F1010

28 27 26 25 24 23 22

21 20 19 18 17 16 15

DD

AV AV

SS

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 RE4 RE5V

DD SS

V PGC/EMUC/SDI1/SDA/U1RX/RF7 PGD/EMUD/SDO1/SCL/U1TX/RF8 SFLT2/INT0/OCFLTA/RA9 PGC2/EMUC2/OC1/SFLT1/INT1/RD0

AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3

AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5

V

OSC1/CLKI/RB6

OSC2/CLKO/RB7

1 2 3 4

SS

5 6 7

AVDDAVSSPWM1L/RE0

MCLR

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

232425262728

dsPIC30F1010

1011

9

PGD1/EMUD1/T2CK/U1AT X/CN1/RE7

1213 14

DD

V

SFLT2/INT0/OCFLTA/RA9

PGC2/EMUC2/OC1/SFLT1/INT1/RD0

PGD2/EMUD2/SCK1/SFLT3/INT2/RF6

PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6

8

PWM1H/RE1

22

21

PWM2L/RE2

20

PWM2H/RE3 RE4

19

RE5

18

V

DD

17

V

SS

16

PGC/EMUC/SDI1/SDA/U1RX/RF7

15

PGD/EMUD/SDO1/SCL/U1TX/RF8

dsPIC30F1010/202X

Pin Diagrams

28-Pin SDIP and SOIC

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 V

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7

PGC1/EMUC1/EXTREF/PWM4L /T1CK/U1ARX/CN0/RE6

PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6

MCLR

V

SS

DD

28-Pin QFN-S

AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5

AN6/CMP3C/CMP4A/OSC1/CLKI/RB6

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7

4

V

SS

1 2 3 4 5 6 7

8 9 10 11 12 13 14

MCLR

AN0/CMP1A/CN2/RB0

AN1/CMP1B/CN3/RB1

1 2 3

dsPIC30F2020

5 6 7

1011

8

9

dsPIC30F2020

AVDDAVSSPWM1L/RE0

232425262728

1213 14

28 27 26 25 24 23 22

21 20 19 18 17 16 15

PWM1H/RE1

22

DD

AV AV

SS

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5V

DD

V

SS

PGC/EMUC/SDI1/SDA/U1RX/RF7 PGD/EMUD/SDO1/SCL/U1TX/RF8 SFLT2/INT0/OCFLTA/RA9 PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0

21

PWM2L/RE2

20

PWM2H/RE3 PWM3L/RE4

19

PWM3H/RE5

18

V

17

DD

V

SS

16

PGC/EMUC/SDI1/SDA/U1RX/RF7

15

DD

V

SFLT2/INT0/OCFLTA/RA9

PGD/EMUD/SDO1/SCL/U1TX/RF8

PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0

PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6

PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7

PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6

Pin Diagrams

44-PIN QFN

dsPIC30F1010/202X

PWM4H/T2CK/U1ATX/CN1/RE7

/

DD

SS

V

PGC2/EMUC2/OC1/IC1/INT1/RD0

SFLT2/INT0/OCFLTA/RA9

PGD2/EMUD2/SCK1/INT2/RF6

PGD/EMUD/SDO1/RF8

AN9/EXTREF/CMP4D/RB9

PGD1/EMUD1

PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6

SFLT1/RA8

OC2/RD1

PGC/EMUC/SDI1/RF7

SYNCO/SS1/RF15

SFLT3/RA10

SFLT4/RA11

SDA/RG3

V

PWM3H/RE5

PWM3L/RE4

PWM2H/RE3

PWM2L/RE2

DD

44

4342 414039 3837 3635

1 2 32 3 4 5

SS

6 7 8 9

10

11

dsPIC30F2023

1213 141516 1718 1920 21

SS

DD

AV

U1RX/RF2

PWM1H/RE1

PWM1L/RE0

SYNCI/RF14

MCLR

34

33

AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6

31

AN8/CMP4C/RB8

30

V

SS

V

29

DD

AN10/IFLT4/RB10

28 27

AN11/IFLT2/RB11

26

AN5/CMP2D/CMP3B/CN7/RB5

25

AN4/CMP2C/CMP3A/CN6/RB4 AN3/CMP1D/CMP2B/CN5/RB3

24

AN2/CMP1C/CMP2A/CN4/RB2

23

22

SCL/ RG2

U1TX/RF3

AN1/CMP1B/CN3/RB1

AN0/CMP1A/CN2/RB0

dsPIC30F1010/202X

Pin Diagrams

4443424140

1 2 3 4 5 6 7 8 9 10

121314

11

15

16

38

39

37

1819202122

17

363435

33 32 31 30 29 28 27 26 25 24

23

dsPIC30F1010/202X

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 9

2.0 CPU Architecture Overview........................................................................................................................................................ 19

3.0 Memory Organization................................................................................................................................................................. 29

4.0 Address Generator Units............................................................................................................................................................ 41

5.0 Interrupts.................................................................................................................................................................................... 47

6.0 I/O Ports.................. ......................... .......................................................................................................................................... 77

7.0 Flash Program Memory............ ................................................................. ......................... ........................................................ 81

8.0 Timer1 Module ........................................................................................................................................................................... 87

9.0 Timer2/3 Module ........................................................................ .. .... .. .. ....... .. .. .. .... .. .. ................................................................. 91

10.0 Input Capture Module..................................................................... .. .... ....... .. .. .... .. .. .. ....... .......................................................... 97

11.0 Output Compare Module................................................................................................ .......................................................... 101

12.0 Power Supply PWM .................................................................................................................................................................107

13.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 145

14.0 I2C™ Module ........................................................................................................................................................................... 153

15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 161

16.0 10-bit 2 Msps Analog-to-Digital Converter (ADC) Module........................................................................................................169

17.0 SMPS Comparator Module ............................................. ....... .. .... .. .. .... ....... .. .. .... .. .... ..... .... .. .................................................... 191

18.0 System Integration................................... .......................... ...................................................................................................... 197

19.0 Instruction Set Summary..........................................................................................................................................................219

20.0 Development Support............................................................................................................................................................... 227

21.0 Electrical Characteristics.......................................................................................................................................................... 231

22.0 Package Marking Information.. ................................................................................................................................................. 267

dsPIC30F1010/202X

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications t o better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

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dsPIC30F1010/202X

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes features of this g roup

of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer tyft877(i)-0.-1.3(rmat)ha8.9(2gy)6597 -10(on.67r8/( devici3i69(h)-00ript)Dn.3(ereDn.n21(rmat)ha8.9(2gy)63e1183(mic)31.880 e5004a9010)1251 1 Tf7iag)12dM6.1(r)3cs,,,,e

This document contains device specific information for the dsPIC30F1010/202X SMPS devices. These devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit mic rocontroller (MCU) architecture, as reflected in the following block diagrams. Figure 1-1 and Table 1-1 describe the dsPIC30F1010 SMPS device, Figure 1-2 and Table1-2 describe the dsPIC30F2020 device and Figure 1-3 and Table 1-3 describe the dsPIC30F2023 SMPS device.

dsPIC30F1010/202X

FIGURE 1-1: dsPIC30F1010 BL OC K DIAGR AM

24

Address Latch

PCH PCL

PCU

Program Counter

X Data Bus

16

Program Memory

(12 Kbytes)

Data Latch

OSC1/CLK1

Instruction

Decode &

Control

Timing

Generation

MCLR

24

IR

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5

16

ALU<16>

Comparator

10-bit ADC

Timers

Output

Compare

Module

SMPS

PWM

I2C™

UART1SPI1

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 RE4 RE5 PGC1/EMUC1/EXTREF/T1CK/

dsPIC30F1010/202X

Table 1-1 provides a brief description of device I/O pinouts for the ds PIC30F1010 and the functions that may be multiple xed to a port pin. Mul tiple functio ns may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010

Pin Name

AN0-AN5 I Analog Analog input channels.

DD P P Positive supply for analog module.

AV AVSS P P Ground reference for analog module. CLKI

CLKO

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2

Type

I

O

I/O I/O I/O I/O I/O I/O

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Opti onally fu nctions a s CLKO in RC and EC mode s. Always associated with OSC2 pin function.

ST ST ST ST ST ST

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin.

Description

INT0 INT1 INT2

SFLT1 SFLT2 SFLT3 PWM1L PWM1H PWM2L PWM2H

MCLR

OC1 O — Compare outputs. OCFLTA I ST Output Compare Fault Pin OSC1

OSC2

PGD PGC PGD1 PGC1 PGD2 PGC2

RB0-RB7 I/O ST PORTB is a bidirectional I/O port. RA9 I/O ST PORTA is a bidirectional I/O port. RD0 I/O ST PORTD is a bidirectional I/O port. Legend: CMOS = CMOS compati ble input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

I I I

I I

I O O O O

I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

I

I/O

I

I/O

I

I/0

I

ST ST ST

— — — —

CMOS—Oscillator crystal input.

ST ST ST ST ST ST

External interrupt 0 External interrupt 1 External interrupt 2

Shared Fault Pin 1 Shared Fault Pin 2 Shared Fault Pin 3 PWM 1 Low output PWM 1 High output PWM 2 Low output PWM 2 High output

active low Reset to the device.

Oscillator cryst al outpu t. Conne cts t o crys tal or resonator in Crys tal O scillato r mode. Optionally functions as CLKO in FRC and EC modes.

In-Circuit Serial Programming™ data input/outpu t pin. In-Circuit Serial Programming clock input pin. In-Circuit Serial Programming data input/output pin 1. In-Circuit Serial Programming clock input pin 1. In-Circuit Serial Programming data input/output pin 2. In-Circuit Serial Programming clock input pin 2.

dsPIC30F1010/202X

TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED)

Pin Name

RE0-RE7 I/O ST PORTE is a bidirectional I/O port. RF6, RF7, RF8 SCK1

SDI1 SDO1

SCL SDA

T1CK T2CK

U1RX U1TX U1ARX U1ATX

CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D

CN0-CN7 I ST Input Change notification inputs

DD P — Positive supply for logic and I/O pins.

V VSS P — Ground reference for logic and I/O pins. EXTREF I Analog External reference to Comparator DAC Legend: CMOS = CMOS compati ble input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Type

I/O ST PORTF is a bidirectional I/O port. I/O

I

O

I/O I/O

I I

I

O

I

O

I I I I I I I I

Buffer

Type

ST ST

—

ST ST

ST

—

ST

—

Analog Analog Analog Analog Analog Analog Analog Analog

Description

Synchronous serial clock input/output for SPI #1. SPI #1 Data In. SPI #1 Data Out.

Synchronous serial clock input/output for I2C™. Synchronous serial data input/output for I

Timer1 external clock input. Timer2 external clock input.

UART1 Receive. UART1 Transmit. Alternate UART1 Receiv e. Alternate UART1 Transmit.

Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D

Can be software programmed for internal weak pull-ups on all inputs.

2

C.

FIGURE 1-2: dsPIC30F2020 BLOCK DIAGRAM

/

dsPIC30F1010/202X

Interrupt

Controller

24

Address Latch

Program Memory

(12 Kbytes)

Data Latch

Instruction

Decode &

24

16

Control

PSV & Table Data Access Control Block

Stack

Control

16

24

Y Data Bus

8

16

PCH PCL

PCU

Program Counter

Logic

Loop

Control

Logic

ROM Latch

IR

Decode

16

Y Data

RAM

(256 bytes)

Address

Latch

Y AGU

Effective Address

16

X Data Bus

16

Data LatchData Latch

X Data

(256 bytes)

Address

16

X RAGU X WAGU

16

16 x 16

W Reg Array

16

RAM

Latch

16

SFLT2/INT0/OCFLTA/RA9

16

PORTA

PORTB

AN0/CMP1A/CN2/RB0 AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5 AN6/CMP3C/CMP4A/ OSC1/CLKI/RB6

AN7/CMP3D/CMP4B/ OSC2/CLKO/RB7

Control Signals to Various Blocks

OSC1/CLK1

Comparator

Module

Timing

Generation

MCLR

10-bit ADC

Timers

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

Input

Capture

Module

Input

Change

Notification

DSP Engine

16

Compare

Module

SMPS

PWM

Output

Divide

Unit

ALU<16>

16

UART1SPI1

I2C™

PORTD

PORTE

PORTF

PGC2/EMUC2/OC1/SFLT1/IC1/ INT1/RD0

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PGC1/EMUC1/EXTREF/PWM4L/

U1ARX/CN0/RE6

T1CK/ PGD1/EMUD1/PWM4H/T2CK/ U1ATX/CN1/RE7

PGD2/EMUD2/SCK1/SFLT3/OC2 INT2/RF6

PGC/EMUC/SDI1/SDA/U1RX/RF7 PGD/EMUD/SD01/SCL/U1TX/RF8

dsPIC30F1010/202X

Table 1-2 provides a brief description of device I/O pinouts for the ds PIC30F2020 and the functions that may be multiple xed to a port pin. Mul tiple functio ns may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020

Pin Name

AN0-AN7 I Analog Analog input channels.

DD P P Positive supply for analog module.

AV AVSS P P Ground reference for analog module. CLKI

CLKO

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2

IC1 I ST Capture input. INT0

INT1 INT2

SFLT1 SFLT2 SFLT3 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

MCLR

OC1-OC2 OCFLTA

OSC1 OSC2

PGD PGC PGD1 PGC1 PGD2 PGC2

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Type

I

O

I/O I/O I/O I/O I/O I/O

I I I

I I

I O O O O O O O O

I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

O

I

I/O

I

I/O

I

I/O

I

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Opti onally fu nctions a s CLKO in RC an d EC modes. Al ways associated with OSC2 pin function.

ST ST ST ST ST ST

ST ST ST

— — — — — — — —

— Compare outputs.

CMOS—Oscillator crystal input.

ST ST ST ST ST ST

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin.

External interrupt 0 External interrupt 1 External interrupt 2

Shared Fault Pin 1 Shared Fault Pin 2 Shared Fault Pin 3 PWM 1 Low output PWM 1 High output PWM 2 Low output PWM 2 High output PWM 3 Low output PWM 3 High output PWM 4 Low output PWM 4 High output

active low Reset to the device.

Output Compar e Fault pin

Oscillator cryst al outpu t. Conne cts t o crys tal or resonator in Crys tal O scillato r mode. Optionally functions as CLKO in FRC and EC modes.

In-Circuit Serial Programming™ data input/outpu t pin. In-Circuit Serial Programming clock input pin. In-Circuit Serial Programming data input/output pin 1. In-Circuit Serial Programming clock input pin 1. In-Circuit Serial Programming data input/output pin 2. In-Circuit Serial Programming clock input pin 2.

Description

dsPIC30F1010/202X

TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED)

Pin Name

RB0-RB7 I/O ST PORTB is a bidirectional I/O port. RA9 I/O ST PORTA is a bidirectional I/O port. RD0 I/O ST PORTD is a bidirectional I/O port. RE0-RE7 I/O ST PORTE is a bidirectional I/O port. RF6, RF7, RF8 SCK1

SDI1 SDO1

SCL SDA

T1CK T2CK

U1RX U1TX U1ARX U1ATX

CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B

CN0-CN7 I ST Input Change notification inputs

DD P — Positive supply for logic and I/O pins.

V VSS P — Ground reference for logic and I/O pins. EXTREF I Analog External reference to Comparator DAC Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Type

I/O ST PORTF is a bidirectional I/O port. I/O

I

O

I/O I/O

I I

I

O

I

O

I I I I I I I I I I I I I I

Buffer

Type

ST ST

—

ST ST

ST

—

ST

O

Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog

Description

Synchronous serial clock input/output for SPI #1. SPI #1 Data In. SPI #1 Data Out.

Synchronous serial clock input/output for I2C™. Synchronous serial data input/output for I

Timer1 external clock input. Timer2 external clock input.

UART1 Receive. UART1 Transmit. Alternate UART1 Receiv e. Alternate UART1 Transmit.

Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D Comparator 3 Channel A Comparator 3 Channel B Comparator 3 Channel C Comparator 3 Channel D Comparator 4 Channel A Comparator 4 Channel B

Can be software programmed for internal weak pull-ups on all inputs.

2

C.

dsPIC30F1010/202X

FIGURE 1-3: dsPIC30F2023 BL OC K DIAGR AM

Interrupt

Controller

24

Address Latch

Program Memory

(12 Kbytes)

Data Latch

Instruction

Decode &

24

16

Control

Y Data Bus

16

8

PCH PCL

PCU

Program Counter

16

24

ROM Latch

IR

Decode

Y AGU

Effective Address

X Data Bus

16

16 16

16

X RAGU X WAGU

16

16 x 16

W Reg Array

16

PORTA

AN0/CMP1A/CN2/RB0 AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5

PORTB

PORTD

OSC1/CLK1

Timing

Generation

Comparator

MCLR

10-bit ADC

Timers

Power-up

Timer

Oscillator

Start-up Timer

POR

Reset

Watchdog

Timer

Input Capture Module

DSP

Engine

16

Output

Compare

Module

Power Supply

PWM

Divide

Unit

ALU<16>

16

UART1SPI1

I2C™

PORTE

PORTG

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2

PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PGC1/EMUC1/PWM4L/T1CK/

SCL/RG2 SDA/RG3

dsPIC30F1010/202X

Table 1-3 provides a brief description of device I/O pinouts for the ds PIC30F2023 and the functions that may be multiple xed to a port pin. Mul tiple functio ns may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023

Pin Name

AN0-AN11 I Analog Analog input channels.

DD P P Positive supply for analog module.

AV AVSS P P Ground reference for analog module. CLKI

CLKO

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2

IC1 I ST Capture input. INT0

INT1 INT2

SFLT1 SFLT2 SFLT3 SFLT4 IFLT2 IFLT4 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

SYNCO SYNCI

MCLR

OC1-OC2 OCFLTA

OSC1 OSC2

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Type

I

O

I/O I/O I/O I/O I/O I/O

I I I

I I I I I

I O O O O O O O O

O

I

I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

O

I

I/O

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Opti onally fun ctions a s CLKO in RC and EC mode s. Always associated with OSC2 pin function.

ST ST ST ST ST ST

ST ST ST

ST ST ST ST ST ST

— — — — — — — —

—

ST

—

ST

CMOS—Oscillator crystal input.

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin.

External interrupt 0 External interrupt 1 External interrupt 2

Shared Fault 1 Shared Fault 2 Shared Fault 3 Shared Fault 4 Independent Fault 2 Independent Fault 4 PWM 1 Low output PWM 1 High output PWM 2 Low output PWM 2 High output PWM 3 Low output PWM 3 High output PWM 4 Low output PWM 4 High output

PWM SYNC output PWM SYNC input

active low Reset to the device. Compare outputs.

Output Compare Fault condi tion.

Oscillator cryst al outpu t. Conne cts t o crys tal or resonator in Crys tal O scillato r mode. Optionally functions as CLKO in FRC and EC modes.

Description

dsPIC30F1010/202X

TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED)

Pin Name

PGD PGC PGD1 PGC1 PGD2 PGC2

RA8-RA11 I/O ST PORTA is a bidirectional I/O port. RB0-RB11 I/O ST PORTB is a bidirectional I/O port. RD0,RD1 I/O ST PORTD is a bidirectional I/O port. RE0-RE7 I/O ST PORTE is a bidirectional I/O port. RF2, RF3,

RF6-RF8, RF14, RF15

RG2, RG3 I/O ST PORTG is a bidirectional I/O port. SCK1

SDI1 SDO1 SS1

SCL SDA

T1CK T2CK

U1RX U1TX U1ARX U1ATX

CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D

CN0-CN7 I ST Input Change notification inputs

DD P — Positive supply for logic and I/O pins.

V

SS P — Ground reference for logic and I/O pins.

V EXTREF I Analog External reference to Comparator DAC Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Type

I/O

I

I/O

I

I/O

I

I/O ST PORTF is a bidirectional I/O port.

I/O

I

O

I

I/O I/O

I I

I

O

I

O

I I I I I I I I I I I I I I I I

Buffer

Type

ST ST ST ST ST ST

ST ST

—

ST ST

—

ST

—

Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog

Description

In-Circuit Serial Programming™ data input/outpu t pin. In-Circuit Serial Programming clock input pin. In-Circuit Serial Programming data input/output pin 1. In-Circuit Serial Programming clock input pin 1. In-Circuit Serial Programming data input/output pin 2. In-Circuit Serial Programming clock input pin 2.

Synchronous serial clock input/output for SPI #1. SPI #1 Data In. SPI #1 Data Out. SPI #1 Slave Synchronization.

2

Synchronous serial clock input/output for I Synchronous serial data input/output for I

Timer1 external clock input. Timer2 external clock input.

UART1 Receive. UART1 Transmit. Alternate UART1 Receiv e. Alternate UART1 Transmit

Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D Comparator 3 Channel A Comparator 3 Channel B Comparator 3 Channel C Comparator 3 Channel D Comparator 4 Channel A Comparator 4 Channel B Comparator 4 Channel C Comparator 4 Channel D

Can be software programmed for internal weak pull-ups on all inputs.

C.

2

C.

dsPIC30F1010/202X

2.0 CPU ARCHITECTURE OVERVIEW

Note: This data sheet summarizes features of this g roup

of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on t he device instruction set and programming, refer to the “dsPIC 30F/ 33F Programmer’s Reference Manual” (DS70157).

2.1 Core Overview

The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear (see Section 3.1 “Program Address Space ”), and the Most Significant bit (MSb) is ignored during no rmal program exec ution, exce pt for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported usin g the DO and REPEAT instructions, both of which are interruptible at any point.

The working register array consists of 16x16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory AGU, which provides the appearance of a single unified data space. The Multiply-Accu mulate (MAC) class of dual s ource DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2 “Data Address Space”). The X and Y data space boundary is device-specific and cannot be altered by the user . Each dat a word consis ts of 2 bytes, and most instruct ions can address data eith er as words or bytes.

There are two methods of accessing data stored in program memory:

• The upper 32 Kbytes of data space memory can be

mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within program space is als o possibl e using any work ing register, via table read and write instructio ns. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports Bit-Reversed Addressing mode on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Secti on 4.0 “Address Generator Units” for details on modulo and Bit-Reversed Addressing.

The core supports In here nt (n o op era nd), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are a ssociated w ith pred efined Addr essing modes, depending upon their functional requirements.

For most i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional b arre l s hi fter. Data in the accum ul ator or any wor kin g regi ste r can be sh ifted up to 15 bi ts right or 16 bits left in a single cycle. The DSP instructions operate seamles sly with all other in struct ion s and have been desi gned for o ptimal re al-time p erformanc e. The MAC class of instructions can concurrently fetch two data operands from memory, while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.

The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved ) an d 54 int errup ts. Each interrupt is prioritized based on a us er-assigned priori ty between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined ‘natural order’. Traps have fi xed prio rities, ranging from 8 to 15.

dsPIC30F1010/202X

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temp orary holding reg ister and can transfer it s con ten ts to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register , only th e Least Significan t Byte (LSB) of th e targ et register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes (MSBs) can be manipulated through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® DSC devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine ca lls and return s. However , W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses , W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC D SC core has a 16-b it STATUS Registe r (SR), the LSB of which is referred to as the SR Low Byte (SRL) and the MSB as the SR High Byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags (including the Z bit), as wel l as the CPU Inter rupt Pri ority Level S t atus bits, IPL<2:0>, and the REPEAT active Status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value, which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23 bi ts wide. Bit 0 is a lways clear. Therefore, the PC can address up to 4M instruction words.

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

dsPIC30F1010/202X

W0/WREG

W1 W2 W3 W4 W5

W6 W7

W8 W9 W10 W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

7

22

TABPAG

TBLPAG

7

PSVPAG

AD39 AD0AD31 ACCA ACCB

0

Data Table Page Address

0

SPLIM Stack Pointer Limit Register

Program Space Visibility Page Address

15

RCOUNT

15

DCOUNT

DOSTART

DOEND

PC0

AD15

Program Counter

0

REPEAT Loop Counter

0

DO Loop Counter

0

DO Loop Start Address

DO Loop End Address

15

CORCON

OA OB SA SB

OAB SAB

SRH

DA DC

IPL2 IPL1

RA

IPL0 OV

SRL

N

0

Core Configuration Register

C

Z

STATUS Register

dsPIC30F1010/202X

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed fractional divide ope rati on , as w ell as 32/16-bit and 16/ 16-bit signed an d unsigned intege r divide operati ons, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or sign-extended during the first iteration.

The divide instructions must be executed within a REPEAT loop. Any other form of exec ution (e.g. a serie s of discrete divide instruc tions) w ill not function c orrectly because the instruction flow depends on RCOUNT. The divide instru ction does not automat icall y set up the RCOUNT value, and it must, therefore, be explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-1 (REPEAT will execute the target instruction {operand value + 1} times). The REPEAT loop count must be set up for 18 iterati ons of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The Divide flow is interruptible. However,

the user needs to save the context as appropriate.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.sw Signed divide: Wm / Wn → W0; Rem → W1 DIV.uw Unsigned divide: Wm / Wn → W0; Rem → W1

dsPIC30F1010/202X

2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x 17-bit multiplier , a barrel s hifter , and a 40-bit adde r/subtracter (with two target accumulators, round and saturation logic).

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 3-3.

A block diagram of the DSP engine is shown in Figure 2-2.

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes ED A = (x – y) EDAC A = A + (x – y) MAC A = A + (x * y) Yes MAC A = A + x MOVSAC No change in A Yes MPY A = x * y No MPY.N A = – x * y No MSC A = A – x * y Yes

2

No No

No

dsPIC30F1010/202X

FIGURE 2-2: DSP ENGINE BLOCK DI AGR AM

40

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

40

Round

Logic

S a

16

t

u

r

a

t

e

40

Barrel Shifter

32

40

16

X Data Bus

16

Zero Backfill

40

Sign-Extend

Y Data Bus

33

17-bit

Multiplier/Scaler

16

To/From W Array

16

dsPIC30F1010/202X

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or unsigned operati on and can mul tiplex i ts ou tput usi ng a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-exten ded into the 17th bit of the mu ltiplier input value. The output of t he 17x17-bit multip lier/ scaler is a 33-bit value, which is sign-extended to 40 bits. Intege r data is inherently rep resented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2 bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF), including 0. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the M SB is defined as a sign b it and the radix point is impl ied to lie just after the sign b it (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1-2 16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF), including 0, and has a precision of 3.01518x1 0 tiply operation generates a 1.31 product, which has a precision of 4.65661x10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or word sized operands. By te opera nds wil l direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

-5

. In Fractional mode, a 16x16 mu l-

-10

N-1

to 2

– 1. For a 16-

1-N

). For a

.

2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or load ed ca n be optio nally sca led v ia th e barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/bo rrow other input is complemented. The adder/subtracter generates overflow Status bits SA/SB and OA/OB, which are latched an d reflected i n the ST ATUS register .

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow Status bits described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow; they are:

1. OA:

ACCA overflowed into guard bits

2. OB:

ACCB overflowed into guard bits

3. SA:

ACCA saturated (bit 31 overflow and sa turation)

or

ACCA overflowed into guard bits and saturated (bit 39 overflow and s aturation)

4. SB:

ACCB saturated (bit 31 overflow and sa turation)

or

ACCB overflowed into guard bits and saturated (bit 39 overflow and s aturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active high and the other input is

input is active low and the

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The SA and SB bits are modified each ti me data pass es through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The overflow and saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both the accumulators.

The device supports three Saturation and Overflow modes.

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator . The SA or SB bit is set and rem ains set until cleared by the user . When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow The bit 39 overflow Status bit from the adder is used to set the SA or SB bit, which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying it s sign). If the C OVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instructio n into data spac e memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are wri tten into the ad dress pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and ad ds it to the AC CxH w ord (bi t s 16 through 31 of the accumulato r). If the ACCxL word (bit s 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succ ession of ran dom roundin g operations, the value will tend to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LSb (bit 16 of the accumu lator) of ACCxH is examined. If it is ‘1’, ACCxH is inc rement ed. If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme w i ll re mo ve any rou ndi ng b ias th at may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the c ontents of the target accumul ator to data mem ory , via the X bu s (subject to data saturation, see Section 2.4.2.4 “Data Space Write Saturation”). Note that for the MAC cl as s of instructions, the accumulator write back operation will function in the s ame mann er , a ddressing co mbine d MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

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2.4.2.4 Data Space Write Saturation

In addition to adder/subtrac ter saturation, writes to dat a space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used t o sele ct the a ppr opriate 1.15 fra ctional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tes te d for ove rflo w and adjusted accordingly. For input data greater than 0x007FFF, data written to memo ry is forced to the maximum positi ve 1. 15 val ue, 0x 7FFF. For input data less than 0xFF8000, da ta wr itten to me mory i s forced to th e maximum negative 1.1 5 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested.

If the SA TDW bi t in the CORCON regis ter is not set , the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single c ycle. The sou rce can be ei ther of th e two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data).

The shifter requi res a signed binary value to determine both the magnitude (num ber of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of ‘0’ will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operati ons and a 16- bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positio ns 0 to 15 for left shift s.

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NOTES: