Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS70083G-page iiPreliminary 2004 Microchip Technology Inc.
dsPIC30F
dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers
General Purpose and Sensor Families
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family ReferenceManual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30FProgrammer’s Reference Manual (DS70030).
High Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of non-volatile data EEPROM
• 16 x 16-bit working register array
• Three Address Generation Units that enable:
- Dual data fetch
- Accumulator write back for DSP operations
• Flexible Addressing modes supporting:
- Indirect, Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single cycle hardware fractional/
integer multiplier
• Single cycle Multiply-Accumulate (MAC)
operation
• 40-stage Barrel Shifter
• Up to 30 MIPs operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• Up to 41 interrupt sources:
- 8 user selectable priority levels
• Vector table with up to 62 vectors:
- 54 interrupt vectors
- 8 processor exceptions and software traps
Peripheral Features:
• High current sink/source I/O pins: 25 mA/25 mA
• Up to 5 external interrupt sources
•Timer module with programmable prescaler:
- Up to five 16-bit timers/counters; optionally
pair up 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions:
- Dual Compare mode available
• Data Converter Interface (DCI) supports common
audio Codec protocols, including I
• 3-wire SPI™ modules (supports 4 Frame modes)
2
•I
C™ module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Addressable UART modules supporting:
- Interrupt on address bit
- Wake-up on Start bit
- 4 characters deep TX and RX FIFO buffers
• CAN bus modules
2
S and AC’97
Analog Features:
• 12-bit Analog-to-Digital Converter (A/D) with:
- 100 Ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low Voltage Detection (PLVD)
• Programmable Brown-out Detection and Reset
generation
6.0Flash Program Memory.............................................................................................................................................................. 63
17.0 CAN Module ............................................................................................................................................................................. 123
18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 135
20.0 System Integration ................................................................................................................................................................... 153
21.0 Instruction Set Summary .......................................................................................................................................................... 169
22.0 Development Support............................................................................................................................................................... 177
Index .................................................................................................................................................................................................. 237
Systems Information and Upgrade Hot Line ...................................................................................................................................... 243
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS70083G-page 16Preliminary 2004 Microchip Technology Inc.
dsPIC30F
1.0DEVICE OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family ReferenceManual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30FProgrammer’s Reference Manual (DS70030).
This document contains device family specific
information for the dsPIC30F family of Digital Signal
Controller (DSC) devices. The dsPIC30F devices
contain extensive Digital Signal Processor (DSP)
functionality within a high performance 16-bit
microcontroller (MCU) architecture.
Figure 1-1 shows a sample device block diagram.
Note:The device(s) depicted in this block
diagram are representative of the
corresponding device family. Other
devices of the same family may vary in
terms of number of pins and multiplexing
of pin functions. Typically, smaller devices
in the family contain a subset of the
peripherals present in the device(s) shown
in this diagram.
DS70083G-page 18Preliminary 2004 Microchip Technology Inc.
dsPIC30F
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
TABLE 1-1:PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN15IAnalogAnalog input channels.
AV
DDPPPositive supply for analog module.
SSPPGround reference for analog module.
AV
CLKI
CLKO
CN0-CN23ISTInput change notification inputs.
COFS
CSCK
CSDI
CSDO
C1RX
C1TX
C2RX
C2TX
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
IC1-IC8ISTCapture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
LVDINIAnalogLow Voltage Detect Reference Voltage input pin.
MCLR
OCFA
OCFB
OC1-OC8
Pin
Typ e
I
O
I/O
I/O
I
O
I
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I/PSTMaster Clear (Reset) input or programming voltage input. This
I
I
O
Legend:CMOS = CMOS compatible input or output Analog = Analog input
ST= Schmitt Trigger input with CMOS levelsO= Output
I= Input P= Power
Buffer
Typ e
AN0 and AN1 are also used for device programming data and
clock inputs, respectively.
ST/CMOS—External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with OSC2 pin
function.
Can be software programmed for internal weak pull-ups on all
inputs.
ST
ST
ST
—
ST
—
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data
input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data
input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
Legend:CMOS = CMOS compatible input or output Analog = Analog input
ST= Schmitt Trigger input with CMOS levelsO= Output
I= Input P= Power
Buffer
Typ e
ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes.
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
ST
ST
—
ST
ST
ST
—
ST/CMOS
ST
ST
ST
ST
ST
ST
—
ST
—
ST
—
In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
PORTA is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
PORTG is a bidirectional I/O port.
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
Synchronous serial clock input/output for I
Synchronous serial data input/output for I
32 kHz low power oscillator crystal output.
32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
DS70083G-page 20Preliminary 2004 Microchip Technology Inc.
dsPIC30F
2.0CPU ARCHITECTURE
OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family ReferenceManual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30FProgrammer’s Reference Manual (DS70030).
2.1Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23-bits wide with the Least Significant
(LS) bit always clear (refer to Section 3.1), and the
Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction
words of user program space. An instruction pre-fetch
mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and
REPEAT instructions, both of which are interruptible at
any point.
The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user. Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of program space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP
algorithms.
The X AGU also supports bit-reversed addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 for details on modulo and
bit-reversed addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
Addressing modes, depending upon their functional
requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits
right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by dedicating certain working registers to each address space
for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions, as outlined in Section 2.3.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.
The programmer’s model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide
data memory space accesses.
2.2.1SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® devices contain a software stack. W15 is
the dedicated software Stack Pointer (SP), and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
Note:In order to protect against misaligned
stack accesses, W15<0> is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2STATUS REGISTER
The dsPIC core has a 16-bit STATUS register (SR), the
LS Byte of which is referred to as the SR Low byte
(SRL) and the MS Byte as the SR High byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
Most SR bits are read/write. Exceptions are:
1.The DA bit: DA is read and clear only because
accidentally setting it could cause erroneous
operation.
2.The RA bit: RA is a read only bit because accidentally setting it could cause erroneous operation. RA is only set on entry into a REPEAT loop,
and cannot be directly cleared by software.
3.The OV, OA, OB and OAB bits: These bits are
read only and can only be set by the DSP engine
overflow logic.
4.The SA, SB and SAB bits: These are read and
clear only and can only be set by the DSP
engine saturation logic. Once set, these flags
remain set until cleared by the user, irrespective
of the results from any subsequent DSP
operations.
Note 1: Clearing the SAB bit will also clear both
the SA and SB bits.
2: When the memory mapped STATUS reg-
ister (SR) is the destination address for
an operation which affects any of the SR
bits, data writes are disabled to all bits.
2.2.2.1Z Status Bit
Instructions that use a carry/borrow input (ADDC,
CPB, SUBB and SUBBR) will only be able to clear Z (for
a non-zero result) and can never set it. A multiprecision sequence of instructions, starting with an
instruction with no carry/borrow input, will thus automatically logically AND the successive results of the
zero test. All results must be zero for the Z flag to
remain set by the end of the sequence.
All other instructions can set as well as clear the Z bit.
2.2.3PROGRAM COUNTER
The program counter is 23-bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
DS70083G-page 22Preliminary 2004 Microchip Technology Inc.
2.One-word, two-cycle (or three-cycle) instructions that are flow control instructions: these
instructions include the relative branches, relative call, skips and returns. When an instruction
changes the PC (other than to increment it), the
pipelined fetch is discarded. This causes the
instruction to take two effective cycles to execute as shown in Figure 2-3. Some instructions
that change program flow require 3 cycles, such
as the RETURN, RETFIE and RETLW instructions, and instructions that skip over 2-word
instructions.
4.Table read/write instructions: these instructions
will suspend the fetching to insert a read or write
cycle to the program memory. The instruction
fetched while executing the table operation is
saved for 1 cycle and executed in the cycle
immediately after the table operation as shown
in Figure 2-5.
these instructions, the fetch after the instruction
provides the remainder of the jump or call destination address. These instructions require 2
cycles to execute, 1 cycle to fetch the 2 instruction words (enabled by a high speed path on the
second fetch), and 1 cycle to flush the pipeline
as shown in Figure 2-6.
6.Two-word instructions for DO: in these instructions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles as shown in
Figure 2-7.
7.Instructions that are subjected to a stall due to a
data dependency between the X RAGU and
X WAGU: an additional cycle is inserted to
resolve the resource conflict as shown in
Figure 2-7. Instruction stalls caused by data
dependencies are further discussed in
Section 4.0.
Fetch 1Execute 1
Fetch 2LNOP
Fetch 2HExecute 2
Fetch 3Execute 3
FIGURE 2-8:INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a. Stall (NOP)
3. MOV.b W0,PORTB
8. Interrupt recognition execution: refer to
Section 6.0 for details on interrupts.
Fetch 1Execute 1
Fetch 2NOP
StallExecute 2
Fetch 3Execute 3
DS70083G-page 26Preliminary 2004 Microchip Technology Inc.
dsPIC30F
2.4Divide Support
The dsPIC devices feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.DIVF - 16/16 signed fractional divide
2.DIV.sd - 32/16 signed divide
3.DIV.ud - 32/16 unsigned divide
4.DIV.sw - 16/16 signed divide
5.DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The quotient for all divide instructions is stored in W0,
and the remainder in W1. DIV and DIVF can specify
any W register for both the 16-bit dividend and divisor.
All other divides can specify any W register for the
16-bit divisor, but the 32-bit dividend must be in an
aligned W register pair, such as W1:W0, W3:W2, etc.
The non-restoring divide algorithm requires one cycle
for an initial dividend shift (for integer divides only), one
cycle per divisor bit, and a remainder/quotient correction cycle. The correction cycle is the last cycle of the
iteration loop but must be performed (even if the
remainder is not required) because it may also adjust
the quotient. A consequence of this is that DIVF will
also produce a valid remainder (though it is of little use
in fractional arithmetic).
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruction as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Note:The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
TABLE 2-1:DIVIDE INSTRUCTIONS
InstructionFunction
DIVF
DIV.sdSigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.sw or
DIV.s
DIV.udUnsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED and EDAC
instructions).
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
Data input to the DSP engine is derived from one of the
following:
1.Directly from the W array (registers W4, W5, W6
or W7) via the X and Y data buses for the MAC
class of instructions (MAC, MSC, MPY,MPY.N, ED, EDAC, CLR and MOVSAC).
2.From the X bus for all other DSP instructions.
3.From the X bus for all MCU instructions which
use the barrel shifter.
Data output from the DSP engine is written to one of the
following:
1.The target accumulator, as defined by the DSP
instruction being executed.
2.The X bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 only. (MPY, MPY.N, ED and EDAC
do not offer an accumulator write option.)
3.The X bus for all MCU instructions which use the
barrel shifter.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.Fractional or integer DSP multiply (IF).
2.Signed or unsigned DSP multiply (US).
3.Conventional or convergent rounding (RND).
4.Automatic saturation on/off for AccA (SATA).
5.Automatic saturation on/off for AccB (SATB).
6.Automatic saturation on/off for writes to data
memory (SATDW).
7.Accumulator Saturation mode selection
(ACCSAT).
Note:For CORCON layout, see Table 4-3.
A block diagram of the DSP engine is shown in
Figure 2-9.
DS70083G-page 28Preliminary 2004 Microchip Technology Inc.
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