MICROCHIP dsPIC30F Technical data

dsPIC30F Data Sheet

General Purpose and Sensor Families

High-Performance

Digital Signal Controllers

 2004 Microchip Technology Inc. Preliminary DS70083G

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

DS70083G-page ii Preliminary  2004 Microchip Technology Inc.

dsPIC30F

dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers

General Purpose and Sensor Families

Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030).

High Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• Up to 144 Kbytes on-chip Flash program space

• Up to 48K instruction words

• Up to 8 Kbytes of on-chip data RAM

• Up to 4 Kbytes of non-volatile data EEPROM

• 16 x 16-bit working register array

• Three Address Generation Units that enable:

- Dual data fetch

- Accumulator write back for DSP operations

• Flexible Addressing modes supporting:

- Indirect, Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturation logic

• 17-bit x 17-bit single cycle hardware fractional/

integer multiplier

• Single cycle Multiply-Accumulate (MAC)

operation

• 40-stage Barrel Shifter

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

• Up to 41 interrupt sources:

- 8 user selectable priority levels

• Vector table with up to 62 vectors:

- 54 interrupt vectors

- 8 processor exceptions and software traps

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

• Up to 5 external interrupt sources

•Timer module with programmable prescaler:

- Up to five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions:

- Dual Compare mode available

• Data Converter Interface (DCI) supports common audio Codec protocols, including I

• 3-wire SPI™ modules (supports 4 Frame modes)

•I

C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Addressable UART modules supporting:

- Interrupt on address bit

- Wake-up on Start bit

- 4 characters deep TX and RX FIFO buffers

• CAN bus modules

S and AC’97

Analog Features:

• 12-bit Analog-to-Digital Converter (A/D) with:

- 100 Ksps conversion rate

- Up to 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset generation

 2004 Microchip Technology Inc. Preliminary DS70083G-page 1

dsPIC30F

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip

low power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™) via 3 pins and power/ground

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low power, high speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

DS70083G-page 2 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

dsPIC30F Sensor Processor Family

Device Pins

Program Memory

Bytes Instructions

dsPIC30F2011 18 12K 4K 1024 0 3 2 2 8 ch 1 1 1

dsPIC30F3012 18 24K 8K 2048 1024 3 2 2 8 ch 1 1 1

dsPIC30F2012 28 12K 4K 1024 0 3 2 2 10 ch 1 1 1

dsPIC30F3013 28 24K 8K 2048 1024 3 2 2 10 ch 2 1 1

Pin Diagrams

18-Pin SOIC and PDIP

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

Input

Cap

Output Comp/

Std PWM

A/D 12-bit

100 Ksps

UART

™

SPI

C™

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

28-Pin PDIP and SOIC

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

28-Pin PDIP and SOIC

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

AN0/VREF+/CN2/RB0

AN1/V

AN2/SS1

/LVDIN/CN4/RB2

OSC2/CLKO/RC15

AN2/SS1/LVDIN/CN4/RB2

OSC2/CLKO/RC15

/LVDIN/CN4/RB2

AN2/SS1

OSC2/CLKO/RC15

MCLR

REF-/CN3/RB1

AN3/CN5/RB3

OSC1/CLKI

MCLR

REF-/CN3/RB1

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

OSC1/CLKI

IC2/INT2/RD9

MCLR

REF-/CN3/RB1

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

OSC1/CLKI

IC2/INT2/RD9

VSS

VDD

VSS

VDD

dsPIC30F2011

dsPIC30F3012

2 3 4 5 6 7

8 9

1 2 3

dsPIC30F2012

4 5 6 7 8 9 10 11 12 13 14

1 2 3 4

dsPIC30F3013

5 6 7

8 9 10 11 12 13 14

AVSS

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

VDD

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

EMUC2/OC1/IC1/INT1/RD0

AV AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

CN17/RF4

CN18/RF5

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

AVDD

AVSS AN6/OCFA/RB6

EMUD2/AN7/RB7

25 24

AN8/OC1/RB8 AN9/OC2/RB9

U2RX/CN17/RF4

22 21

U2TX/CN18/RF5 VDD

20 19

V PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

17 16

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 3

dsPIC30F

Pin Diagrams (Continued)

44-Pin QFN

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

EMUD1/SOSCI/T2CK / U1ATX / CN1 / RC13

EMUC1/SOSCO/T1CK / U1ARX / CN0 / RC14

IC2/INT2/RD9

444342414039383736

PGC/EMUC/U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

AN9/OC2/RB9 AN8/OC1/RB8

1 2 32

NC NC

6 7 8

9 10 11

dsPIC30F3013

121314151617181920

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

Note: For descriptions of individual pins, see Section 1.0.

AVDD

MCLR

REF-/CN3/RB1

REF+/CN2/RB0

EMUC3/AN1/V

EMUD3/AN0/V

OSC2/CLKO/RC15 OSC1/CLKI VSS

31 30

NC NC

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

25 24

AN2/SS1/LVDIN/CN4/RB2

DS70083G-page 4 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

dsPIC30F General Purpose Controller Family

Program Memory

Device Pins

Bytes Instructions

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

dsPIC30F3014 40/44 24K 8K 2048 1024 3 2 2 — 13 ch 2 1 1 -

dsPIC30F4013 40/44 48K 16K 2048 1024 5 4 4 AC’97, I

dsPIC30F5011 64 66K 22K 4096 1024 5 8 8 AC’97, I

dsPIC30F6011 64 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2

dsPIC30F6012 64 144K 48K 8192 4096 5 8 8 AC’97, I

dsPIC30F5013 80 66K 22K 4096 1024 5 8 8 AC’97, I

dsPIC30F6013 80 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2

dsPIC30F6014 80 144K 48K 8192 4096 5 8 8 AC’97, I

Pin Diagrams

40-Pin PDIP

Input

Cap

Output

Comp/Std

PWM

Codec

Interface

A/D 12-bit

100 Ksps

S 13 ch 2 1 1 1

S 16 ch 2 2 1 2

UART

™

SPI

C™

CAN

AN0/V

AN1/V

AN2/SS1

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

40-Pin PDIP

AN0/V

AN1/V

AN2/SS1

/LVDIN/CN4/RB2

AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

MCLR

REF

+/CN2/RB0

REF

-/CN3/RB1

/LVDIN/CN4/RB2

AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5

AN8/RB8

OSC1/CLKI

INT0/RA11

IC2/INT2/RD9

RD3

MCLR

REF

+/CN2/RB0

REF

-/CN3/RB1

AN3/CN5/RB3

AN8/RB8

OSC1/CLKI

INT0/RA11

IC2/INT2/RD9

OC4/RD3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

dsPIC30F3014

40 39 38 37 36 35

dsPIC30F4013

34 33 32 31 30 29 28 27 26 25 24 23 22 21

AN9/RB9

AN10/RB10

AN11/RB11

AN12/RB12

EMUC2/OC1/RD0

EMUD2/OC2/RD1

RF0

RF1

29 28

U2RX/CN17/RF4 U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/INT1/RD8

RD2

AV AV

AN9/CSCK/RB9 AN10/CSDI/RB10 AN11/CSDO/RB11 AN12/COFS/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 V

C1RX/RF0 C1TX/RF1 U2RX/CN17/RF4 U2TX/CN18/RF5 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/INT1/RD8 OC3/RD2 V

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 5

dsPIC30F

Pin Diagrams (Continued)

44-Pin TQFP

EMUC3/SCK1/RF6

INT1/RD8

RD2

VSSRD3

IC2/INT2/RD1

dsPIC30F3014

1819202122

AVSS

AN9/RB9

AN10/RB10

MCLR

REF+/CN2/RB0

AN0/V

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

INT0/RA11

363435

REF-/CN3/RB1

/LVDIN/CN4/RB2

AN1/V

AN2/SS1

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

C1TX/RF1

C1RX/RF0

VSS

EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/RB12

AN11/RB11

EMUD3/U1TX/SDO1/SCL/RF3

4443424140

1 2 3 4 5 6 7 8 9 10 11

121314

Note: For descriptions of individual pins, see Section 1.0.

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI

VSS

29 28

27 26 25

24 23

AN3/CN5/RB3

V AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/CN7/RB5 AN4/CN6/RB4

DS70083G-page 6 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin TQFP

dsPIC30F

EMUC3/SCK1/RF6

IC1/INT1/RD8

OC3/RD2

VSSOC4/RD3

IC2/INT2/RD1

1819202122

AVSS

MCLR

AN9/CSCK/RB9

AN10/CSDI/RB10

REF+/CN2/RB0

AN0/V

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

INT0/RA11

363435

REF-/CN3/RB1

/LVDIN/CN4/RB2

AN1/V

AN2/SS1

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

CTX1/RF1 CRX1/RF0

VSS

V EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/COFS/RB12 AN11/CSDO/RB11

EMUD3/U1TX/SDO1/SCL/RF3

4443424140

1 2 3 4 5

dsPIC30F4013

6 7 8 9 10 11

121314

Note: For descriptions of individual pins, see Section 1.0.

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI

VSS

28 27 26 25

24 23

AN3/CN5/RB3

AN8/RB8 PGD/EMUD/TB7/AN7/RB7 PGC/EMUC/TB6/AN6/OCFA/RB6 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

 2004 Microchip Technology Inc. Preliminary DS70083G-page 7

dsPIC30F

Pin Diagrams (Continued)

44-Pin QFN

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5

U2RX/CN17/RF4

C1TX/RF1

C1RX/RF0

EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/RB12

EMUD3/U1TX/SDO1/SCL/RF3

1 2 32 3 4 5 6

VSS

VDD

9 10 11

121314151617181920

EMUC3/SCK1/RF6

IC1/INT1/RD8

RD2

434241403938373635

dsPIC30F3014

RD3

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

IC2/INT2/RD9

INT0/RA11

OSC2/CLKO/RC15 OSC1/CLKI

VSS

VDD

AN8/RB8

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

AN5/CN7/RB5

AN4/CN6/RB4

AN11/RB11

AVSS

AN9/RB9

AN10/RB10

Note: For descriptions of individual pins, see Section 1.0.

MCLR

REF-/CN3/RB1

REF+/CN2/RB0

AN1/V

AN0/V

AN3/CN5/RB3

S1/LVDIN/CN4/RB2

AN2/S

DS70083G-page 8 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin QFN

dsPIC30F

EMUC3/SCK1/RF6

INT1/RD8

TOC3/RD2

VSSOC4/RD3

dsPIC30F4013

AVSS

MCLR

AN9/CSCK/RB9

AN10/CSDI/RB10

IC2/INT2/RD1

REF+/CN2/RB0

AN0/V

U1RX/SDI1/SDA/RF2

U2TX/CN18/RF5 U2RX/CN17/RF4

CTX1/RF1

CRX1/RF0

VSS

VDD

EMUD2/OC2/RD1 EMUC2/OC1/RD0

AN12/COFS/RB12

EMUD3/U1TX/SDO1/SCL/RF3

444342414039383736

1 2 32 3 4 5 6 7 8

9 10 11

121314151617181920

AN11/CSDO/RB11

Note: For descriptions of individual pins, see Section 1.0.

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

INT0/RA11

OSC2/CLKO/RC15 OSC1/CLKI

VSS

VDD V

AN8/RB8

PGD/EMUD/TB7/AN7/RB7

PGC/EMUC/TB6/AN6/OCFA/RB6

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

REF-/CN3/RB1

AN3/CN5/RB3

/LVDIN/CN4/RB2

AN1/V

AN2/SS1

 2004 Microchip Technology Inc. Preliminary DS70083G-page 9

dsPIC30F

Pin Diagrams (Continued)

64-Pin TQFP

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

AN2/SS1

AN1/V

AN0/V

COFS/RG15

T2CK/RC1 T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

/LVDIN/CN4/RB2

MCLR

/CN11/RG9

SS2

AN3/CN5/RB3

REF-/CN3/RB1

REF+/CN2/RB0

VSS

VDD

CSDO/RG13

CSDI/RG12

CSCK/RG14

C2TX/RG1

C2RX/RG0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425

PGC/EMUC/AN6/OCFA/RB6

dsPIC30F5011

AVSS

AN8/RB8

PGD/EMUD/AN7/RB7

C1TX/RF1

VDD

C1RX/RF0

AN9/RB9

AN11/RB11

AN10/RB10

OC8/CN16/RD7

VSS

OC7/CN15/RD6

OC6/IC6/CN14/RD5

545352

VDD

AN12/RB12

AN13/RB13

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

504951

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

AN14/RB14

U2TX/CN18/RF5

U2RX/CN17/RF4

AN15/OCFB/CN12/RB15

EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0

IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8

V OSC2/CLKO/RC15 OSC1/CLKI

V SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3

Note: For descriptions of individual pins, see Section 1.0.

DS70083G-page 10 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin TQFP

RG13

RG12

RG14

C2TX/RG1

C1TX/RF1

C2RX/RG0

VDD

C1RX/RF0

OC8/CN16/RD7

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

EMUD2/OC2/RD1

OC3/RD2

dsPIC30F

SDO2/CN10/RG8

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

AN2/SS1

PGC/EMUC/AN1/V

PGD/EMUD/AN0/V

RG15 T2CK/RC1 T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

SS2/CN11/RG9

VSS

VDD

AN3/CN5/RB3

/LVDIN/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425

AN6/OCFA/RB6

AVSS

AN7/RB7

dsPIC30F6011

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

VDD

545352

AN12/RB12

504951

AN13/RB13

AN14/RB14

U2RX/CN17/RF4

AN15/OCFB/CN12/RB15

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0

46 45

IC4/INT4/RD11 IC3/INT3/RD10

44 43

IC2/INT2/RD9

IC1/INT1/RD8

V OSC2/CLKO/RC15

OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

U2TX/CN18/RF5

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 11

dsPIC30F

Pin Diagrams (Continued)

64-Pin TQFP

CSDO/RG13

CSDI/RG12

CSCK/RG14

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

OC8/CN16/RD7

VDD

OC3/RD2

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

EMUD2/OC2/RD1

SDO2/CN10/RG8

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

AN2/SS1

PGC/EMUC/AN1/V

PGD/EMUD/AN0/V

COFS/RG15

T2CK/RC1 T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

/CN11/RG9

SS2

AN3/CN5/RB3

/LVDIN/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

VSS VDD

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425

AN6/OCFA/RB6

AVSS

AN7/RB7

dsPIC30F6012

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

VDD

545352

AN12/RB12

504951

AN13/RB13

AN14/RB14

U2RX/CN17/RF4

AN15/OCFB/CN12/RB15

48 47 46 45

44 43 42 41 40 39 38 37

U2TX/CN18/RF5

EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8

V OSC2/CLKO/RC15 OSC1/CLKI

V SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3

Note: For descriptions of individual pins, see Section 1.0.

DS70083G-page 12 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

CSCK/RG14

CSDO/RG13

RA7/CN23

CSDI/RG12

RA6/CN22

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

OC8/CN16/RD7

VSS

IC5/RD12

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

OC7/CN15/RD6

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

dsPIC30F

COFS/RG15

T2CK/RC1

T3CK/RC2

T4CK/RC3 T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD

INT1/RA12

INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4 AN3/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

2324252627282930313233

REF-/RA9

AN7/RB7

AN6/OCFA/RB6

AVDD

VREF+/RA10

767877

AVSS

727473

7170696867666564636261

dsPIC30F5013

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

AN12/RB12

AN13/RB13

AN14/RB14

IC7/CN20/RD14

IC8/CN21/RD15

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14 V

OSC2/CLKO/RC15 OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

U1RX/RF2

U1TX/RF3

AN15/OCFB/CN12/RB15

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 13

dsPIC30F

Pin Diagrams (Continued)

80-Pin TQFP

RG14

RA7/CN23

RA6/CN22

C2RX/RG0

RG13

RG12

C2TX/RG1

C1TX/RF1

C1RX/RF0

OC8/CN16/RD7

VSS

OC6/CN14/RD5

OC7/CN15/RD6

IC5/RD12

OC4/RD3

OC5/CN13/RD4

IC6/CN19/RD13

OC3/RD2

EMUD2/OC2/RD1

RG15

T2CK/RC1

T3CK/RC2

T4CK/RC3 T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD

INT1/RA12

INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4 AN3/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

2324252627282930313233

AN7/RB7

VREF-/RA9

AN6/OCFA/RB6

VREF+/RA10

767877

AVSS

727473

7170696867666564636261

dsPIC30F6013

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

AN12/RB12

AN13/RB13

AN14/RB14

IC8/CN21/RD15

IC7/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15 OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

U1RX/RF2

U1TX/RF3

AN15/OCFB/CN12/RB15

Note: For descriptions of individual pins, see Section 1.0.

DS70083G-page 14 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

CSCK/RG14

CSDO/RG13

RA7/CN23

CSDI/RG12

RA6/CN22

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

OC8/CN16/RD7

VSS

IC5/RD12

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

OC7/CN15/RD6

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

dsPIC30F

COFS/RG15

T2CK/RC1

T3CK/RC2

T4CK/RC3 T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD

INT1/RA12

INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4 AN3/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

2324252627282930313233

REF-/RA9

AN7/RB7

AN6/OCFA/RB6

AVDD

VREF+/RA10

767877

AVSS

727473

7170696867666564636261

dsPIC30F6014

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

AN12/RB12

AN13/RB13

AN14/RB14

IC7/CN20/RD14

IC8/CN21/RD15

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14 V

OSC2/CLKO/RC15 OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

U1RX/RF2

U1TX/RF3

AN15/OCFB/CN12/RB15

Note: For descriptions of individual pins, see Section 1.0.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 15

dsPIC30F

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 17

2.0 CPU Architecture Overview........................................................................................................................................................ 21

3.0 Memory Organization ................................................................................................................................................................. 35

4.0 Address Generator Units............................................................................................................................................................ 47

5.0 Interrupts .................................................................................................................................................................................... 55

6.0 Flash Program Memory.............................................................................................................................................................. 63

7.0 Data EEPROM Memory ............................................................................................................................................................. 69

8.0 I/O Ports ..................................................................................................................................................................................... 75

9.0 Timer1 Module ........................................................................................................................................................................... 81

10.0 Timer2/3 Module ........................................................................................................................................................................ 85

11.0 Timer4/5 Module ....................................................................................................................................................................... 91

12.0 Input Capture Module ................................................................................................................................................................. 95

13.0 Output Compare Module ............................................................................................................................................................ 99

14.0 SPI Module ............................................................................................................................................................................... 103

15.0 I2C Module ............................................................................................................................................................................... 107

16.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 115

17.0 CAN Module ............................................................................................................................................................................. 123

18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 135

19.0 12-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 145

20.0 System Integration ................................................................................................................................................................... 153

21.0 Instruction Set Summary .......................................................................................................................................................... 169

22.0 Development Support............................................................................................................................................................... 177

23.0 Electrical Characteristics .......................................................................................................................................................... 183

24.0 Packaging Information.............................................................................................................................................................. 223

Index .................................................................................................................................................................................................. 237

On-Line Support................................................................................................................................................................................. 243

Systems Information and Upgrade Hot Line ...................................................................................................................................... 243

Reader Response .............................................................................................................................................................................. 244

Product Identification System............................................................................................................................................................. 245

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

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Customer Notification System

DS70083G-page 16 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

1.0 DEVICE OVERVIEW

This document contains device family specific information for the dsPIC30F family of Digital Signal Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture.

Figure 1-1 shows a sample device block diagram.

Note: The device(s) depicted in this block

diagram are representative of the corresponding device family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. Typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown in this diagram.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 17

dsPIC30F

FIGURE 1-1: dsPIC30F5013/6013/6014 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(144 Kbytes)

Data EEPROM

(4 Kbytes)

Data Latch

Control Signals

to Various Blocks

OSC1/CLKI

Generation

Instruction

Decode &

Control

Timing

MCLR

VDD, V

, AV

PSV & Table Data Access

Control Block

Stac k

Control

Start-up Timer

Low Voltage

Y Data Bus

PCH PCL

PCU Program Counter

Logic

Power-up

Oscillator

POR/BOR

Watchdog

ROM Latch

Timer

Reset

Timer

Detect

Loop

Control

Logic

Decode

Y AGU

DSP Engine

X Data Bus

Y Data

RAM

(4 Kbytes)

Address

Latch

X RAGU X WAGU

Effective Address

16 x 16

W Reg Array

ALU<16>

Data LatchData Latch

X Data

RAM

(4 Kbytes)

Address

Latch

Divide

Unit

PORTA

PORTB

PORTC

PORTD

CN22/RA6 CN23/RA7 V

REF

-/RA9

REF

+/RA10

INT1/RA12

INT2/RA13 INT3/RA14 INT4/RA15

PGD/EMUD/AN0/CN2/RB0

PGC/EMUC/AN1/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

AN6/OCFA/RB6

AN7/RB7

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15

T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 EMUD1/SOSCI/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6

OC8/CN16/RD7

IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15

CAN1,

CAN2

12-bit ADC

Timers

Input Capture Module

DCI

Output

Compare

Module

SPI1, SPI2

I2C

UART1,

UART2

PORTF

PORTG

C1RX/RF0

C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

/CN11/RG9

SS2

CSDI/RG12

CSDO/RG13

CSCK/RG14

COFS/RG15

DS70083G-page 18 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN15 I Analog Analog input channels.

DD P P Positive supply for analog module.

SS P P Ground reference for analog module.

CLKI

CLKO

CN0-CN23 I ST Input change notification inputs.

COFS CSCK CSDI CSDO

C1RX C1TX C2RX C2TX

EMUD EMUC EMUD1

EMUC1 EMUD2 EMUC2 EMUD3

EMUC3

IC1-IC8 I ST Capture inputs 1 through 8.

INT0 INT1 INT2 INT3 INT4

LVDIN I Analog Low Voltage Detect Reference Voltage input pin.

MCLR

OCFA OCFB OC1-OC8

Typ e

I/O I/O

I/O I/O I/O

I/O I/O I/O I/O

I/O

I I I I I

I/P ST Master Clear (Reset) input or programming voltage input. This

I I

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

AN0 and AN1 are also used for device programming data and clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin

function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ST ST ST

—

ST ST ST

ST ST ST ST

ST ST ST ST ST

ST ST

—

Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin. Data Converter Interface serial data input pin. Data Converter Interface serial data output pin.

CAN1 bus receive pin. CAN1 bus transmit pin. CAN2 bus receive pin. CAN2 bus transmit pin

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

pin is an active low Reset to the device.

Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare Fault B input (for Compare channels 5, 6, 7 and 8). Compare outputs 1 through 8.

Description

 2004 Microchip Technology Inc. Preliminary DS70083G-page 19

dsPIC30F

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

OSC1

OSC2

PGD PGC

RA6-RA7 RA9-RA10 RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1-RC4 RC13-RC15

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RF0-RF8 I/O ST PORTF is a bidirectional I/O port.

RG0-RG3 RG6-RG9 RG12-RG15

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL SDA

SOSCO SOSCI

T1CK T2CK T3CK T4CK T5CK

U1RX U1TX U1ARX U1ATX U2RX U2TX

DD P — Positive supply for logic and I/O pins.

SS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Typ e

I/O

I/O I/O I/O

I/O I/O

I/O I/O I/O

I/O

I/O I/O

I I I I I

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

ST ST

ST ST ST

ST ST

ST ST ST

ST ST

— ST ST ST

— ST

ST ST

—

ST/CMOS

ST ST ST ST ST

— ST

—

In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Synchronous serial clock input/output for SPI2. SPI2 Data In. SPI2 Data Out. SPI2 Slave Synchronization.

Synchronous serial clock input/output for I Synchronous serial data input/output for I

32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input.

UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit.

Description

DS70083G-page 20 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

The core has a 24-bit instruction word. The Program Counter (PC) is 23-bits wide with the Least Significant (LS) bit always clear (refer to Section 3.1), and the Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes.

There are two methods of accessing data stored in program memory:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within

program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.

For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.

The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions, as outlined in Section 2.3.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to 15.

 2004 Microchip Technology Inc. Preliminary DS70083G-page 21

dsPIC30F

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAME POINTER

The dsPIC® devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC core has a 16-bit STATUS register (SR), the LS Byte of which is referred to as the SR Low byte (SRL) and the MS Byte as the SR High byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit.

Most SR bits are read/write. Exceptions are:

1. The DA bit: DA is read and clear only because accidentally setting it could cause erroneous operation.

2. The RA bit: RA is a read only bit because accidentally setting it could cause erroneous operation. RA is only set on entry into a REPEAT loop, and cannot be directly cleared by software.

3. The OV, OA, OB and OAB bits: These bits are read only and can only be set by the DSP engine overflow logic.

4. The SA, SB and SAB bits: These are read and clear only and can only be set by the DSP engine saturation logic. Once set, these flags remain set until cleared by the user, irrespective of the results from any subsequent DSP operations.

Note 1: Clearing the SAB bit will also clear both

the SA and SB bits.

2: When the memory mapped STATUS reg-

ister (SR) is the destination address for an operation which affects any of the SR bits, data writes are disabled to all bits.

2.2.2.1 Z Status Bit

Instructions that use a carry/borrow input (ADDC, CPB, SUBB and SUBBR) will only be able to clear Z (for

a non-zero result) and can never set it. A multiprecision sequence of instructions, starting with an instruction with no carry/borrow input, will thus automatically logically AND the successive results of the zero test. All results must be zero for the Z flag to remain set by the end of the sequence.

All other instructions can set as well as clear the Z bit.

2.2.3 PROGRAM COUNTER

The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

DS70083G-page 22 Preliminary  2004 Microchip Technology Inc.

FIGURE 2-1: PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

W0/WREG

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

dsPIC30F

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31

AccA

AccB

Data Table Page Address

SPLIM

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOSTART

DOEND

PC0

Stack Pointer Limit Register

AD15

Program Counter

REPEAT Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

 2004 Microchip Technology Inc. Preliminary DS70083G-page 23

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

Status Register

dsPIC30F

2.3 Instruction Flow

There are 8 types of instruction flows:

1. Normal one-word, one-cycle instructions: these instructions take one effective cycle to execute as shown in Figure 2-2.

FIGURE 2-2: INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV.b #0x55,W0

2. MOV.b #0x35,W1

3. ADD.b W0,W1,W2

2. One-word, two-cycle (or three-cycle) instructions that are flow control instructions: these instructions include the relative branches, relative call, skips and returns. When an instruction changes the PC (other than to increment it), the pipelined fetch is discarded. This causes the instruction to take two effective cycles to execute as shown in Figure 2-3. Some instructions that change program flow require 3 cycles, such as the RETURN, RETFIE and RETLW instructions, and instructions that skip over 2-word instructions.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

FIGURE 2-3: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x55,W0

2. BTSC W1,#3

3. ADD W0,W1,W2

4. BRA SUB_1

5. SUB W0,W1,W3

6. Instruction @ address SUB_1

Fetch 1 Execute 1

Fetch 2 Execute 2

Skip Taken

Fetch 3 Flush

Fetch 4 Execute 4

Fetch 5 Flush

Fetch SUB_1

DS70083G-page 24 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

3. One-word, two-cycle instructions that are not

flow control instructions: the only instructions of this type are the MOV.D (load and store doubleword) instructions, as shown in Figure 2-4.

FIGURE 2-4: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.D OPERATIONS

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV W0,0x1234

2. MOV.D [W0++],W1

3. MOV W1,0x00AA

3a. Stall

4. MOV 0x0CC, W0

4. Table read/write instructions: these instructions

will suspend the fetching to insert a read or write cycle to the program memory. The instruction fetched while executing the table operation is saved for 1 cycle and executed in the cycle immediately after the table operation as shown in Figure 2-5.

Fetch 1 Execute 1

Fetch 2 Execute 2

R/W Cycle 1

Fetch 3 Execute 2

R/W Cycle2

Stall Execute 3

Fetch 4 Execute 4

FIGURE 2-5: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x1234,W0

2. TBLRDL [W0++],W1

3. MOV #0x00AA,W1

3a. Table Operation

4. MOV #0x0CC,W0

5. Two-word instructions for CALL and GOTO: in

these instructions, the fetch after the instruction provides the remainder of the jump or call destination address. These instructions require 2 cycles to execute, 1 cycle to fetch the 2 instruction words (enabled by a high speed path on the second fetch), and 1 cycle to flush the pipeline as shown in Figure 2-6.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 2

Read Cycle

Bus Read Execute 3

Fetch 4 Execute 4

FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x1234,W0

2. GOTO LABEL

2a. Second Word

3. Instruction @ address LABEL

4. BSET W1, #BIT3

Fetch 1 Execute 1

Fetch 2L Update PC

Fetch 2H NOP

Fetch LABEL

Execute LABEL

Fetch 4 Execute 4

 2004 Microchip Technology Inc. Preliminary DS70083G-page 25

dsPIC30F

6. Two-word instructions for DO: in these instructions, the fetch after the instruction contains an address offset. This address offset is added to the first instruction address to generate the last loop instruction address. Therefore, these instructions require 2 cycles as shown in Figure 2-7.

FIGURE 2-7: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW

TCY0TCY1TCY2TCY3TCY4

1. PUSH DOEND

2. DO LABEL,#COUNT

2a. Second Word

3. 1st Instruction of Loop

7. Instructions that are subjected to a stall due to a data dependency between the X RAGU and X WAGU: an additional cycle is inserted to resolve the resource conflict as shown in Figure 2-7. Instruction stalls caused by data dependencies are further discussed in Section 4.0.

Fetch 1 Execute 1

Fetch 2L NOP

Fetch 2H Execute 2

Fetch 3 Execute 3

FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV.b W0,[W1]

2. MOV.b [W1],PORTB

2a. Stall (NOP)

3. MOV.b W0,PORTB

8. Interrupt recognition execution: refer to Section 6.0 for details on interrupts.

Fetch 1 Execute 1

Fetch 2 NOP

Stall Execute 2

Fetch 3 Execute 3

DS70083G-page 26 Preliminary  2004 Microchip Technology Inc.

dsPIC30F

2.4 Divide Support

The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.sw - 16/16 signed divide

5. DIV.uw - 16/16 unsigned divide

The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration.

The quotient for all divide instructions is stored in W0, and the remainder in W1. DIV and DIVF can specify any W register for both the 16-bit dividend and divisor. All other divides can specify any W register for the 16-bit divisor, but the 32-bit dividend must be in an aligned W register pair, such as W1:W0, W3:W2, etc.

The non-restoring divide algorithm requires one cycle for an initial dividend shift (for integer divides only), one cycle per divisor bit, and a remainder/quotient correction cycle. The correction cycle is the last cycle of the iteration loop but must be performed (even if the remainder is not required) because it may also adjust the quotient. A consequence of this is that DIVF will also produce a valid remainder (though it is of little use in fractional arithmetic).

The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the REPEAT instruction as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The divide flow is interruptible. However,

the user needs to save the context as appropriate.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw or DIV.s

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.uw or DIV.u

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

 2004 Microchip Technology Inc. Preliminary DS70083G-page 27

dsPIC30F

2.5 DSP Engine

Concurrent operation of the DSP engine with MCU instruction flow is not possible, though both the MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED and EDAC instructions).

The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

Data input to the DSP engine is derived from one of the following:

1. Directly from the W array (registers W4, W5, W6 or W7) via the X and Y data buses for the MAC class of instructions (MAC, MSC, MPY, MPY.N, ED, EDAC, CLR and MOVSAC).

2. From the X bus for all other DSP instructions.

3. From the X bus for all MCU instructions which use the barrel shifter.

Data output from the DSP engine is written to one of the following:

1. The target accumulator, as defined by the DSP instruction being executed.

2. The X bus for MAC, MSC, CLR and MOVSAC accumulator writes, where the EA is derived from W13 only. (MPY, MPY.N, ED and EDAC do not offer an accumulator write option.)

3. The X bus for all MCU instructions which use the barrel shifter.

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 4-3.

A block diagram of the DSP engine is shown in Figure 2-9.

DS70083G-page 28 Preliminary  2004 Microchip Technology Inc.

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