This application note describes the ATA8352 module, which provides hardware setup guidance for the ATA8352
Ultra-Wide Band (UWB) device. The ATA8352 module is available in two versions:
1.A Demo version with a 48 MHz crystal used in the Demo kit
2.A TDoA version with an external clock and sync signal used in the TDoA kit
Additionally, this document provides the following:
• Current consumption data with the current profile operating in the Prover or the Verifier mode
• Bill of Material (BOM) for the module
Note: The schematic, layout and BOM are provided in a zip folder.
The Microchip Website.................................................................................................................................15
The ATA8352 Module includes the following components to set up a UWB system, controlled by an external MCU
host using an SPI connection (see the following figure):
• ATA8352 Module UWB transceiver device
• 48 MHz crystal for Demo version or external clock supply for TDoA version
• SMA connector for a UWB antenna
The version V1.1 of the module does not include the following:
• UWB prefilter for the 6 GHz to 8.2 GHz band
• Integrated UWB antenna for the 6 GHz to 8.2 GHz band (Replacing the SMA connector)
Figure 2-1. ATA8352 Module (without SMA Connector)
AN3770
ATA8352 Module
2.1 Schematic
The following figure shows the overview of a schematic for the ATA8352 module. This module includes the following
components:
1.ATA8352 UWB device with BGA 33-pin package
2.SMA connector
3.48 MHz crystal for Demo version or external clock circuitry for TDoA version
4.A 30 to 50Ω microstrip transformation line for the RFIO pin
Some components are marked as not mounted as they are not necessary for application use.
The following figure shows the top layer of the ATA8352 module with the routing of the RF path and GND routing of
the ATA8352 device with the blocking capacitors. The structure connection between the PCB and SMA connector
contains a 30 to 50Ω convertor. The recommended guidelines are:
1.Use the same structure and follow the GND connection, as shown in the ATA8352 device layout and the
capacitors to achieve the required sensitivity level. The layout shown in the following figure is designed in such
a way to avoid loop connections for the power and ground supplies.
2.Place three vias below the ATA8352 device for the GND connection.
3.Place a short and straight connection for the RF path to the SMA connector and copy the 30 to 50Ω
conversion.
The following figure illustrates the module footprint.
This chapter provides the ATA8352 module's current consumption profiles of the Prover and Verifier modes. The
measurement conditions are:
• t
• VDDIO = 3.0V
Note: The data sheet defines the electrical characteristics of the ATA8352 module's RF and IO pins. The 3.3V IO
supply provides voltage to the DC/DC converter on the module.
3.1 Supply Current Profile
The supply current profile for a complete Verifier operation including power-up, initialization, calibration of the Verifier
offset mode with Prover response and power-down is shown in Figure 3-1, Figure 3-2 and Figure 3-3. The figures
show the analog signals, VDD_CORE (supply voltage for the core), IDD_CORE (supply current for the core) at 1.25V
and IDD_SUP at 3.3V (supply domain), and the digital signals, N_RST, 1V2_ENA, SPI_CE, IRQ and Controller state
signals. The complete sequence of operations requires ~7.6 ms. The measurement was performed with the
evaluation kit using a SAMC21 MCU with 48 MHz clock and an SPI communication with an 8 MHz clock frequency.
The supply current (IDD_SUP) includes the current for the VDD_IO domain and the current for a DC/DC converter to
supply the VDD_CORE domain (the DC/DC converter used for the measurement is TPS62244-Q1 with a 1.25V
output voltage).
Following is the sequence operation:
1.The DC/DC is switched On at -7.1 ms when the signal, 1V2_ENA, is set to high and, after 1 ms, release the
2.Switch On the crystal oscillator at -5.8 ms.
3.Load the device registers.
4.Initialize the PLL at -3.7 ms and the calibration of the FLL RX at -3.2 ms.
5.Set the RF RX and TX frequencies at -1.7 ms, and enter the READY mode at -1.0 ms.
= 25°C
ambient
N_RST signal.
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Current Consumption Profile
3.2 Verifier Mode Current Consumption
The Verifier mode, VRo, is started with the transmission state and the controller state at 1101 (for details, refer to the
ATA8352 User Manual). See the following figure. The turnaround phases follow this and receive a locked state at
0110. The IRQ signal is activated when the receive is complete and the registers are read. Enable the reset signal
(N_RST) to start the power-down sequence and disable the DC/DC converter.
The following figure shows the Prover mode, PRo, where the initialization occurs similarly to the sequence in Figure
3-2. The Prover is operating in the Receiver Search mode as the controller state at 0101 indicates. When a valid
preamble and sync word are received, the Receiver Locked mode is entered as the controller state at 0110 shows.
When the data telegram is received, the turnaround sequence is executed and the Prover transmits the telegram, as
the controller state at 1101 shows. This sequence is completed with an IRQ and the activation of the Prover mode,
PRo, for the next data telegram.
Figure 3-3. Current Profile for the Prover Mode PRo
The following figure shows the RF spectrum for the ATA8352 module for the composite signal (with low and high
modulation switched on).
Note: The RF filter is not used in the current version of the module, that is, the spectrum shown is the RF output
signal of the device with the default settings, fTX at 6.52 GHz.
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