MICROCHIP 93AA56A, 93AA56B, 93AA56C, 93LC56A, 93LC56B Technical data

...
93AA56A/B/C, 93LC56A/B/C,
93C56A/B/C
2K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range ORG Pin Word Size Temp Ranges Packages
93AA56A 1.8-5.5 No 8-bit I P, SN, ST , MS, OT 93AA56B 1.8-5-5 No 16-bit I P, SN, ST , MS, OT 93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT 93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT 93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST , MS 93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST , MS
93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS
Features
• Low-power CMOS technology
• ORG pin to select word size for ‘56C version
• 256 x 8-bit organization ‘A’ ver. devices (no ORG)
• Self-timed ERASE/WRITE cycles (including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device St a tus signal (READ Y/BUSY)
• Sequential READ function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Pin Function Table
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No internal conn ec tio n
ORG Memory Configuration
V
CC Power Supply
Description
The Microchip Technology Inc. 93XX56A/B/C devices are 2K bit low voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93AA56C, 93LC56C or 93C56C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93AA56A, 93LC56A or 93C56A devices are available, while the 93AA56B, 93LC56B and 93C56B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for low power, nonvolatile memory applications. The entire 93XX Series is available in standard packages includ­ing 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is also available.
Package Types (not to scale)
ROTATED SOIC (ex: 93LC56BX)
NC
1
8
V
CS
CLK
CC
2 3 4
ORG*
7
SS
V
6
DO DI
5
TSSOP/MSOP
(ST, MS)
1
CS
2
CLK
3
DI
4
DO
* ORG pin is NC on A/B devices
8
V
CC
7
NC
6
ORG*
5
V
SS
CS
CLK
DO
DO
V
SS
DI
DI
PDIP/SOIC
(P, SN)
1 2 3 4
SOT-23
(OT)
1
6
2
5
3
4
V
CC
8 7
NC
6
ORG*
SS
V
5
V
CC
CS
CLK
2003 Microchip Technology Inc. DS21794B-page 1
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rat ing on ly and funct ional operati on of th e dev ice at those or any oth er con dit ions abov e thos e indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply over the speci fied ranges unless otherwise noted.
Param.
D1 V
D2 V
D3 Vol1
Symbol Parameter Min Typ Max Units Conditions
No.
IH1 IH2
V
IL1 IL2
V
High-level input volt ag e 2.0
Low-level input voltage -0.3
Low-level output voltag e
Vol2
D4 VOH1
OH2
V
D5 I
LI Input leakage current ±1 µAVIN = VSS to VCC
High-level output volt ag e 2.4
D6 ILO Output leakage current ±1 µAVOUT = VSS to VCC D7 CIN,
C
OUT
Pin capacitance (all inputs/ outputs)
D8 ICC write Write current
D9 I
D10 I
CC read Read current
CCS Standby current
D11 VPOR VCC voltage detect
93AA56A/B/C, 93LC56A/B/C 93C56A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions. 3: READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".
VCC = range by device (see Table on Page 1) Industrial (I): T Automotive (E): T
0.7 VCC
-0.3
VCC - 0.2——
A = -40°C to +85°C A = -40°C to +125°C
——VCC +1
CC +1
V
— —
— —
0.8
0.2 VCC
0.4
0.2 —
VVV
CC 2.7V CC < 2.7V
V
VVVCC 2.7V
CC < 2.7V
V
VVIOL = 2.1 mA, VCC = 4.5V
I
OL = 100 µA, VCC = 2.5V
VVI
OH = -400 µA, VCC = 4.5V OH = -100 µA, VCC = 2.5V
I
——7pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
— —
500
— —
100
— —
2
1
500
1 5
mAµAFCLK = 3 MHz, Vcc = 5.5V
CLK = 2 MHz, Vcc = 2.5V
F
mA
µA µA
CLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 3.0V
F
CLK = 2 MHz, VCC = 2.5V
F
µAµAI – Temp
E – Temp CLK = Cs = 0V ORG = DI = V
(Note 2) (Note 3)
— —
1.5V
3.8V
— —
VV(Note 1)
SS or VCC
DS21794B-page 2 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the specified ranges unless otherwise noted.
CC = range by device (see Table on Page 1)
V Industrial (I): T Automotive (E): T
A = -40°C to +85°C A = -40°C to +125°C
Param.
No.
A1 FCLK Clock frequency 3
A2 TCKH Clock high time 200
A3 TCKL Clock low time 100
A4 TCSS Chip Select setup time 50
Symbol Parameter Min Max Units Conditions
MHz
4.5V VCC < 5.5V, 93XX56C only 2 1
—ns 250 450
—ns 200 450
—ns 100 250
MHz MHz
2.5V V
1.8V V
CC < 5.5V CC < 2.5V
4.5V VCC < 5.5V, 93XX56C only ns ns
2.5V V
1.8V V
CC < 5.5V CC < 2.5V
4.5V VCC < 5.5V, 93XX56C only ns ns
2.5V V
1.8V V
CC < 5.5V CC < 2.5V
4.5V VCC < 5.5V ns ns
2.5V V
1.8V V
CC < 4.5V CC < 2.5V
A5 TCSH Chip Select hold time 0 ns 1.8V ≤ VCC < 5.5V A6 T A7 TDIS Data input setup time 50
A8 TDIH Data input hold time 50
A9 TPD Data output delay time 200
A10 TCZ Data output disable time 100
A11 T
A12 T
CSL Chip Select low tim e 250 ns 1.8V ≤ VCC < 5.5V
—ns 100 250
—ns 100 250
250 400
4.5V VCC < 5.5V, 93XX56C only ns ns
2.5V V
1.8V V
CC < 5.5V CC < 2.5V
4.5V VCC < 5.5V, 93XX56C only ns
2.5V V
1.8V V
ns ns
4.5V VCC < 5.5V, CL = 100 pF ns
2.5V V
1.8V V
ns
CC < 5.5V CC < 2.5V
CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF
nsns4.5V VCC < 5.5V, (Note 1)
200
SV Status valid time 200
300 500
WC Program cycle time 6 ms Erase/Write mode (AA and LC
ns ns ns
1.8V V
4.5V V
2.5V V
1.8V V
CC < 4.5V, (Note 1) CC < 5.5V, CL = 100 pF
CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF
versions)
A13 T
WC 2 ms Erase/Write mode
(93C versions)
A14 T
EC 6 ms ERAL mode, 4.5V ≤ VCC 5.5V
A15 TWL 15 ms WRAL mode, 4.5V VCC 5.5V A16 Endurance 1M cycles 25°C, V
CC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from www.microchip.com.
2003 Microchip Technology Inc. DS21794B-page 3
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

FIGURE 1-1 : SY NCH R ON OUS DA TA TIMING

IH
V
CS
CSS
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
VOH
DO
(READ)
(PROGRAM)
Note: TSV is relative to CS.
DO
VOL VOH
VOL
TSV
T
TCKH
TDIH
TPD
TCKL
TPD
STATUS VALID
TCSH
TCZ
TCZ

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 (RDY/BSY)11 ERAL 1 00 10XXXXXX (RDY/BSY EWDS 1 00 00XXXXXX HIGH-Z 11 EWEN 1 00 11XXXXXX HIGH-Z 11 READ 1 10 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 27 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY)27 WRAL 1 00 01XXXXXXD15 D0(RDY/BSY
)11
)27

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0)

Instruction SB Opcode Address Data In Data Out
ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY ERAL 1 00 10XXXXXXX (RDY/BSY EWDS 1 00 00XXXXXXX HIGH-Z 12 EWEN 1 00 11XXXXXXX HIGH-Z 12 READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 20 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY)20 WRAL 1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY
Req. CLK
Cycles
)12 )12
)20
DS21794B-page 4 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG* pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write d ata a re clocke d into the D I pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/
status during a programming operation. The
BUSY READY/BUSY Write operation by polli ng the DO pi n; DO low indicate s that programming is still in progress, while DO high indicates the de vi ce is rea dy. DO will enter the HIGH-Z state on the falling edge of CS.
2.1 START Condition
The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.
Before a ST ART condi tion is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, or WRAL). As soon as CS is high, the device is no longer in Standby mode.
An instruction following a START condition will only be executed if the requi red opcode, address and data bits for any particular instruction are clocked in.
status can be verified during an Erase/
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that preced es t he R ead o per atio n, i f A0 i s a l ogi c hi gh level. Under such a condition the voltage level seen at Data Out i s undefined a nd will d epend upon the relativ e impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO.
2.3 Data Protection
All modes of operation ar e inhibited when VCC is below a typical voltage of 1.5V for '93AA' and '93LC' devices or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.
Note: For added protection, an EWDS command
should be performed after every write operation.
After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed.
Block Diagram
CC VSS
V
Memory
Array
Data Register
DI
Mode
ORG*
CS
CLK
*ORG input is not avai lable on A/B devices
Decode
Logic
Clock
Register
Address Decoder
Address
Counter
Output
Buffer
DO
2003 Microchip Technology Inc. DS21794B-page 5
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4 ERASE
The DO pin indicates the READY/BUSY device if CS is brought high after a minimum of 250 ns
The ERASE instruction forces all data bits of the speci­fied address to the logical ‘1’ state. CS is brought low following the loa ding of th e last a ddress b it. This fall ing edge of the CS pin initiates the self-timed program­ming cycle, except on ‘93C’ devices where the rising
low (T CSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction.
Note: Issuing a ST ART bit and then taking C S low edge of CLK before the last address bit initiates the write cycle.

FIGURE 2-1 : ERASE TIMI NG FOR 9 3A A AN D 93L C D EVIC E S

CSL
T
CS
CLK
N
1A
AN-1 AN-2
•••
A0
DO
1
DI
HIGH-Z
1
will clear the READY/BUSY DO.
CHECK STATUS
T
SV TCZ
BUSY READY
status of the
status from
HIGH-Z

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

CS
CLK
DO
DI
HIGH-Z
1
1
1A
N
AN-1 AN-2
•••
A0
WC
T
CSL
T
CHECK STATUS
T
SV TCZ
BUSY READY
WC
T
HIGH-Z
DS21794B-page 6 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.5 ERASE ALL (ERAL)
The Erase Al l (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the ERASE cycle, except for the different
The DO pin indicates the READY/BUSY device, if CS is brough t high a fter a minimum of 250 n s low (TCSL).
Note: Issuing a ST ART bit and then taking C S low
opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS, except on
CC must be 4.5V for proper operation of ERAL.
‘93C’ devices where the rising edge of CLK before the
V last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.

FIGURE 2-3 : ERAL TIMIN G FO R 93 AA A ND 9 3L C DEVI C E S

CSL
T
CS
CLK
DI
DO
HIGH-Z
VCC must be 4.5V for proper operation of ERAL.
10010X
•••
X
will clear the READY/BUSY DO.
CHECK STATUS
T
SV TCZ
BUSY READY
EC
T
HIGH-Z
status of the
status from

FIGURE 2-4: ERAL TIMING FOR 93C DE VICE S

CS
CLK
DO
DI
HIGH-Z
10010X
•••
CSL
T
CHECK STATUS
X
T
SV TCZ
BUSY READY
T
EC
HIGH-Z
2003 Microchip Technology Inc. DS21794B-page 7
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX56A/B/C powers up in the ERASE/WRITE Disable (EWDS) state. All Programming modes must be preceded by an ERASE/WRITE En able (EWEN) instruc­tion. Once the EWEN instruction is executed, program­ming remains enabled until an EWDS instruction is executed or Vcc is removed from the device.

FIGURE 2-5: EWDS TIMING

CS
CLK
DI
10
000X

FIGURE 2-6: EWEN TIMING

CS
To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/ WRITE functions and should follow all programming operations. Executio n of a READ instruction i s ind epen­dent of both the EWEN and EWDS instructions.
T
CSL
•••
X
TCSL
CLK
1X
DI
00 1 1X
2.7 READ
The READ instruction outputs the serial data of the addressed memory lo cation on the DO pin. A dummy zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion devices) or 16-bit (If ORG pin is high or B-version

FIGURE 2-7 : READ TIMIN G

CS
CLK
A0
•••
An
0Dx
DO
DI
110
HIGH-Z
•••
devices) output st rin g. The ou tput dat a bi t s will toggle on the rising edge of the CLK and are stable after the spec­ified time dela y (T
PD). Sequentia l read is po ssibl e when
CS is held high. The memory data will automatically cycle to the next re gi ster and output seque nt ia ll y.
•••
D0 Dx
•••
D0
Dx D0
•••
DS21794B-page 8 2003 Microchip Technology Inc.
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