Part NumberVCC RangeORG PinWord SizeTemp RangesPackages
93AA56A1.8-5.5No8-bitIP, SN, ST , MS, OT
93AA56B1.8-5-5No16-bitIP, SN, ST , MS, OT
93LC56A2.5-5.5No8-bitI, EP, SN, ST, MS, OT
93LC56B2.5-5.5No16-bitI, EP, SN, ST, MS, OT
93C56A4.5-5.5No8-bitI, EP, SN, ST, MS, OT
93C56B4.5-5.5No16-bitI, EP, SN, ST, MS, OT
93AA56C1.8-5.5Yes8 or 16-bitIP, SN, ST , MS
93LC56C2.5-5.5Yes8 or 16-bitI, EP, SN, ST , MS
93C56C4.5-5.5Yes8 or 16-bitI, EP, SN, ST, MS
Features
• Low-power CMOS technology
• ORG pin to select word size for ‘56C version
• 256 x 8-bit organization ‘A’ ver. devices (no ORG)
• 128 x 16-bit organization ‘B’ ver. devices (no
ORG)
The Microchip Technology Inc. 93XX56A/B/C devices
are 2K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA56C, 93LC56C or 93C56C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA56A, 93LC56A or 93C56A devices are available,
while the 93AA56B, 93LC56B and 93C56B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rat ing on ly and funct ional operati on of th e dev ice at those or any oth er con dit ions abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:DC CHARACTERISTICS
All parameters apply over the speci fied
ranges unless otherwise noted.
Param.
D1V
D2V
D3Vol1
SymbolParameterMinTypMaxUnitsConditions
No.
IH1
IH2
V
IL1
IL2
V
High-level input volt ag e2.0
Low-level input voltage-0.3
Low-level output voltag e—
Vol2
D4VOH1
OH2
V
D5I
LIInput leakage current——±1µAVIN = VSS to VCC
High-level output volt ag e2.4
D6ILOOutput leakage current——±1µAVOUT = VSS to VCC
D7CIN,
C
OUT
Pin capacitance (all inputs/
outputs)
D8ICC write Write current—
D9I
D10I
CC read Read current—
CCSStandby current—
D11VPORVCC voltage detect
93AA56A/B/C, 93LC56A/B/C
93C56A/B/C
Note 1:This parameter is periodically sampled and not 100% tested.
2:ORG pin not available on ‘A’ or ‘B’ versions.
3:READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".
VCC = range by device (see Table on Page 1)
Industrial (I): T
Automotive (E): T
0.7 VCC
-0.3
—
VCC - 0.2——
A = -40°C to +85°C
A = -40°C to +125°C
——VCC +1
CC +1
V
—
—
—
—
0.8
0.2 VCC
0.4
0.2
—
—
VVV
CC≥ 2.7V
CC < 2.7V
V
VVVCC≥ 2.7V
CC < 2.7V
V
VVIOL = 2.1 mA, VCC = 4.5V
I
OL = 100 µA, VCC = 2.5V
VVI
OH = -400 µA, VCC = 4.5V
OH = -100 µA, VCC = 2.5V
I
——7pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
—
—
—
—
—
500
—
—
100
—
—
2
—
1
500
—
1
5
mAµAFCLK = 3 MHz, Vcc = 5.5V
CLK = 2 MHz, Vcc = 2.5V
F
mA
µA
µA
CLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 3.0V
F
CLK = 2 MHz, VCC = 2.5V
F
µAµAI – Temp
E – Temp
CLK = Cs = 0V
ORG = DI = V
(Note 2) (Note 3)
—
—
1.5V
3.8V
—
—
VV(Note 1)
SS or VCC
DS21794B-page 2 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
TABLE 1-2:AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write d ata a re clocke d into the D I pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
status during a programming operation. The
BUSY
READY/BUSY
Write operation by polli ng the DO pi n; DO low indicate s
that programming is still in progress, while DO high
indicates the de vi ce is rea dy. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a ST ART condi tion is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a START condition will only be
executed if the requi red opcode, address and data bits
for any particular instruction are clocked in.
status can be verified during an Erase/
2.2Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that preced es t he R ead o per atio n, i f A0 i s a l ogi c hi gh
level. Under such a condition the voltage level seen at
Data Out i s undefined a nd will d epend upon the relativ e
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3Data Protection
All modes of operation ar e inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
CCVSS
V
Memory
Array
Data Register
DI
Mode
ORG*
CS
CLK
*ORG input is not avai lable on A/B devices
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
2003 Microchip Technology Inc.DS21794B-page 5
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4ERASE
The DO pin indicates the READY/BUSY
device if CS is brought high after a minimum of 250 ns
The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low
following the loa ding of th e last a ddress b it. This fall ing
edge of the CS pin initiates the self-timed programming cycle, except on ‘93C’ devices where the rising
low (T CSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:Issuing a ST ART bit and then taking C S low
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1 :ERASE TIMI NG FOR 9 3A A AN D 93L C D EVIC E S
CSL
T
CS
CLK
N
1A
AN-1AN-2
•••
A0
DO
1
DI
HIGH-Z
1
will clear the READY/BUSY
DO.
CHECK STATUS
T
SVTCZ
BUSYREADY
status of the
status from
HIGH-Z
FIGURE 2-2:ERASE TIMING FOR 93C DEVICES
CS
CLK
DO
DI
HIGH-Z
1
1
1A
N
AN-1AN-2
•••
A0
WC
T
CSL
T
CHECK STATUS
T
SVTCZ
BUSYREADY
WC
T
HIGH-Z
DS21794B-page 6 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.5ERASE ALL (ERAL)
The Erase Al l (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
The DO pin indicates the READY/BUSY
device, if CS is brough t high a fter a minimum of 250 n s
low (TCSL).
Note:Issuing a ST ART bit and then taking C S low
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
CC must be ≥ 4.5V for proper operation of ERAL.
‘93C’ devices where the rising edge of CLK before the
V
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3 :ERAL TIMIN G FO R 93 AA A ND 9 3L C DEVI C E S
CSL
T
CS
CLK
DI
DO
HIGH-Z
VCC must be ≥ 4.5V for proper operation of ERAL.
10010X
•••
X
will clear the READY/BUSY
DO.
CHECK STATUS
T
SVTCZ
BUSYREADY
EC
T
HIGH-Z
status of the
status from
FIGURE 2-4:ERAL TIMING FOR 93C DE VICE S
CS
CLK
DO
DI
HIGH-Z
10010X
•••
CSL
T
CHECK STATUS
X
T
SVTCZ
BUSYREADY
T
EC
HIGH-Z
2003 Microchip Technology Inc.DS21794B-page 7
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.6ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX56A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All Programming modes must be
preceded by an ERASE/WRITE En able (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is
executed or Vcc is removed from the device.
FIGURE 2-5:EWDS TIMING
CS
CLK
DI
10
000X
FIGURE 2-6:EWEN TIMING
CS
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all ERASE/
WRITE functions and should follow all programming
operations. Executio n of a READ instruction i s ind ependent of both the EWEN and EWDS instructions.
T
CSL
•••
X
TCSL
CLK
1X
DI
00 1 1X
2.7READ
The READ instruction outputs the serial data of the
addressed memory lo cation on the DO pin. A dummy
zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion
devices) or 16-bit (If ORG pin is high or B-version
FIGURE 2-7 :READ TIMIN G
CS
CLK
A0
•••
An
0Dx
DO
DI
110
HIGH-Z
•••
devices) output st rin g. The ou tput dat a bi t s will toggle on
the rising edge of the CLK and are stable after the specified time dela y (T
PD). Sequentia l read is po ssibl e when
CS is held high. The memory data will automatically cycle
to the next re gi ster and output seque nt ia ll y.
•••
D0Dx
•••
D0
DxD0
•••
DS21794B-page 8 2003 Microchip Technology Inc.
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