MICROCHIP 93LC46A, 93LC46B Technical data

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93LC46A/B
1K 2.5V Microwire
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 128 x 8 bit organization (93LC46A)
• 64 x 16 bit organization (93LC46B)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
®
Serial EEPROM
BLOCK DIAGRAM
ADDRESS DECODER
ADDRESS COUNTER
OUTPUT
BUFFER
Vcc Vss
DI
CS
CLK
MEMORY
ARRAY
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
DESCRIPTION
The Microchip Technology Inc. 93LC46AX/BX are 1K­bit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP, 8-pin surface mount SOIC, and TSSOP packages. The 93LC46 AX/BX are of fered only in a 150-mil SOIC package.
DO
PACKAGE T YPE
DIP
CS
1
CLK
DI
DO
Microwire is a registered trademark of National Semiconductor Incorporated.
2000 Microchip Technology Inc. DS21173E-page 1
93LC46A/B
2
3
4
Vcc
8
NC
7
6
NC
5
Vss
CS
CLK
DO
1 2
3
DI
4
8
93LC46A/B
V
7
NC
6
NC
5
Vss
NC
CC
Vcc
CS
CLK
SOICSOIC
93LC46AX/BX
1 2
3
4
8
NC
7
Vss
6
DO
5
DI
CS
CLK
DO
TSSOP
93LC46A/B
1 2 3
DI
4
8
Vcc
7
NC
6
NC
5
Vss
93LC46A/B
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
Vcc...................................................................................7.0V
All inputs and outputs w.r.t. Vss ...............-0.6V to Vcc +1.0V
Storage temperature.....................................-65°C to +150°C
Ambient temp. with power applied................-65°C to +125 °C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins.................................. ..............4 kV
*Notice: Stresses abov e those listed under “Maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicat ed in th e o per ati o nal li st i ngs of t his sp ecific a tion i s not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
CC Power Supply
V
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified operating ranges unless otherwise noted
Parameter Symbol Min. Max. Units Conditions
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current I Output leakage current I Pin capacitance
(all inputs/outputs)
Operating current
Standby current I Clock frequency FCLK Clock high time T
Clock low time T Chip select setup time T Chip select hold time T Chip select low time T Data input setup time T Data input hold time T Data output delay time T Data output disable time T Status valid time T
Program cycle time
Endurance 1M cycles 25°C, V
Note 1: This parameter is tested at Tamb = 25°C and Fclk = 1 MHz.
2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on our website.
Commercial (C): VCC = +2.5V to +6.0V Tamb = 0°C to +70°C Industrial (I): V
IH12.0Vcc +1 V2.7V < VCC 6.0 V (Note 2)
V
IH2 0.7 VCC Vcc +1 V VCC < 2.7V
V
IL1-0.3 0.8 VVCC > 2.7V (Note 2)
V
IL2 -0.3 0.2 Vcc V VCC < 2.7V
V
OL1 0.4 V IOL = 2.1 mA; Vcc = 4.5V
V
OL2 0.2 V IOL =100 µA; Vcc = Vcc Min.
V
OH12.4 VIOH = -400 µA; Vcc = 4. 5V
V
OH2VCC-0.2 VIOH = -100 µA; Vcc = Vcc Min.
V
LI -10 10 µA VIN = VSS to Vcc
LO -10 10 µA VOUT = VSS to Vcc
IN, COUT 7pF
C
CC write 1.5 mA
I
CC read
I
CCS 1 µA CS = Vss; DI = VSS
CKH 250 ns CKL 250 ns CSS 50 ns Relative to CLK CSH 0 ns Relative to CLK CSL 250 ns
DIS 100 ns Relative to CLK DIH 100 ns Relative to CLK
PD 400 ns CL = 100 pF CZ 100 ns CL = 100 pF (Note 2) SV 500 ns CL = 100 pF
T
WC 6msERASE/WRITE mode EC 6 ms ERAL mode
T
WL 15 ms WRAL mode
T
CC = +2.5V to +6.0V Tamb = -40°C to +85°C
1
500
2 1
mA
µA
MHz MHz
V
IN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, F
CLK = 2 MHz; Vcc = 6.0V
F
CLK = 1 MHz; Vcc = 3.0V
F
CC > 4.5V
V V
CC < 4.5V
CLK = 1 MHz
CC = 5.0V, Block Mode (Note 3)
DS21173E-page 2 2000 Microchip Technology Inc.
93LC46A/B
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects the device and forc es it into s tandb y mod e. H owever, a programming cycle wh ic h is al ready in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brou gh t l ow duri ng a p rogram cycle, the device will go into stand by mode as soon as the pro­gramming cycle is completed.
CS must be low for 250 ns minimum (T consecutive instructions. If CS is low, the internal con­trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi­cation between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge o f CLK. Data bits are also clocked out on the posit ive edge of CL K.
CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T clock low time (T
CKL). This gives the controlling master
freedom in preparing opcode, address, and data. CLK is a Don't Care if CS is low (device deselected).
If CS is high, but the START condition has not been detected, an y number of cloc k cycles can be rec eived by the device without changing its status (i.e., waiting for a START condition).
TABLE 2-1 INSTRUCTION SET FOR 93LC46A
CSL) between
CKH) and
CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a ST ART cond ition the spec ified num­ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected.
2.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out (DO) is used in the READ mode to outpu t data synchronously with the CLK input (T positive edge of CLK).
This pin also provides READY/BUSY tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated.
The status signal is not available on DO, if CS is held low during th e entire ERASE or W RITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be hig h to indicate the device is ready.
PD after the
status informa-
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
ERAL EWDS EWEN
READ
WRITE
WRAL
1 11 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY)10 1 00 10XXXXX (RDY/BSY)10 1 00 00XXXXX HIGH-Z 10 1 00 11XXXXX HIGH-Z 10 1 10 A6 A5 A4 A3 A2 A1 A0 D7 - D0 18 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)18 1 00 0 1 X X X X X D7 - D0 (RDY/BSY)18
TABLE 2-2 INSTRUCTION SET FOR 93LC46B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
ERAL EWDS EWEN READ
WRITE
WRAL
1 11 A5 A4 A3 A2 A1 A0 (RDY/BSY)9 1 00 10XXXX (RDY/BSY)9 1 00 00XXXX HIGH-Z 9 1 00 11XXXX HIGH-Z 9 1 10 A5 A4 A3 A2 A1 A0 D15 - D0 25 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25 1 00 0 1 X X X X D15 - D0 (RDY/B SY)25
2000 Microchip Technology Inc. DS21173E-page 3
93LC46A/B
3.0 FUNCTIONAL DESCRIPTION
Instructions, add resses, and wri te data are cl ocked into the DI pin on the rising e dge of the clock (CLK ). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY The READY/BUSY ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high ind icates the devic e is ready . Th e DO will enter the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.
Before a ST ART condi tion is detected, CS, CLK, and DI may change in any combination (except to that of a ST ART conditio n), without re sulting i n any devic e oper­ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.
An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any parti cular instructio n is clocked in.
status during a programming operation.
status can be verified during an
After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don’t care bits un til a new START condition is detected.
3.2 Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high le ve l, i t is po ss ible for a bus conflict to occur during the dummy zero that precedes the READ operati on. Under such a co ndition the volta ge level seen at D O is und efined an d will depend u pon the relative impedances of DO and the signal source driv­ing A0. The higher the cu rrent sourcing c apability of A0, the higher the voltage at the DO pin.
3.3 Data Protection
During power-up, all programming modes of operation are inhibited until Vc c has reac he d a l ev el g reate r tha n
2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional protection against accidentally programming during normal operation.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
VIH
CS
CSS
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
VOH
DO
(READ)
(PROGRAM)
Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V
DO
VOL VOH
VOL
T
TSV
TCKH
TDIH
TPD
TCKL
STATUS VALID
TPD
TCSH
TCZ
TCZ
DS21173E-page 4 2000 Microchip Technology Inc.
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