MICROCHIP 93AA46A, 93AA46B, 93AA46C, 93LC46A, 93LC46B Technical data
...
93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range ORG Pin Word Size Temp Ranges Packages
93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT
93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT
93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST , MS, OT
93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93AA46C 1.8-5.5
93LC46C 2.5-5.5 Yes 8 or 16-bit I, E
93C46C 4.5-5.5 Yes 8 or 16-bit I, E
Yes
8 or 16-bit I P, SN, ST , MS
P, SN, ST, MS
P, SN, ST, MS
Features
• Low-power CMOS technology
• ORG pin to select word size for ‘46C version
• 128 x 8-bit organization ‘A’ ver. devices (no ORG)
• 64 x 16-bit organization ‘B’ ver. devices (no ORG)
• Self-timed ERASE/WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device St a tus signal (READ Y/BUSY
)
• Sequential READ function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Pin Function Table
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
V
SS Ground
NC No internal connection
ORG Memory Configuration
V
CC Power S upply
Description
The Microchip Technology Inc. 93XX46A/B/C devices
are 1K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
Package Types (not to scale)
ROTATED SOIC
(ex: 93LC46BX)
NC
1
8
V
CS
CLK
CC
2
3
4
ORG*
7
SS
V
6
DO
DI
5
TSSOP/MSOP
(ST, MS)
1
CS
2
CLK
3
DI
4
DO
* ORG pin is NC on A/B devices
8
V
CC
7
NC
6
ORG*
5
V
SS
CS
CLK
DO
DO
V
SS
DI
DI
PDIP/SOIC
(P, SN)
1
2
3
4
SOT-23
(OT)
1
6
2
5
3
4
V
CC
8
7
NC
6
ORG*
SS
V
5
V
CC
CS
CLK
2003 Microchip Technology Inc. DS21749D-page 1
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
† NOTICE: Stres ses above those listed under “Absolute Max imum Rat ing s” m ay cause pe rmanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the opera tional lis tings of thi s specifica tion is not implied. Expo sure to max imum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
V
All parameter s apply over the specified ranges
unless otherwise noted.
Param. No. Symbol Parameter Min Typ Max Units Conditions
D1 VIH1
IH2
V
D2 V
IL1
IL2
V
D3 VOL1
V
OL2
D4 VOH1
OH2
V
D5 I
LI Input leakage current — — ±1 µAVIN = VSS to VCC
High-level input voltage 2.0
Low-level input voltage -0.3
Low-level output voltage —
High-level output voltage 2.4
D6 ILO Output leakage current — — ±1 µAVOUT = VSS to VCC
D7 CIN,
C
OUT
D8 ICC
Pin capacitanc e
(all inputs/outputs)
Write current —
write
D9 I
D10 I
CC read Read current —
CCS Standby current —
D11 VPOR VCC voltage detect
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: READY/BUSY
status must be cleared from DO, see Section3.4 "Data Out (DO)".
CC = range by device (see Table on Page 1)
Industrial (I): T
Automotive (E): T
0.7 VCC
-0.3
—
VCC - 0.2——
A = -40°C to +85°C
A = -40°C to +125°C
——VCC +1
CC +1
V
—
—
—
—
0.8
0.2 VCC
0.4
0.2
—
—
VVV
CC ≥ 2.7V
CC < 2.7V
V
VVVCC ≥ 2.7V
CC < 2.7V
V
OL = 2.1 mA, VCC = 4.5V
VVI
I
OL = 100 µA, VCC = 2.5V
VVI
OH = -400 µA, VCC = 4.5V
OH = -100 µA, VCC = 2.5V
I
——7pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
—
—
—
—
—
500
—
—
100
—
—
2
—
1
500
—
1
5
mAµAFCLK = 3 MHz, VCC = 5.5V
CLK = 2 MHz, VCC = 2.5V
F
mA
CLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 3.0V
F
µA
CLK = 2 MHz, VCC = 2.5V
F
µA
I-Temp
µA
µA
E-Temp
CLK = CS = 0V
ORG = DI = VSS or VCC
OTE 3)
—
—
1.5V
3.8V
—
—
(Note 2) (N
VV(Note 1)
DS21749D-page 2 2003 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param. No. Symbol Parameter Min Max Units Conditions
A1 FCLK Clock frequency — 3
A2 TCKH Clock high time 200
A3 TCKL Clock low time 100
A4 TCSS Chip Select setup time 50
A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V
A6 T
CSL Chip Select low time 250 — ns 1.8V ≤ VCC < 5.5V
A7 TDIS Data input setup time 50
A8 TDIH Data input hold time 50
A9 TPD Data output delay time —
A10 TCZ Data output disable time —
A11 T
A12 T
A13 T
A14 T
SV Status valid time — 200
WC Program cycle time — 6 ms Erase/Write mode (AA and LC
WC — 2 ms Erase/Write mode (93C versions)
EC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15 TWL — 15 m s WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please co nsult the Total Endurance™ Model which may be obtained from w ww .microchip.com.
VCC = range by device (see Table on Page 1)
Industrial (I): T
Automotive (E): T
250
450
200
450
100
250
A = -40°C to +85°C
A = -40°C to +125°C
MHz
2
MHz
1
MHz
—ns
ns
ns
—ns
ns
ns
—ns
ns
ns
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
—ns4.5V ≤ VCC < 5.5V, 93XX46C only
100
250
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
—ns4.5V ≤ VCC < 5.5V, 93XX46C only
100
250
—
—
—
200
250
400
100
200
300
500
2.5V ≤ V
1.8V ≤ V
ns 4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ V
1.8V ≤ V
ns 4.5V ≤ VCC < 5.5V, (Note 1)
1.8V ≤ V
ns 4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF
CC < 4.5V, (Note 1)
CC < 5.5V, CL = 100 pF
CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF
versions)
2003 Microchip Technology Inc. DS21749D-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1 : SYNCHRONOUS DA TA TIMING
IH
V
CS
CSS
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
VOH
DO
(READ)
(PROGRAM)
DO
VOL
VOH
VOL
TSV
Note: TSV is relative to CS.
T
TCKH
TDIH
TPD
TCKL
TPD
STATUS VALID
TCSH
TCZ
TCZ
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1 11 A5A4A3A2A1A0 — (RDY/BSY)9
1 00 1 0 X X X X — (RDY/BSY)9
1 00 0 0 X X X X — HIGH-Z 9
1 00 1 1 X X X X — HIGH-Z 9
1 10 A5A4A3A2A1A0 — D15 - D0 25
1 01 A5A4A3A2A1A0 D15 - D0 (RDY/BSY)25
1 00 0 1 X X X X D15 - D0 (RDY/BSY)25
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1 11 A6A5A4A3A2A1A0 — (RDY/BSY)10
1 00 10XXXXX — (RDY/BSY)10
1 00 00XXXXX — HIGH-Z 10
1 00 11XXXXX — HIGH-Z 10
1 10 A6A5A4A3A2A1A0 — D7 - D0 18
1 01 A6A5A4A3A2A1A0 D7 - D0 (RDY/BSY)18
1 00 0 1 X X X X X D7 - D0 (RDY/BSY)18
DS21749D-page 4 2003 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write d ata a re clocke d into the D I pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
status during a programming operation. The
BUSY
READY/BUSY
Write operation by polli ng the DO pi n; DO low indicate s
that programming is still in progress, while DO high
indicates the de vi ce is rea dy. DO will ente r th e HI GH -Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start conditi on is detect ed, CS, CL K, and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the requi red opcode, address and data bits
for any particular instruction are clocked in.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ ope r atio n, i f A0 is a lo gic hig h
level. Under such a condition the voltage level seen at
Data Out is undefine d and will depend upon the rela tive
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
status can be verified during an Erase/
2.3 Data Protection
All modes of operation ar e inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note: For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
V
CC VSS
Memory
Array
Data Register
DI
Mode
ORG*
CS
CLK
*ORG input is not avai lable on A/B devices
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
2003 Microchip Technology Inc. DS21749D-page 5
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4 ERASE
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle , exc ept on ‘93C ’ dev ices w here th e
rising edge of CLK before the last address bit initiates
The DO pin indicates the READY/BUSY
device if CS is brought high after a minimum of 250 ns
low (T CSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note: Issuing a Start bit and then taking CS low
the write cycle.
FIGURE 2-1 : ERASE TI MI NG FOR 9 3A A AN D 93L C D EVIC E S
CSL
T
CS
CLK
DO
DI
HIGH-Z
1
1
1A
N
AN-1 AN-2
•••
A0
will clear the READY/BUSY
DO.
CHECK STATUS
T
SV TCZ
BUSY READY
status of the
status from
HIGH-Z
FIGURE 2-2: ERASE TIMING FOR 93C DEVICES
CS
CLK
DO
DI
HIGH-Z
1
1
1A
N
AN-1 AN-2
•••
A0
WC
T
CSL
T
CHECK STATUS
T
SV TCZ
BUSY READY
WC
T
HIGH-Z
DS21749D-page 6 2003 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5 ERASE ALL (ERAL)
The Erase Al l (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
The DO pin indicates the READY/BUSY
device, if CS is brough t high a fter a minimum of 250 n s
low (TCSL).
Note: Issuing a Start bit and then taking CS low
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
CC must be ≥ 4.5V for proper operation of ERAL.
‘93C’ devices where the rising edge of CLK before the
V
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3 : ERAL TIM IN G FO R 93 AA A ND 9 3L C DE VI C ES
CSL
T
CS
CLK
DI
DO
HIGH-Z
VCC must be ≥ 4.5V for proper operation of ERAL.
10010X
•••
X
will clear the READY/BUSY
DO.
CHECK STATUS
T
SV TCZ
BUSY READY
EC
T
status of the
status from
HIGH-Z
FIGURE 2-4: ERAL TIMIN G FOR 93 C DEVI CES
CS
CLK
DO
DI
HIGH-Z
10010X
•••
CSL
T
CHECK STATUS
X
T
SV TCZ
BUSY READY
T
EC
HIGH-Z
2003 Microchip Technology Inc. DS21749D-page 7
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX46A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All Programming modes must be
preceded by an ERASE/WRITE Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruction is
executed or Vcc is removed from the device.
FIGURE 2-5: EWDS TIMING
CS
CLK
DI
10
000X
FIGURE 2-6: EWEN TIMING
CS
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming operatio ns.
Execution of a READ instruction is independent of both the
EWEN and EWDS instructions.
T
CSL
•••
X
TCSL
CLK
1X
DI
00 1 1X
2.7 READ
The READ instruction outputs the serial data of the
addressed memory lo cation on the DO pin. A dummy
zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion
devices) or 16-bit (If ORG pin is high or B-version
devices) output st ring. The ou tput da ta bi ts will togg le on
FIGURE 2-7 : READ TIMI N G
CS
CLK
DI
110
An
••• A0
•••
the rising edge of the CLK and are stable after the
specified ti me delay (T
PD). Sequential read is possible
when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
DO
DS21749D-page 8 2003 Microchip Technology Inc.
HIGH-Z
0Dx
•••
D0 Dx
•••
D0
Dx D0
•••
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